Backside power island for backside power application

Abstract

A semiconductor structure is provided that includes a plurality of backside power islands, rather than backside power rails. The backside power island is present in the first device track and the second device track. Each backside power island located in the first device track and the second device track is isolated by a first cut region, and the backside power island located in the first device track is separated from the backside power island located in the second device track by a second cut region. The second cutting region is oriented perpendicular to the first cutting region.

Description

BACKGROUND

[0001] The present invention relates to semiconductor technology, and more specifically to semiconductor structures containing multiple backside power islands.

[0002] When forming structures including multiple complementary metal-oxide-semiconductor (CMOS) devices, such as integrated circuits, standard cells can be used as a basic unit for designing and manufacturing integrated circuits. The standard cells can be used to form one or more functional circuits, and each standard cell can have the same size. Using standard cells when designing complex circuits and components reduces design and manufacturing costs.

[0003] In use, each standard cell of a semiconductor structure requires a power input (Vdd) and ground (Vss) connection. To power its individual components, each standard cell is typically coupled with a backside power rail that is electrically connected to the active layer of the standard cell to provide power (Vdd). In some cases, multiple backside power rails can be provided for each standard cell to provide power (Vdd) and ground (Vss) separately.

[0004] In cells containing backside contact structures that provide a direct connection of the backside power rail to one of the source / drain regions of the transistors, the backside first metal level (Ml) is very small in side-by-side pitch. Even at this very small side-by-side pitch, the backside overlay requirements are very high (i.e., sigma less than 10 nm). This problem gets worse for mixed cell heights (i.e., 6T cells and 9T cells). SUMMARY

[0005] A semiconductor structure is provided that includes multiple backside power islands instead of backside power rails. In one embodiment, the semiconductor structure includes backside power islands located in a first device track and a second device track, wherein each backside power island located in the first device track and the second device track is isolated by a first cut region, and the backside power islands located in the first device track are separated from the backside power islands located in the second device track by a second cut region, and wherein the second cut region is oriented perpendicular to the first cut region. Including backside power islands instead of backside power rails allows for structures with mixed cell heights and small side-by-side pitch backside first metal levels.

[0006] In some embodiments of the invention, each of the first device track and the second device track includes p-type field effect transistors and n-type field effect transistors arranged in rows and columns.

[0007] In some embodiments of the invention, the first cut region is located between each n-type field effect transistor to p-type field effect transistor pair present in the first device track and the second device track.

[0008] In some embodiments of the invention, the backside power islands in the first device track have a first width, and the backside power islands in the second device track have a second width, wherein the first width is less than the second width.

[0009] In some embodiments of the invention, the first device track includes first active regions, each first active region having a first width, and the second device track includes second active regions, each second active region having a second width greater than the first width.

[0010] In some embodiments of the invention, both the first cut region and the second cut region are filled with a layer of backside interconnect dielectric material.

[0011] In some embodiments of the invention, the layer of backside interconnect dielectric material in both the first cut region and the second cut region is in direct physical contact with a sidewall of at least one of the backside power islands.

[0012] In some embodiments of the invention, the layer of backside interconnect dielectric material contacts a surface of the backside power distribution network.

[0013] In some embodiments of the invention, the backside power distribution network is connected to at least one of the backside power islands located in both the first device track and the second device track through a metal via contact structure.

[0014] In some embodiments of the invention, the metal via contact structure includes a diffusion barrier liner positioned along sidewalls and a bottom wall of the conductive metal or conductive metal alloy.

[0015] In some embodiments of the invention, a first surface of each backside power island contacts the diffusion barrier layer, and a second surface of each backside power island opposite the first surface contacts the hardmask layer, and wherein the first surface of each backside power island is further from the backside power distribution network than the second surface of each backside power island.

[0016] In some embodiments of the invention, at least one of the backside power islands is electrically connected to a source / drain region of a p-type field effect transistor or an n-type field effect transistor in at least one of the first device track or the second device track through a backside source / drain contact structure.

[0017] In some embodiments of the invention, at least one source / drain region of a p-type field effect transistor or an n-type field effect transistor in at least one of the first device track or the second device track is electrically connected to a front side back end of line (BEOL) structure through a front side source / drain contact structure.

[0018] In some embodiments of the invention, the structure further comprises a carrier wafer located on a surface of the front side BEOL structure.

[0019] In some embodiments of the invention, the source / drain regions electrically connected to the front side BEOL structure are located on a surface of the bottom dielectric isolation layer.

[0020] In some embodiments of the invention, the p-type field effect transistors and the n-type field effect transistors are nanosheet-containing transistors comprising a gate structure surrounding at least one semiconductor channel material nanosheet.

[0021] In some embodiments of the invention, the diffusion break point structure separates the first device track from the second device track, and in such embodiments, the second cut region is located below the diffusion break point structure.

[0022] In some embodiments of the invention, the diffusion break point structure is composed of a dielectric material, and the diffusion break point structure extends into the backside ILD layer.

[0023] In some embodiments of the invention, the backside ILD layer is located above each backside power island.

[0024] In another embodiment of the invention, the semiconductor structure comprises a first device track positioned laterally adjacent to a second device track, wherein each of the first device track and the second device track comprises p-type field effect transistors and n-type field effect transistors arranged in rows and columns; a diffusion break point structure separating the first device track from the second device track; and backside power islands located in both the first device track and the second device track, wherein the backside power islands located in the first device track and the backside power islands located in the second device track are separated by a first cut region, and the backside power islands located in the first device track are separated from the backside power islands located in the second device track by a second cut region, and wherein the second cut region is located below the diffusion break point structure and is oriented perpendicular to the first cut region.

[0025] In this other embodiment of the invention, the first cut region can be located between each n-type field effect transistor to p-type field effect transistor pair present in the first device track and the second device track.

[0026] In this other embodiment of the invention, the backside power islands in the first device track have a first width, and the backside power islands in the second device track have a second width, wherein the first width is less than the second width.

[0027] In this other embodiment of the invention, the first device tracks include first active regions, each first active region having a first width, and the second device tracks include second active regions, each second active region having a second width greater than the first width.

[0028] In this other embodiment of the invention, both the first cut region and the second cut region are filled with a layer of backside interconnect dielectric material.

[0029] In this other embodiment of the invention, the layer of backside interconnect dielectric material in both the first cut region and the second cut region is in direct physical contact with sidewalls of at least one of the backside power islands. BRIEF DESCRIPTION OF DRAWINGS

[0030] Figure 1 is a top-down view showing a device layout that can be employed in the invention, the device layout including a plurality of gate structures located in different device tracks; the shown device layout includes cuts Y1-Y1, cuts Y2-Y2, and cuts X-X.

[0031] Figure 2A , Figure 2B and Figure 2C are cross-sectional views along cuts Y1-Y1, cuts Y2-Y2, and cuts X-X, respectively, of an exemplary semiconductor structure that can be employed in the invention, the exemplary structure including a substrate, a layer of placeholder material located on the substrate, and a material stack located on the layer of placeholder material, the material stack consisting of alternating layers of sacrificial semiconductor material and semiconductor channel material.

[0032] Figure 3A , Figure 3B and Figure 3C are cross-sectional views of the exemplary semiconductor structures shown in Figure 2A , Figure 2B and Figure 2C , respectively, after the material stack and the layer of placeholder material have been patterned into separate patterned material stacks, each separate patterned material stack including a remaining portion of the material stack and a remaining portion of the layer of placeholder material.

[0033] Figure 4 is a top-down view showing the device layout shown in Figure 1 , showing regions in which backside contacts (BCs) will be subsequently formed.

[0034] Figure 5A , Figure 5B and Figure 5C are cross-sectional views of the exemplary semiconductor structures shown in Figure 3A , Figure 3B and Figure 3CFIGS. 1, 2, and 3 are cross-sectional views of exemplary semiconductor structures shown in

[0035] Figure 6A , Figure 6B and Figure 6C are cross-sectional views of exemplary semiconductor structures shown in Figure 5A , Figure 5B and Figure 5C after formation of a front-side interlayer dielectric (ILD) material layer and planarization.

[0036] Figure 7A , Figure 7B and Figure 7C are cross-sectional views of exemplary semiconductor structures shown in Figure 6A , Figure 6B and Figure 6C after formation of a self-aligned diffusion stopper region.

[0037] Figure 8A , Figure 8B and Figure 8C are cross-sectional views of exemplary semiconductor structures shown in Figure 7A , Figure 7B and Figure 7C after formation of a dielectric material in the self-aligned diffusion stopper region to provide a diffusion stopper structure.

[0038] Figure 9A , Figure 9B and Figure 9C are cross-sectional views of exemplary semiconductor structures shown in Figure 8A , Figure 8B and Figure 8C after further nanosheet device processing including removal of the sacrificial gate structures, leaving the semiconductor channel material nanosheets of each nanosheet stack dangling, formation of gate structures around the dangling semiconductor channel material nanosheets of each nanosheet stack, formation of additional front-side ILD material, front-side source / drain contact structures, front-side back end of line (BEOL) structures, and a carrier wafer.

[0039] Figure 10A , Figure 10B and Figure 10C are cross-sectional views of exemplary semiconductor structures shown in Figure 9A , Figure 9B and Figure 9C after removal of the first semiconductor material layer of the substrate.

[0040] Figure 11A , Figure 11B and Figure 11C are cross-sectional views of the exemplary semiconductor structure shown in FIGS. 1 1, Figure 10A , Figure 10B and Figure 10C after removal of the etch stop layer and the second semiconductor layer of the substrate.

[0041] Figure 12A , Figure 12B and Figure 12C are cross-sectional views of the exemplary semiconductor structure shown in FIGS. 1 1, Figure 11A , Figure 11B and Figure 11C after formation of the first backside ILD material layer.

[0042] Figure 13A , Figure 13B and Figure 13C are cross-sectional views of the exemplary semiconductor structure shown in FIGS. 1 1, Figure 12A , Figure 12B and Figure 12C after removal of the backside contact placeholder material to physically expose surfaces of some of the source / drain regions and formation of backside source / drain contact structures that contact the physically exposed surfaces of the source / drain regions.

[0043] Figure 14A , Figure 14B and Figure 14C are cross-sectional views of the exemplary semiconductor structure shown in FIGS. 1 1, Figure 13A , Figure 13B and Figure 13C after formation of a diffusion barrier layer and a backside power rail conductive material layer.

[0044] Figure 15A , Figure 15B and Figure 15C are cross-sectional views of the exemplary semiconductor structure shown in FIGS. 1 1, Figure 14A , Figure 14B and Figure 14C after formation of a hardmask layer on the backside power rail conductive material layer and performing a first backside metal cut (i.e., an X-direction cut) in the hardmask layer.

[0045] Figure 16A , Figure 16B and Figure 16C are cross-sectional views of the exemplary semiconductor structure shown in FIGS. 1 1, Figure 15A , Figure 15B and Figure 15C after formation of an organic planarization layer and performing a second backside metal cut (i.e., a Y-direction cut) in the organic planarization layer and the hardmask layer.

[0046] Figure 17A ,Figure 17B and Figure 17C are cross-sectional views of exemplary semiconductor structures as illustrated in Figure 16A , Figure 16B and Figure 16C after removal of the organic planarization layer and patterning of the backside power rail conductive material layer using the patterned hardmask layer as an etch mask.

[0047] Figure 18A , Figure 18B and Figure 18C are cross-sectional views of exemplary semiconductor structures as illustrated in Figure 17A , Figure 17B and Figure 17C after formation of a second backside ILD material layer.

[0048] Figure 19A , Figure 19B and Figure 19C are cross-sectional views of exemplary semiconductor structures as illustrated in Figure 18A , Figure 18B and Figure 18C after formation of a metal via contact structure and a backside power distribution network.

[0049] FIG. 20 is a schematic diagram illustrating a prior art backside power rail.

[0050] Figure 21 is a schematic diagram illustrating a backside power island according to the present application. DETAILED DESCRIPTION

[0051] The present application will now be described in greater detail by reference to the following discussion and accompanying drawings. It is noted that the drawings of the application are provided solely for purposes of illustration and thus the drawings are not drawn to scale. It is further noted that identical and corresponding elements are denoted by identical reference numerals throughout the several views.

[0052] In the following description, numerous specific details are set forth, such as particular structures, components, materials, dimensions, processing steps and techniques, in order to provide an understanding of various embodiments of the present application. However, it will be appreciated by one of ordinary skill in the art that the various embodiments of the present application can be practiced without these specific details. In other instances, well-known structures or processing steps have not been described in detail in order to avoid obscuring the application.

[0053] It will be understood that when an element (e.g., a layer, region, or substrate) is referred to as being "on" or "over" another element, it can be directly on the other element or intervening elements can also be present. In contrast, when an element is referred to as being "directly on" or "directly over" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "under" or "beneath" another element, it can be directly under the other element, or intervening elements can also be present. In contrast, when an element is referred to as being "directly under" or "directly beneath" another element, there are no intervening elements present.

[0054] As described above, a semiconductor structure is provided that includes a plurality of backside power islands instead of a backside power rail. In one embodiment of the invention, the backside power islands are cut segments of a layer of backside power rail conductive material. The backside power islands are present in a first device track (i.e., a first device region) and a second device track (i.e., a second device region). The backside power islands located in the first device track and the backside power islands located in the second device track are isolated by a first cut region; the first cut region is typically located between each n-type field effect transistor to p-type field effect transistor pair present in the first device track and the second device track. The backside power islands located in the first device track are separated from the backside power islands located in the second device track by a second cut region. In one embodiment of the invention, the second cut region is oriented perpendicular to the first cut region. The second cut region is located beneath a diffusion stop structure (i.e., a dielectric material pillar) that separates the first device track from the second device track. The second cut region extends along the entire length of the diffusion stop structure. The inclusion of backside power islands instead of a backside power rail allows for a structure with mixed cell height and small side-by-side space backside first metal levels.

[0055] Referring first to Figure 1 , a device layout that can be employed in the invention is shown. Figure 1The illustrated device layout includes multiple gate structures GS located in different device tracks (i.e., first device track DT1 and second device track DT2). In one embodiment of the invention, DT1 has a first active region (AA1), and DT2 has a second active region (AA2), wherein AA2 has a width greater than (i.e., wider than) AA1. The different device tracks, DT1 and DT2, are laterally adjacent to each other, and each device track includes p-type field-effect transistors (i.e., PFETs) and n-type field-effect transistors (NFETs) arranged in rows and columns. The NFETs and PFETs are typically (but not always) nanosheet transistors, which include a gate structure surrounding at least one semiconductor channel material nanosheet (preferably, the gate structure surrounds multiple vertically stacked and spaced semiconductor channel material nanosheets). In some embodiments and as shown Figure 1 As shown, DT1 is a 6T design, which, read from the bottom of the page upwards, includes columns of PFETs, NFETs, NFETs, PFETs, PFETs, and NFETs, while DT2 is a 9T design, which, read from the bottom of the page upwards, includes columns of NFETs, PFETs, PFETs, and NFETs. In one embodiment of the invention, XX cuts are performed along the rows containing the bottommost PFET in DT1 and the bottommost NFET in DT2, Y1-Y1 cuts are located between the gate structures GS positioned in DT1 and along the longitudinal direction of the gate structures GS, and Y2-Y2 cuts are located between the gate structures GS positioned in DT2 and along the length direction of the gate structures GS. It should be noted that this device layout is not limited to device layouts including 6T and 9T devices.

[0056] Now for reference Figure 2A , Figure 2B and Figure 2C The following are examples of methods used to demonstrate the use of... Figure 1 The exemplary structures obtained by cutting Y1-Y1, Y2-Y2, and XX can be used in this invention. The exemplary structure includes substrates 10, 12, and 14, a placeholder material layer 16L on substrates 10, 12, and 14, and a material stack consisting of alternating sacrificial semiconductor material layers (i.e., sacrificial semiconductor material layer 18L) and semiconductor channel material layers (i.e., semiconductor material layer 20L) on the placeholder material layer 16L.

[0057] In some embodiments, and as Figure 2A , Figure 2B and Figure 2CAs shown, the substrate can include a first semiconductor material layer 10, an etch stop layer 12, and a second semiconductor material layer 14. In other embodiments, the etch stop layer 12 and the second semiconductor material layer 14 can be omitted, and in such embodiments, the substrate consists of the first semiconductor material layer 10. In yet other embodiments, the etch stop layer 12 can be omitted, and in such embodiments, the substrate consists of the first semiconductor material layer 10 and the second semiconductor material layer 14 (in such embodiments, the semiconductor materials providing the first semiconductor material layer 10 and the second semiconductor material layer 14 are compositionally different from one another).

[0058] The first semiconductor material layer 10 consists of a first semiconductor material. The second semiconductor material layer 14 consists of a second semiconductor material. The term "semiconductor material" is used throughout this application to refer to a material having semiconductor properties. Examples of semiconductor materials that can be used in the present application to provide the first semiconductor material and the second semiconductor material include, but are not limited to, silicon (Si), a silicon germanium (SiGe) alloy, a silicon germanium carbon (SiGeC) alloy, germanium (Ge), a III / V compound semiconductor, or a II / VI compound semiconductor. The second semiconductor material providing the second semiconductor material layer 14 can be compositionally the same as or different from the first semiconductor material providing the first semiconductor material layer 10. In some embodiments of the present application, the etch stop layer 12 can consist of a dielectric material such as, for example, silicon dioxide and / or boron nitride. In other embodiments of the present application, the etch stop layer 12 consists of a third semiconductor material that is compositionally different from the first semiconductor material providing the first semiconductor material layer 10 and the second semiconductor material providing the second semiconductor material layer 14. In one example, the first semiconductor material layer 10 consists of silicon, the etch stop layer 12 consists of silicon dioxide, and the second semiconductor material layer 14 consists of silicon. In another example, the first semiconductor material layer 10 consists of silicon, the etch stop layer 12 consists of silicon germanium, and the second semiconductor material layer 14 consists of silicon.

[0059] The substrate including the first semiconductor material layer 10, the etch stop layer 12, and the second semiconductor material layer 14 can be formed using techniques well known to those skilled in the art. For example, the substrate including the first semiconductor material layer 10, the etch stop layer 12, and the second semiconductor material layer 14 can be formed by an oxygen ion implantation separation process or wafer bonding.

[0060] The placeholder material layer 16L is composed of a fourth semiconductor material that is different in composition from the uppermost semiconductor material portion of the substrate and the semiconductor material that provides the sacrificial semiconductor material layers 18L and the semiconductor channel material layers 20L. In one example, the placeholder material layer 16L is composed of a silicon-germanium alloy having a germanium content of 40 atomic percent to 75 atomic percent. Typically, the placeholder material layer 16L has a thickness of 5 nm to 20 nm; however, other thicknesses can be considered and can be used as the thickness of the placeholder material layer 16L.

[0061] As noted above, the material stack includes alternating sacrificial semiconductor material layers 18L and semiconductor channel material layers 20L. In some embodiments and as shown in FIGS. 1A and IB, the number of sacrificial semiconductor material layers 18L is equal to the number of semiconductor channel material layers 20L. That is, the material stack can include an "n" number of semiconductor channel material layers 20L and an "n" number of sacrificial semiconductor material layers 18L, where n is an integer starting at 1. By way of one example, the material stack includes three sacrificial semiconductor material layers 18L and three semiconductor channel material layers 20L. Each of the sacrificial semiconductor material layers 18L is composed of a fifth semiconductor material, while each of the semiconductor channel material layers 20L is composed of a sixth semiconductor material that is different in composition from the fifth semiconductor material; note that both the fifth semiconductor material and the sixth semiconductor material are different in composition from the fourth semiconductor material. Figure 2A Figure 2B and Figure 2C As noted above, the material stack includes alternating sacrificial semiconductor material layers 18L and semiconductor channel material layers 20L. In some embodiments and as shown in FIGS. 1A and IB, the number of sacrificial semiconductor material layers 18L is equal to the number of semiconductor channel material layers 20L. That is, the material stack can include an "n" number of semiconductor channel material layers 20L and an "n" number of sacrificial semiconductor material layers 18L, where n is an integer starting at 1. By way of one example, the material stack includes three sacrificial semiconductor material layers 18L and three semiconductor channel material layers 20L. Each of the sacrificial semiconductor material layers 18L is composed of a fifth semiconductor material, while each of the semiconductor channel material layers 20L is composed of a sixth semiconductor material that is different in composition from the fifth semiconductor material; note that both the fifth semiconductor material and the sixth semiconductor material are different in composition from the fourth semiconductor material.

[0062] In some embodiments, the sixth semiconductor material that provides each of the semiconductor channel material layers 20L is capable of providing high channel mobility for an n-type field effect transistor (FET) device. In other embodiments, the sixth semiconductor material that provides each of the semiconductor channel material layers 20L is capable of providing high channel mobility for a p-type FET device. The fifth semiconductor material that provides each of the sacrificial semiconductor material layers 18L and the sixth semiconductor material that provides each of the semiconductor channel material layers 20L can include one of the semiconductor materials described above. In one example, each of the sacrificial semiconductor material layers 18L is composed of a silicon-germanium alloy having a germanium content of 20 atomic percent to 40 atomic percent (note that each of the sacrificial semiconductor material layers 18L is different in composition from the sacrificial placeholder material layer 16L described above), and the sixth semiconductor material that provides each of the semiconductor channel material layers 20L is composed of silicon. Other combinations of semiconductor materials are possible as long as the fifth semiconductor material that provides each of the sacrificial semiconductor material layers 18L is different in composition from the sixth semiconductor material that provides each of the semiconductor channel material layers 20L, and the semiconductor material that provides the sacrificial semiconductor material layers 18L and the semiconductor channel material layers 20L is different in composition from the semiconductor material that provides the sacrificial placeholder material layer 16L.

[0063] ​Each sacrificial semiconductor material layer 18L can have a first thickness, and each semiconductor channel material layer 20L can have a second thickness. In embodiments of the application, the first thickness can be equal to, greater than, or less than the second thickness.

[0064] Figure 2A Figure 2B Figure 2C The exemplary structures shown in Figure 3A Figure 3B Figure 3C Figure 2A Figure 2B Figure 2C may be formed by first depositing a sacrificial placeholder material layer 16L on a substrate (in the illustrated embodiment, the sacrificial placeholder material layer 16L is formed on the second semiconductor material layer 14 of the substrate), and then second depositing a material stack on the sacrificial placeholder material layer 16L. The second deposition includes forming the above-described alternating blanket layers of the fifth semiconductor material and the sixth semiconductor material. The first and second depositions can include one of chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or epitaxial growth. The term “epitaxial growth” or “grown epitaxially” refers to growing a semiconductor material on a growth surface of another semiconductor material, where the growing semiconductor material has the same crystal characteristics as the growth surface of the other semiconductor material. In epitaxial deposition processes, chemical reactants provided by source gases are controlled and system parameters are set such that the depositing atoms reach the growth surface of the other semiconductor material with sufficient energy to move on and adapt themselves to the crystal arrangement of the atoms of the growth surface. Examples of various epitaxial growth process equipment that can be employed in the present application include, for example, rapid thermal chemical vapor deposition (RTCVD), low-energy plasma deposition (LEPD), ultrahigh vacuum chemical vapor deposition (UHVCVD), atmospheric pressure chemical vapor deposition (APCVD), and molecular beam epitaxy (MBE). The temperature of epitaxial deposition is typically in the range of 550 °C to 900 °C. Although higher temperatures generally result in faster deposition, faster deposition can result in crystal defects and film cracks.

[0065] Referring now to Figure 3A Figure 3B Figure 3C Figure 2A Figure 2B Figure 2C , respectively, show structures of the exemplary semiconductor structures shown in Figure 2A Figure 2B Figure 2C after patterning the material stack and the placeholder material layer 16L into individual patterned material stacks PS, each including a remaining portion of the material stack and a remaining portion of the placeholder material layer 16L. That is, each individual patterned material stack PS includes a remaining portion of the placeholder material layer 16L (hereinafter referred to as a patterned placeholder material layer 16), a remaining portion of each sacrificial semiconductor material layer 18L (hereinafter referred to as a patterned sacrificial semiconductor material layer 18), and a remaining portion of each semiconductor channel material layer (hereinafter referred to as a patterned semiconductor channel material layer 20). As shown, inFigure 3A Each patterned material stack PS formed in Figure 3B Each patterned material stack PS formed in

[0066] The patterning of the material stack includes lithography and etching. In some embodiments, a hard mask can be formed on top of the material stack, and the hard mask is patterned by lithography and etching to form a patterned hard mask on the material stack. The patterned hard mask can be designed to have different widths depending on the regions where the patterned hard mask is formed. The pattern provided by the patterned hard mask can be transferred into the material stack by etching, and thereafter the patterned hard mask can be removed from each individual patterned material stack PS.

[0067] As Figure 3A-3B Further shown, shallow trench isolation structures 22 can be formed in the substrate; in the illustrated embodiment, shallow trench isolation structures 22 are formed in the second semiconductor material layer 14. The shallow trench isolation structures 22 are composed of any trench dielectric material, such as, for example, silicon oxide. In some embodiments, a trench dielectric liner composed of, for example, SiN can be present on the sidewalls and bottom wall of the trench dielectric material. The shallow trench isolation structures 22 can have a topmost surface that is coplanar with the topmost surface of the unetched portions of the substrate; in the illustrated embodiment, the shallow trench isolation structures 22 can have a topmost surface that is coplanar with the topmost surface of the unetched portions of the second semiconductor material layer 14. The shallow trench isolation structures 22 can be formed by first forming (by lithography and etching) a trench in the upper portion of the substrate (in the illustrated embodiment, the trench is formed in the upper portion of the second semiconductor material layer 14), depositing an optional trench dielectric liner material and a trench dielectric material in the trench, and then performing an etch-back process.

[0068] Reference is now made to Figure 4 , which shows the device layout of Figure 1 , where the regions where the backside contacts (BC) will be subsequently formed are shown. The BC will be formed in the regions that include the backside contact placeholder material 34 shown in Figure 5A , Figure 5B and Figure 5C .

[0069] Reference is now made to Figure 5A , Figure 5B and Figure 5C , which show Figure 3A , Figure 3B and Figure 3CThe exemplary semiconductor structure shown in the middle is after a nanosheet device process including formation of sacrificial gate structures 24, gate spacers 28, bottom dielectric isolation layers 30, nanosheet stacks, backside contact placeholder material 34, and source / drain regions 36. Each nanosheet stack includes alternating sacrificial semiconductor material nanosheets 18NS and semiconductor channel material nanosheets 20NS. In addition, Figure 5A , Figure 5B and Figure 5C Also shown are sacrificial gate caps 26 and inner spacers 32, both of which are formed during the nanosheet device process.

[0070] The nanosheet device process includes first formation of a sacrificial gate material layer (not specifically shown) and a sacrificial gate cap material layer (not specifically shown). In some embodiments, a sacrificial gate dielectric material layer (also not specifically shown) can be formed prior to formation of the sacrificial gate dielectric material. The optional sacrificial gate dielectric material layer can be composed of a dielectric material such as, for example, silicon dioxide. The sacrificial gate material layer includes a sacrificial gate material such as, for example, but not limited to, polysilicon, amorphous silicon, amorphous silicon germanium, or amorphous germanium. The sacrificial gate cap is composed of a hard mask material such as, for example, silicon nitride. The optional sacrificial gate dielectric material layer, the sacrificial gate material layer, and the sacrificial gate cap material layer can be formed utilizing a deposition process such as, for example, CVD, PECVD, physical vapor deposition (PVD), or atomic layer deposition (ALD). In one embodiment of the invention, the optional sacrificial gate dielectric material and the sacrificial gate material layer are deposited prior to deposition of the sacrificial gate cap material layer. In some embodiments, formation of the sacrificial gate cap material layer can be omitted.

[0071] The optional sacrificial gate dielectric material layer, the sacrificial gate material layer, and the sacrificial gate cap material layer are then patterned by photolithography and etching to provide the sacrificial gate structures 24 capped with the sacrificial gate caps 26. Each sacrificial gate structure 24 includes at least an unetched portion of the sacrificial gate material layer. Each sacrificial gate structure 24 can also include an unetched portion of the sacrificial gate dielectric material layer. Each sacrificial gate cap 26 includes an unetched portion of the sacrificial gate cap material layer.

[0072] After formation of the sacrificial gate structures 24 capped with the sacrificial gate caps 26, the patterned placeholder material layer 16 is removed to form a gap under each patterned material stack PS. The patterned material stacks PS are non-floating structures that are anchored in place by at least the sacrificial gate structures 24. Removal of the patterned placeholder material layer 16 includes an etching process that selectively removes the fourth semiconductor material that provided the placeholder material layer 16L.

[0073] After the patterned placeholder material layer 16 is removed from each patterned material stack, nanosheet device processing continues with the formation of gate spacers 28 along the sidewalls of the sacrificial gate structure of each sacrificial gate cap, which structure is the combination of the sacrificial gate structure 24 and the sacrificial gate cap 26. During the formation of the gate spacers 28, the gap formed under each patterned material stack PS is filled, thereby forming a bottom dielectric isolation layer 30. Thus, the gate spacers 28 and the bottom dielectric isolation layer 30 are composed of the same dielectric spacer material and are of unitary construction. Exemplary dielectric spacer materials that can be used to provide the gate spacers 28 and the bottom dielectric isolation layer 30 include, but are not limited to, silicon oxide, SiN, SiBCN, SiOCN, or SiOC. The gate spacers 28 and the bottom dielectric isolation layer 30 can be formed by a deposition process, such as, for example, CVD, PECVD, or ALD.

[0074] After the gate spacers 28 and the bottom dielectric isolation layer 30 are formed, each patterned material stack PS is converted to a nanosheet stack. This conversion includes etching with each gate spacer 28 and the sacrificial gate structure of the sacrificial gate cap as an etch mask. The etching can include reactive ion etching. The term “nanosheet stack” means that the various material layers present in the stack are nanosheets. In a nanosheet stack, each remaining patterned sacrificial semiconductor material layer 18 can be referred to as a sacrificial semiconductor material nanosheet 18NS and each remaining patterned semiconductor channel material layer 20 can be referred to as a semiconductor channel material nanosheet 20NS.

[0075] Next, each sacrificial semiconductor material nanosheet 18NS present in the nanosheet stack is recessed by using a recess etch process. The recess etch process is a selective lateral etch process for removing a portion of each sacrificial semiconductor material nanosheet 18NS. Note that the recessed sacrificial semiconductor material nanosheet 18NS has a width that is less than the width of each semiconductor channel material nanosheet 20NS present in the nanosheet stack.

[0076] Next, an inner spacer 32 is formed at the lateral neighbor of each recessed semiconductor material nanosheet 18NS in each nanosheet stack. Each inner spacer 32 is composed of one of the dielectric spacer materials described above for forming the gate spacers 28 and the bottom dielectric isolation layer 30. The dielectric spacer material that provides each inner spacer 32 can be the same in composition or different from the dielectric material that provides the gate spacers 28 and each bottom dielectric isolation layer 30. The inner spacers 32 are formed by deposition and etching.

[0077] After forming the inner spacers 32, backside contact placeholder materials 34 are formed at selected locations of the structure by etching through the upper portion of the bottom dielectric isolation layer 30 and the substrate that does not include the shallow trench isolation structures 22 (in the illustrated embodiment, this etching is through the upper portion of the second semiconductor material layer 14). The openings resulting from this etching are then filled with a sacrificial material (such as, for example, SiGe, TiOx, or AlOx) by a deposition process such as, for example, epitaxy, CVD, or PECVD, and a recess etch can be performed to provide the backside contact placeholder materials 34 shown in Figure 5A 、 Figure 5B and Figure 5C .

[0078] Next, source / drain regions 36 are formed. The source / drain regions 36 are typically formed by an epitaxial growth process as described above. The source / drain regions 36 extend outward from the sidewalls of each semiconductor channel material nanosheet 20NS. Some of the source / drain regions 36 are formed in direct physical contact with the bottom dielectric isolation layer 30, while other source / drain regions 36 are formed in direct physical contact with the backside contact placeholder materials 34. Each source / drain region 36 is composed of a semiconductor material and a dopant. As used herein, a “source / drain” region can be a source region or a drain region, depending on subsequent wiring and voltage application during transistor operation. The semiconductor material providing each source / drain region 36 is composed of one of the semiconductor materials described above. The semiconductor material providing the source / drain regions 36 can be the same or different in composition from each semiconductor channel material nanosheet 20NS. However, the semiconductor material providing each source / drain region 36 is different in composition from each recessed sacrificial semiconductor material nanosheet 18NS. The dopant present in the source / drain regions 36 can be a p-type dopant or an n-type dopant. The term “p-type” refers to the addition of impurities to an intrinsic semiconductor to create a deficiency of valence electrons. In silicon-containing semiconductor materials, examples of p-type dopants (i.e., impurities) include, but are not limited to, boron, aluminum, gallium, phosphorus, and indium. “n-type” refers to the addition of impurities that contribute free electrons to the intrinsic semiconductor. In silicon-containing semiconductor materials, examples of n-type dopants (i.e., impurities) include, but are not limited to, antimony, arsenic, and phosphorus. In one example, each source / drain region can have a dopant concentration from 4 x 1019atoms / cm3to 3 x 1020atoms / cm3. 20 3 21 3

[0079] Referring now to Figure 6A 、 Figure 6B and Figure 6C , respectively, are shown Figure 5A 、 Figure 5B and Figure 5C ​​​​The exemplary semiconductor structure shown is the structure after forming and planarizing a front-side interlayer dielectric (ILD) material layer 38. The front-side ILD material layer 38 is composed of a dielectric material including, for example, silicon oxide, silicon nitride, undoped silicate glass (USG), fluorosilicate glass (FSG), borosilicate glass (BPSG), spin-coated low-k dielectric layer, chemical vapor deposition (CVD) low-k dielectric layer, or any combination thereof. The term "low-k" as used throughout this application refers to a dielectric material having a dielectric constant less than 4.0 (all dielectric constants mentioned herein are relative to vacuum unless otherwise stated). The front-side ILD material layer 38 can be formed by deposition processes including, but not limited to, CVD, PECVD, or spin-coating. Planarization processes include chemical mechanical polishing (CMP). Figure 6C As shown, the planarization process removes the upper portion of each sacrificial gate cap 26 and the upper portion of each gate spacer 28.

[0080] Now for reference Figure 7A , Figure 7B and Figure 7C They respectively showed Figure 6A , Figure 6B and Figure 6C The exemplary semiconductor structure shown is the structure after the formation of the self-aligned diffusion braking point region 42. The self-aligned diffusion braking point region 42 is formed in the region between each transistor present in the first device track and each transistor present in the second device track of the structure. The self-aligned diffusion braking point region 42 can be formed by first... Figure 6A , Figure 6B and Figure 6C An organic planarization layer (OPL) 40 is formed on the structure provided. The OPL 40 can be formed by a deposition process including, for example, CVD, PECVD, or spin coating. The OPL 40 is then patterned by photolithography and etching to include openings therein. Etching is then used to transfer the openings in the OPL 40 to the upper portion of the substrate (in the illustrated embodiment, etching transfers the openings in the OPL 40 to the upper portion of the second semiconductor material layer 14). Etching completely removes any front-side ILD material layer 38, source / drain regions 36, and bottom dielectric isolation layer 30 located directly below the openings in the OPL 40, and partially removes the upper portion of the substrate, such as... Figure 7C As shown.

[0081] Now for reference Figure 8A , Figure 8B and Figure 8C They respectively showed Figure 7A , Figure 7B and Figure 7CThe exemplary semiconductor structure shown is the structure after forming a dielectric material in the self-aligned diffusion braking point region 42 to provide the diffusion braking point structure 44. The dielectric material providing the diffusion braking point structure 44 may include, for example, silicon dioxide, silicon nitride, or silicon oxynitride; the dielectric material providing the diffusion braking point structure 44 differs in composition from the dielectric material providing the sacrificial gate cap 26. Prior to forming this dielectric material, the OPL 40 is removed using a selective removal process.

[0082] The dielectric material providing the diffusion braking point structure 44 is then deposited (CVD, PECVD, etc.) onto the remainder of the self-aligned diffusion braking point region 42 and overlaid on top of the structure, and then a planarization process such as CMP is employed to provide the final diffusion braking point structure 44. This planarization process removes the dielectric material formed outside the self-aligned diffusion braking point region 42, the upper portion of the front ILD material layer 38, the remainder of each sacrificial gate cap 26, and the upper portion of the remaining gate spacers 28.

[0083] Now for reference Figure 9A , Figure 9B and Figure 9C They respectively showed Figure 8A , Figure 8B and Figure 8C The exemplary semiconductor structure shown is the structure after further nanosheet device processing (including removing the sacrificial gate structure 24, suspending the semiconductor channel material nanosheets 20NS of each nanosheet stack, forming a gate structure 45 around the suspended semiconductor channel material nanosheets 20NS of each nanosheet stack, forming additional front-side ILD material, front-side source / drain contact structure 46, front-side BEOL structure 48 and carrier wafer 50).

[0084] Removing the sacrificial gate structure 24 (which exposes the nanosheet stack) includes any material removal process, such as etching, that selectively removes the sacrificial gate structure 24. Removing the sacrificial semiconductor nanosheets 18NS (which leaves each semiconductor channel nanosheet 20NS suspended) includes any material removal process, such as etching, that selectively removes the sacrificial semiconductor nanosheets 18NS.

[0085] Next, a gate structure 45 is formed. The gate structure 45 includes a gate dielectric material and a gate electrode, both of which are not shown separately but are intended to be within the area defined by the gate structure 45. As known to those skilled in the art, the gate dielectric material directly contacts the physically exposed surfaces of each semiconductor channel material nanosheet 20NS, and the gate electrode is formed on the gate dielectric material. The gate dielectric material has a dielectric constant of 4.0 or greater. Illustrative examples of the gate dielectric material include, but are not limited to, silicon dioxide, hafnium oxide (Hf02), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), lanthanum oxide (La203), lanthanum aluminum oxide (LaAl03), zirconium oxide (Zr02), zirconium silicon oxide (ZrSi04), zirconium silicon oxynitride (ZrSiON), tantalum oxide (Ta02), titanium oxide (TiO), barium strontium titanium oxide (Ba06SrTi2), barium titanium oxide (BaTi03), strontium titanium oxide (SrTi03), ytterbium oxide (Yb203), aluminum oxide (Al203), scandium tantalum lead oxide (Pb(Sc,Ta)03), and / or zinc niobium lead oxide (Pb(Zn,Nb)O). The gate dielectric material can also include dopants, such as lanthanum (La), aluminum (Al), and / or magnesium (Mg). x N y ), tantalum oxide (TaO x ), titanium oxide (TiO), barium strontium titanium oxide (Ba06SrTi2), barium titanium oxide (BaTi03), strontium titanium oxide (SrTi03), ytterbium oxide (Yb203), aluminum oxide (Al203), scandium tantalum lead oxide (Pb(Sc,Ta)03), and / or zinc niobium lead oxide (Pb(Zn,Nb)O). The gate dielectric material can also include dopants, such as lanthanum (La), aluminum (Al), and / or magnesium (Mg).

[0086] The gate electrode can include a work function metal (WFM) and an optional conductive metal. The WFM can be used to set the threshold voltage of the transistor to a desired value. In some embodiments, the WFM can be selected to achieve an n-type threshold voltage shift. As used herein, an “n-type threshold voltage shift” refers to a shift in the effective work function of the work function metal containing material to the silicon conduction band in a silicon containing material. In one embodiment, the work function of the n-type work function metal ranges from 4.1 eV to 4.3 eV. Examples of such materials capable of achieving an n-type threshold voltage shift include, but are not limited to, aluminum titanium, aluminum titanium carbide, tantalum nitride, titanium nitride, hafnium nitride, hafnium silicide, or combinations thereof. In other embodiments, the WFM can be selected to achieve a p-type threshold voltage shift. In one embodiment, the work function of the p-type work function metal ranges from 4.9 eV to 5.2 eV. As used herein, the “threshold voltage” is the lowest obtainable gate voltage that can turn on a semiconductor device (e.g., a transistor) by rendering the channel of the device conductive. As used herein, the term “p-type threshold voltage shift” refers to a shift in the effective work function of the work function metal containing material to the silicon valence band in a silicon containing material. Examples of such materials capable of achieving a p-type threshold voltage shift include, but are not limited to, titanium nitride, tantalum carbide, hafnium carbide, and combinations thereof. The optional conductive metal can include, but is not limited to, aluminum (Al), tungsten (W), or cobalt (Co). The gate structure 45 can be formed by depositing the gate dielectric material and the gate electrode material, followed by a planarization process.

[0087] After the gate structure 45 is formed, additional front-side ILD material is formed. The additional front-side ILD material typically comprises the same dielectric material as the previously formed front-side ILD material layer 38. Collectively, the additional front-side ILD material and the previously formed front-side ILD material layer 38 provide a front-side middle-of-line (MOL) dielectric layer 39 that will house the front-side source / drain contact structures 46. The additional front-side ILD material can be formed utilizing the deposition process used to provide the previous front-side ILD material layer 38.

[0088] The front-side source / drain contact structures 46 are then formed by utilizing a metallization process that includes forming front-side contact openings in the MOL dielectric material layer 39 and thereafter filling (including deposition and planarization) each front-side contact opening with at least one contact conductor material. The contact conductor material can include, for example, a silicide liner (such as Ni, Pt, NiPt), an adhesion metal liner (such as TiN), and a conductive metal (such as W, Cu, Al, Co, Ru, Mo, Os, Ir, Rh, or alloys thereof). The front-side source / drain contact structures 46 can also include one or more contact liners (not shown). In one or more embodiments, the contact liner(s) (not shown) can include a diffusion barrier material. Exemplary diffusion barrier materials include, but are not limited to, Ti, Ta, Ni, Co, Pt, W, Ru, TiN, TaN, WN, WC, alloys thereof, or stacks thereof (such as Ti / TiN and Ti / WC). In one or more embodiments in which a contact liner is present, the contact liner(s) (not shown) can include a silicide liner (such as Ti, Ni, NiPt, etc.) and a diffusion barrier material as described above. Each front-side source / drain contact structure 46 contacts a source / drain region 36 that is directly on the bottom dielectric isolation layer 30; the front-side source / drain contact structure 46 does not physically contact a source / drain region 36 that is on the backside contact placeholder material 34. Each front-side source / drain contact structure 46 has a topmost surface that is coplanar with a topmost surface of the MOL dielectric material layer 39. The front-side source / drain contact structures 46 and the front-side MOL dielectric material layer 39 represent a MOL structure.

[0089] The front-side BEOL structure 48 can include one or more interconnect dielectric material layers (including one of the dielectric materials described above for the front-side ILD material layer 38) that contain one or more wiring regions (the wiring regions can include any conductive metal or conductive metal alloy) embedded therein. The front-side BEOL structure 48 can be formed by utilizing any interconnect device processing techniques. In some embodiments, the wiring regions are Cu wiring regions. The carrier 50 can include one of the semiconductor materials described above for the first semiconductor material layer 10. After the front-side BEOL structure 48 is formed, the carrier wafer 50 is bonded to the front-side BEOL structure 48.

[0090] Referring now to Figure 10A , Figure 10B and Figure 10C , respectively, illustrate structures of the exemplary semiconductor structure shown in Figure 9A , Figure 9B and Figure 9C after removal of the first semiconductor material layer 10 of the substrate. Removal of the first semiconductor material layer 10 typically includes flipping the wafer 180° to physically expose the backside of the substrate. For clarity, this flipping step is not shown in the drawings of the present application. In the illustrated embodiment, the substrate includes the first semiconductor material layer 10, the etch stop layer 12, and the second semiconductor material layer 14. Thus, the flipping can physically expose the first semiconductor layer 10 of the substrate. This flipping step will allow for backside processing of the exemplary structure. Backside processing occurs on the side of the wafer that is opposite to the side on which the transistors (i.e., gate structures 45) have been formed. Flipping of the structure can be performed manually or by utilizing mechanical means such as, for example, a robotic arm.

[0091] Removal of the physically exposed first semiconductor material layer 10 of the substrate physically exposes the etch stop layer 12 of the substrate. Removal of the first semiconductor material layer 10 of the substrate can be performed by utilizing a material removal process that selectively removes the material that provides the first semiconductor material layer 10.

[0092] Referring now to Figure 11A , Figure 11B and Figure 11C , respectively, illustrate structures of the exemplary semiconductor structure shown in Figure 10A , Figure 10B and Figure 10C after removal of the etch stop layer 12 and the second semiconductor layer 14 of the substrate. Removal of the etch stop layer 12 includes a material removal process that selectively removes the material of the etch stop layer 12. Removal of the etch stop layer 12 physically exposes the second semiconductor layer 14 of the substrate. The physically exposed second semiconductor material layer 14 of the substrate can be removed by utilizing a material removal process that selectively removes this layer from the structure. Other material removal processes can be used depending on the type of substrate used. For example, in embodiments where some substrates are composed entirely of one semiconductor material, one material removal process can be used instead of the multiple material removal processing steps described herein.

[0093] Referring now to Figure 12A , Figure 12B and Figure 12C , respectively, illustrate structures of the exemplary semiconductor structure shown in Figure 11A , Figure 11B and Figure 11CThe exemplary semiconductor structure shown is the structure after the formation of the first back-side ILD material layer 52. The first back-side ILD material layer 52 may include one of the dielectric materials described above for the front-side ILD material layer 38. The first back-side ILD material layer 52 can be formed using one of the deposition processes described above for forming the front-side ILD material layer 38. A planarization process may follow the deposition process for forming the first back-side ILD material layer 52. In an embodiment of the invention, the first back-side ILD material layer 52 has a surface coplanar with the surface of the back-side contact occupant material 34. It should be noted that the back-side contact occupant material 34 is embedded in the lower portion of the diffusion braking point structure 44.

[0094] Now for reference Figure 13A , Figure 13B and Figure 13C They respectively showed Figure 12A , Figure 12B and Figure 12C The exemplary semiconductor structure shown is the structure after removing the back-side contact occupant material 34 to physically expose the surfaces of some source / drain regions 36 and forming a back-side source / drain contact structure 54 that contacts the physically exposed surfaces of some source / drain regions 36. Removing the back-side contact occupant material 34 includes a material removal process, such as etching, that selectively removes the back-side contact occupant material 34. The physically exposed source / drain regions 36 are those source / drain contacts that do not include the front-side source / drain contact structure 46. The back-side source / drain contact structure 54 includes the material used for the front-side source / drain contact structure 46 as described above. The back-side source / drain contact structure 54 can be formed by the metallization process used for the front-side source / drain contact structure 46 as described above. The back-side source / drain contact structure 54 has a surface coplanar with the surface of the first back-side ILD material layer 52.

[0095] Now for reference Figure 14A , Figure 14B and Figure 14C They respectively showed Figure 13A , Figure 13B and Figure 13C The exemplary semiconductor structure shown is the structure after the formation of the diffusion barrier layer 56 and the back-side power rail conductive material layer 58.

[0096] The diffusion barrier layer 56 includes a diffusion barrier material that will prevent diffusion of metal ions from the backside power rail conductive material layer 58 into the backside source / drain contact structure 54. Illustrative examples of diffusion barrier materials that can be used as the diffusion barrier layer 56 include TiN, TaN, or a multilayer structure of TaN and TaN. The diffusion barrier layer 56 can be formed by utilizing a deposition process such as, for example, CVD, PECVD, atomic layer deposition (ALD), sputtering, or electroplating. The diffusion barrier layer 56 typically has a thickness of 1 nm to 20 nm; although other thicknesses can be considered and can be utilized as the thickness of the diffusion barrier layer 56.

[0097] The backside power rail conductive material layer 58 is composed of any conductive power rail material including, but not limited to, tungsten (W), cobalt (Co), ruthenium (Ru), aluminum (Al), copper (Cu), platinum (Pt), rhodium (Rh), or palladium (Pd). The backside power rail conductive material layer 58 can be formed by utilizing a deposition process such as, for example, CVD, PECVD, ALD, sputtering, or electroplating. The backside power rail conductive material layer 58 typically has a thickness of 10 nm to 100 nm; although other thicknesses can be considered and can be utilized as the thickness of the backside power rail conductive material layer 58.

[0098] Referring now to Figure 15A , Figure 15B and Figure 15C , respectively, are shown structures of the exemplary semiconductor structures shown in Figure 14A , Figure 14B and Figure 14C after forming a hard mask layer 60 on the backside power rail conductive material layer 58 and performing a first backside metal cut (i.e., an X-direction cut) into the hard mask layer 60. An opening 62 is formed by the metal cut in the X-direction. The hard mask layer 60 includes a dielectric material such as, for example, silicon dioxide or silicon nitride. The metal cut in the X-direction includes lithography and metal etching.

[0099] Referring now to Figure 16A , Figure 16B and Figure 16C , respectively, are shown structures of the exemplary semiconductor structures shown in Figure 15A , Figure 15B and Figure 15C after forming an organic planarization layer 64 and performing a second backside metal cut (i.e., a Y-direction cut) into the organic planarization layer 64 and the hard mask layer 60. An opening 66 is formed by the metal cut in the Y-direction. The organic planarization layer 64 fills the opening 62 and is formed utilizing a deposition process such as, for example, CVD, PECVD, or spin coating. The opening 66 is in a region below the diffusion brake point structure 44. The metal cut in the Y-direction includes lithography and metal etching.

[0100] Referring now toFigure 17A 、 Figure 17B and Figure 17C , respectively, illustrate structures of the exemplary semiconductor structures shown in Figure 16A 、 Figure 16B and Figure 16C after removal of the organic planarization layer 64 and patterning using the patterned hardmask layer 58 as an etch mask. The backside power rail conductive material layer 58 is patterned into individual backside power islands 58P by this process. Removal of the organic planarization layer 64 is performed with any material removal process that selectively removes the material of the organic planarization layer 64 from the structure. The patterning includes a metal etch that selectively etches the backside power rail conductive material layer 58. Openings 68A and openings 68B are formed. The openings 68A are in the X-direction, and the openings 68B are in the Y-direction. This patterning step cuts the backside power rail conductive material layer 58 in the X-direction and the Y-direction. Thus, individual backside power islands 58P are formed at the first backside metal level BM1 and can be used as Vss or Vdd elements as shown in Figure 19A 、 Figure 19B and Figure 19C . In one embodiment of the invention, a first surface of each backside power island 58P contacts the diffusion barrier layer 56, and a second surface of each backside power island 58P opposite the first surface contacts the hardmask layer 60, where the first surface of each backside power island 58P is farther from the backside power distribution network 76 than the second surface of each backside power island 58P.

[0101] Reference is now made to Figure 18A 、 Figure 18B and Figure 18C , respectively, illustrate structures of the exemplary semiconductor structures shown in Figure 17A 、 Figure 17B and Figure 17C after formation of the second backside ILD material layer 70. The second backside ILD material layer 70 includes any of the dielectric materials described above for the first frontside ILD material layer 38. The dielectric material providing the second backside ILD material layer 70 can be the same or different in composition from the dielectric material providing the first backside ILD material layer 52. The second backside ILD material layer 70 can be formed by a deposition process such as, for example, CVD, PECVD, or spin-on. As shown in Figure 18A 、 Figure 18B and Figure 18C , the openings 68A and openings 68B are filled with the second backside ILD material layer 70.

[0102] In Figure 18A and Figure 18B , a first cut region CT1 is shown. Each CT1 is present between each n-type field effect transistor to p-type field effect transistor pair present in the first device track and the second device track. InFigure 18C In particular, a second cut region CT2 is shown. CT2 is present in the region between the first and second device tracks and is located below the diffusion braking point structure 44. It should be noted that each CT1 extends perpendicular to CT2 and that both CT1 and CT2 are filled with a second backside ILD material layer 70. It should also be noted that the second backside ILD material layer 70 in CT1 and CT2 directly contacts the sidewalls of the backside power island 58P.

[0103] Reference is now made to Figure 19A , Figure 19B and Figure 19C which show the exemplary semiconductor structure shown in Figure 18A , Figure 18B and Figure 18C after formation of the metal via contact structures and the backside power distribution network 76. Each metal via contact structure includes a conductive material 74 and a diffusion barrier liner 72. The diffusion barrier liner 72 can include one of the diffusion barrier materials described above for the diffusion barrier layer 56 and the conductive material 74 includes one of the conductive power rail materials described above for the backside power rail conductive material layer 58. The metal via contact structures (including the conductive material 74 and the diffusion barrier liner 72) can be formed using a metallization process. The metallization process includes forming openings into the second backside ILD material layer 70 and the patterned hardmask layer 60 which physically expose one of the backside power islands 58P. These openings are filled to include the conductive material 74 and the diffusion barrier liner 72. As shown in Figure 19A , Figure 19B and Figure 19C the backside power distribution network 76 is formed in contact with the second backside ILD material layer 70 and each metal via contact structure. Thus, the backside power distribution network 76 is in electrical contact with at least one backside power island 59P (now labeled BM1 Vdd) through the metal via contact structure; some backside power islands 59P are configured as BM1 Vss elements. The backside power distribution network 76 includes elements / components configured to distribute electrical power to the transistors.

[0104] Reference is now made to Fig. 20 which shows a schematic diagram showing prior art backside power rails, and Figure 21 Fig. 21 which shows a schematic diagram showing backside power islands according to the present application. As shown in Fig. 20, prior art backside power rails (labeled Vss and Vdd) are metal lines which would continuously extend across different device tracks. In contrast, Figure 21Backside power islands (labeled Vss and Vdd) are shown located in both DT1 and DT2, with the backside power island located in DT1 and the backside power island located in DT2 separated by a first cut region (i.e., CT1), and the backside power island located in the first device track DT1 separated from the backside power island located in the second device track DT2 by a second cut region CT2. As shown, CT2 is oriented perpendicular to CT1, and each CT1 is oriented parallel to each other. In one embodiment of the invention, CT1 is located between each n-type field effect transistor to p-type field effect transistor pair present in the first and second device tracks. In one embodiment of the invention, and as shown, Figure 21 the backside power island in DT1 has a first width wl, and the backside power island in DT2 has a second width w2, where wl is less than w2. This aspect provides for the backside power island in DT1 to be staggered with respect to the backside power island in DT2.

[0105] While the present invention has been particularly shown and described with reference to preferred embodiments, it will be understood to those skilled in the art that various changes in form and details can be made therein without departing from the spirit and scope of the invention. Accordingly, the present invention is not limited to the described and illustrated exact forms and details, but falls within the scope of the appended claims.

[0106] In a preferred embodiment of the invention described herein, a semiconductor structure is provided that includes a first device track positioned laterally adjacent to a second device track, where each of the first device track and the second device track includes p-type field effect transistors and n-type field effect transistors arranged in rows and columns; a diffusion brake point structure separating the first device track from the second device track; and backside power islands in both the first device track and the second device track, where the backside power islands in the first device track and the backside power islands in the second device track are isolated by a first cut region, and the backside power islands in the first device track are separated from the backside power islands in the second device track by a second cut region, where the second cut region is located below the diffusion brake point structure and is oriented perpendicular to the first cut region. The first cut region can be located between each n-type field effect transistor to p-type field effect transistor pair present in the first device track and the second device track. The backside power islands in the first device track can have a first width, and the backside power islands in the second device track can have a second width, where the first width is less than the second width. The first device track can include first active regions, each first active region having the first width, and the second device track can include second active regions, each second active region having a second width that is greater than the first width. Both the first cut region and the second cut region can be filled with a backside interconnect dielectric material layer. The backside interconnect dielectric material layer in the first cut region and the second cut region can be in direct physical contact with a sidewall of at least one of the backside power islands.

Claims

1. A semiconductor structure comprising: backside power islands located in both a first device track and a second device track, wherein each backside power island located in the first device track and the second device track is isolated by a first cut region, and the backside power islands located in the first device track are separated from the backside power islands located in the second device track by a second cut region, and further wherein the second cut region is oriented perpendicular to the first cut region.

2. The semiconductor structure of claim 1, wherein each of the first device track and the second device track comprises p-type field effect transistors and n-type field effect transistors arranged in rows and columns.

3. The semiconductor structure of claim 2, wherein the first cut region is located between each n-type field effect transistor to p-type field effect transistor pair present in the first device track and the second device track.

4. The semiconductor structure of claim 1, wherein the backside power islands in the first device track have a first width and the backside power islands in the second device track have a second width, wherein the first width is less than the second width.

5. The semiconductor structure of claim 1, wherein the first device track comprises first active regions, each of the first active regions having a first width, and the second device track comprises second active regions, each of the second active regions having a second width that is greater than the first width.

6. The semiconductor structure of claim 1, wherein both the first cut region and the second cut region are filled with a layer of backside interconnect dielectric material.

7. The semiconductor structure of claim 6, wherein the layer of backside interconnect dielectric material in both the first cut region and the second cut region is in direct physical contact with a sidewall of at least one of the backside power islands.

8. The semiconductor structure of claim 6, wherein the layer of backside interconnect dielectric material contacts a surface of a backside power distribution network.

9. The semiconductor structure of claim 8, wherein the backside power distribution network is connected to at least one of the backside power islands located in both the first device track and the second device track by a metal via contact structure.

10. The semiconductor structure of claim 9, wherein the metal via contact structure comprises a diffusion barrier liner positioned along sidewalls and a bottom wall of a conductive metal or conductive metal alloy.

11. The semiconductor structure of claim 8, wherein a first surface of each of the backside power islands contacts a diffusion barrier layer, and a second surface of each of the backside power islands opposite the first surface contacts a hardmask layer, and wherein the first surface of each of the backside power islands is further from the backside power distribution network than the second surface of each of the backside power islands.

12. The semiconductor structure of claim 1, wherein at least one of the backside power islands is electrically connected to a source / drain region of a p-type field effect transistor or an n-type field effect transistor in at least one of the first device track or the second device track through a backside source / drain contact structure.

13. The semiconductor structure of claim 1, wherein at least one source / drain region of a p-type field effect transistor or an n-type field effect transistor in at least one of the first device track or the second device track is electrically connected to a frontside back end of line (BEOL) structure through a frontside source / drain contact structure.

14. The semiconductor structure of claim 13, further comprising a carrier wafer located on a surface of the frontside BEOL structure.

15. The semiconductor structure of claim 13, wherein the source / drain region electrically connected to the frontside BEOL structure is located on a surface of a bottom dielectric isolation layer.

16. The semiconductor structure of claim 2, wherein the p-type field effect transistor and the n-type field effect transistor are nanosheet-containing transistors comprising a gate structure surrounding at least one semiconductor channel material nanosheet.

17. The semiconductor structure of claim 1, further comprising a diffusion break point structure separating the first device track from the second device track, wherein the second cut region is located below the diffusion break point structure.

18. The semiconductor structure of claim 17, wherein the diffusion break point structure is composed of a dielectric material, and the diffusion break point structure extends into a backside interlayer dielectric material layer.

19. The semiconductor structure of claim 18, wherein the backside interlayer dielectric material layer is located above each of the backside power islands.

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