A consumable chip, a consumable cartridge, and a communication method

Abstract

Embodiments of the present application provide a consumable chip, a consumable box and a communication method. The consumable box is detachably mounted on an image forming device, the image forming device sends a clock signal to the consumable chip, and the consumable chip is used to adjust the clock signal in response to a first instruction after receiving the first instruction sent by the image forming device. In the embodiments of the present application, the consumable chip can adjust the clock signal, indicating that the consumable chip is successfully mounted, thereby proving that the chip is successfully mounted through the consumable chip side, and avoiding the problem that the printer side cannot detect the installation.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the field of printing technology, in particular to a consumable chip, a consumable cartridge and a communication method. BACKGROUND

[0002] In the printing imaging process, the image forming device needs the assistance of the imaging auxiliary information of the consumable cartridge to complete the imaging process. The imaging auxiliary information of the image forming device is recorded not only on the image forming device but also on the consumable chip. The consumable chip can be installed on the consumable cartridge, for example, the consumable cartridge can include an ink cartridge filled with ink or a toner cartridge filled with toner, wherein the ink and the toner are recording materials. The function of the consumable chip is to control the authentication and data matching between the consumable cartridge and the image forming device, and to provide imaging auxiliary information in the subsequent imaging process. The consumable chip is provided with a wafer and a terminal for realizing electrical connection with the stylus of the image forming device. The terminal of the consumable chip can include a chip select terminal for controlling the data read and write operation of the consumable cartridge; the wafer stores information such as toner amount information, manufacturer information, serial number and the like.

[0003] In the prior art, the image forming device sends a clock signal to the consumable chip, and detects whether the consumable chip is correctly installed through an instruction, however, the detection is to prove that the consumable chip has been successfully installed by the installation detection mechanism on the image forming device side, and it is not disclosed that whether the chip is successfully installed is proved by the consumable chip side, thereby causing the installation detection mechanism on the printer side to possibly malfunction and fail to detect the installation problem. SUMMARY

[0004] Therefore, embodiments of the present application provide a consumable chip, a consumable cartridge and a communication method for proving that the chip is successfully installed by the consumable chip side.

[0005] The first aspect provides a consumable chip, the consumable chip is used to be installed on a consumable cartridge, the consumable cartridge is detachably installed on an image forming device, the image forming device sends a clock signal to the consumable chip, the consumable chip is used to adjust the clock signal after receiving a first instruction sent by the image forming device, and respond to the first instruction; the clock signal includes a first clock and a second clock with low voltage and high voltage alternately, wherein the voltage of the second clock is greater than the voltage of the first clock; the consumable chip is specifically used to pull the first clock in a specific clock period to a third clock; the consumable chip is further used to send a first data signal to the image forming device when adjusting the clock signal stage, and the first data signal is sent to the image forming device at least when the first clock is pulled to the third clock.

[0006] In one possible implementation, the consumable chip is specifically used to pull the second clock to a fourth clock within a specific clock cycle, wherein the voltage of the third clock is greater than or equal to the voltage of the fourth clock.

[0007] In one possible implementation, the first clock that is pulled to the third clock is time-prior to the second clock that is pulled to the fourth clock.

[0008] In one possible implementation, the consumable chip is configured to pull the first clock to the third clock during the first half of a specific clock cycle and send a first data signal to the image forming apparatus; and during the second half of the specific clock cycle, not send the first data signal to the image forming apparatus.

[0009] In one possible implementation, the consumable chip is used to adjust the clock signal within a specific clock cycle of the second set of clock cycles in response to the first instruction.

[0010] In one possible implementation, the voltage of the third clock is equal to the voltage of the second clock, and the voltage of the fourth clock is equal to the voltage of the first clock; or,

[0011] The voltage of the third clock is equal to the voltage of the fourth clock, and the voltage of the third clock is less than the voltage of the second clock; or,

[0012] The voltage of the third clock is greater than the voltage of the fourth clock, and the voltage of the third clock is less than or equal to the voltage of the second clock.

[0013] In one possible implementation, the first data signal is a high voltage.

[0014] In one possible implementation, the first data signal is transmitted to the image forming apparatus for at least a specific time period, the length of which is less than or equal to half a clock cycle.

[0015] A second aspect provides a consumable chip for mounting in a consumable cartridge, the consumable cartridge being detachably mounted in an image forming apparatus. The image forming apparatus sends a clock signal to the consumable chip. The consumable chip is configured to pull up the first clock signal when the first clock is at a low voltage during a specific clock cycle; the consumable chip is configured to send a first data signal to the image forming apparatus during the pull-up phase of the first clock; and / or, the consumable chip is configured to pull down the second clock signal when the second clock is at a high voltage during a specific clock cycle; the consumable chip is configured to send the first data signal to the image forming apparatus before or after the second clock is pulled down.

[0016] In one possible implementation, the consumable chip is used to pull down the second clock when the pull-up action of the first clock lasts for a first cycle, wherein the first cycle is half a cycle of a specific clock cycle, or the first cycle is a portion of a half cycle of a specific clock cycle.

[0017] In one possible implementation, the consumable chip includes a timing module; the consumable chip is used to pull down the second clock when the timing module starts timing from the pull-up action to the first cycle.

[0018] In one possible implementation, the consumable chip is configured to pull up the first clock for a first cycle, and then pull down the second clock for a second cycle that is set at an interval from the first cycle, wherein the second cycle is half a cycle of other clock cycles.

[0019] In one possible implementation, the consumable chip includes a timing module; the consumable chip is used to pull down the second clock when the timing module starts timing from the start of the pull-up action to the start of the second cycle.

[0020] In one possible implementation, the consumable chip is configured to pull down the second clock during a first specific period of the first set of two clock cycles, and pull up the first clock during a second specific period of the second set of clock cycles; or...

[0021] The consumable chip is used to pull up the first clock in a first specific period of the first clock cycle of the first set of two clock cycles, and to pull down the second clock in a second specific period of the second set of clock cycles; or...

[0022] The consumable chip includes at least two sets of clock cycles, and the consumable chip is used to pull up the first clock and pull down the second clock in the second set of clock cycles.

[0023] In one possible implementation, when the consumable chip pulls up the first clock and pulls down the second clock in the second set of clock cycles, the time for pulling up the first clock is earlier than the time for pulling down the second clock.

[0024] In one possible implementation, the pull-up of the first clock and the pull-down of the second clock occur within one clock cycle or within two consecutive clock cycles.

[0025] In one possible implementation, the clock signal includes a first clock and a second clock that alternate between low and high voltages, wherein the voltage of the second clock is greater than the voltage of the first clock.

[0026] The consumable chip is specifically used to pull up the first clock to the third clock.

[0027] The consumable chip is specifically used to pull down the second clock to the fourth clock;

[0028] The voltage of the third clock is greater than or equal to the voltage of the fourth clock.

[0029] In one possible implementation, the consumable chip includes a control module, which includes a first resistor, a first switch, a second resistor, and a second switch. The first resistor and the first switch are connected in series between a first voltage terminal and a first node, and the second resistor and the second switch are connected in series between the first node and the second voltage terminal.

[0030] The first resistor is used to make the signal of the first node the third clock when the first switch is closed and the second switch is open.

[0031] The second resistor is used to make the signal of the first node the fourth clock when the first switch is open and the second switch is closed.

[0032] The third aspect provides a consumable chip, the consumable chip comprising: the consumable chip of the first aspect or any possible implementation of the first aspect; or, the consumable chip of the second aspect or any possible implementation of the second aspect;

[0033] The consumable chip further includes: a brand new consumable substrate and data terminals, clock terminals and a brand new wafer disposed on the brand new consumable substrate, wherein the data terminals and the clock terminals are electrically connected to the brand new wafer;

[0034] When the consumable cartridge is installed in the image forming apparatus, the data terminal and the clock terminal contact the contact pins of the image forming apparatus to form an electrical connection;

[0035] The fourth aspect provides a consumable chip, the consumable chip comprising: the consumable chip of the first aspect or any possible implementation of the first aspect; or, the consumable chip of the second aspect or any possible implementation of the second aspect;

[0036] The consumable chip also includes: an original consumable substrate, a brand new wafer disposed on the original consumable substrate, and a number of functional terminals, wherein the functional terminals are electrically connected to the brand new wafer;

[0037] When the consumable cartridge is installed in the image forming apparatus, the functional terminal contacts the contact pin of the image forming apparatus to form an electrical connection.

[0038] The fifth aspect provides a consumable chip, the consumable chip comprising: the consumable chip of the first aspect or any possible implementation thereof; or, the consumable chip of the second aspect or any possible implementation thereof;

[0039] The consumable chip further includes: an original consumable substrate, a brand new wafer disposed on the original consumable substrate, and a plurality of terminals, wherein the plurality of terminals includes multiple effective terminals, and each of the effective terminals is electrically connected to the brand new wafer;

[0040] The consumable chip further includes a flexible circuit board disposed on the original consumable substrate; when the consumable box is installed on the image forming apparatus, at least one of the effective terminals is not positioned corresponding to the contact pins of the image forming apparatus, and the flexible circuit board contacts the contact pins of the image forming apparatus so that at least one of the effective terminals is electrically connected to the image forming apparatus through the flexible circuit board.

[0041] The sixth aspect provides a consumable chip, the consumable chip comprising: the consumable chip of the first aspect or any possible implementation thereof; or, the consumable chip of the second aspect or any possible implementation thereof;

[0042] The consumable chip further includes: an original consumable substrate and a plurality of terminals disposed on the original consumable substrate, the plurality of terminals including multiple functional terminals; when the consumable box is installed in the image forming apparatus, each of the functional terminals is disposed at a position corresponding to a contact pin of the image forming apparatus and contacts the corresponding contact pin to form an electrical connection;

[0043] The consumable chip further includes: a flexible circuit board, which is disposed on the original consumable substrate, and a brand new wafer is disposed on the flexible circuit board, and each of the functional terminals is electrically connected to the brand new wafer;

[0044] The new wafer is used to control the functional terminals to implement the set signal processing functions.

[0045] A seventh aspect provides a consumable box, comprising: a consumable chip in the first aspect or any possible implementation of the first aspect; or, a consumable chip in the second aspect or any possible implementation of the second aspect; or, a consumable chip in the third aspect or any possible implementation of the third aspect; or, a consumable chip in the fourth aspect; or, a consumable chip in the fifth aspect; or, a consumable chip in the sixth aspect or any possible implementation of the sixth aspect.

[0046] The eighth aspect provides a communication method applied to a consumable chip in the first aspect or any possible implementation of the first aspect; or, a consumable chip in the second aspect or any possible implementation of the second aspect; or, a consumable chip in the third aspect or any possible implementation of the third aspect; or, a consumable chip in the fourth aspect; or, a consumable chip in the fifth aspect; or, a consumable chip in the sixth aspect or any possible implementation of the sixth aspect.

[0047] In the technical solution provided in this application embodiment, the image forming apparatus is used to send a clock signal to the consumable chip. The consumable chip is used to adjust the clock signal in response to the first instruction sent by the image forming apparatus after receiving the first instruction. In this application embodiment, the ability of the consumable chip to adjust the clock signal indicates that the consumable chip has been successfully installed, thereby realizing the proof of successful chip installation from the consumable chip side and avoiding the problem that the printer side cannot detect the installation. Attached Figure Description

[0048] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0049] Figure 1 This application provides a schematic diagram of the structure of a communication system according to an embodiment of the present application.

[0050] Figure 2 This is a schematic diagram of the structure of a stylus holder for an image forming apparatus provided in an embodiment of this application;

[0051] Figure 3 This is a schematic diagram of the structure of a first stylus provided in an embodiment of this application;

[0052] Figure 4 This is a schematic diagram of the structure of the first type of consumable chip provided in the embodiments of this application;

[0053] Figure 5 This is a schematic diagram of the structure of a consumable box provided in an embodiment of this application;

[0054] Figure 6 This is a schematic diagram of the structure of the first plane of the consumable chip provided in the embodiments of this application;

[0055] Figure 7 This is a schematic diagram of the second plane of the consumable chip provided in the embodiments of this application;

[0056] Figure 8 A circuit structure diagram of an image forming apparatus and a consumable chip provided in an embodiment of this application;

[0057] Figure 9 This is a first communication timing diagram of the image forming apparatus and consumable chip provided in an embodiment of this application;

[0058] Figure 10 This is a second communication timing diagram of the image forming apparatus and consumable chip provided in the embodiments of this application;

[0059] Figure 11 This is a third communication timing diagram of the image forming apparatus and consumable chip provided in the embodiments of this application;

[0060] Figure 12 This is a fourth communication timing diagram of the image forming apparatus and consumable chip provided in the embodiments of this application;

[0061] Figure 13A This is a schematic diagram of the structure of the first plane of the second type of consumable chip provided in the embodiments of this application;

[0062] Figure 13B for Figure 13A A schematic diagram of the second plane of the consumable chip;

[0063] Figure 14A This is a schematic diagram of the structure of the first plane of the third type of consumable chip provided in the embodiments of this application;

[0064] Figure 14B for Figure 14A A schematic diagram of the second plane of the consumable chip;

[0065] Figure 15A This is a schematic diagram of the structure of the fourth type of consumable chip provided in the embodiments of this application;

[0066] Figure 15B for Figure 15A A schematic diagram of the first plane of the original consumables substrate;

[0067] Figure 15C forFigure 15A A schematic diagram of the second plane of the original consumables substrate;

[0068] Figure 16A This is a schematic diagram of the structure of the fifth type of consumable chip provided in the embodiments of this application;

[0069] Figure 16B for Figure 16A A schematic diagram of the structure of the second plane;

[0070] Figure 16C for Figure 16A A schematic diagram of the structure of a flexible circuit board. Detailed Implementation

[0071] To better understand the technical solution of this application, the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0072] It should be understood that the described embodiments are merely some, not all, of the embodiments in this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0073] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. The singular forms “a,” “the,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0074] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0075] Figure 1 This is a schematic diagram of the structure of a communication system provided in an embodiment of this application, such as... Figure 1As shown, the communication system may include an image forming apparatus 1 and a consumable chip 21. The image forming apparatus 1 is provided with a communication port 10, and the consumable chip 21 is provided with an interface module 20. A communication link is established between the communication port 10 and the interface module 20, and information is transmitted between the communication port 10 and the interface module 20 through the communication link. For example, during the imaging process, the consumable chip 20 can be used to provide identification information and information on the usage status of the recording material, such as ink or toner. When the image forming apparatus 1 sends a signal to the consumable chip 20, the image forming apparatus 1 is the sender, and the consumable chip 20 is the receiver; conversely, when the consumable chip 20 sends a signal to the image forming apparatus 1, the consumable chip 20 is the sender, and the image forming apparatus 1 is the receiver.

[0076] Examples of image forming apparatus 1 include inkjet printers, laser printers, light-emitting diode (LED) printers, copiers, scanners, or multifunction fax machines, as well as multi-function peripherals (MFPs) that perform the above functions in a single device. Image forming apparatus 1 includes an image forming control unit and an image forming unit. The image forming control unit controls the entire image forming apparatus, and the image forming unit, under the control of the image forming control unit, forms an image on the delivered medium based on image forming data and a developer such as toner stored in consumables.

[0077] As an alternative, the information transmission process between the image forming apparatus 1 and the consumable chip 20 is achieved by physical electrical contact between the stylus on the image forming apparatus 1 and the terminal on the consumable chip 20, or it can be achieved through wireless, jumper wire or other means.

[0078] Figure 2 This is a schematic diagram of the structure of a stylus holder for an image forming apparatus provided in an embodiment of this application, as shown below. Figure 2 As shown, the image forming apparatus 1 includes a stylus holder 11. The stylus holder 11 includes an upper end face 111 and a front end face 112, wherein the upper end face 11 is arranged along the Y-axis, and the front end face 112 is arranged along the X-axis. The stylus holder 11 also includes a first stylus 113, a second stylus 114, a third stylus 115, a fourth stylus 116, and a fifth stylus 117. Figure 2 As shown, the length of the stylus holder 11 can be L, and the value of L can be set according to the needs of the product. Figure 3 This is a schematic diagram of the structure of a first stylus provided in an embodiment of this application, as shown below. Figure 3As shown, the first contact pin 113 includes a first contact pin tip 1131, a first contact pin front end 1132, a first contact pin bevel end 1133, and a first contact pin tip 1134. The first contact pin tip 1131, the first contact pin front end 1132, the first contact pin bevel end 1133, and the first contact pin tip 1134 can all form contact with terminals on the consumable chip 21 for electrical connection. Thus, the consumable chip 21 can achieve a communication connection with the image forming apparatus 1 via the contact pins. In this embodiment, only the first contact pin 113 is described as an example of the specific structure of the contact pin; the specific structures of the other contact pins 114, 115, 116, and 117 are the same as those of the first contact pin 113, and will not be described again here.

[0079] Figure 4 This is a schematic diagram of the structure of the first type of consumable chip provided in the embodiments of this application, as shown below. Figure 4 As shown, the consumable chip 20 may include multiple terminals, which may include a data terminal SDA, a chip select terminal RST, a clock terminal SCL, a power supply terminal VCC, and a ground terminal GND. In this embodiment, Figure 1 The interface module 20 may include Figure 4 The interface module 20 may include multiple terminals, namely a data terminal SDA, a chip select terminal RST, a clock terminal SCL, a power supply terminal VCC, and a ground terminal GND.

[0080] like Figure 2 to Figure 4 As shown, as an optional solution, the first contact pin 113, the second contact pin 114, the third contact pin 115, the fourth contact pin 116 and the fifth contact pin 116 can all make contact with the data terminal SDA, the chip select terminal RST, the clock terminal SCL, the power terminal VCC and the ground terminal GND of the multiple terminals of the consumable chip 21 through the contact pin tips respectively.

[0081] In this embodiment, the consumable chip 21 is used to be installed in the consumable box, and the consumable box is detachably installed in the image forming apparatus 1. Figure 5 This is a structural schematic diagram of a consumable box provided in an embodiment of this application, as shown below. Figure 5 As shown, the consumable box 2 may include an upper surface 201 and a front surface 202, and the consumable chip 21 may be mounted on the front surface 202 of the consumable box 2. Furthermore, after mounting the consumable chip 21 onto the consumable box 2, the consumable box 2 can be mounted onto the image forming apparatus 1, enabling information transmission between the image forming apparatus 1 and the consumable chip 20.

[0082] Specifically, the image forming apparatus 1 can send data signals to the consumable chip 21 via the data terminal SDA; the image forming apparatus 1 can send a chip select signal to the consumable chip 21 via the chip select terminal RST; the image forming apparatus 1 can send a periodic, alternating low-voltage and high-voltage clock signal to the consumable chip 21 via the clock terminal SCL; the image forming apparatus 1 can provide operating voltage to the consumable chip 21 via the power supply terminal VCC; and the image forming apparatus 1 can provide a unified reference low voltage for receiving and transmitting data between the image forming apparatus 1 and the consumable chip 21 via the ground terminal GND, thereby ensuring the correctness and stability of the communication process.

[0083] Figure 6 This is a schematic diagram of the structure of the first plane of the consumable chip provided in the embodiments of this application. Figure 7 This is a schematic diagram of the structure of the second plane of the consumable chip provided in the embodiments of this application, as shown below. Figure 6 and Figure 7 As shown, the consumable chip 21 may include a first substrate 210, which may include a first plane 211 and a second plane 212. For example, the first plane 211 may be the front side of the first substrate 210, and the second plane 212 may be the back side of the first substrate 210.

[0084] like Figure 6 As shown, the first plane 211 can be provided with at least two terminals, which are electrically connected to the contact pins of the image forming apparatus 1 to enable communication between the image forming apparatus and the consumable chip 21. Alternatively, the first plane 211 can be provided with five terminals, specifically, a first terminal 2111, a second terminal 2112, a third terminal 2113, a fourth terminal 2114, and a fifth terminal 2115. The first terminal 2111 can be a data terminal (SDA), the second terminal 2112 can be a chip select terminal (RST), the third terminal 2113 can be a clock terminal (SCL), the fourth terminal 2114 can be a power supply terminal (VCC), and the fifth terminal 2115 can be a ground terminal (GND). Of course, in practical applications, the number of terminals in this application embodiment is not limited. For example, when the number of terminals is two, the first plane 211 can be provided with a first terminal 2111 and a third terminal 2113, wherein the first terminal 2111 can be a data terminal SDA and the third terminal 2113 can be a clock terminal SCL. For another example, the number of terminals can also be three or four. For example, multiple terminals can include a data terminal SDA, a clock terminal SCL, a power terminal VCC, or include a data terminal SDA and a clock terminal SCL, as well as one or more or a combination of a power terminal VCC, a chip select terminal RST, and a ground terminal GND. These will not be listed one by one here.

[0085] like Figure 7As shown, the second plane 212 can be provided with the first device 213, for example, the first device 213 can be a wafer. Figure 6 The first terminal 2111, the second terminal 2112, the third terminal 2113, the fourth terminal 2114, and the fifth terminal 2115 can be electrically connected to the first device 213 via wires or wireless means. For example... Figure 7 As shown, the first device 213 may include a timing module 2131 (or a module that performs a similar timing function, such as a delay module, a clock module, a counting module, etc.), a storage module 2132, and a control module 2133. The timing module 2131 is used for timing, the storage module 2132 is used for storing imaging auxiliary information, and the control module 2133 is used for controlling the communication between the consumable chip 21 and the image forming apparatus 1.

[0086] As an optional solution, the storage module 2132 can employ common non-volatile storage cells, such as erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory, ferroelectric storage cells, phase-change storage cells, etc. Alternatively, it can employ volatile storage cells combined with a power supply, such as static random access memory (SRAM) with a battery or capacitor, or dynamic random access memory (DRAM) with a battery or capacitor. The control module 2133 can be used to control the communication between the consumable chip 21 and the image forming apparatus 1. The image forming apparatus 1 can read information from and store information in the first device 213. Specifically, the control unit 2133 can be a microcontroller unit (MCU), microcontroller, field-programmable gate array (FPGA), application-specific integrated circuit (ASIC), etc. The composition of the first device 213 can be selected according to actual needs, and this application embodiment does not limit this.

[0087] Figure 8 This is a schematic diagram of a circuit structure for the image forming apparatus and consumable chip provided in an embodiment of this application, such as... Figure 8As shown, the consumable chip 21 transmits signals externally through the interface module 20, and the first node N1 within the consumable chip 21 is connected to the interface module 20. The consumable chip 21 may include a control module 2133, which may include a first resistor R1, a first switch S1, a second resistor R2, and a second switch S2. The first resistor R1 and the first switch S1 are connected in series between a first voltage terminal and the first node N1, and the second resistor R2 and the second switch S2 are connected in series between the first node N1 and the second voltage terminal. The voltage at the first voltage terminal is greater than the voltage at the second voltage terminal. The first voltage terminal can be a high voltage terminal VCC, and the second voltage terminal can be a low voltage terminal, for example, a ground terminal GND. The first end of the first resistor R1 is connected to the high voltage terminal VCC, and the second end of the first resistor R1 is connected to the first end of the first switch S1, which is connected to the first node N1. The first end of the second switch S2 is connected to the first node N1, and the second end of the second switch S2 is connected to the first end of the second resistor R2, which is connected to the ground terminal GND. The first resistor R1 is a current-limiting resistor. Connected in series between the first switch S1 and the high-voltage terminal VCC, it limits the current and prevents excessive current. The second resistor R2 is a current-limiting resistor. Connected in series between the second switch S2 and the ground terminal GND, it limits the current and prevents excessive discharge current.

[0088] like Figure 8 As shown, the consumable chip 21 can change the voltage of the first node N1 according to the signal to be transmitted. When the consumable chip 21 sends a signal to the image forming apparatus 1 (i.e., during the uplink period), if a high voltage signal needs to be sent, the first switch S1 is closed, so that the first node N1 is selectively connected to the high voltage terminal VCC through the first resistor R1. At this time, the second switch S2 is open, and the signal of the first node N1 is high voltage. If a low voltage signal needs to be sent, the second switch S2 is closed, so that the first node N1 is selectively connected to the ground terminal GND through the second resistor R2. At this time, the first switch S1 is open, and the signal of the first node N1 is low voltage. Of course, in addition to setting the first resistor R1 and the second resistor R2, other devices capable of voltage division can be set, and there are no restrictions here.

[0089] like Figure 8As shown, the image forming apparatus 1 transmits signals externally through the communication port 10, and the second node M1 within the image forming apparatus 1 is connected to the communication port 10. The image forming apparatus 1 may include a third resistor R3, a third switch S3, and a fourth resistor R4. The third resistor R3 is connected between the third voltage terminal and the second node M1, and the third switch S3 and the fourth resistor R4 are connected in series between the second node M1 and the fourth voltage terminal. The third voltage terminal can be a high voltage terminal VCC, and the fourth voltage terminal can be a low voltage terminal, for example, the low voltage terminal can be the ground terminal GND. The first end of the third resistor R3 is connected to the high voltage terminal VCC, and the second end of the third resistor R3 is connected to the second node M1; the first end of the third switch S3 is connected to the second node M1, the second end of the third switch S3 is connected to the first end of the fourth resistor R4, and the second end of the fourth resistor R4 is connected to the ground terminal GND. The third resistor R3 is a pull-up resistor; by providing a pull-up resistor between the high voltage terminal VCC and the second node M1, the voltage of the second node M1 can be clamped to a high voltage. The fourth resistor R4 is a current-limiting resistor. A current-limiting resistor is connected in series between the third switch S3 and the ground terminal GND to limit the current and prevent the discharge current from being too large.

[0090] like Figure 8 As shown, the image forming apparatus 1 changes the voltage of the second node M1 according to the signal to be transmitted. When the image forming apparatus 1 sends a signal to the consumable chip 1 (i.e., during the downlink period), if a high voltage signal needs to be sent, the third switch S3 is open, and the third resistor R3 clamps the voltage of the second node M1 at a high voltage, so the signal of the second node M1 is a high voltage; if a low voltage signal needs to be sent, the third switch S3 is closed, so that the second node M1 is selectively connected to the ground terminal GND through the fourth resistor R4, so the signal of the second node M1 is a low voltage. Of course, in addition to the resistor R3, a fourth switch similar to the first switch S1 can also be set between the second node M1 and VCC in the image forming apparatus 1, and there is no limitation here.

[0091] In related technologies, the image forming apparatus sends a clock signal to the consumable chip and detects whether the consumable chip is correctly installed via instructions. However, this detection relies on the installation detection mechanism on the image forming apparatus side to prove that the consumable chip has been successfully installed, without revealing that the chip is successfully installed via the consumable chip side. This could lead to a malfunction of the installation detection mechanism on the printer side, making it unable to detect installation problems.

[0092] To solve the above-mentioned technical problems, based on the above... Figure 1 to Figure 8The image forming apparatus 1 and consumable chip 21 shown in this application embodiment provide a consumable chip 21 for mounting in a consumable cartridge 2, which is detachably mounted in the image forming apparatus 1. The consumable chip 21 is used to adjust a clock signal in response to a first instruction sent by the image forming apparatus 1. The clock signal includes a first clock and a second clock alternating between low and high voltages, wherein the voltage of the second clock is greater than the voltage of the first clock. Specifically, the consumable chip is used to pull the first clock to a third clock within a specific clock cycle.

[0093] The consumable chip is used to pull up a first clock when the first clock of the clock signal is at a low voltage during a specific clock cycle; and / or, the consumable chip is used to pull down a second clock when the second clock of the clock signal is at a high voltage during a specific clock cycle; the consumable chip is used to send a first data signal to the image forming apparatus during the first clock being pulled up; or, the consumable chip is used to send a first data signal to the image forming apparatus before or after the second clock is pulled down.

[0094] The first instruction can be the first instruction sent by the image forming apparatus 1 to the consumable chip 21 during each read / write operation of the image forming apparatus 1 on the consumable chip 21. For example, the first instruction can be an installation detection instruction.

[0095] When the consumable chip 21 receives an installation detection command from the image forming apparatus, it can only adjust the clock signal if the installation is successful. In other words, if the consumable chip 21 can adjust the clock signal after receiving the installation detection command, it indicates that the consumable chip 21 has been successfully installed.

[0096] In the technical solution provided in this application embodiment, the image forming apparatus is used to send a clock signal to the consumable chip. The consumable chip is used to adjust the clock signal in response to the first instruction sent by the image forming apparatus after receiving the first instruction. In this application embodiment, the ability of the consumable chip to adjust the clock signal indicates that the consumable chip has been successfully installed, thereby realizing the proof of successful chip installation from the consumable chip side and avoiding the problem that the printer side cannot detect the installation.

[0097] As an optional configuration, the consumable chip 21 is also used to send a first data signal to the image forming apparatus 1. When adjusting the clock signal, the consumable chip 21 sends the first data signal to the image forming apparatus 1; the first data signal is sent to the image forming apparatus at least when the first clock signal is pulled back to the third clock signal, i.e., during the clock signal adjustment process, including the process of pulling the first clock signal back to the third clock signal, the first data signal is sent to the image forming apparatus at least when the first clock signal is pulled back to the third clock signal.

[0098] In this embodiment of the application, the image forming apparatus detects the installation of the consumable chip by sending a first instruction. During the installation detection process, if the consumable chip can adjust the clock signal and send a first data signal to the image forming apparatus, it indicates that the consumable chip has been successfully installed, thereby realizing the dual detection of clock signal and data signal.

[0099] As an alternative, the consumable chip 21 is used to pull the first clock to the third clock during the first half of a specific clock cycle and send a first data signal to the image forming apparatus 1; and during the second half of the specific clock cycle, it does not send the first data signal to the image forming apparatus 1.

[0100] As an alternative, the consumable chip 21 is used to adjust the clock signal within a specific clock cycle of the second set of clock cycles in response to the first instruction.

[0101] Figure 9 This is a first communication timing diagram of the image forming apparatus and consumable chip provided in the embodiments of this application, such as... Figure 9 As shown, Figure 9 As shown, the image forming apparatus 1 sends a clock signal SCK to the consumable chip 21. The clock signal includes a first clock and a second clock that alternate between low voltage and high voltage. The voltage of the second clock is greater than the voltage of the first clock. The first clock can be a low voltage, for example, 0V; the second clock can be a high voltage, for example, 3.3V.

[0102] like Figure 9 As shown, the image forming apparatus 1 performs installation detection on the consumable chip 21 within two sets of clock cycles. The first set of clock cycles may include the first D1 to D9 clock cycles, and the second set of clock cycles may include the second D1 to D9 clock cycles. Of course, the number of clock cycles in a set of clock cycles can be one or more, and the number of clock cycles in the first set and the second set of clock cycles can be equal or unequal.

[0103] like Figure 9As shown, the specific clock cycle can be the D8 clock cycle of the second set of clock cycles, that is, the specific clock cycle can be the second D8 clock cycle. Then, the consumable chip 21 can send a first data signal to the image forming apparatus 1 during the first half of the second D8 clock cycle; and not send the first data signal to the image forming apparatus 1 during the second half of the second D8 clock cycle. As an optional solution, the first data signal can be a high voltage. In this embodiment, if the consumable chip 21 can send the first data signal to the image forming apparatus 1 during the first half of the specific clock cycle, it indicates that the consumable chip 21 has been successfully installed. It should be noted that different colored consumable cartridges respond to different specific clock cycles. The embodiments of this application mainly select consumable cartridges that respond to the image forming apparatus 1 during the D8 clock cycle. The response to the image forming apparatus during different specific clock cycles depends on the instruction ID sent by the image forming apparatus to the consumable cartridge. Different instruction IDs correspond to different specific clock cycles for the consumable cartridges. Of course, it can also respond to the image forming apparatus 1 during other specific clock cycles, such as D7.

[0104] like Figure 9 As shown, the specific clock cycle of the second set of clock cycles can be the D8 clock cycle of the second set of clock cycles, that is, the specific clock cycle can be the second D8 clock cycle. Then the consumable chip 21 can be used to adjust the clock signal within the second D8 cycle.

[0105] As an alternative, such as Figure 9 As shown, the consumable chip 21 can pull the first clock to the third clock within a specific clock cycle, thereby pulling the clock signal from the original first clock to the third clock in the first half of the second D8 clock cycle. Pulling refers to the consumable chip 21 interfering with the clock signal sent by the image forming apparatus 1. It should be noted that when the consumable chip 21 does not interfere with the clock signal sent by the image forming apparatus 1, the clock signal sent by the image forming apparatus 1 to the consumable chip 21 consists of a first clock and a second clock that alternate between low and high voltages. The first clock is low voltage, and the second clock is high voltage; that is, the clock signal is formed by alternating and repeating low and high voltages. For example, when the first half of the second D8 clock cycle arrives, the signal received by the consumable chip 21 from the image forming apparatus 1 is the first clock. Therefore, the consumable chip 21 pulls the first clock to the third clock in the first half of the second D8 cycle. Specifically, since the first clock is at a low voltage, the consumable chip 21 pulls the first clock up to the third clock during the first half of the second D8 cycle. The voltage of the third clock is greater than that of the first clock, thereby achieving the regulation of the clock signal.

[0106] In this embodiment of the application, if the consumable chip 21 pulls the first clock to the third clock, it indicates that the clock signal can be adjusted, and the consumable chip is successfully installed, thereby proving that the chip is successfully installed through the consumable chip side.

[0107] As an alternative, such as Figure 9 As shown, the consumable chip 21 can pull the second clock to the fourth clock, thereby causing the clock signal to be pulled from the original second clock to the fourth clock during the latter half of the second D8 clock cycle. The voltage of the third clock is greater than or equal to the voltage of the fourth clock. The voltage of the third clock can be equal to the voltage of the second clock, and the voltage of the fourth clock can also be equal to the voltage of the second clock. "Pulling" refers to the consumable chip 21 interfering with the clock signal sent by the image forming apparatus 1. For example, when the latter half of the second D8 clock cycle arrives, if the signal received by the consumable chip 21 from the image forming apparatus 1 is the second clock, then the consumable chip 21 will pull the second clock to the fourth clock during the latter half of the second D8 cycle. Specifically, since the second clock is a high voltage, the consumable chip 21 will pull the second clock down to the fourth clock during the latter half of the second D8 cycle, making the voltage of the second clock greater than the voltage of the fourth clock, thus achieving adjustment of the clock signal.

[0108] The first clock corresponding to the third clock can be earlier in time than the second clock corresponding to the fourth clock.

[0109] In this embodiment, if the consumable chip 21 pulls the second clock to the fourth clock, it further indicates that the clock signal can be adjusted and the consumable chip is successfully installed. This allows the consumable chip to be proven to be successfully installed again from the consumable chip side, preventing the consumable chip from shifting after the first successful adjustment of the clock signal, which would affect subsequent printing and other operations.

[0110] like Figure 7 and Figure 8 As shown, the interface module 20 is used to receive the clock signal sent by the image forming apparatus 1; the control module 2133 is used to adjust the clock signal in response to the first instruction sent by the image forming apparatus 1 after the interface module 20 receives the first instruction.

[0111] As an alternative, the interface module 20 is also used to send a first data signal to the image forming apparatus 1.

[0112] In this embodiment of the application, the consumable chip 21 is used to pull up the second clock when the first clock of the clock signal is at a low voltage; and / or, to pull down the second clock when the second clock of the clock signal is at a high voltage.

[0113] The consumable chip 21 can pull up the second clock when the first clock signal is low voltage, and / or pull down the second clock when the second clock signal is high voltage, indicating that the consumable chip can adjust the clock signal and the chip is successfully installed, thus proving the successful installation of the chip through the consumable chip side.

[0114] The consumable chip 21 is used to pull up the first clock for the first cycle and pull down the second clock.

[0115] The consumable chip 21 is used to pull down the second clock when the timing module 2131 starts timing from the pull-up action to the end of the first cycle. In this case, the timing module 2131 starts timing from the pull-up action to the end of the first cycle, and then the consumable chip 21 pulls down the second clock.

[0116] For example, such as Figure 9 As shown, the first cycle is half a cycle of a specific clock cycle, and the specific clock cycle is the second D8 clock cycle. Therefore, the first cycle is half a cycle of the second D8 clock cycle, for example, the first half cycle. When the consumable chip 21 pulls up the first clock for the first half cycle of the second D8 clock cycle, it pulls down the second clock. However, the consumable chip 21 can also pull down the second clock during the second half cycle of the second D8 clock cycle.

[0117] The control module 2133 is specifically used to pull the first clock signal within a specific clock cycle to the third clock signal, so that in the first half of the second D8 clock cycle, the clock signal is pulled from the original first clock signal to the third clock signal. "Pulling" refers to the control module 2133 interfering with the clock signal sent by the image forming apparatus 1. For example, when the first half of the second D8 clock cycle arrives, if the interface module 20 receives the first clock signal sent by the image forming apparatus 1, the control module 2133 will pull the first clock signal to the third clock signal.

[0118] As an optional solution, the control module 2133 pulls the first clock signal up to a third clock signal, where the voltage of the third clock signal is greater than the voltage of the first clock signal, thereby regulating the clock signal. Figure 8 As shown, the first resistor R1 is used to make the signal of the first node N1 the third clock when the first switch S1 is closed and the second switch S2 is open. The control module 2133 controls the first switch S1 to close and the second switch S2 to open. At this time, the first node N1 is connected to the high voltage terminal VCC through the first resistor R1, so that the signal of the first node N1 is the third clock. This realizes that the control module 2133 pulls the first clock to the third clock in the first half of the second D8 clock cycle.

[0119] In this embodiment of the application, if the control module 2133 pulls the first clock within a specific clock cycle to the third clock, it indicates that the clock signal can be adjusted and the consumable chip is successfully installed, thereby realizing the proof of successful chip installation through the consumable chip side.

[0120] Specifically, control module 2133 pulls the second clock signal to the fourth clock signal, thereby causing the clock signal to be pulled from the original second clock signal to the fourth clock signal during the latter half of the second D8 clock cycle. "Pulling" refers to the consumable chip 21 interfering with the clock signal sent by the image forming apparatus 1. For example, if the interface module 20 receives the second clock signal from the image forming apparatus 1 during the latter half of the second D8 clock cycle, then control module 2133 will pull the second clock signal to the fourth clock signal during the latter half of the second D8 clock cycle.

[0121] As an optional solution, the control module 2133 pulls down the second clock to the fourth clock during the first half of the second D8 clock cycle, from the start of the pull-up action of the timing module 2131. The voltage of the second clock is greater than the voltage of the fourth clock, thus achieving adjustment of the clock signal. For example... Figure 8 As shown, the second resistor R2 is used to make the signal of the first node N1 the fourth clock when the first switch S1 is open and the second switch S2 is closed. When the timing module 2131 starts timing from the pull-up action to the first half of the second D8 clock cycle, the control module 2133 controls the second switch S2 to close and the first switch S1 to open. At this time, the first node N1 is connected to the ground terminal GND through the second resistor R2, so that the signal of the first node N1 is the fourth clock. This realizes that the control module 2133 pulls the second clock down to the fourth clock in the second half of the second D8 clock cycle.

[0122] In this embodiment of the application, if the control module 2133 pulls the second clock to the fourth clock, it indicates that the clock signal can be adjusted, indicating that the consumable chip has been successfully installed, thereby realizing the proof of successful chip installation through the consumable chip side.

[0123] In this embodiment of the application, during the adjustment of the clock signal, the period of pulling up the first clock and the period of pulling down the second clock can be continuous or discontinuous.

[0124] As an alternative, such as Figure 9 As shown, when the first clock is at a low voltage, the consumable chip 21 pulls the first clock up to the third clock; when the timing module 2131 starts timing from the pull-up action to the first cycle, the consumable chip 21 pulls the second clock down to the fourth clock, and the voltage of the third clock is greater than or equal to the voltage of the fourth clock. For example, as... Figure 9As shown, when the consumable chip 21 pulls up the first clock for the first half of the second D8 clock cycle, it pulls down the second clock for the second half of the second D8 clock cycle. Therefore, the period of pulling up the first clock is the first half of the second D8 clock cycle, and the period of pulling down the second clock is the second half of the second D8 clock cycle. The periods of pulling up the first clock and pulling down the second clock are continuous.

[0125] As an alternative, the consumable chip 21 is used to pull down a second clock during a second cycle, which is half a cycle of other clock cycles, after the pull-up action of the first clock has lasted for a first cycle. Specifically, the consumable chip includes a timing module, and the consumable chip 21 is used to pull down the second clock during the second cycle, after the timing module 2131 has started timing from the start of the pull-up action. For example, as... Figure 9 As shown, the first cycle is half a cycle of a specific clock cycle, and the specific clock cycle is the second D8 clock cycle. Therefore, the first cycle is half a cycle of the second D8 clock cycle, and the second cycle can be half a cycle of the second D9 clock cycle. During the first half of the second D8 clock cycle, consumable chip 21 pulls the first clock up to the third clock. While the pull-up of the first clock continues for the first half of the second D8 clock cycle, during the second half of the second D9 clock cycle, consumable chip 21 pulls the second clock down to the fourth clock. Therefore, the period for pulling up the first clock is the first half of the second D8 clock cycle, and the period for pulling down the second clock is the second half of the second D9 clock cycle. The periods for pulling up the first clock and pulling down the second clock are discontinuous, and this situation is not specifically depicted.

[0126] As another alternative, the consumable chip 21 can adjust the clock signal in the first specific period and the second specific period of the same set of clock cycles. The first specific period can be a specific time period of half a cycle in the second D8 clock cycle. Specifically, the first specific period can be a part of the first half cycle of the second D8 clock cycle, or a part of the second half cycle of the second D8 clock cycle. The time period of pulling up the first clock and the time period of pulling down the second clock can be continuous or discontinuous. This case is not specifically shown.

[0127] As another optional solution, the consumable chip 21 can adjust the clock signal in the first and second clock cycles of two sets of clock cycles respectively. Specifically, the consumable chip 21 is used to pull down the second clock in a first specific cycle of the first set of clock cycles and pull up the first clock in a second specific cycle of the second set of clock cycles; or, the consumable chip 21 is used to pull up the first clock in a first specific cycle of the first set of clock cycles and pull down the second clock in a second specific cycle of the second set of clock cycles; or, the consumable chip includes at least two sets of clock cycles, and the consumable chip is used to pull up the first clock and pull down the second clock in the second set of clock cycles, wherein the first specific cycle and the second specific cycle are not continuous; for example, such as Figure 9 As shown, the first specific period of the first group of clock cycles can be the second half of the first D8 clock cycle, and the second specific period of the second group of clock cycles is the first half of the second D8 clock cycle. The consumable chip 21 can pull down the second clock in the second half of the first D8 clock cycle and pull up the first clock in the first half of the second D8 clock cycle. Therefore, the period for pulling down the second clock is the second half of the first D8 clock cycle, and the period for pulling up the first clock is the first half of the second D8 clock cycle. The periods for pulling up the first clock and pulling down the second clock are not continuous, and this case is not specifically drawn.

[0128] As another alternative, when the consumable chip pulls up the first clock and pulls down the second clock in the second clock cycle, the pull-up first clock occurs earlier than the pull-down second clock. The pull-up first clock and pull-down second clock occur within one clock cycle or within two consecutive clock cycles.

[0129] As another alternative, the timing of adjusting the second clock by the consumable chip 21 can be earlier than the timing of adjusting the first clock.

[0130] In this embodiment, the control module 2133 of the consumable chip 21 can set the pull-up amplitude of the first clock and the pull-down amplitude of the second clock as needed. For example... Figure 8 As shown, for example, the pull-up amplitude of the first clock can be controlled by controlling the resistance value of the first resistor R1; and the pull-down amplitude of the second clock can be controlled by controlling the resistance value of the second resistor R2.

[0131] As an alternative, the voltage of the third clock is equal to the voltage of the second clock, and the voltage of the fourth clock is equal to the voltage of the first clock. Figure 10 This is a second communication timing diagram of the image forming apparatus and consumable chip provided in the embodiments of this application, such as... Figure 10As shown, when the control module 2133 pulls the first clock up to the third clock, the pull-up amplitude is L1, so that the voltage of the third clock after the pull-up is equal to the voltage of the second clock. In this case, the first resistor R1 can make the clock of the first node N1 reach the high voltage of the high voltage terminal VCC, that is, the third clock is the high voltage of the high voltage terminal VCC. When the control module 2133 pulls the second clock down to the fourth clock, the pull-down amplitude is L2, so that the voltage of the fourth clock after the pull-down is equal to the voltage of the first clock. In this case, the second resistor R2 can make the clock of the first node N1 reach the low voltage of the ground terminal GND, that is, the fourth clock is the low voltage of the ground terminal GND. Figure 10 As shown, the amplitude of the pull-up is equal to the amplitude of the pull-down, i.e., L1=L2, so that the voltage of the third clock is equal to the voltage of the second clock and the voltage of the fourth clock is equal to the voltage of the first clock. By controlling the amplitude of the pull-up and pull-down to be consistent, the first resistor R1 and the second resistor R2 can be selected with the same resistance value, thereby reducing the complexity of the circuit design.

[0132] As an alternative, the voltage of the third clock is equal to the voltage of the fourth clock, but the voltage of the third clock is less than the voltage of the second clock. Figure 11 This is a third communication timing diagram of the image forming apparatus and consumable chip provided in the embodiments of this application, such as... Figure 11 As shown, when control module 2133 pulls the first clock up to the third clock, the pull-up amplitude is L1. In this case, the first resistor R1 ensures that the clock signal of the first node N1 is between the high voltage of the high voltage terminal VCC and the low voltage of the ground terminal GND, that is, the third clock is between the high voltage of the high voltage terminal VCC and the low voltage of the ground terminal GND. When control module 2133 pulls the second clock down to the fourth clock, the pull-down amplitude is L2. In this case, the second resistor R2 ensures that the clock signal of the first node N1 is between the low voltage of the ground terminal GND and the high voltage of the high voltage terminal VCC, that is, the fourth clock is between the low voltage of the ground terminal GND and the high voltage of the high voltage terminal VCC. Figure 11 As shown, the voltage of the third clock is equal to the voltage of the fourth clock, ensuring that the clock signal output by the consumable chip 21 remains consistent with the voltage of the fourth clock. Figure 10 Compared to the embodiment shown, the clock port of the image forming apparatus 1 can be better protected.

[0133] As another alternative, the voltage of the third clock is greater than the voltage of the fourth clock, and the voltage of the third clock is less than or equal to the voltage of the second clock. Figure 12 This is a fourth communication timing diagram of the image forming apparatus and consumable chip provided in the embodiments of this application, such as... Figure 12As shown, when control module 2133 pulls the first clock up to the third clock, the pull-up amplitude is L1. In this case, the first resistor R1 ensures that the clock signal of the first node N1 is between the high voltage of the high voltage terminal VCC and the low voltage of the ground terminal GND, that is, the third clock is between the high voltage of the high voltage terminal VCC and the low voltage of the ground terminal GND. When control module 2133 pulls the second clock down to the fourth clock, the pull-down amplitude is L2. In this case, the second resistor R2 ensures that the clock of the first node N1 is between the low voltage of the ground terminal GND and the high voltage of the high voltage terminal VCC, that is, the fourth clock is between the low voltage of the ground terminal GND and the high voltage of the high voltage terminal VCC. Figure 12 As shown, the voltage of the third clock is lower than the voltage of the second clock, but higher than the voltage of the fourth clock. This causes a stepped change in the voltage of the clock signal output by the consumable chip 21, resulting in variations in the output clock signal. This allows for better differentiation between the early and late halves of each clock cycle. In practical applications, the voltage of the third clock can also be equal to the voltage of the second clock; this case is not specifically illustrated.

[0134] This application also provides a consumable chip for mounting in a consumable cartridge, which is detachably mounted in an image forming apparatus. The image forming apparatus sends a clock signal to the consumable chip; the consumable chip, upon receiving a first instruction from the image forming apparatus, adjusts the clock signal in response to the first instruction by sending a first data signal to the image forming apparatus. The first data signal is sent to the image forming apparatus for at least a specific time period, the length of which is less than or equal to half a clock cycle.

[0135] The first data signal can appear in the first half of a specific clock cycle, but not in the second half. For example... Figure 9 As shown, a specific clock cycle is the second D8 clock cycle. The first half of the specific clock cycle is the first half of the second D8 clock cycle, and the second half of the specific clock cycle is the second half of the second D8 clock cycle. Therefore, the first data signal appears in the first half of the second D8 clock cycle and not in the second half of the second D8 clock cycle. The first data signal is a high voltage. For a description of the pull-out configuration of the first and second clocks in this embodiment, please refer to the above... Figure 9 to Figure 12 The description of the illustrated embodiment will not be repeated here. Of course, the first half-cycle and the second half-cycle are relative, and it can also occur in the second half-cycle of a certain clock.

[0136] It should be noted that, through the above description and variations, many methods should fall within the protection scope of this invention. For example, when adjusting the clock, only one clock can be adjusted, two clocks can be adjusted simultaneously, three clocks can be adjusted, or even multiple clocks can be adjusted simultaneously. The adjusted clocks can be continuous or discontinuous. This clock adjustment method is preferably the time period used by the image forming apparatus to detect whether the consumable box is successfully installed, such as half a cycle of D8 in the first set of clock cycles as described above, and the entire cycle of D8 in the second set of clock cycles. If the clock sent by the image forming apparatus is a ...high...low high... signal, then through the embodiments of this application, the adjusted clock signal can be ...high...high high..., ...high...high high..., ...high...low low..., any adjustment characteristic clock cycle can be a high or low level, or a combination of two or three, such as the adjusted clock signal can be ...high...high low..., ...high...low lower... Here, high and low are relative. High indicates that the signal voltage is higher than low. Therefore, it is not an absolute limitation. For example, the high voltage must be 3.3V, and the low voltage must be 0V. The terms "high" and "high" are relative. For example, 3.3V, 2.5V, and 1.8V can be described as "high" or "low".

[0137] Furthermore, when sending the first data signal, especially when the specific clock is at the first level (i.e., low level), the voltage of the first level clock is pulled up. There are many ways to send the first data signal to the image forming apparatus, such as sending the first data for the entire cycle when the first level is pulled up, sending the first data when the first level is pulled up, or sending the first data signal for a certain period of time after the first level is pulled up. The transmission time of the first data signal must be detectable by the image forming apparatus so that the image forming apparatus can also synchronously detect the installation of the consumable box, preventing the consumable chip proof chip installation success from affecting the image forming apparatus's detection and installation of the consumable box.

[0138] Various modifications should be within the scope of protection of this application without departing from the spirit of the invention.

[0139] In this embodiment of the application, the image forming apparatus sends a clock signal to the consumable chip. When the consumable chip receives a first instruction from the image forming apparatus, it can adjust the clock signal in response to the first instruction and send a first data signal to the image forming apparatus, indicating that the chip has been successfully installed. This enables the consumable chip to be proven to have been successfully installed.

[0140] In this embodiment of the application, during the installation and testing of the consumable chip by the image forming apparatus, the consumable chip adjusts its clock signal based on sending a first data signal to the image forming apparatus.

[0141] Figure 13AThis is a schematic diagram of the structure of the first plane of the second type of consumable chip provided in the embodiments of this application. Figure 13B for Figure 13A A schematic diagram of the second plane of the consumable chip is shown below. Figure 13A and Figure 13B As shown, the consumable chip 21 may include a new consumable substrate 40 and a data terminal 2101, a clock terminal 2102, and a new wafer 41 disposed on the new consumable substrate 40. The data terminal 2101 and the clock terminal 2102 are electrically connected to the new wafer 41. When the consumable cartridge is mounted in an image forming apparatus, the data terminal 2101 and the clock terminal 2102 contact the contact pins of the image forming apparatus to form an electrical connection. The data terminal 2101 is used to transmit data signals, and the clock terminal 2102 is used to transmit clock signals.

[0142] The first plane can be the front, therefore Figure 13A The front side of the consumable chip 21 is shown; the second plane can be the back side, therefore Figure 13B The back of consumable chip 21 is shown. (As shown) Figure 13A As shown, data terminal 2101 and clock terminal 2102 are disposed on the front side of the new consumable substrate 40; as Figure 13B As shown, the second plane may include a new wafer 41, which is disposed on the back side of the new consumable substrate 40. Of course, the front side of the new consumable substrate 40 may include multiple terminals, such as data terminals, clock terminals, and one or more of power terminals, chip select terminals, and ground terminals.

[0143] Figure 14A This is a schematic diagram of the first plane of the third type of consumable chip provided in the embodiments of this application. Figure 14B for Figure 14A A schematic diagram of the second plane of the consumable chip is shown below. Figure 14A and Figure 14B As shown, the consumable chip 21 may include: an original consumable substrate 42, a new wafer 41 disposed on the original consumable substrate 42, and a plurality of functional terminals, the functional terminals being electrically connected to the new wafer 41. When the consumable cartridge is installed in the image forming apparatus, the functional terminals contact the contact pins of the image forming apparatus to form an electrical connection.

[0144] The first plane can be the front, therefore Figure 14A The front side of the consumable chip 21 is shown; the second plane can be the back side, therefore Figure 14B The back of consumable chip 21 is shown. (As shown) Figure 14A As shown, multiple terminals are disposed on the front side of the original consumable substrate 42. For example, the multiple terminals may include a data terminal SDA, a chip select terminal RST, a clock terminal SCL, a power supply terminal VCC, and a ground terminal GND; Figure 14BAs shown, the second plane may include a brand new wafer 41, which is disposed on the back side of the original consumable substrate 42.

[0145] In this embodiment, the consumable chip 21 can be a recycled original consumable chip. The original wafer on the original consumable substrate of the original consumable chip is removed and replaced with a brand new wafer 41 to form a new consumable chip 21.

[0146] Figure 15A-15C This is a schematic diagram of the structure of the fourth type of consumable chip provided in this application embodiment. The consumable chip 21 may include: an original consumable substrate 43, a new wafer 41 disposed on the original consumable substrate 43, and a plurality of terminals. The plurality of terminals includes multiple active terminals, each of which is electrically connected to the new wafer 41. For example, in this application embodiment, the active terminals include the original consumable substrate 43's data terminal SDA, chip select terminal RST, clock terminal SCL, power supply terminal VCC, and ground terminal GND. The consumable chip 21 also includes a flexible circuit board 50, which is disposed on the original consumable substrate 43, such as... Figure 15A As shown, the flexible circuit board 50 can cover or partially cover the original consumable substrate 43. When the consumable box is installed in the image forming apparatus, at least one active terminal is not positioned corresponding to the contact pin of the image forming apparatus. The flexible circuit board contacts the contact pin of the image forming apparatus so that at least one active terminal is electrically connected to the image forming apparatus through the flexible circuit board.

[0147] In this embodiment, the consumable chip 21 can be a recycled original consumable chip. The original wafer on the original consumable substrate of the original consumable chip is removed and replaced with a brand new wafer 41 to form a new consumable chip 21.

[0148] Figure 16A This is a schematic diagram of the structure of the fifth type of consumable chip provided in the embodiments of this application. Figure 16B for Figure 16A A schematic diagram of the structure of the second plane. Figure 16C for Figure 16A A schematic diagram of the structure of a flexible circuit board. (Example) Figure 16A and Figure 16B As shown, the consumable chip 21 may include: an original consumable substrate 43 and a plurality of terminals disposed on the original consumable substrate 43, the plurality of terminals including multiple functional terminals. When the consumable cartridge is mounted in an image forming apparatus, each functional terminal contacts a contact pin of the image forming apparatus to form an electrical connection. The consumable chip 21 also includes a flexible circuit board 51 disposed on the original consumable substrate 43, and a new wafer 41 disposed on the flexible circuit board 51. Each functional terminal is electrically connected to the new wafer 41. The new wafer 41 is used to control the functional terminals to implement the set signal processing functions.

[0149] likeFigure 16B As shown, the consumable chip 21 also includes an original wafer 44 disposed on the original consumable substrate 43.

[0150] Figure 16A The first plane of the consumable chip 21 is shown. The first plane can be the front side. Multiple terminals are disposed on the first plane of the consumable chip 21, that is, multiple terminals are disposed on the front side of the consumable chip 21. Figure 16B The second plane of the consumable chip 21 is shown. This second plane can be the back side. The original wafer 44 is disposed on the second plane of the consumable chip 21, that is: the original wafer 44 is disposed on the back side of the original consumable substrate 43.

[0151] like Figure 16A As shown, the original consumable substrate 43 includes multiple terminals, which may include a data terminal SDA, a chip select terminal RST, a clock terminal SCL, a power terminal VCC, a ground terminal GND, short-circuit detection terminals NC1 and NC2, and high-voltage receiving terminals A and B. The short-circuit detection terminals NC1 and NC2 are used to detect short circuits, and the high-voltage receiving terminals A and B are used to receive high voltage. Among these multiple terminals, the terminals that correspond to the contacts of the image forming apparatus when the consumable cartridge is installed in the image forming apparatus are defined as functional terminals. The contacts of the image forming apparatus contact the terminals on the original consumable substrate 43. For example, the multiple functional terminals may include a short-circuit detection terminal NC1, a chip select terminal RST, a high-voltage receiving terminal A, a power terminal VCC, and a high-voltage receiving terminal B. The SDA, SCL, RST, VCC, and GND contacts of the image forming apparatus are respectively in contact with the short-circuit detection terminal NC1, the high-voltage receiving terminal A, the chip select terminal RST, the power terminal VCC, and the high-voltage receiving terminal B.

[0152] The new wafer 41 is used to control the signal processing functions set by the function terminals. For example... Figure 16AAs shown, when the functional terminal is the short-circuit detection terminal NC1, the signal processing function set for the short-circuit detection terminal NC1 is the signal processing function of the data terminal SDA. In this case, the new wafer 41 is used to control the short-circuit detection terminal NC1 to implement the signal processing function of the data terminal SDA, and the signal processing function of the data terminal SDA is to transmit a data signal. When the functional terminal is the chip select terminal RST, the signal processing function set for the chip select terminal RST is the signal processing function of the chip select terminal RST itself. In this case, the new wafer 41 is used to control the chip select terminal RST to implement the signal processing function of the chip select terminal RST, and the signal processing function of the segment terminal RST is to transmit a chip select signal. When the functional terminal is the high-voltage receiving terminal A, the signal processing function set for the high-voltage receiving terminal A is the signal processing function of the clock terminal SCL. The new wafer 41 is used to control the high-voltage receiving terminal A to realize the signal processing function of the clock terminal SCL. The signal processing function of the clock terminal SCL is to send a clock signal. The functional terminal is the power supply terminal VCC. The signal processing function set for the power supply terminal VCC is the signal processing function of the power supply terminal VCC itself. The new wafer 41 is used to control the power supply terminal VCC to realize the signal processing function of the power supply terminal VCC. The signal processing function of the power supply terminal VCC is to provide the working voltage. The functional terminal is the high-voltage receiving terminal B. The signal processing function set for the high-voltage receiving terminal B is the signal processing function of the ground terminal GND. The new wafer 41 is used to control the high-voltage receiving terminal B to realize the signal processing function of the ground terminal GND. The signal processing function of the ground terminal GND is to provide a reference low voltage.

[0153] like Figure 16A to Figure 16C As shown, the flexible circuit board 51 includes a first structural portion 510 and a second structural portion 511 connected to the first structural portion 510. The first structural portion 510 is provided with contact portions corresponding to the positions of each functional terminal. A new wafer 41 is disposed on the second structural portion 511. The first structural portion 510 is disposed on the side of the original consumable substrate 43 where the terminals are provided. The contact portions are used to contact the corresponding functional terminals, and the contact portions are also electrically connected to the new wafer, so that the functional terminals are electrically connected to the new wafer 41 through the contact portions. For example, the contact portions can achieve contact with the corresponding functional terminals by soldering.

[0154] like Figure 16A and Figure 16CAs shown, the contact portion corresponding to the short-circuit detection terminal NC1 is the first contact portion C1, the contact portion corresponding to the chip select terminal RST is the second contact portion C2, the contact portion corresponding to the high-voltage receiving terminal A is the third contact portion C3, the contact portion corresponding to the power supply terminal VCC is the fourth contact portion C4, and the contact portion corresponding to the high-voltage receiving terminal B is the fifth contact portion C5. The first structural part 510 is provided with the first contact portion C1, the second contact portion C2, the third contact portion C3, the fourth contact portion C4, and the fifth contact portion C5. The first contact portion C1 is located at the position corresponding to the short-circuit detection terminal NC1 and makes contact; the second contact portion C2 is located at the position corresponding to the chip select terminal RST and makes contact; the third contact portion C3 is located at the position corresponding to the high-voltage receiving terminal A and makes contact; the fourth contact portion C4 is located at the position corresponding to the power supply terminal VCC and makes contact; and the fifth contact portion C5 is located at the position corresponding to the high-voltage receiving terminal B and makes contact.

[0155] like Figure 16B and Figure 16C As shown, the second structural portion 511 is bent so that it is located on the side of the original consumable substrate 43 where the original wafer 44 is disposed. The bent second structural portion 511 reduces the area of ​​the consumable chip, thus facilitating its mounting on the consumable box. Of course, in practical applications, the second structural portion 511 may not be bent.

[0156] In this embodiment, the original wafer 44 is retained on the original consumable substrate 43 without replacing the original wafer 44. Instead, a new wafer 41 is set on the flexible circuit board 51, and the functional terminals are controlled through the new wafer 41.

[0157] In the embodiments of this application, Figure 13A to Figure 16C The consumable chip shown can be used to achieve the above. Figure 1 to Figure 12 The functions of the consumable chip shown.

[0158] This application provides a consumable box, which may include the consumable chip described in the above embodiments. For a detailed description of the consumable chip, please refer to the above... Figure 1 to Figure 16C The descriptions in the illustrated embodiments will not be repeated here.

[0159] This application provides a communication method, which is applied to the consumable chip in the above embodiments. For a detailed description, please refer to the above. Figure 1 to Figure 16C The descriptions in the illustrated embodiments will not be repeated here.

[0160] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A consumable chip, the consumable chip being mounted in a consumable cartridge, the consumable cartridge being detachably mounted in an image forming apparatus, the image forming apparatus sending a clock signal to the consumable chip, characterized in that, The consumable chip is used to adjust the clock signal in response to the first instruction sent by the image forming apparatus after receiving the first instruction; the clock signal includes a first clock and a second clock with alternating low and high voltages, wherein the voltage of the second clock is greater than the voltage of the first clock; the consumable chip is specifically used to pull the first clock to a third clock within a specific clock cycle; the consumable chip is also used to send a first data signal to the image forming apparatus during the clock signal adjustment phase, the first data signal being sent to the image forming apparatus at least when the first clock is pulled to the third clock.

2. The consumable chip according to claim 1, characterized in that, The consumable chip is specifically used to pull the second clock to the fourth clock within a specific clock cycle, wherein the voltage of the third clock is greater than or equal to the voltage of the fourth clock.

3. The consumable chip according to claim 2, characterized in that, The first clock that is pulled to the third clock is earlier in time than the second clock that is pulled to the fourth clock.

4. The consumable chip according to claim 1, characterized in that, The consumable chip is used to pull the first clock to the third clock during the first half of a specific clock cycle and send a first data signal to the image forming apparatus; and during the second half of the specific clock cycle, it does not send the first data signal to the image forming apparatus.

5. The consumable chip according to claim 1, characterized in that, The consumable chip is used to adjust the clock signal within a specific clock cycle of the second set of clock cycles in response to the first instruction.

6. The consumable chip according to claim 2, characterized in that, The voltage of the third clock is equal to the voltage of the second clock, and the voltage of the fourth clock is equal to the voltage of the first clock; or, The voltage of the third clock is equal to the voltage of the fourth clock, and the voltage of the third clock is less than the voltage of the second clock; or, The voltage of the third clock is greater than the voltage of the fourth clock, and the voltage of the third clock is less than or equal to the voltage of the second clock.

7. The consumable chip according to any one of claims 1 to 6, characterized in that, The first data signal is a high voltage.

8. The consumable chip according to claim 7, characterized in that, The first data signal is transmitted to the image forming apparatus for at least a specific time period, the length of which is less than or equal to half a clock cycle.

9. A consumable chip, characterized in that, The consumable chip is mounted in a consumable cartridge, which is detachably mounted in the image forming apparatus. The image forming apparatus sends a clock signal to the consumable chip. The consumable chip is configured to, upon receiving a first instruction from the image forming apparatus, in response to the first instruction, pull up the first clock signal when the first clock of the clock signal is at a low voltage within a specific clock cycle; the consumable chip is configured to send a first data signal to the image forming apparatus during the pull-up phase of the first clock; and / or, upon receiving a first instruction from the image forming apparatus, in response to the first instruction, pull down the second clock signal when the second clock of the clock signal is at a high voltage within a specific clock cycle; the consumable chip is configured to send the first data signal to the image forming apparatus before or after the second clock is pulled down.

10. The consumable chip according to claim 9, characterized in that, The consumable chip is used to pull down the second clock when the action of pulling up the first clock lasts for a first cycle, wherein the first cycle is half a cycle of a specific clock cycle, or the first cycle is a portion of a half cycle of a specific clock cycle.

11. The consumable chip according to claim 10, characterized in that, The consumable chip includes a timing module; The consumable chip is used to pull down the second clock when the timing module starts timing from the pull-up action to the first cycle.

12. The consumable chip according to claim 9, characterized in that, The consumable chip is used to pull up the first clock for a first cycle, and then pull down the second clock for a second cycle that is set at an interval from the first cycle, wherein the second cycle is half a cycle of other clock cycles.

13. The consumable chip according to claim 12, characterized in that, The consumable chip includes a timing module; the consumable chip is used to pull down the second clock when the timing module starts timing from the pull-up action to the start of the second cycle.

14. The consumable chip according to claim 9, characterized in that, The consumable chip is used to pull down the second clock in a first specific period of the first clock cycle of the first set of two clock cycles, and to pull up the first clock in a second specific period of the second set of clock cycles; or... The consumable chip is used to pull up the first clock in a first specific period of the first clock cycle of the first set of two clock cycles, and to pull down the second clock in a second specific period of the second set of clock cycles; or... The consumable chip includes at least two sets of clock cycles, and the consumable chip is used to pull up the first clock and pull down the second clock in the second set of clock cycles.

15. The consumable chip according to claim 14, characterized in that, When the consumable chip pulls up the first clock and pulls down the second clock in the second clock cycle, the time to pull up the first clock is earlier than the time to pull down the second clock.

16. The consumable chip according to claim 15, characterized in that, The pull-up of the first clock and the pull-down of the second clock occur within one clock cycle or within two consecutive clock cycles.

17. The consumable chip according to any one of claims 9 to 16, characterized in that, The clock signal includes a first clock and a second clock that alternate between low and high voltages, wherein the voltage of the second clock is greater than the voltage of the first clock. The consumable chip is specifically used to pull up the first clock to the third clock. The consumable chip is specifically used to pull down the second clock to the fourth clock; The voltage of the third clock is greater than or equal to the voltage of the fourth clock.

18. The consumable chip according to claim 17, characterized in that, The consumable chip includes a control module, which includes a first resistor, a first switch, a second resistor, and a second switch. The first resistor and the first switch are connected in series between a first voltage terminal and a first node, and the second resistor and the second switch are connected in series between the first node and the second voltage terminal. The first resistor is used to make the signal of the first node the third clock when the first switch is closed and the second switch is open. The second resistor is used to make the signal of the first node the fourth clock when the first switch is open and the second switch is closed.

19. A consumable chip, characterized in that, The consumable chip includes the consumable chip according to any one of claims 1 to 18; The consumable chip further includes: a brand new consumable substrate and data terminals, clock terminals and a brand new wafer disposed on the brand new consumable substrate, wherein the data terminals and the clock terminals are electrically connected to the brand new wafer; When the consumable cartridge is installed in the image forming apparatus, the data terminal and the clock terminal contact the contact pins of the image forming apparatus to form an electrical connection.

20. A consumable chip, characterized in that, The consumable chip includes the consumable chip according to any one of claims 1 to 18; The consumable chip also includes: an original consumable substrate, a brand new wafer disposed on the original consumable substrate, and a number of functional terminals, wherein the functional terminals are electrically connected to the brand new wafer; When the consumable cartridge is installed in the image forming apparatus, the functional terminal contacts the contact pin of the image forming apparatus to form an electrical connection.

21. A consumable chip, characterized in that, The consumable chip includes the consumable chip according to any one of claims 1 to 18; The consumable chip further includes: an original consumable substrate, a brand new wafer disposed on the original consumable substrate, and a plurality of terminals, wherein the plurality of terminals includes multiple effective terminals, and each of the effective terminals is electrically connected to the brand new wafer; The consumable chip further includes a flexible circuit board disposed on the original consumable substrate; when the consumable box is installed on the image forming apparatus, at least one of the effective terminals is not positioned corresponding to the contact pins of the image forming apparatus, and the flexible circuit board contacts the contact pins of the image forming apparatus so that at least one of the effective terminals is electrically connected to the image forming apparatus through the flexible circuit board.

22. A consumable chip, characterized in that, The consumable chip includes the consumable chip according to any one of claims 1 to 18; The consumable chip further includes: an original consumable substrate and a plurality of terminals disposed on the original consumable substrate, the plurality of terminals including multiple functional terminals; when the consumable box is installed in the image forming apparatus, each of the functional terminals contacts a contact pin of the image forming apparatus to form an electrical connection; The consumable chip further includes: a flexible circuit board, which is disposed on the original consumable substrate, and a brand new wafer is disposed on the flexible circuit board, and each of the functional terminals is electrically connected to the brand new wafer; The new wafer is used to control the functional terminals to implement the set signal processing functions.

23. A consumable box, characterized in that, include: The consumable chip according to any one of claims 1 to 22.

Images