Automatic test system for power driver chips

Abstract

The application discloses an automatic test system of a power driving chip, and particularly relates to the technical field of automatic test, which comprises a dynamic test control module, a multi-level parallel test module, an abnormal power detection module and a safety verification diagnosis module. The application is based on the cooperative work of a programmable electronic load and a digital signal processor, verifies the dynamic response capability of the chip under different working conditions, generates abnormal power data under extreme load conditions, synchronously collects the electric parameters and thermal parameters of the chip, analyzes the correlation between abnormal power performance and temperature, distinguishes the temperature rise difference caused by power-off protection and electric leakage, extracts and classifies abnormal power waveforms to distinguish the power-off protection and electric leakage events, quantifies the influence degree of environmental charge interference, finally simulates the response effectiveness of the chip protection circuit under a strong charge environment caused by electric leakage, calibrates according to the collected correction value, and thus improves the automation degree of the system and enhances the test robustness.

Description

Technical Field

[0001] This invention relates to the field of automated testing technology, and more specifically, to an automated testing system for power drive chips. Background Technology

[0002] Power drive chips are widely used in electric vehicles, industrial motors, power conversion and other fields. The driving capability, dynamic response, voltage and current withstand characteristics and reliability of the chip directly affect the system safety and energy efficiency. Therefore, power drive chips often need to undergo a rigorous testing process.

[0003] Traditional automatic testing systems for power drive chips mainly use programmable power supplies and signal generators to generate the required voltage and current waveforms, which are then applied to the chip's input pins to simulate actual operating conditions, such as switching actions and load changes. At the same time, devices such as oscilloscopes, multimeters, and power analyzers capture key parameters of the chip's output, such as on-resistance R, switching time, and power consumption. The test process is then controlled by an industrial control computer or PLC, and the collected data is compared with preset thresholds to determine the chip's qualification.

[0004] However, with the evolution of technology and the continuous improvement of industry demands, the problems of traditional automatic test systems for power drive chips have gradually become apparent. These problems include low test efficiency, insufficient dynamic performance, poor scalability and compatibility, thermal management defects, high power consumption without feedback, and limited fault coverage. These defects reduce work efficiency and increase production and testing costs. Therefore, the industry and the market need an automatic test system for power drive chips that meets their requirements. Summary of the Invention

[0005] To overcome the aforementioned deficiencies of the prior art, embodiments of the present invention provide an automated testing system for power drive chips. Based on the collaborative operation of a programmable electronic load and a digital signal processor, the system verifies the dynamic response capability of the chip under different operating conditions, generates abnormal power data under extreme load conditions, synchronously collects the chip's electrical and thermal parameters, analyzes the correlation between abnormal power performance and temperature, distinguishes the temperature rise difference caused by power-off protection and leakage, extracts and classifies abnormal power waveforms to differentiate between power-off protection and leakage events, quantifies the impact of environmental charge interference, and finally simulates the response effectiveness of the chip's protection circuit under a strong charge environment caused by leakage. The system is calibrated based on the collected correction values, thereby improving the system's automation level and enhancing test robustness, thus solving the problems mentioned in the background art.

[0006] To achieve the above objectives, the present invention provides the following technical solution:

[0007] An automated testing system for power driver chips includes the following modules:

[0008] The dynamic test control module works in collaboration with a programmable electronic load and a digital signal processor to simulate load characteristics in real-world scenarios, verify the chip's dynamic response capability under different operating conditions, and generate abnormal power data under extreme load conditions.

[0009] The multi-level parallel test module integrates a high-speed ADC (semiconductor integrated circuit), thermocouples and infrared thermal imagers to simultaneously acquire the chip's electrical and thermal parameters, analyze the correlation between abnormal power performance and temperature, and distinguish the temperature rise difference caused by power failure protection and leakage.

[0010] The abnormal power detection module extracts and classifies abnormal power waveforms, distinguishes between power outage protection and leakage events, and quantifies the impact of environmental charge interference.

[0011] The safety verification and diagnostic module uses a high-voltage pulse generator and a switch array to simulate a high-charge environment caused by leakage current and verify the effectiveness of the chip's protection circuit response. It also calibrates the circuit based on the collected correction values.

[0012] Specifically, in the dynamic test control module, to achieve a high degree of automation in the power chip testing system, a parameterized load model library is adopted. Based on chip specifications (such as withstand voltage and current rating), preset operating conditions (motor stall, battery reverse connection, etc.) are automatically matched. A digital signal processor (DSP) analyzes the equation parameters in real time, dynamically adjusting the electronic load mode without manual intervention. Automatic adjustment of the load current is achieved based on a PID algorithm. When a power anomaly is detected, the system automatically switches to fault analysis mode, performing automatic feature extraction, automatic model reasoning, and automatic result feedback. The algorithm endows the system with self-sensing, self-decision-making, and self-execution capabilities, fully leveraging its high speed, high precision, and repeatability. In practical use, due to factors such as equipment cost and the complexity of periodic testing, this invention is based on the normal operation of the power drive chip testing system under complex scenarios and relatively stable environmental conditions such as temperature and humidity. This may lead to abnormal operation at a certain testing moment.

[0013] The dynamic test control module mainly includes a programmable electronic load (supporting CC / CV / CR modes, switching rate ≥100A / μs), a high-speed DSP (TI C2000 series, 200MHz main frequency), and a high-precision current sensor (10MHz bandwidth, ±0.05% accuracy).

[0014] The stalled motor scenario is described using a nonlinear load characteristic equation, which can be described as follows: ,in The magnitude of the back electromotive force. Angular frequency, Where t is the impedance, i is the time, and L is the current. The load control signal is calculated in real time by the DSP and output.

[0015] Adjusting load current using a PID algorithm: ,in To control the output, the output current of the programmable electronic load is controlled to track the target waveform and minimize errors. Target current Dynamically adjust based on test cases The collected load current is input into the PID algorithm as a reference parameter. This is the error integral term, used to compensate for the zero drift of the current sensor caused by increased ambient temperature. The error differential term is used to predict the current fluctuation trend during sudden load changes. For proportional control coefficient, Integral control coefficient, Differential control coefficient;

[0016] The specific process involves setting the electronic load to CR mode (constant resistance mode) and initial resistance. Inductance L = 100μH, back electromotive force amplitude =50V, and configure the DSP to generate a sinusoidal modulation signal with a frequency of f=1kHz, which is then superimposed on the load control terminal;

[0017] Trigger chip drive signal (PWM duty cycle 50%), record load current and chip output voltage Sampling rate 1 MS / s;

[0018] At t=5ms, the load current is suddenly increased to 200% of the rated value to simulate a stall event, which recovers after 10μs.

[0019] Capture the current waveform using an oscilloscope to verify the load switching time. And ensure the overcurrent protection action time of the chip. ;

[0020] Meanwhile, during the actual execution of the dynamic test control module, weights are set according to the actual situation. For example, when the PID algorithm adjusts the load current, the proportional control is adjusted accordingly. Integral control Differential control The expert weighting method is adopted, which involves inviting experts in relevant fields to determine the weights of each indicator through professional opinion surveys and comprehensive evaluations. This ensures that the weight coefficients accurately reflect the importance of each indicator in the assessment of the impact of external light. In addition, methods such as the analytic hierarchy process (AHP) and fuzzy comprehensive evaluation can also be considered to determine the weight coefficients, ensuring their objectivity and scientific validity. These will not be elaborated upon here.

[0021] In the multi-level parallel test module, data information from a 16-bit high-speed ADC, miniature thermocouples, and an infrared thermal imager is acquired. FPGA is used to implement multi-channel trigger alignment, and the timing error model is as follows: ,in Let be the standard deviation of the clock jitter of the i-th channel. To compensate for the signal transmission path delay of the i-th channel, calibration is used to reduce the synchronization error of multi-channel signal acquisition. The synchronization error consists of the time error and path error in the timing error model, and the total error is no greater than 1ns;

[0022] Junction temperature calculated using the thermistor method : ,in, For chip junction temperature, For ambient temperature, , The thermistor power is t, where t is time and t is thermal resistance. Determined by chip packaging parameters;

[0023] In the multi-level parallel test module, the specific test process is as follows: a small current (1A) is applied under constant temperature conditions, and measurements are taken. Calculate the initial thermal resistance using thermocouple data. Run the chip to full load ( =20A), synchronous recording , Thermocouple temperature Infrared thermal images were collected by cutting off the power supply at t=10ms (simulating power failure protection) and applying high voltage between the chip pins (simulating leakage current), and collecting parameter changes at the moment of power failure and after power recovery.

[0024] In a multi-level parallel testing module, when plummeted to 0 and An exponential decrease indicates that the voltage rapidly returns to zero and the temperature continues to drop, which is normal protection.

[0025] when There is residual voltage and Continued to rise ( If the voltage does not return to zero and the temperature continues to rise, it can be determined that leakage is causing charge accumulation.

[0026] In the abnormal power detection module, wavelet transform is used to extract high-frequency components of the transient signal. Specifically, two types of abnormalities are injected 100 times each (50 times for power failure protection and 50 times for leakage current), and waveform data is collected and labeled. We selected the Dobessi 4 wavelet basis and decomposed it using scales a = 1 to 5. The larger the value of a, the wider the wavelet, corresponding to low-frequency components; the smaller the value of a, the narrower the wavelet, corresponding to high-frequency components. The basic wavelet of the function, Let b be the original signal input at time t, and b be the translation function, representing the scaling function. In the support region, a support vector machine classifier is constructed. The dataset is divided into training and test sets in a 7:3 ratio. Grid search is used to optimize the SVM hyperparameters, with radial basis function (RBF) as the kernel function. ,in, For kernel function, The bandwidth parameter of the Gaussian kernel controls the rate at which the similarity between samples decays. The input feature vector includes the voltage drop slope. Residual voltage V, temperature rise rate The system collects abnormal event data in real time, extracts features, and inputs them into an SVM classifier. It outputs class probabilities P(power outage) and P(leakage). If leakage is identified, the environmental charge density is calculated. : Where E is the voltage between chip pins And the spacing d is determined , The vacuum permittivity is set to a threshold value of 1. If the limit is exceeded, an alarm will be triggered;

[0027] In the safety verification and diagnostic module, data information from the high-voltage pulse generator and the RF relay matrix is ​​collected. The leakage current scenario is modeled as a transient high-voltage pulse superimposed with a DC bias. The high-voltage pulse is applied to the chip's power supply pins, and the voltage between the chip pins is obtained. : ,set up The initial time, Pulse amplitude pulse width =100ns, recorded using a high-speed oscilloscope (≥1GHz bandwidth) Measure the trigger time of the protection circuit If the chip does not respond or By locating the failure point (such as gate oxide breakdown) through thermal imaging, the protection action delay time is defined. ,Require (Complies with ISO 26262 ASIL Class D standard);

[0028] In the security verification and diagnostic module, the correction value for each module under similar test scenarios is calculated using an objective function, expressed as follows: ,in, , , and These are the measured values ​​for each item. , , and For project error terms, , , , These are the factor adjustment coefficients for each project, and , , , All are greater than 0;

[0029] In the safety verification and diagnostic module, when the correction value change is less than the set correction threshold, it indicates that the error value generated in the automatic test system of the power drive chip is small, and the automatic loop detection process continues.

[0030] When the correction value change is greater than or equal to the set correction threshold, it indicates that the error value generated in the automatic test system of the power drive chip is large, and recalibration is required, and the automatic loop detection process should be paused.

[0031] The technical effects and advantages of this invention are as follows:

[0032] This invention is based on the collaborative operation of a programmable electronic load and a digital signal processor to verify the dynamic response capability of a chip under different operating conditions, generate abnormal power data under extreme load conditions, synchronously collect the chip's electrical and thermal parameters, analyze the correlation between abnormal power performance and temperature, distinguish the temperature rise difference caused by power failure protection and leakage, extract and classify abnormal power waveforms to distinguish between power failure protection and leakage events, quantify the impact of environmental charge interference, and finally simulate the response effectiveness of the chip's protection circuit under a strong charge environment caused by leakage. The circuit is calibrated based on the collected correction values, thereby improving the system's automation level and enhancing test robustness, thus solving the problems mentioned in the background art. Attached Figure Description

[0033] Figure 1 This is a flowchart of the automatic testing system for the power drive chip of the present invention. Detailed Implementation

[0034] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0035] The automatic testing system for power drive chips of this invention is based on the collaborative operation of a programmable electronic load and a digital signal processor. It verifies the dynamic response capability of the chip under different operating conditions, generates abnormal power data under extreme load conditions, synchronously collects the chip's electrical and thermal parameters, analyzes the correlation between abnormal power performance and temperature, distinguishes the temperature rise difference caused by power failure protection and leakage, extracts and classifies abnormal power waveforms to differentiate between power failure protection and leakage events, quantifies the impact of environmental charge interference, and finally simulates the response effectiveness of the chip's protection circuit under a strong charge environment caused by leakage. The system is calibrated based on the collected correction values, thereby improving the system's automation level and enhancing test robustness to solve the problems mentioned in the background art.

[0036] Example 1

[0037] like Figure 1 As shown, the steps of the automated testing system for power driver chips are as follows:

[0038] An automated testing system for power driver chips includes the following modules:

[0039] The dynamic test control module works in collaboration with a programmable electronic load and a digital signal processor to simulate load characteristics in real-world scenarios, verify the chip's dynamic response capability under different operating conditions, and generate abnormal power data under extreme load conditions.

[0040] The multi-level parallel test module integrates a high-speed ADC (semiconductor integrated circuit), thermocouples and infrared thermal imagers to simultaneously acquire the chip's electrical and thermal parameters, analyze the correlation between abnormal power performance and temperature, and distinguish the temperature rise difference caused by power failure protection and leakage.

[0041] The abnormal power detection module extracts and classifies abnormal power waveforms, distinguishes between power outage protection and leakage events, and quantifies the impact of environmental charge interference.

[0042] The safety verification and diagnostic module uses a high-voltage pulse generator and a switch array to simulate a high-charge environment caused by leakage current and verify the effectiveness of the chip's protection circuit response. It also calibrates the circuit based on the collected correction values.

[0043] Specifically, in the dynamic test control module, to achieve a high degree of automation in the power chip testing system, a parameterized load model library is adopted. Based on chip specifications (such as withstand voltage and current rating), preset operating conditions (motor stall, battery reverse connection, etc.) are automatically matched. A digital signal processor (DSP) analyzes the equation parameters in real time, dynamically adjusting the electronic load mode without manual intervention. Automatic adjustment of the load current is achieved based on a PID algorithm. When a power anomaly is detected, the system automatically switches to fault analysis mode, performing automatic feature extraction, automatic model reasoning, and automatic result feedback. The algorithm endows the system with self-sensing, self-decision-making, and self-execution capabilities, fully leveraging its high speed, high precision, and repeatability. In practical use, due to factors such as equipment cost and the complexity of periodic testing, this invention is based on the normal operation of the power drive chip testing system under complex scenarios and relatively stable environmental conditions such as temperature and humidity. This may lead to abnormal operation at a certain testing moment.

[0044] The dynamic test control module mainly includes a programmable electronic load (supporting CC / CV / CR modes, switching rate ≥100A / μs), a high-speed DSP (TI C2000 series, 200MHz main frequency), and a high-precision current sensor (10MHz bandwidth, ±0.05% accuracy).

[0045] The stalled motor scenario is described using a nonlinear load characteristic equation, which can be described as follows: ,in The magnitude of the back electromotive force. Angular frequency, Where t is the impedance, i is the time, and L is the current. The load control signal is calculated in real time by the DSP and output.

[0046] Adjusting load current using a PID algorithm: ,in To control the output, the output current of the programmable electronic load is controlled to track the target waveform and minimize errors. Target current Dynamically adjust based on test cases The collected load current is input into the PID algorithm as a reference parameter. This is the error integral term, used to compensate for the zero drift of the current sensor caused by increased ambient temperature. The error differential term is used to predict the current fluctuation trend during sudden load changes. For proportional control coefficient, Integral control coefficient, Differential control coefficient;

[0047] The specific process involves setting the electronic load to CR mode (constant resistance mode) and initial resistance. Inductance L = 100μH, back electromotive force amplitude =50V, and configure the DSP to generate a sinusoidal modulation signal with a frequency of f=1kHz, which is then superimposed on the load control terminal;

[0048] Trigger chip drive signal (PWM duty cycle 50%), record load current and chip output voltage Sampling rate 1 MS / s;

[0049] At t=5ms, the load current is suddenly increased to 200% of the rated value to simulate a stall event, which recovers after 10μs.

[0050] Capture the current waveform using an oscilloscope to verify the load switching time. And ensure the overcurrent protection action time of the chip. ;

[0051] Meanwhile, during the actual execution of the dynamic test control module, weights are set according to the actual situation. For example, when the PID algorithm adjusts the load current, the proportional control is adjusted accordingly. Integral control Differential control The expert weighting method is adopted, which involves inviting experts in relevant fields to determine the weights of each indicator through professional opinion surveys and comprehensive evaluations. This ensures that the weight coefficients accurately reflect the importance of each indicator in the assessment of the impact of external light. In addition, methods such as the analytic hierarchy process (AHP) and fuzzy comprehensive evaluation can also be considered to determine the weight coefficients, ensuring their objectivity and scientific validity. These will not be elaborated upon here.

[0052] In the multi-level parallel test module, data information from a 16-bit high-speed ADC, miniature thermocouples, and an infrared thermal imager is acquired. FPGA is used to implement multi-channel trigger alignment, and the timing error model is as follows: ,in Let be the standard deviation of the clock jitter of the i-th channel. To compensate for the signal transmission path delay of the i-th channel, calibration is used to reduce the synchronization error of multi-channel signal acquisition. The synchronization error consists of the time error and path error in the timing error model, and the total error is no greater than 1ns;

[0053] Junction temperature calculated using the thermistor method : ,in, For chip junction temperature, For ambient temperature, , The thermistor power is t, where t is time and t is thermal resistance. Determined by chip packaging parameters;

[0054] In the multi-level parallel test module, the specific test process is as follows: a small current (1A) is applied under constant temperature conditions, and measurements are taken. Calculate the initial thermal resistance using thermocouple data. Run the chip to full load ( =20A), synchronous recording , Thermocouple temperature Infrared thermal images were collected by cutting off the power supply at t=10ms (simulating power failure protection) and applying high voltage between the chip pins (simulating leakage current), and collecting parameter changes at the moment of power failure and after power recovery.

[0055] In a multi-level parallel testing module, when plummeted to 0 and An exponential decrease indicates that the voltage rapidly returns to zero and the temperature continues to drop, which is normal protection.

[0056] when There is residual voltage and Continued to rise ( If the voltage does not return to zero and the temperature continues to rise, it can be determined that leakage is causing charge accumulation.

[0057] In the abnormal power detection module, wavelet transform is used to extract high-frequency components of the transient signal. Specifically, two types of abnormalities are injected 100 times each (50 times for power failure protection and 50 times for leakage current), and waveform data is collected and labeled. We selected the Dobessi 4 wavelet basis and decomposed it using scales a = 1 to 5. The larger the value of a, the wider the wavelet, corresponding to low-frequency components; the smaller the value of a, the narrower the wavelet, corresponding to high-frequency components. The basic wavelet of the function, Let b be the original signal input at time t, and b be the translation function, representing the scaling function. In the support region, a support vector machine classifier is constructed. The dataset is divided into training and test sets in a 7:3 ratio. Grid search is used to optimize the SVM hyperparameters, with radial basis function (RBF) as the kernel function. ,in, For kernel function, The bandwidth parameter of the Gaussian kernel controls the rate at which the similarity between samples decays. The input feature vector includes the voltage drop slope. Residual voltage V, temperature rise rate The system collects abnormal event data in real time, extracts features, and inputs them into an SVM classifier. It outputs class probabilities P(power outage) and P(leakage). If leakage is identified, the environmental charge density is calculated. : Where E is the voltage between chip pins And the spacing d is determined , The vacuum permittivity is set to a threshold value of 1. If the limit is exceeded, an alarm will be triggered;

[0058] In the safety verification and diagnostic module, data information from the high-voltage pulse generator and the RF relay matrix is ​​collected. The leakage current scenario is modeled as a transient high-voltage pulse superimposed with a DC bias. The high-voltage pulse is applied to the chip's power supply pins, and the voltage between the chip pins is obtained. : ,set up The initial time, Pulse amplitude pulse width =100ns, recorded using a high-speed oscilloscope (≥1GHz bandwidth) Measure the trigger time of the protection circuit If the chip does not respond or By locating the failure point (such as gate oxide breakdown) through thermal imaging, the protection action delay time is defined. ,Require (Complies with ISO 26262 ASIL Class D standard);

[0059] In the security verification and diagnostic module, the correction value for each module under similar test scenarios is calculated using an objective function, expressed as follows: ,in, , , and These are the measured values ​​for each item. , , and For project error terms, , , , These are the factor adjustment coefficients for each project, and , , , All are greater than 0;

[0060] In the safety verification and diagnostic module, when the correction value change is less than the set correction threshold, it indicates that the error value generated in the automatic test system of the power drive chip is small, and the automatic loop detection process continues.

[0061] When the correction value change is greater than or equal to the set correction threshold, it indicates that the error value generated in the automatic test system of the power drive chip is large, and recalibration is required, and the automatic loop detection process should be paused.

[0062] The above formulas are all dimensionless calculations. Dimensionless calculations can be performed using various methods such as standardization, which will not be elaborated here. The formulas are derived from software simulations based on a large amount of collected data, and the preset parameters in the formulas can be set by those skilled in the art according to the actual situation.

[0063] The above embodiments can be implemented, in whole or in part, by software, hardware, firmware, or any other combination thereof. When implemented using software, the above embodiments can be implemented, in whole or in part, as a computer program product. The computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer programs are loaded or executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more sets of available media. The available medium can be a magnetic medium (e.g., floppy disk, ATA hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium. The semiconductor medium can be a solid-state ATA hard disk.

[0064] It should be understood that in the various embodiments of this application, the order of the above-mentioned processes does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0065] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0066] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0067] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment, depending on actual needs.

[0068] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0069] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable ATA hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0070] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. An automated testing system for power drive chips, characterized in that: The dynamic test control module works in collaboration with a programmable electronic load and a digital signal processor to simulate load characteristics in real-world scenarios, verify the chip's dynamic response capability under different operating conditions, and generate abnormal power data under extreme load conditions. The multi-level parallel test module integrates high-speed semiconductor circuits, thermocouples, and infrared thermal imagers to simultaneously collect chip electrical and thermal parameters, analyze the correlation between abnormal power performance and temperature, and distinguish the temperature rise difference caused by power failure protection and leakage. The abnormal power detection module distinguishes between power outage protection and leakage events by measuring voltage drop slope, residual voltage, and temperature rise rate, and quantifies the impact of environmental charge interference. The safety verification and diagnostic module uses a high-voltage pulse generator and a switch array to simulate a strong charge environment caused by leakage current and verify the effectiveness of the chip's protection circuit response. At the same time, it calculates correction values ​​based on the collected test data and performs calibration based on the correction values.

2. The automatic testing system based on the power drive chip according to claim 1, characterized in that: The dynamic test control module mainly includes a programmable electronic load, a high-speed digital signal processor, and a high-precision current sensor. The stalled motor scenario is described using a nonlinear load characteristic equation: ,in The magnitude of the back electromotive force. Angular frequency, Where t is the impedance, i is the time, and L is the current, the load control signal is calculated in real time by a high-speed digital signal processor and output. Adjusting load current using a PID algorithm: ,in To control the output, the output current of the programmable electronic load is controlled to track the target waveform and minimize errors. Target current Dynamically adjust based on test cases The collected load current is input into the PID algorithm as a reference parameter. This is the error integral term, used to compensate for the zero drift of the current sensor caused by increased ambient temperature. The error differential term is used to predict the current fluctuation trend during sudden load changes. For proportional control coefficient, Integral control coefficient, Differential control coefficient; The specific process involves setting the initial resistance, inductance, and back EMF amplitude, and configuring the DSP to generate a sinusoidal modulation signal at a specific frequency, which is then superimposed onto the load control terminal. Trigger the chip drive signal and record the load current and chip output voltage; Simulate a traffic jam event and turn around after collecting data; Capture the current waveform using an oscilloscope to verify the load switching time and ensure the overcurrent protection action time of the chip.

3. The automatic testing system based on the power drive chip according to claim 2, characterized in that: In the multi-level parallel test module, data information from a 16-bit high-speed semiconductor integrated circuit, a miniature thermocouple, and an infrared thermal imager is acquired to achieve multi-channel trigger alignment. The timing error model is as follows: ,in Let be the standard deviation of the clock jitter of the i-th channel. To compensate for the signal transmission path delay of the i-th channel, calibration is used to reduce the synchronization error of multi-channel signal acquisition. The synchronization error consists of the time error and path error in the timing error model, and the total error is no greater than 1ns; Junction temperature calculated using the thermistor method : ,in, For chip junction temperature, For ambient temperature, , The chip power loss is represented by t, where t is time and thermal resistance is also represented by t. Determined by chip packaging parameters; In the multi-level parallel test module, the specific test process is as follows: a small current is applied under constant temperature environment, voltage and thermocouple data are measured, initial thermal resistance is calculated, the chip is run to full load, and voltage, current, thermocouple temperature and infrared thermal image are recorded simultaneously. The power supply is cut off at a set time and a high voltage is applied between the chip pins, and the parameter changes at the moment of power failure and after recovery are collected.

4. The automatic testing system for the power drive chip according to claim 3, characterized in that: In a multi-level parallel testing module, when plummeted to 0 and If the decline is exponential, it is considered normal protection. when There is residual voltage and If the voltage continues to rise, it is determined that leakage is causing charge accumulation.

5. The automatic testing system based on the power drive chip according to claim 4, characterized in that: In the abnormal power detection module, wavelet transform is used to extract high-frequency components of transient signals. Specifically, two types of anomalies are injected, waveform data is collected and labeled. We selected the Dobessi 4 wavelet basis and decomposed it at scales a = 1 to 5. The basic wavelet of the function, Let b be the original signal input at time t, and b be the translation function, representing the scaling function. In the support region, a support vector machine classifier is constructed. The dataset is divided into training and test sets in a 7:3 ratio. Grid search is used to optimize the hyperparameters of the vector machine, and the kernel function is the radial basis function. ,in, For kernel function, The bandwidth parameter of the Gaussian kernel controls the rate at which the similarity between samples decays. The input feature vector includes the voltage drop slope. residual voltage rate of temperature rise The system collects abnormal event data in real time, extracts features, and inputs them into a vector machine classifier. The output category is the probability of power outage or leakage. If leakage is determined, the ambient charge density is calculated. : E is determined by the voltage between chip pins and the spacing d, where , The vacuum permittivity is set to a threshold value of 1. If the limit is exceeded, an alarm will be triggered.

6. An automatic testing system for the power drive chip according to claim 5, characterized in that: In the safety verification and diagnostic module, data information from the high-voltage pulse generator and the RF relay matrix is ​​collected. The leakage current scenario is modeled as a transient high-voltage pulse superimposed with a DC bias. The high-voltage pulse is applied to the chip power supply pin, and the voltage and drive signal are recorded using a high-speed oscilloscope. The trigger time of the protection circuit is measured. If the chip does not respond, the failure point is located by thermal imaging, and the protection action delay time is defined.

7. An automatic testing system based on the power drive chip according to claim 6, characterized in that: In the security verification and diagnostic module, the correction value for each module under similar test scenarios is calculated using an objective function, expressed as follows: ,in, , , and These are the measured values ​​for each item. , , and For project error terms, , , , These are the factor adjustment coefficients for each project, and , , , All are greater than 0.

8. An automatic testing system based on the power drive chip according to claim 7, characterized in that: In the security verification and diagnostic module, when the correction value change is less than the set correction threshold, the automatic loop detection process continues. When the correction value change is greater than or equal to the set correction threshold, recalibration is required, and the automatic loop detection process is paused.

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