Chip debugging system and method

Abstract

A platform debugging controller monitors the state of a power rail of a target development board, monitors the state of a central processing unit after determining that a to-be-tested chip is successfully powered on, and feeds back that the to-be-tested chip is successfully started to an upper computer after determining that the central processing unit is successfully started and an operating system is loaded; after the to-be-tested chip is successfully started, the upper computer sends a first type of log request to the platform debugging controller, and the first type of log request comprises a first type of target event identifier; the platform debugging controller sends the first-class log request to the central processing unit and feeds back a first-class target log fed back by the central processing unit to the upper computer; the upper computer conducts debugging analysis on the central processing unit according to the first type of target logs, and whether the central processing unit passes debugging or not is determined. Related information of the chip to be tested is automatically collected through the platform debugging controller and provided for the upper computer to be analyzed, the labor cost is reduced, and the debugging efficiency is improved.

Description

Technical Field

[0001] This invention relates to the field of chip debugging, and more specifically, to a chip debugging system and method. Background Technology

[0002] During the chip backend testing and customer delivery process, it is necessary to analyze and collect logs of problems encountered during chip verification, including hardware debugging and log collection of the processor, in order to determine the specific location of the problem and track its status, so as to provide a basis for subsequent problem analysis and solutions.

[0003] Currently, the main method of data collection and judgment relies on manual methods, which not only consumes a lot of manpower and time, but may also lead to judgment errors. Summary of the Invention

[0004] The purpose of this invention is to provide a chip debugging system and method to improve the above-mentioned problems.

[0005] To achieve the above objectives, the technical solutions adopted in the embodiments of the present invention are as follows: In a first aspect, embodiments of the present invention provide a chip debugging system, the chip debugging system comprising: a platform debugging controller and a host computer; The platform debug controller is connected to the input / output port of the target development board, the input / output port of the target development board is connected to the power rail on the target development board, the i-th power rail of the target development board is connected to the i-th power rail of the chip under test, and the first UART serial port of the platform debug controller is connected to the central processing unit of the chip under test. The platform debug controller is used to monitor the power rail status of the target development board. After confirming that the chip under test has been successfully powered on, it monitors the status of the central processing unit. After confirming that the central processing unit has been successfully started and the operating system has been loaded, it sends feedback to the host computer that the chip under test has been successfully started. The host computer is used to send a first type of log request to the platform debug controller after the chip under test has successfully started up, wherein the first type of log request includes a first type of target event identifier; The platform debugging controller is used to send the first type of log request to the central processing unit, and to feed back the first type of target log fed back by the central processing unit to the host computer. The host computer is used to perform debugging analysis on the central processing unit based on the first type of target log to determine whether the central processing unit has passed the debugging process.

[0006] Optionally, the target development board is provided with a selector, which includes N input terminals. The i-th input terminal of the selector is connected to the i-th power rail of the target development board. The output terminal of the selector is connected to the platform debug controller through the input / output port of the target development board. The control terminal of the selector is also connected to the platform debug controller. After debugging begins, the platform debugging controller controls the first input terminal of the selector to be connected to its output terminal to obtain the level state of the first power rail of the target development board. After the first power rail of the target development board jumps to a high level, the controller controls the Nth input terminal of the selector to be connected to its output terminal to obtain the level state of the Nth power rail of the target development board. If the Nth power rail jumps to a high level within a preset time length after the first power rail jumps, then the power-on is determined to be successful. Wherein, the first power rail of the target development board is the power-on startup power rail, and the Nth power rail of the target development board is the power rail for the completion state.

[0007] Optionally, if the Nth power rail does not switch to high within a preset time period after the first power rail switches, the platform debugging controller determines that the power-on has failed and controls the selector to switch its internal conduction relationship, thereby determining the faulty power rail, which is the first power rail that remains at a low level.

[0008] Optionally, when a power-on failure is determined, the platform debug controller controls the Xth input terminal of the selector to be connected to its output terminal to obtain the level state of the Xth power rail of the target development board; if the Xth power rail is high, the selector is controlled to be connected from the X+1th input terminal to the N-1th input terminal and its output terminal to determine the faulty power rail; if the Xth power rail is low, the selector is controlled to be connected from the X-1th input terminal to the 2nd input terminal and its output terminal to determine the faulty power rail, where X is the quotient of N divided by 2.

[0009] Optionally, the second UART serial port of the platform debug controller is connected to the chip control unit of the chip under test; After the first power rail of the target development board transitions to a high level, the platform debug controller monitors the status of the chip control unit to determine whether the chip control unit has started successfully. If the chip control unit starts successfully, it determines whether the chip control unit has finished loading. When the chip control unit starts up successfully and completes loading, it is determined that the chip control unit has passed the debugging process.

[0010] Optionally, the third UART serial port of the platform debug controller is connected to the power distribution unit of the chip under test; After the first power rail of the target development board transitions to a high level, the platform debug controller monitors the status of the power distribution unit to determine whether the power distribution unit has started successfully. If the power distribution unit starts successfully, it determines whether the power distribution unit has finished loading. When the power distribution unit starts up successfully and completes loading, it is determined that the power distribution unit has passed the debugging process.

[0011] Optionally, the fourth UART serial port of the platform debug controller is connected to the target processor of the chip under test; The host computer is also used to send a second type of log request to the platform debug controller after the chip under test has started successfully, wherein the second type of log request includes a second type of target event identifier; The platform debugging controller is used to send the second type of log request to the target processor, and to send the second type of target log returned by the target processor back to the host computer; The host computer is used to perform debugging analysis on the target processor based on the second type of target log, and to determine whether the target processor has passed the debugging process.

[0012] Optionally, the target development board is also used to adjust the over-temperature flag to an over-temperature protection state when the chip temperature of the chip under test is detected to be higher than the target temperature. The platform debug controller is used to monitor the over-temperature flag of the target development board to determine whether over-temperature protection is triggered.

[0013] Secondly, embodiments of the present invention provide a chip debugging method, applied to the aforementioned chip debugging system, the method comprising: The platform debugging controller monitors the power rail status of the target development board. After confirming that the chip under test has been successfully powered on, it monitors the status of the central processing unit. After confirming that the central processing unit has been successfully started and the operating system has been loaded, it reports to the host computer that the chip under test has been successfully started. After the chip under test is successfully started, the host computer sends a first type of log request to the platform debug controller, wherein the first type of log request includes a first type of target event identifier; The platform debugging controller sends the first type of log request to the central processing unit, and feeds back the first type of target log from the central processing unit to the host computer. The host computer performs debugging analysis on the central processing unit based on the first type of target log to determine whether the central processing unit has passed the debugging process.

[0014] Thirdly, embodiments of the present invention provide a chip debugging method, applied to a platform debugging controller in the aforementioned chip debugging system, the method comprising: The platform debugging controller monitors the power rail status of the target development board. After confirming that the chip under test has been successfully powered on, it monitors the status of the central processing unit. After confirming that the central processing unit has been successfully started and the operating system has been loaded, it reports to the host computer that the chip under test has been successfully started. The platform debugging controller sends the first type of log request transmitted by the host computer to the central processing unit, and feeds back the first type of target log from the central processing unit to the host computer, so that the host computer can perform debugging analysis on the central processing unit based on the first type of target log and determine whether the central processing unit has passed the debugging. The first type of log request includes a first type of target event identifier.

[0015] Compared to existing technologies, the chip debugging system and method provided in this invention involves a platform debugging controller connected to the input / output ports of a target development board. The input / output ports of the target development board are connected to power rails on the board. The i-th power rail of the target development board is connected to the i-th power rail of the chip under test (DUT). The first UART serial port of the platform debugging controller is connected to the central processing unit (CPU) of the DUT. The platform debugging controller monitors the power rail status of the target development board. After confirming successful power-on of the DUT, it monitors the CPU status. After confirming successful CPU startup and operating system loading, it reports successful startup of the DUT to the host computer. The host computer sends a first type of log request to the platform debugging controller after successful startup of the DUT. This first type of log request includes a first type of target event identifier. The platform debugging controller sends the first type of log request to the CPU and feeds back the first type of target log from the CPU to the host computer. The host computer performs debugging analysis on the CPU based on the first type of target log to determine whether the CPU has passed debugging. By automatically collecting relevant information about the DUT through the platform debugging controller and providing it to the host computer for analysis, labor costs are reduced and debugging efficiency is improved.

[0016] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is one of the schematic diagrams of the chip debugging system provided in the embodiment of the present invention.

[0019] Figure 2 This is the second schematic diagram of the chip debugging system provided in the embodiment of the present invention.

[0020] Figure 3 This is one of the flowcharts illustrating the chip debugging method provided in an embodiment of the present invention.

[0021] Figure 4 This is the second flowchart illustrating the chip debugging method provided in this embodiment of the invention. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0023] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0024] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this invention, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0025] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0026] In the description of this invention, it should be noted that the terms "upper," "lower," "inner," "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of this invention is usually placed when in use. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0027] In the description of this invention, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set" and "connection" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0028] The following detailed description of some embodiments of the present invention is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0029] This invention provides a chip debugging system; please refer to [the relevant documentation]. Figure 1 , Figure 1 This is one of the schematic diagrams of a chip debugging system provided in an embodiment of the present invention. The chip debugging system includes: a platform debugging controller (also known as a PDC) and a host computer, wherein the platform debugging controller and the host computer are connected by wired communication or wireless communication.

[0030] The platform debug controller is connected to the input / output port (GPIO) of the target development board, which is an engineering development board (EVB) with the chip under test deployed.

[0031] The input / output ports of the target development board are connected to the power rails on the target development board. The i-th power rail of the target development board is connected to the i-th power rail of the chip under test (1≤i≤N, where N is the total number of power rails of the chip under test). The first UART serial port of the platform debug controller is connected to the central processing unit of the chip under test.

[0032] UART stands for Universal Asynchronous Receiver / Transmitter.

[0033] The platform debug controller is used to monitor the power rail status of the target development board. After confirming that the chip under test has been successfully powered on, it monitors the status of the central processing unit. After confirming that the central processing unit has started successfully and completed the loading of the operating system, it sends a message to the host computer that the chip under test has started successfully.

[0034] Optionally, the platform debug controller monitors the power rail status of the target development board through the input / output ports of the target development board. The platform debug controller can also determine whether the central processing unit has started successfully and loaded successfully based on the register status of the corresponding central processing unit.

[0035] The host computer is used to send a first type of log request (corresponding to the central processing unit) to the platform debug controller after the chip under test has successfully started. The first type of log request includes a first type of target event identifier.

[0036] The platform debug controller is used to send the first type of log request to the central processing unit and to feed back the first type of target log from the central processing unit to the host computer. The first type of target log is the log record corresponding to the first type of target event.

[0037] The host computer is used to perform debugging analysis on the central processing unit based on the first type of target logs to determine whether the central processing unit has passed the debugging process. If no errors are found in all the first type of target logs, the central processing unit is considered to have passed the debugging process.

[0038] In the chip debugging system provided in this embodiment of the invention, the platform debugging controller automatically collects relevant information of the chip under test and provides it to the host computer for analysis, thereby reducing labor costs and improving debugging efficiency.

[0039] Building upon the preceding text, this invention provides an optional implementation method for determining whether the chip under test has successfully powered on. Please refer to the following documentation. Figure 1 .

[0040] The target development board is equipped with a selector, which has N input terminals. The i-th input terminal of the selector is connected to the i-th power rail of the target development board. The output terminal of the selector is connected to the platform debugging controller through the input / output port of the target development board. The control terminal of the selector is also connected to the platform debugging controller.

[0041] After debugging begins, the platform debugging controller controls the first input terminal of the selector to be connected to its output terminal to obtain the level state of the first power rail of the target development board. After the first power rail of the target development board jumps to a high level (power-on state), the Nth input terminal of the selector is connected to its output terminal to obtain the level state of the Nth power rail of the target development board. If the Nth power rail jumps to a high level within a preset time length after the first power rail jumps, then the power-on is confirmed to be successful.

[0042] Among them, the first power rail of the target development board is the power-on startup power rail, and the Nth power rail of the target development board is the power rail for the completion state.

[0043] If the Nth power rail does not switch to high within a preset time period after the first power rail switches, the platform debugging controller determines that the power-on has failed and controls the selector to switch its internal conduction relationship, thereby identifying the faulty power rail. The faulty power rail is the first power rail that remains at a low level.

[0044] Building upon the foregoing, in order to quickly locate the problem, this embodiment of the invention also provides an optional implementation method, which is described below.

[0045] When a power-on failure is detected, the platform debug controller controls the Xth input terminal of the selector to conduct with its output terminal to obtain the level state of the Xth power rail of the target development board. If the Xth power rail is high, the selector is controlled to conduct from the X+1th input terminal to the N-1th input terminal and its output terminal to determine the faulty power rail. If the Xth power rail is low, the selector is controlled to conduct from the X-1th input terminal to the 2nd input terminal and its output terminal to determine the faulty power rail. Here, X is the quotient of N divided by 2.

[0046] Please continue to refer to this. Figure 1 In one optional implementation, the second UART serial port of the platform debug controller is connected to the chip control unit of the chip under test. The chip control unit may, but is not limited to, a microcontroller unit (MCU).

[0047] After the first power rail of the target development board transitions to a high level, the platform debug controller monitors the status of the chip control unit to determine whether the chip control unit has started successfully. If the chip control unit starts successfully, it determines whether the chip control unit has finished loading.

[0048] When the chip control unit starts up successfully and completes loading, it is determined that the chip control unit has passed the debugging process. When the chip control unit fails to start up successfully or fails to complete loading, it indicates that the debugging process has failed, and an error report of the chip control unit is generated.

[0049] Please continue to refer to this. Figure 1 In one optional implementation, the third UART serial port of the platform debug controller is connected to the power distribution unit of the chip under test. The power distribution unit may, but is not limited to, a microcontroller unit (MCU).

[0050] After the first power rail of the target development board transitions to a high level, the platform debug controller monitors the status of the power distribution unit to determine whether the power distribution unit has started successfully. If the power distribution unit starts successfully, it determines whether the power distribution unit has finished loading.

[0051] When the power distribution unit starts up successfully and completes loading, it is determined that the power distribution unit has passed the debugging process. When the power distribution unit fails to start up successfully or fails to complete loading, it indicates that the debugging process has failed, and an error report for the power distribution unit is generated.

[0052] Please refer to Figure 2 , Figure 2 This is a second schematic diagram of the chip debugging system architecture provided in an embodiment of the present invention. The fourth UART serial port of the platform debugging controller is connected to the target processor of the chip under test. The target processor can be, but is not limited to, a display processing unit (DPU), a neural network processing unit (NPU), a video processing unit (VPU), or a graphics processing unit (GPU).

[0053] The host computer is also used to send a second type of log request (corresponding to the target processor) to the platform debug controller after the chip under test has successfully started. The second type of log request includes a second type of target event identifier.

[0054] The platform debug controller is used to send the second type of log request to the target processor and to feed back the second type of target log from the target processor to the host computer. The second type of target log is the log record corresponding to the second type of target event.

[0055] The host computer is used to perform debugging analysis on the target processor based on the second type of target logs to determine whether the target processor has passed debugging. If no errors are found in all the second type of target logs, it is considered to have passed debugging.

[0056] The chip debugging system provided in this invention supports the collection of key register states of the corresponding IP (target processor) to confirm the health status of submodules. This helps to gain a more comprehensive understanding of the system's operation, providing support for subsequent rapid iterations and expansion of requirements. It not only meets current needs but also possesses good scalability, enabling it to adapt to potentially complex scenarios and diverse requirements in the future.

[0057] Please continue to refer to this. Figure 2 The target development board is also used to adjust the over-temperature flag to over-temperature protection state when the chip temperature of the chip under test is detected to be higher than the target temperature.

[0058] The platform debug controller is used to monitor the over-temperature flag of the target development board to determine whether over-temperature protection is triggered.

[0059] This allows for the deployment of more GPIO controllers to collect critical board-level status signals. For example, detecting whether a chip has triggered critical signals such as over-temperature protection can further enrich the information available for problem diagnosis.

[0060] This invention also provides a chip debugging method, applied to the aforementioned chip debugging system. Please refer to [link / reference]. Figure 3 , Figure 3 This is one of the flowcharts illustrating a chip debugging method provided in an embodiment of the present invention. The chip debugging method includes steps S11, S21, S12, and S22, which are described in detail below.

[0061] S11, the platform debug controller monitors the power rail status of the target development board. After confirming that the chip under test has been successfully powered on, it monitors the status of the central processing unit. After confirming that the central processing unit has been successfully started and the operating system has been loaded, it sends a message to the host computer that the chip under test has been successfully started.

[0062] S21. After the chip under test is successfully started, the host computer sends a first type of log request to the platform debug controller. The first type of log request includes a first type of target event identifier.

[0063] S12, the platform debug controller sends the first type of log request to the central processing unit, and feeds back the first type of target log from the central processing unit to the host computer.

[0064] S22, the host computer performs debugging analysis on the central processing unit based on the first type of target log to determine whether the central processing unit has passed the debugging.

[0065] This invention also provides a chip debugging method, applied to the platform debugging controller in the aforementioned chip debugging system. Please refer to [link / reference needed]. Figure 4 , Figure 4This is a second schematic flowchart of the chip debugging method provided in an embodiment of the present invention. The chip debugging method includes steps S31 and S32, as detailed below.

[0066] S31, the platform debug controller monitors the power rail status of the target development board. After confirming that the chip under test has been successfully powered on, it monitors the status of the central processing unit. After confirming that the central processing unit has been successfully started and the operating system has been loaded, it reports to the host computer that the chip under test has been successfully started. S32, the platform debugging controller sends the first type of log request transmitted by the host computer to the central processing unit, and feeds back the first type of target log from the central processing unit to the host computer, so that the host computer can perform debugging analysis on the central processing unit based on the first type of target log and determine whether the central processing unit has passed the debugging. The first type of log request includes the first type of target event identifier.

[0067] In summary, the chip debugging system and method provided by this invention includes a platform debugging controller connected to the input / output port of a target development board. The input / output port of the target development board is connected to a power rail on the target development board. The i-th power rail of the target development board is connected to the i-th power rail of the chip under test (DUT). The first UART serial port of the platform debugging controller is connected to the central processing unit (CPU) of the DUT. The platform debugging controller monitors the power rail status of the target development board. After confirming that the DUT has successfully powered on, it monitors the status of the CPU. After confirming that the CPU has successfully started and completed operating system loading, it reports successful startup of the DUT to the host computer. The host computer sends a first type of log request to the platform debugging controller after successful startup of the DUT. The first type of log request includes a first type of target event identifier. The platform debugging controller sends the first type of log request to the CPU and feeds back the first type of target log from the CPU to the host computer. The host computer performs debugging analysis on the CPU based on the first type of target log to determine whether the CPU has passed debugging. By automatically collecting relevant information about the DUT through the platform debugging controller and providing it to the host computer for analysis, labor costs are reduced and debugging efficiency is improved.

[0068] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

[0069] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

Claims

1. A chip debugging system, characterized in that, The chip debugging system includes: a platform debugging controller and a host computer; The platform debug controller is connected to the input / output port of the target development board, the input / output port of the target development board is connected to the power rail on the target development board, the i-th power rail of the target development board is connected to the i-th power rail of the chip under test, and the first UART serial port of the platform debug controller is connected to the central processing unit of the chip under test. The platform debug controller is used to monitor the power rail status of the target development board. After confirming that the chip under test has been successfully powered on, it monitors the status of the central processing unit. After confirming that the central processing unit has been successfully started and the operating system has been loaded, it sends feedback to the host computer that the chip under test has been successfully started. The host computer is used to send a first type of log request to the platform debug controller after the chip under test has successfully started up, wherein the first type of log request includes a first type of target event identifier; The platform debugging controller is used to send the first type of log request to the central processing unit, and to feed back the first type of target log fed back by the central processing unit to the host computer. The host computer is used to perform debugging analysis on the central processing unit based on the first type of target log to determine whether the central processing unit has passed the debugging process.

2. The chip debugging system as described in claim 1, characterized in that, The target development board is equipped with a selector, which includes N input terminals. The i-th input terminal of the selector is connected to the i-th power rail of the target development board. The output terminal of the selector is connected to the platform debugging controller through the input / output port of the target development board. The control terminal of the selector is also connected to the platform debugging controller. After debugging begins, the platform debugging controller controls the first input terminal of the selector to be connected to its output terminal to obtain the level state of the first power rail of the target development board. After the first power rail of the target development board jumps to a high level, the controller controls the Nth input terminal of the selector to be connected to its output terminal to obtain the level state of the Nth power rail of the target development board. If the Nth power rail jumps to a high level within a preset time length after the first power rail jumps, then the power-on is determined to be successful. Wherein, the first power rail of the target development board is the power-on startup power rail, and the Nth power rail of the target development board is the power rail for the completion state.

3. The chip debugging system as described in claim 2, characterized in that, If the Nth power rail does not switch to high within a preset time period after the first power rail switches, the platform debugging controller determines that the power-on has failed and controls the selector to switch its internal conduction relationship, thereby determining the faulty power rail, which is the first power rail that remains at a low level.

4. The chip debugging system as described in claim 3, characterized in that, When a power-on failure is detected, the platform debug controller controls the Xth input terminal of the selector to conduct with its output terminal to obtain the level state of the Xth power rail of the target development board; if the Xth power rail is high, the selector is controlled to conduct from the X+1th input terminal to the N-1th input terminal and its output terminal to determine the faulty power rail; if the Xth power rail is low, the selector is controlled to conduct from the X-1th input terminal to the 2nd input terminal and its output terminal to determine the faulty power rail, where X is the quotient of N divided by 2.

5. The chip debugging system as described in claim 1, characterized in that, The second UART serial port of the platform debug controller is connected to the chip control unit of the chip under test; After the first power rail of the target development board transitions to a high level, the platform debug controller monitors the status of the chip control unit to determine whether the chip control unit has started successfully. If the chip control unit starts successfully, it determines whether the chip control unit has finished loading. When the chip control unit starts up successfully and completes loading, it is determined that the chip control unit has passed the debugging process.

6. The chip debugging system as described in claim 1, characterized in that, The third UART serial port of the platform debug controller is connected to the power distribution unit of the chip under test; After the first power rail of the target development board transitions to a high level, the platform debug controller monitors the status of the power distribution unit to determine whether the power distribution unit has started successfully. If the power distribution unit starts successfully, it determines whether the power distribution unit has finished loading. When the power distribution unit starts up successfully and completes loading, it is determined that the power distribution unit has passed the debugging process.

7. The chip debugging system as described in claim 1, characterized in that, The fourth UART serial port of the platform debug controller is connected to the target processor of the chip under test; The host computer is also used to send a second type of log request to the platform debug controller after the chip under test has started successfully, wherein the second type of log request includes a second type of target event identifier; The platform debugging controller is used to send the second type of log request to the target processor, and to send the second type of target log returned by the target processor back to the host computer; The host computer is used to perform debugging analysis on the target processor based on the second type of target log, and to determine whether the target processor has passed the debugging process.

8. The chip debugging system as described in claim 1, characterized in that, The target development board is also used to adjust the over-temperature flag to an over-temperature protection state when the chip temperature of the chip under test is detected to be higher than the target temperature. The platform debug controller is used to monitor the over-temperature flag of the target development board to determine whether over-temperature protection is triggered.

9. A chip debugging method, characterized in that, The method, applied to the chip debugging system according to any one of claims 1-8, comprises: The platform debugging controller monitors the power rail status of the target development board. After confirming that the chip under test has been successfully powered on, it monitors the status of the central processing unit. After confirming that the central processing unit has been successfully started and the operating system has been loaded, it reports to the host computer that the chip under test has been successfully started. After the chip under test is successfully started, the host computer sends a first type of log request to the platform debug controller, wherein the first type of log request includes a first type of target event identifier; The platform debugging controller sends the first type of log request to the central processing unit, and feeds back the first type of target log from the central processing unit to the host computer. The host computer performs debugging analysis on the central processing unit based on the first type of target log to determine whether the central processing unit has passed the debugging process.

10. A chip debugging method, characterized in that, The platform debugging controller applied to the chip debugging system according to any one of claims 1-8, the method comprising: The platform debugging controller monitors the power rail status of the target development board. After confirming that the chip under test has been successfully powered on, it monitors the status of the central processing unit. After confirming that the central processing unit has been successfully started and the operating system has been loaded, it reports to the host computer that the chip under test has been successfully started. The platform debugging controller sends the first type of log request transmitted by the host computer to the central processing unit, and feeds back the first type of target log from the central processing unit to the host computer, so that the host computer can perform debugging analysis on the central processing unit based on the first type of target log and determine whether the central processing unit has passed the debugging. The first type of log request includes a first type of target event identifier.

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