Dead pixel detection method of photoresist three-dimensional morphology, medium, product and equipment

Abstract

The invention provides a photoresist three-dimensional morphology dead pixel detection method, a medium, a product and equipment. The method comprises the following steps: screening layout graphs of a to-be-detected design layout to obtain training graphs; simulating the training graph by using a pre-established physical simulation model to obtain a photoresist three-dimensional shape; extracting a top simulation contour of the photoresist from the three-dimensional morphology of the photoresist; training by using the training graph and the corresponding photoresist top simulation contour to obtain a photoresist dead pixel detection model; and carrying out photoresist three-dimensional morphology dead pixel detection on the design layout by using the photoresist dead pixel detection model to obtain a potential dead pixel region related to the photoresist three-dimensional morphology in the design layout. Through the method, on one hand, the physical simulation model is utilized to obtain accurate training data, and on the other hand, the photoresist dead pixel detection model is utilized to quickly detect the whole chip, so that the accuracy of photoresist three-dimensional shape dead pixel detection can be ensured, and the dead pixel detection efficiency can be improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method, medium, product, and equipment for detecting defects in the three-dimensional morphology of photoresist. Background Technology

[0002] In the current semiconductor technology field, the most crucial step in semiconductor chip manufacturing is transferring the chip design pattern onto a silicon wafer. Among the many process steps in chip manufacturing, photolithography and etching are the most directly related to pattern transfer. However, with the continuous evolution of chip technology nodes, the size of the design layout is now much smaller than the wavelength of photolithography. This leads to a strong diffraction effect, commonly known as the optical proximity effect, causing a significant deviation between the morphology of the chip design layout and the morphology printed on the photoresist through photolithography. To compensate for this deviation, in the integrated circuit manufacturing process, wafer fabs need to obtain optical proximity correction (OPC) mask data from the original design layout before proceeding with the wafer fabrication. In practice, the original design pattern is input into the OPC Recipe for processing. The OPC recipe is essentially a technical solution for photolithography image correction, a series of optimization strategies and parameter settings. The general process involves implementing OPC optimization on the design layout, followed by photolithography simulation inspection. If defects are found, the OPC Recipe is iteratively improved. The model typically used for lithography simulation and testing is the same lithography model used for OPC.

[0003] However, in real-world manufacturing processes, ordinary OPC models are unable to predict defects related to the three-dimensional morphology of the photoresist based on a given layout. Even if OPC model simulations show that the contour of a certain preset plane in the photoresist meets the requirements, if the thickness of the upper layer of the photoresist is too thin after the photolithography process, or if the overall photoresist sidewall angle (SWA) deviates too much from 90 degrees, it is easy for subsequent etching processes to fail to provide sufficient protection for the covered area, leading to defects. Therefore, how to predict defects caused by the three-dimensional morphology of the photoresist in advance has become a pressing technical challenge in the field of semiconductor technology. Summary of the Invention

[0004] In view of the above problems, the present invention proposes a method, medium, product and equipment for detecting defects in the three-dimensional morphology of photoresist to overcome or at least partially solve the above problems.

[0005] One objective of this invention is to improve the efficiency of defect detection in the three-dimensional morphology of photoresist;

[0006] Another further objective of this invention is to improve the accuracy of defect detection in the three-dimensional morphology of photoresist.

[0007] Specifically, this invention provides a method for detecting defects in the three-dimensional morphology of photoresist, comprising:

[0008] Training graphics are obtained by filtering from the layout graphics of the design layout to be tested;

[0009] The training pattern is simulated using a pre-established physical simulation model to obtain the three-dimensional morphology of the photoresist. The physical simulation model is used to simulate the input layout pattern to obtain the three-dimensional morphology of the photoresist.

[0010] Extracting the simulated top contour of the photoresist from its three-dimensional morphology;

[0011] The photoresist defect detection model is obtained by training the training pattern and its corresponding simulated top contour of the photoresist.

[0012] A photoresist defect detection model is used to detect defects in the three-dimensional morphology of the photoresist in the design layout, thereby obtaining potential defect areas in the design layout that are related to the three-dimensional morphology of the photoresist.

[0013] Optionally, after obtaining the potential defect regions related to the three-dimensional morphology of the photoresist in the design layout, the method further includes:

[0014] The potential defect area was simulated using a physical simulation model to obtain the three-dimensional morphology of the photoresist in the potential defect area;

[0015] The three-dimensional morphology of the photoresist in the potential defect area is inspected to determine whether there are actual defects in the potential defect area.

[0016] Optionally, if actual bad pixels exist in the potential bad pixel area, the following additional steps are also included:

[0017] Extract the simulated top contour of the photoresist in the bad pixel region from the three-dimensional morphology of the photoresist in the bad pixel region corresponding to the real bad pixel;

[0018] The photoresist defect detection model is iteratively optimized using real defective pixels and their corresponding defective pixel regions, along with the simulated top contour of the photoresist.

[0019] Optionally, the training steps for the physical simulation model include:

[0020] Construct a physical simulation model framework;

[0021] The training data for the physical simulation model framework is obtained. The training data includes wafer slicing data and scanning electron microscope measurement data. The wafer slicing data is the slice data corresponding to the wafer sample after being processed by the same photolithography process as the design layout. The scanning electron microscope measurement data includes the image and size data obtained by measuring the wafer sample using a scanning electron microscope.

[0022] The parameters in the physical simulation model framework are optimized by using training data, thereby obtaining the physical simulation model.

[0023] Optionally, the step of selecting training graphics from the layout graphics of the design layout to be tested includes:

[0024] The map graphics are grouped according to their graphic characteristics, resulting in multiple graphic groups;

[0025] Select the training graphs to be used for training from the selected graph group.

[0026] Optionally, the steps for training a photoresist defect detection model using training images and their corresponding simulated top contours of the photoresist include:

[0027] Extract feature points from the simulated contour at the top of the photoresist;

[0028] Determine the initial model parameters for the photoresist defect detection model;

[0029] The simulated contour is obtained by performing simulation operations on the training graphics based on the initial model parameters;

[0030] The initial model parameters are iteratively optimized based on feature points and simulated contours to obtain a photoresist defect detection model.

[0031] Optionally, the step of iteratively optimizing the initial model parameters based on feature points and simulated contours includes:

[0032] Calculate the deviation distance between each feature point and the simulated contour;

[0033] An evaluation function corresponding to the photoresist defect detection model is generated based on the deviation distance;

[0034] The initial model parameters are iteratively optimized until the evaluation function meets the preset convergence condition, thus obtaining the photoresist defect detection model.

[0035] According to another aspect of the present invention, a computer-readable storage medium is also provided, on which a computer program is stored, wherein the computer program, when executed by a processor, implements the steps of the defect detection method for the three-dimensional morphology of photoresist described above.

[0036] According to another aspect of the present invention, a computer program product is also provided, comprising a computer program that, when executed by a processor, implements the steps of the defect detection method for the three-dimensional morphology of photoresist described above.

[0037] According to another aspect of the present invention, a computer device is also provided, including a memory, a processor, and a machine-executable program stored in the memory and running on the processor, wherein the processor executes the machine-executable program to implement the steps of the above-described method for detecting defects in the three-dimensional morphology of photoresist.

[0038] The defect detection method for the three-dimensional morphology of photoresist of the present invention first selects training patterns from the layout patterns of the design to be inspected, and simulates the training patterns using a pre-established physical simulation model to obtain the three-dimensional morphology of the photoresist; then, extracts the simulated top contour of the photoresist from the three-dimensional morphology; trains the model using the training patterns and their corresponding simulated top contours to obtain a photoresist defect detection model; finally, uses the photoresist defect detection model to detect defects in the three-dimensional morphology of the photoresist on the design layout, obtaining potential defect areas in the design layout related to the three-dimensional morphology of the photoresist. This method can, on the one hand, obtain accurate training data using a physical simulation model, and on the other hand, use the trained photoresist defect detection model to quickly detect defects in the entire chip's design layout. This ensures both the accuracy and efficiency of defect detection in the three-dimensional morphology of the photoresist.

[0039] Furthermore, the defect detection method for the three-dimensional morphology of photoresist of the present invention, after obtaining the potential defect region related to the three-dimensional morphology of the photoresist in the design layout, further utilizes a physical simulation model to simulate the potential defect region, obtaining the three-dimensional morphology of the photoresist in the potential defect region; the three-dimensional morphology of the photoresist in the potential defect region is then detected to determine whether there are actual defects in the potential defect region. Through this method, the potential defect region detected by the photoresist defect detection model can be further screened using a physical simulation model, thereby further improving the accuracy of defect detection in the three-dimensional morphology of the photoresist.

[0040] The above and other objects, advantages and features of the present invention will become more apparent to those skilled in the art from the following detailed description of specific embodiments of the invention in conjunction with the accompanying drawings. Attached Figure Description

[0041] The following sections will describe some specific embodiments of the invention in detail by way of example and not limitation, with reference to the accompanying drawings. The same reference numerals in the drawings denote the same or similar parts or portions. Those skilled in the art should understand that these drawings are not necessarily drawn to scale. In the drawings:

[0042] Figure 1This is a schematic flowchart of a method for detecting defects in the three-dimensional morphology of photoresist according to an embodiment of the present invention;

[0043] Figure 2 This is a schematic flowchart of a method for detecting defects in the three-dimensional morphology of photoresist according to another embodiment of the present invention;

[0044] Figure 3 This is a schematic diagram of a computer program product according to an embodiment of the present invention;

[0045] Figure 4 This is a schematic diagram of a computer-readable storage medium according to an embodiment of the present invention; and

[0046] Figure 5 This is a schematic diagram of a computer device according to an embodiment of the present invention. Detailed Implementation

[0047] Those skilled in the art should understand that the embodiments described below are merely a part of the embodiments of the present invention, and not all of the embodiments of the present invention. These partial embodiments are intended to explain the technical principles of the present invention and are not intended to limit the scope of protection of the present invention. Based on the embodiments provided by the present invention, all other embodiments obtained by those skilled in the art without creative effort should still fall within the scope of protection of the present invention.

[0048] It should be noted that the logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be specifically implemented in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus or device (such as a computer-based system, a processor-included system or other system that can fetch and execute instructions from, an instruction execution system, apparatus or device).

[0049] In the current semiconductor technology field, the most crucial step in semiconductor chip manufacturing is transferring the chip's design pattern onto a silicon wafer. Among the many process steps in chip manufacturing, the processes directly related to pattern transfer are mainly photolithography and etching, often referred to as patterning. In current mainstream integrated circuit manufacturing processes, photolithography involves chemically changing photoresist under exposure to specific wavelengths of light, such as 193nm or 248nm, and then transferring the pattern designed on the mask to the photoresist morphology on the silicon wafer through development. Etching, on the other hand, selectively removes unwanted material with the help of the photoresist morphology, ultimately creating the desired micro-patterns on the silicon wafer.

[0050] As chip technology nodes continue to evolve, the size of the design layout has become much smaller than the wavelength of photolithography (193nm). This leads to a strong diffraction effect, commonly known as the optical proximity effect, causing a significant deviation between the morphology of the chip design layout and the morphology printed on the photoresist through photolithography. To compensate for this deviation, during the integrated circuit manufacturing process, the foundry (FAB) needs to obtain optical proximity correction (OPC) mask data from the original design layout before proceeding with the wafer fabrication. In practice, the original design pattern is input into the OPC Recipe for processing. The OPC recipe is essentially a technical solution for photolithography image correction, consisting of a series of optimization strategies and parameter settings. The general process involves implementing OPC optimization on the design layout, followed by photolithography simulation inspection. If defects are found, the OPC Recipe is iteratively improved. The model typically used for photolithography simulation inspection is the same photolithography model used for OPC.

[0051] The OPC lithography model was built during the Technology Development (TD) phase of the FAB (Factory Automation) project. It was primarily constructed based on silicon wafer data from typical test patterns and a subset of real device layouts along with corresponding critical dimension scanning electron microscope (CD-SEM) measurement images, with a focus on typical test patterns. The OPC model's construction is a data-driven model calibration process. The core of this process is to use measurement data collected from actual silicon wafers to fit and optimize the model's internal parameters, ensuring that the simulation results closely match the physical reality on the silicon wafer.

[0052] The silicon wafer data relied upon for model construction typically refers to the images and dimensional data obtained after measuring a silicon wafer that has undergone photolithography using a critical-size scanning electron microscope (CSE). CD-SEM utilizes a finely focused electron beam to rapidly scan the surface of the sample under test (such as a silicon wafer coated with photoresist). The high-energy electron beam interacts with the sample material, exciting various signals. Among these, the emission intensity of secondary electrons (SE) is most sensitive to the microstructure of the sample surface. At the edges of patterns, due to the greater surface area exposed to the electron beam, the secondary electron yield is higher, appearing as brighter bands in the image. A detector collects these secondary electron signals and synchronizes their intensity with the position of the electron beam, thereby constructing a high-resolution grayscale image of the sample surface on the display screen. The measurement algorithm determines the edges of features by detecting abrupt changes in the grayscale intensity profile of the image (usually at the locations where the grayscale value changes most drastically at the edges of lines). By calculating the distance between two opposite edges, the critical dimension (CD) value of the feature can be obtained.

[0053] The working principle of CD-SEM dictates that it provides a two-dimensional planar image observed from a top-down perspective. The CD value it reports is typically a cross-sectional width measured on a default or preset probe plane (determined by a grayscale intensity thresholding algorithm, generally located near the bottom of the photoresist). However, after exposure and development, the photoresist forms a pattern with complex three-dimensional contours. Key three-dimensional attributes such as sidewall angles (SWA), bottom feet, or top rounding cannot be directly obtained from traditional CD-SEM two-dimensional images. OPC models, because they are designed for simulation on the entire chip scale, are essentially semi-empirical and semi-physical models for faster computation. They primarily rely on actual silicon wafer measurements from CD-SEM. Therefore, OPC models can only simulate the photoresist contour on a preset probe plane. Consequently, photolithography simulation inspection based on OPC models cannot predict defects related to the three-dimensional morphology of the photoresist.

[0054] Ordinary OPC models are unable to predict defects related to the 3D morphology of the photoresist based on a given mask layout. However, in real-world processes, even if OPC model simulations show that the contour of a predetermined plane (usually the bottom) of the photoresist meets requirements, if the top-loss layer on the photoresist is too thin after the photolithography process, or if the overall photoresist SWA (side wall angle) deviates significantly from 90 degrees, it is easy for subsequent etching processes to fail to provide sufficient protection for the covered area, leading to defects. Therefore, predicting defects caused by the 3D morphology of the photoresist in advance is essential.

[0055] To address the aforementioned issues, two approaches are currently employed in the semiconductor technology field. The first involves using a variant of the OPC model, changing the preset simulation plane to the top of the photoresist. This provides simulation results for the top of the photoresist and, in conjunction with calculations of spatial image quality parameters (NILS: Normalized Image Log Slope), helps identify potential dead pixels. However, this approach is still based on the standard OPC model. The OPC model is initially built upon a large amount of CD-SEM data measured on a specific plane of the photoresist (usually the bottom). There is a lack of substantial measurement data supporting the top of the photoresist. Directly extending this data to the top of the photoresist, while providing some reference value, cannot guarantee sufficient prediction accuracy.

[0056] Another approach is to use rigorous lithography simulation for key areas of interest. In computational lithography, simulation models are mainly divided into two categories: one is an empirical model based primarily on data, like the OPC model; the other is a rigorous lithography simulation model, which is based on fundamental physical principles to accurately calculate the results of each step in the lithography process. It does not rely on extensive silicon wafer measurement data for empirical fitting, but rather directly solves the governing equations describing the physical process, and uses a very small amount of wafer slicing data and CD-SEM data to fit physical parameters to predict imaging results. Using rigorous lithography simulation tools, the complete three-dimensional morphology of the photoresist after development can be simulated and output, allowing for the evaluation of lithographic performance in key areas of interest. While this approach, using a physical model fitted with parameters from a small amount of wafer slicing data and CD-SEM measurements, can simulate the complete three-dimensional morphology of the photoresist, rigorous lithography simulation has extremely high computational complexity and is very slow, making it unsuitable for large-scale application. It can only be applied to given key areas, but engineers must first identify these key areas. Therefore, in practice, rigorous lithography simulation tools are often used to perform simulation predictions for extremely critical individual areas, while also being used to further confirm and analyze defective areas that have been reported at the process stage.

[0057] In summary, the first method is fast and can cover the entire chip layout, but it cannot accurately predict the information on the top of the photoresist. The second method is capable of outputting the complete three-dimensional morphology of the photoresist after development, but it is extremely slow due to computational complexity and cannot cover the entire chip layout.

[0058] To comprehensively improve the efficiency and accuracy of defect detection in the three-dimensional morphology of photoresist, this invention provides a method for defect detection in the three-dimensional morphology of photoresist, the specific process of which is as follows: Figure 1 As shown, Figure 1 This is a schematic flowchart of a method for detecting defects in the three-dimensional morphology of photoresist according to an embodiment of the present invention. The method for detecting defects in the three-dimensional morphology of photoresist includes at least the following steps S101 to S105.

[0059] Step S101: Select training graphics from the layout graphics of the design layout to be tested. Since the full chip design layout contains graphics of all functional areas of the chip (such as transistor gates, interconnects, vias, etc.), directly using all graphics to train the model would lead to a surge in computation, and a large number of repetitive or similar graphics would cause training redundancy. Therefore, this invention selects layout graphics to obtain layout graphics that meet the conditions as training graphics for subsequent training.

[0060] Optionally, the step of selecting training graphics from the layout graphics of the design to be tested generally includes: grouping the layout graphics according to graphic features to obtain multiple graphic groups; and selecting training graphics from the selected graphic groups. The grouping method can be pattern grouping technology, which divides the entire chip layout graphics into multiple groups according to graphic features (such as shape, line width, spacing, layer stacking relationships, etc.), ensuring that each group of graphics has similar core features. Representative graphics are then selected from each group for training. Pattern grouping techniques generally include exact grouping and fuzzy grouping. Those skilled in the art can choose the specific grouping technology for selection based on actual needs.

[0061] The training graphics selected through this step can represent the features of various graphics across the entire chip. The model trained subsequently can detect bad pixels on the overall layout without relying on the graphics across the entire chip, thus laying the foundation for efficient model training.

[0062] Step S102 involves simulating the training pattern using a pre-established physical simulation model to obtain the three-dimensional morphology of the photoresist. The physical simulation model, also known as a rigorous photolithography simulation tool, is generally used to simulate the input layout pattern to obtain the three-dimensional morphology of the photoresist. The physical simulation model is primarily based on fundamental physical principles to accurately calculate the results of each step in the photolithography process. It does not rely on extensive silicon wafer measurement data for empirical fitting, but rather directly solves the governing equations describing the physical process, and uses a very small amount of slice data and CD-SEM data to fit physical parameters to predict imaging results. Using the physical simulation model, the complete three-dimensional morphology of the photoresist after development can be accurately output. However, due to the extremely high computational complexity and slow simulation speed of the physical simulation model, it cannot be applied on a large scale. Based on the above analysis, the inventors chose to use only the physical simulation model to simulate the training pattern selected in step S101 in this invention, thereby obtaining representative training data through the physical simulation model.

[0063] Optionally, the training steps for a physical simulation model may generally include: constructing a physical simulation model framework; acquiring training data for the physical simulation model framework, including wafer slicing data and scanning electron microscope (SEM) measurement data, wherein the wafer slicing data is the slice data corresponding to the wafer sample after being processed by the same photolithography process as the design layout, and the SEM measurement data includes the image and size data obtained by measuring the wafer sample using a scanning electron microscope; and optimizing the parameters in the physical simulation model framework using the training data to obtain the physical simulation model.

[0064] The physical simulation model framework generally includes two core physical processes: an optical model of the exposure process and a photoresist model of the development process. The optical model is a mathematical model describing the light intensity distribution from the photolithography source to the mask and then to the silicon wafer surface. It simulates the diffraction of light at the mask edges, and the refraction and absorption of light within the photoresist, outputting the exposure dose distribution within the photoresist. The photoresist model is generally used to describe the morphological changes of the photoresist.

[0065] After constructing the physical simulation model framework, training data for the framework needs to be acquired. This primarily includes wafer slicing data and scanning electron microscopy (SEM) measurement data. The target lithography process corresponding to the design layout to be inspected is determined, and wafer samples processed with the same target lithography process are obtained. Subsequently, wafer slicing data of these samples is acquired. In addition, the wafer samples need to be scanned using equipment such as a critical-dimensional scanning electron microscope to obtain images and dimensional data of the photoresist on the wafer samples. Finally, the parameters in the physical simulation model framework are optimized using the training data to obtain a physical simulation model that rigorously simulates the target lithography process.

[0066] Step S103: Extract the simulated top contour of the photoresist from the 3D morphology of the photoresist. The simulated top contour of the photoresist is a necessary feature in the 3D morphology of the photoresist that is strongly correlated with defective pixels. Its core features generally include: local thickness at the top (vertical distance between the contour and the substrate), edge slope (reflecting the sidewall angle), and contour continuity (whether there are gaps or depressions). When the top of the photoresist is too thin, the edge slope is abnormal, or the contour is discontinuous, it will directly lead to the inability to effectively protect the silicon wafer during etching, resulting in defective pixels. Therefore, extracting the simulated top contour of the photoresist can retain the key basis for defective pixel detection, making subsequent model training more focused on core features, while reducing the amount of data to improve detection efficiency.

[0067] Step S104 involves training the model using the training pattern and its corresponding simulated top contour of the photoresist to obtain a photoresist defect detection model. While physical simulation models can output accurate 3D shapes, single-pattern simulation is time-consuming and cannot meet the rapid detection requirements of the entire chip. Therefore, this invention selects to train the model using the training pattern selected in step S101 and the simulated top contour of the photoresist extracted in step S103 to obtain the photoresist defect detection model. This trained photoresist defect detection model can directly and quickly predict defect areas in the top contour using the layout pattern.

[0068] In some optional embodiments, the training steps of the photoresist defect detection model may generally include: extracting feature points from the simulated contour on the top of the photoresist; determining the initial model parameters of the photoresist defect detection model; performing simulation operations on the training graphic based on the initial model parameters to obtain the simulated contour; and iteratively optimizing the initial model parameters based on the feature points and the simulated contour to obtain the photoresist defect detection model.

[0069] The feature point extraction operation typically targets the simulated contour on top of the photoresist. It uses image segmentation, edge detection, and other algorithms (such as the Canny operator and threshold segmentation) to extract the physical contour of the actual pattern on the wafer surface, i.e., the actual wafer contour, such as geometric shapes like line edges, corners, and via boundaries. Then, key feature points (point gauges) are selected from the contour, such as edge inflection points, linewidth extreme points, and boundary coordinates of defect areas. These points need to accurately reflect the process deviations of the pattern (such as linewidth shrinkage and edge concavity) and potential defect features.

[0070] The subsequent step of determining the initial model parameters for the photoresist defect detection model generally involves pre-setting the initial model parameters based on the physical laws of the patterning process. These initial model parameters can be set based on theoretical calculations or historical data from similar processes, serving as the starting point for model optimization.

[0071] The next step in the simulation operation typically involves inputting the training pattern obtained in step S101 into the photoresist defect detection model, simulating the physical process of photolithography using the initial model parameters, and finally outputting a simulated contour corresponding to the training pattern, which is the pattern shape that the wafer surface should form after the process, as predicted by the model. The simulated contour serves as a "predicted value" output by the model, providing a reference for subsequent deviation analysis from the simulated contour on top of the photoresist.

[0072] Finally, the initial model parameters are iteratively optimized based on the feature points and simulated contours to obtain the photoresist defect detection model. Optionally, the steps of iteratively optimizing the initial model parameters based on feature points and simulated contours generally include: calculating the deviation distance between each feature point and the simulated contour; generating an evaluation function corresponding to the photoresist defect detection model based on the deviation distance; and iteratively optimizing the initial model parameters until the evaluation function meets the preset convergence condition, thereby obtaining the photoresist defect detection model.

[0073] The operation of calculating the deviation distance can generally be to calculate the spatial distance (such as Euclidean distance) between each feature point in the simulated contour on the top of the photoresist and the corresponding position on the simulated contour for each feature point. This quantifies the difference between the actual process result and the model prediction result. The larger the deviation, the lower the accuracy of the model prediction.

[0074] Subsequently, an evaluation function (such as mean squared error (MSE) or mean absolute error (MAE) is constructed based on the deviation distances of all feature points to comprehensively measure the overall fit between the simulated profile and the actual wafer profile. For example, the evaluation function can be defined as "the mean of the squares of the deviation distances of all feature points," with a smaller value indicating better model prediction performance.

[0075] The iterative optimization process typically involves using optimization methods such as gradient descent and genetic algorithms to continuously adjust the initial parameters of the model (e.g., photolithography exposure dose, etching power), and regenerate the simulated profile, calculate the deviation distance, and evaluate the function value. This process is repeated until the evaluation function value is less than a preset threshold (e.g., the average deviation distance < 1 nm). At this point, the model parameters reach their optimal state, and the final photoresist defect detection model is output. By iterating, the deviation between simulation and reality is eliminated, ensuring that the prediction results of the photoresist defect detection model closely approximate the actual process conditions.

[0076] Step S105: Use the photoresist defect detection model to perform photoresist three-dimensional morphology defect detection on the design layout to obtain potential defect areas in the design layout related to the photoresist three-dimensional morphology.

[0077] The method of this invention, on the one hand, utilizes Pattern Grouping technology to more effectively sample the layout of the entire chip, thereby selecting representative layout patterns as training patterns and improving the generalization ability of the photoresist defect detection model. In actual operation, the sampling quantity is generally on the order of several thousand images. With the current speed of physical simulation models, this can be completed in about one day using about eight GPU servers on a distributed platform. On the other hand, the method of this invention leverages the complete three-dimensional lithography simulation capability of the physical simulation model. The photoresist defect detection model can have relatively accurate top morphology information of the photoresist as input, breaking through the limitation of previous ordinary OPC model modeling which only has bottom data. This allows the construction of a model that can predict the top contour of the photoresist across the entire chip, and thus predict defects related to the three-dimensional morphology of the photoresist in advance across the entire chip.

[0078] In some alternative embodiments, to further ensure the accuracy of defect detection, the present invention selects to verify the potential defect region using a physical simulation model. Therefore, after obtaining the potential defect region related to the three-dimensional morphology of the photoresist in the design layout, the method generally includes: simulating the potential defect region using a physical simulation model to obtain the three-dimensional morphology of the photoresist in the potential defect region; and detecting the three-dimensional morphology of the photoresist in the potential defect region to determine whether there are actual defects in the potential defect region. Although the physical simulation model is slow and cannot simulate the three-dimensional morphology of the photoresist across the entire chip, with the support of a distributed computing platform, it is entirely possible to perform simulations on multiple specific local locations (i.e., potential defect regions). Furthermore, the photoresist defect detection model is essentially obtained by fitting the simulation contour of a rigorous simulation model. Although it offers the speed to perform simulations across the entire chip, the accuracy will inevitably decrease compared to the original rigorous photolithography simulation tools. The discovered defects are then sent to a rigorous photolithography simulation tool for confirmation, thus forming a complete solution that involves initial screening using a photoresist defect detection model followed by fine screening using a rigorous photolithography simulation model, achieving a good balance between speed and accuracy.

[0079] Optionally, when actual defects exist in the potential defect area, the process may further include: extracting the simulated top contour of the photoresist in the defect area from the 3D morphology of the photoresist in the defect area corresponding to the actual defect; and iteratively optimizing the photoresist defect detection model using the actual defect and its corresponding simulated top contour of the photoresist in the defect area. This operation can further iteratively optimize the photoresist defect detection model, thereby improving its detection level.

[0080] Figure 2 This is a schematic flowchart of a method for detecting defects in the three-dimensional morphology of photoresist according to another embodiment of the present invention, as shown below. Figure 2As shown, the defect detection method for the three-dimensional morphology of the photoresist includes at least the following steps S201 to S208.

[0081] Step S201: Group the layout graphics in the design layout according to their graphic characteristics to obtain multiple graphic groups. The purpose of grouping is to ensure that the graphics within the same group have similar lithographic response patterns (i.e., similar sensitivity to lithography processes and defect patterns), laying the foundation for subsequent targeted training and detection.

[0082] Step S202 involves selecting training images from the chosen image groups. After grouping in step S201, it's unnecessary to train on all images (otherwise, it would lead to sample redundancy and model complexity). Instead, "representative images" (such as images that frequently appear in production or those historically prone to producing defective pixels) are selected as training samples. This focuses on key image types, reduces the amount of training data, and allows the model to prioritize learning more representative image features, improving training efficiency and relevance.

[0083] Step S203 involves simulating the training pattern using a pre-established physical simulation model to obtain the three-dimensional morphology of the photoresist. The physical simulation model is a high-precision tool built based on the principles of photolithography. For the selected training pattern, the physical simulation model simulates its morphological changes during the actual photolithography process, resulting in a final output photoresist three-dimensional morphology that most closely approximates the actual photolithography result.

[0084] Step S204: Extract the simulated top contour of the photoresist from the three-dimensional morphology of the photoresist.

[0085] Step S205: Train the model using the training image and its corresponding simulated top contour of the photoresist to obtain a photoresist defect detection model. Use the training image and its corresponding simulated top contour of the photoresist as model input, and train the model through machine learning (such as deep learning, regression models, etc.). The model will learn the mapping relationship between the training image and the top contour of the photoresist, thereby detecting defects on the simulated top contour of the photoresist.

[0086] Step S206: The photoresist defect detection model is used to perform photoresist three-dimensional morphology defect detection on the design layout to obtain potential defect areas in the design layout related to the photoresist three-dimensional morphology. Since the photoresist defect detection model has a fast simulation speed, it can be used to perform large-scale detection on the entire chip layout, thereby quickly determining potential defect areas in the design layout.

[0087] Step S207 involves simulating the potential defective area using a physical simulation model to obtain the three-dimensional morphology of the photoresist in the potential defective area. The photoresist defect detection model can quickly and roughly screen out defects related to the three-dimensional morphology across the entire chip. These initially screened defects can be input into the physical simulation model to obtain the complete three-dimensional morphology of the photoresist after development, allowing for finer screening and further defect confirmation. This achieves a good balance between speed and accuracy.

[0088] Step S208: Detect the three-dimensional morphology of the photoresist in the potential bad spot area to determine whether there are actual bad spots in the potential bad spot area.

[0089] This method organically integrates a photoresist defect detection model for rapid full-chip simulation and a physical simulation model that provides a complete three-dimensional morphology of the photoresist. On the one hand, it constructs a photoresist defect detection model based on the top contour of the photoresist provided by the rigorous photolithography simulation model, thereby quickly screening out defects related to the three-dimensional morphology of the photoresist across the entire chip. On the other hand, these coarsely screened defects are sent to the rigorous simulation model for further fine screening and confirmation. This forms a full-chip photoresist three-dimensional morphology defect prediction mechanism that leverages the photoresist defect detection model, originating from and returning to the rigorous physical simulation model. This ensures both full-chip screening and that the detected defects are judged based on a complete three-dimensional morphology, balancing the speed and accuracy of defect detection.

[0090] It should be noted that different combinations of steps involved in the solution of this invention, or the workflow formed by replacing or simplifying any step, should be considered as alternatives to this solution. For example, in this solution, pattern grouping technology is used to obtain the pattern corresponding to the top contour of the photoresist used to fit the photoresist defect detection model. Alternatively, random sampling can be used, or pattern grouping technology can be used to select representative patterns first, and then random sampling can be performed on these patterns. Or, pattern grouping technology can be used to select representative patterns first, and then a portion of patterns with relatively large differences between the top and bottom contours can be selected from these patterns.

[0091] It should be understood that in some embodiments, the components may be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods may be implemented using software or firmware stored in memory and executed by a suitable instruction execution system.

[0092] This embodiment also provides a computer program product 10, a computer-readable storage medium 20, and a computer device 30. Figure 3 This is a schematic diagram of a computer program product 10 according to an embodiment of the present invention. Figure 4This is a schematic diagram of a computer-readable storage medium 20 according to an embodiment of the present invention. Figure 5 This is a schematic diagram of a computer device 30 according to an embodiment of the present invention. The computer program product 10 includes a computer program 11, which, when executed by the processor 32, implements the steps of the defect detection method for the three-dimensional morphology of photoresist described above. A computer-readable storage medium 20 stores the computer program 11 thereon, which, when executed by the processor 32, implements the steps of the defect detection method for the three-dimensional morphology of photoresist described above. The computer device 30 may include a memory 31, a processor 32, and the computer program 11 stored in the memory 31 and running on the processor 32.

[0093] The computer program 11 used to perform the operations of this invention may be assembly instructions, Instruction Set Architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, integrated circuit configuration data, or source code or object code written in any combination of one or more programming languages ​​and procedural programming languages. The computer program 11 may execute entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer via any type of network, including a Local Area Network (LAN) or Wide Area Network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, to perform aspects of this invention, electronic circuits, including, for example, programmable logic circuits, Field-Programmable Gate Arrays (FPGAs), or Programmable Logic Arrays (PLAs), may execute computer-readable program instructions using status information from computer-readable program instructions to personalize the electronic circuits.

[0094] For the purposes of this embodiment, computer program product 10 is a related product containing computer program 11. For the purposes of this embodiment, computer-readable storage medium 20 is a tangible device capable of holding and storing computer program 11, and can be any device capable of containing, storing, communicating, propagating, or transmitting program 11 for use by or in conjunction with an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable storage medium 20 include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable optical disc read-only memory (CD-ROM), digital versatile disc (DVD), memory stick, floppy disk, mechanical encoding device, and any suitable combination thereof.

[0095] Computer device 30 can be, for example, a server, desktop computer, laptop computer, tablet computer, or smartphone. In some examples, computer device 30 can be a cloud computing node. Computer device 30 can be described in the general context of computer system executable instructions (such as program modules) executed by a computer system. Typically, program modules can include routines, programs, object programs, components, logic, data structures, etc., that perform specific tasks or implement specific abstract data types. Computer device 30 can be implemented in a distributed cloud computing environment where tasks are performed by remote processing devices linked through a communication network. In a distributed cloud computing environment, program modules can reside on local or remote computing system storage media, including storage devices.

[0096] Computer device 30 may include a processor 32 adapted to execute stored instructions and a memory 31 that provides temporary storage space for the operation of said instructions during operation. The processor 32 may be a single-core processor, a multi-core processor, a computing cluster, or any other configuration. The memory 31 may include random access memory (RAM), read-only memory, flash memory, or any other suitable storage system.

[0097] Computer device 30 may also include a network adapter / interface and an input / output (I / O) interface. The I / O interface allows external devices that can be connected to the computer device to input and output data. The network adapter / interface provides communication between the computer device and a network, typically represented as a communication network.

[0098] Therefore, those skilled in the art should recognize that although numerous exemplary embodiments of the present invention have been shown and described in detail herein, many other variations or modifications conforming to the principles of the present invention can be directly determined or derived from the disclosure of the present invention without departing from the spirit and scope of the invention. Thus, the scope of the present invention should be understood and construed as covering all such other variations or modifications.

Claims

1. A method for detecting defects in the three-dimensional morphology of photoresist, comprising: Training graphics are obtained by filtering from the layout graphics of the design layout to be tested; The training pattern is simulated using a pre-established physical simulation model to obtain the three-dimensional morphology of the photoresist. The physical simulation model is used to simulate the input layout pattern to obtain the three-dimensional morphology of the photoresist. Extract the simulated top contour of the photoresist from the three-dimensional morphology of the photoresist; The photoresist defect detection model is obtained by training the training pattern and its corresponding simulated top contour of the photoresist. The photoresist defect detection model is used to detect defects in the three-dimensional morphology of the photoresist in the design layout, thereby obtaining potential defect regions in the design layout that are related to the three-dimensional morphology of the photoresist.

2. The method for detecting defects in the three-dimensional morphology of photoresist according to claim 1, wherein, Following the step of obtaining the potential defect region related to the three-dimensional morphology of the photoresist in the design layout, the method further includes: The potential defect region was simulated using the physical simulation model to obtain the three-dimensional morphology of the photoresist in the potential defect region; The three-dimensional morphology of the photoresist in the potential defect area is inspected to determine whether there are actual defects in the potential defect area.

3. The method for detecting defects in the three-dimensional morphology of photoresist according to claim 2, further comprising, when actual defects exist in the potential defect region: Extract the simulated top contour of the photoresist in the bad spot region from the three-dimensional morphology of the photoresist in the bad spot region corresponding to the real bad spot; The photoresist defect detection model is iteratively optimized using the actual defective pixels and the corresponding simulated contour of the top of the photoresist in the defective pixel region.

4. The method for detecting defects in the three-dimensional morphology of photoresist according to claim 1, wherein, The training steps for the physical simulation model include: Construct a physical simulation model framework; The training data of the physical simulation model framework is obtained. The training data includes wafer slicing data and scanning electron microscope measurement data. The wafer slicing data is the slice data corresponding to the wafer sample after being processed by the same photolithography process as the design layout. The scanning electron microscope measurement data includes the image and size data obtained by measuring the wafer sample using a scanning electron microscope. The parameters in the physical simulation model framework are optimized using the training data to obtain the physical simulation model.

5. The method for detecting defects in the three-dimensional morphology of photoresist according to claim 1, wherein, The step of selecting training graphics from the layout graphics of the design layout to be detected includes: The graphic layout is grouped according to its graphic features to obtain multiple graphic groups; The training graphs used for training are selected from the selected group of graphs.

6. The method for detecting defects in the three-dimensional morphology of photoresist according to claim 1, wherein, The step of training the photoresist defect detection model using the training pattern and its corresponding simulated top contour of the photoresist includes: Extract feature points from the simulated contour at the top of the photoresist; Determine the initial model parameters of the photoresist defect detection model; Based on the initial model parameters, a simulated contour is obtained by performing a simulation operation on the training graphic. The initial model parameters are iteratively optimized based on the feature points and the simulated contours to obtain the photoresist defect detection model.

7. The method for detecting defects in the three-dimensional morphology of photoresist according to claim 6, wherein, The step of iteratively optimizing the initial model parameters based on the feature points and the simulated contour includes: Calculate the deviation distance between each feature point and the simulated contour; An evaluation function corresponding to the photoresist defect detection model is generated based on the deviation distance; The initial model parameters are iteratively optimized until the evaluation function meets the preset convergence condition, thereby obtaining the photoresist defect detection model.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that... When the computer program is executed by the processor, it implements the steps of the method for detecting bad pixels in the three-dimensional morphology of photoresist according to any one of claims 1 to 7.

9. A computer program product comprising a computer program that, when executed by a processor, implements the steps of the defect detection method for the three-dimensional morphology of photoresist according to any one of claims 1 to 7.

10. A computer device comprising a memory, a processor, and a machine-executable program stored in the memory and running on the processor, wherein the processor, when executing the machine-executable program, implements the steps of the method for detecting bad pixels in the three-dimensional morphology of photoresist according to any one of claims 1 to 7.

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