Current-limiting voltage stabilizing circuit and controller
By combining the first PNP transistor and the third switching transistor, the reliability problem of the current limiting circuit under load short circuit is solved, and the protection of zero output voltage and current is achieved. It can independently detect open circuit and short circuit, reduce cost and improve temperature drift characteristics.
Patent Information
- Application Number
- CN202511309048.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-12
- Publication Date
- 2025-11-11
AI Technical Summary
When the load is short-circuited, the existing current limiting circuit operates the MOSFET in the linear amplification region, and the output current remains constant, which increases the possibility of the load burning out and reduces the reliability of the circuit. In addition, the existing solution is expensive, has poor temperature drift characteristics, and cannot independently realize open circuit and short circuit detection.
The system employs a combination of a first PNP transistor, a second semiconductor transistor, and a third switching transistor. When the load is short-circuited, the third switching transistor cuts off the first PNP transistor, resulting in zero output voltage and current, thus protecting the load. Simultaneously, open-circuit and short-circuit detection are achieved through a symmetrical design and a detection module, avoiding the use of current-limiting resistors and reducing costs.
It improves circuit reliability, reduces power consumption, enables independent open-circuit and short-circuit detection, reduces component costs, adapts to different GPIO ports, and improves temperature drift characteristics.
Smart Images
Figure CN120928898A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of circuits, and more particularly to a current-limiting voltage regulator circuit and controller. Background Technology
[0002] With the continuous development of technology, current limiting circuits have been widely used in various electronic devices to protect them and increase reliability. In existing solutions, the current limiting main switch is usually a MOSFET, and a current limiting resistor and another MOSFET are set on the input side. The voltage is supplied to the load by controlling the MOSFET, which acts as the main switch.
[0003] However, in the existing scheme, when the load is short-circuited, both MOSFETs operate in the linear amplification region. The output current remains constant due to the current-limiting resistor, and the load still has output current flowing through it. This greatly increases the possibility of the load burning out and reduces the reliability of the circuit. Summary of the Invention
[0004] This application provides a current-limiting voltage regulator circuit and controller for protecting the load.
[0005] The first aspect of this application provides a current-limiting voltage regulator circuit, including: a first semiconductor transistor, a second semiconductor transistor, a third semiconductor transistor, and a first resistor, wherein the first semiconductor transistor is a first PNP transistor, which is provided with an emitter, a collector, and a base; the second semiconductor transistor is provided with an input terminal and an output terminal; and the third semiconductor transistor is a third switching transistor, which is provided with a current input terminal, a current output terminal, and a control terminal.
[0006] The emitter of the first PNP transistor is connected to the input terminal of the second semiconductor transistor, the collector of the first PNP transistor is connected to the control terminal of the third switch transistor, the base of the first PNP transistor is connected to the current input terminal of the third switch transistor, the output terminal of the second semiconductor transistor is connected to the current output terminal of the third switch transistor and one end of the first resistor, the other end of the first resistor is grounded, the emitter of the first PNP transistor is connected to the total input terminal of the circuit, and the collector of the first PNP transistor is connected to the total output terminal of the circuit.
[0007] Optionally, the circuit further includes: a first capacitor;
[0008] One end of the first capacitor is connected to the input terminal of the second semiconductor transistor, and the other end of the first capacitor is connected to the control terminal of the third switching transistor.
[0009] Optionally, the circuit further includes a ninth semiconductor transistor and a tenth semiconductor transistor, wherein both the ninth semiconductor transistor and the tenth semiconductor transistor are provided with an input terminal and an output terminal;
[0010] Wherein, the emitter of the first PNP transistor is connected to the input terminal of the ninth semiconductor transistor, and the output terminal of the ninth semiconductor transistor is connected to the input terminal of the second semiconductor transistor, so that the emitter of the first PNP transistor is connected to the input terminal of the second semiconductor transistor.
[0011] The collector of the first PNP transistor is connected to the input terminal of the tenth semiconductor transistor, and the output terminal of the tenth semiconductor transistor is connected to the control terminal of the third switch transistor, so that the collector of the first PNP transistor is connected to the control terminal of the third switch transistor.
[0012] Optionally, the ninth semiconductor tube is a ninth diode, with the anode of the ninth diode serving as the input terminal and the cathode of the ninth diode serving as the output terminal; or, the ninth semiconductor tube is a ninth transistor, with the base and collector of the ninth transistor connected, the collector of the ninth transistor serving as the input terminal and the emitter of the ninth transistor serving as the output terminal.
[0013] The tenth semiconductor transistor is a tenth diode, with its anode serving as the input terminal and its cathode serving as the output terminal; or, the tenth semiconductor transistor is a thirteenth diode, with its base and collector connected, its collector serving as the input terminal and its emitter serving as the output terminal.
[0014] Optionally, the circuit may further include: a control module and / or a twelfth resistor;
[0015] The control module is connected to the control terminal of the third switching transistor, and the control module is used to control the third switching transistor to turn on or off.
[0016] The base of the first PNP transistor is connected to one end of the twelfth resistor, and the other end of the twelfth resistor is connected to the current input terminal of the third switch, so that the base of the first PNP transistor is connected to the current input terminal of the third switch.
[0017] Optionally, the second semiconductor transistor is a second diode, with the anode of the second diode serving as the input terminal and the cathode of the second diode serving as the output terminal; or, the second semiconductor transistor is a second NPN transistor, with the base and collector of the second NPN transistor connected, the collector of the second NPN transistor serving as the input terminal and the emitter of the second NPN transistor serving as the output terminal; or, the second semiconductor transistor is a second Darlington transistor, with the base and collector of the second Darlington transistor connected, the collector of the second Darlington transistor serving as the input terminal and the emitter of the second Darlington transistor serving as the output terminal.
[0018] The third switching transistor is a third NPN transistor, with its base serving as the control terminal, its collector serving as the current input terminal, and its emitter serving as the current output terminal. Alternatively, the third switching transistor is a third Darlington transistor, with its base serving as the control terminal, its collector serving as the current input terminal, and its emitter serving as the current output terminal.
[0019] Optionally, the circuit further includes: a fourth semiconductor transistor, a fifth semiconductor transistor, a third resistor, a fourth resistor, and a detection module, wherein the fourth semiconductor transistor is provided with an input terminal and an output terminal, the fifth semiconductor transistor is a fifth switching transistor and is provided with a current input terminal, a current output terminal, and a control terminal, and the detection module is provided with an input terminal and an output terminal;
[0020] The input terminal of the fourth semiconductor transistor is connected to the total input terminal. The output terminal of the fourth semiconductor transistor is connected to the base of the fifth switching transistor and one end of the third resistor, respectively. The other end of the third resistor is grounded. The current input terminal of the fifth switching transistor is connected to the total output terminal. The current output terminal of the fifth switching transistor is connected to the input terminal of the detection module and one end of the fourth resistor, respectively. The other end of the fourth resistor is grounded. The output terminal of the detection module is connected to the open-circuit signal detection terminal of the external device.
[0021] Optionally, the detection module includes: a sixth PNP transistor, a seventh NPN transistor, a fifth resistor, a sixth resistor, a seventh resistor, and an eighth resistor;
[0022] The base of the sixth PNP transistor serves as the input terminal of the detection module. The emitter of the sixth PNP transistor is connected to the collector of the seventh NPN transistor via the eighth resistor. The emitter of the sixth PNP transistor is also connected to the power supply module outside the circuit. The collector of the sixth PNP transistor is connected to one end of the fifth resistor and one end of the sixth resistor, respectively. The other end of the fifth resistor is grounded. The other end of the sixth resistor is connected to the base of the seventh NPN transistor and one end of the seventh resistor, respectively. The other end of the seventh resistor and the emitter of the seventh NPN transistor are both grounded.
[0023] Optionally, the fourth semiconductor transistor is a fourth diode, with the anode of the fourth diode serving as the input terminal and the cathode of the fourth diode serving as the output terminal; or, the fourth semiconductor transistor is a fourth PNP transistor, with the base and collector of the fourth PNP transistor connected, the collector of the fourth PNP transistor serving as the output terminal and the emitter of the fourth PNP transistor serving as the input terminal; or, the fourth semiconductor transistor is a fourth Darlington transistor, with the base and collector of the fourth Darlington transistor connected, the collector of the fourth Darlington transistor serving as the output terminal and the emitter of the fourth Darlington transistor serving as the input terminal.
[0024] The fifth switching transistor is a fifth PNP transistor, with its base serving as the control terminal, its collector serving as the current output terminal, and its emitter serving as the current input terminal. Alternatively, the fifth switching transistor is a fifth Darlington transistor, with its base serving as the control terminal, its collector serving as the current output terminal, and its emitter serving as the current input terminal.
[0025] Optionally, the circuit further includes: an eighth NPN transistor, a ninth resistor, a tenth resistor, and an eleventh resistor;
[0026] One end of the ninth resistor is connected to the total output terminal, and the other end of the ninth resistor is connected to the base of the eighth NPN transistor and one end of the tenth resistor. The other end of the tenth resistor and the emitter of the eighth NPN transistor are both grounded. The collector of the eighth NPN transistor is connected to the power supply module outside the circuit through the eleventh resistor. The collector of the eighth NPN transistor is connected to the short-circuit signal detection terminal of the device outside the circuit.
[0027] The second aspect of this application provides a controller, including the current limiting and voltage regulating circuit as described above, and further including: a first power supply and a second power supply;
[0028] The first power supply is connected to the total input terminal of the current limiting and voltage regulating circuit, the second power supply is connected to the current limiting and voltage regulating circuit, and the total output terminal of the current limiting and voltage regulating circuit is connected to the load outside the controller. The input voltages provided by the first power supply and the second power supply are different.
[0029] As can be seen from the above technical solutions, the embodiments of this application have the following advantages:
[0030] The current-limiting and voltage-regulating circuit of this application includes a first PNP transistor, a second semiconductor transistor, and a third switching transistor. The first PNP transistor is the main switch, the second semiconductor transistor is on the input side, and the third switching transistor is on the output side. When the load is short-circuited and overcurrent occurs, the third switching transistor enables the gate of the first PNP transistor to be at a high level, thus turning off the first PNP transistor. This results in zero output voltage and zero output current, protecting the load and improving the reliability of the circuit. Attached Figure Description
[0031] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained based on these drawings.
[0032] Figure 1 This is a schematic diagram of an embodiment of a current-limiting voltage regulator circuit disclosed in this application;
[0033] Figure 2 This is a schematic diagram of another embodiment of a current-limiting voltage regulator circuit disclosed in this application;
[0034] Figure 3 This is a schematic diagram of an embodiment of the current limiting section in the current limiting voltage regulator circuit disclosed in this application;
[0035] Figure 4 This is a schematic diagram of another embodiment of the current limiting part in the current limiting voltage regulator circuit disclosed in this application;
[0036] Figure 5 This is a schematic diagram of the open-circuit detection section in the current-limiting and voltage-regulating circuit disclosed in this application;
[0037] Figure 6 This is a schematic diagram of the short-circuit detection section in the current-limiting voltage regulator circuit disclosed in this application;
[0038] Figure 7 This is a schematic diagram illustrating the relationship between output current and output voltage disclosed in this application;
[0039] Figure 8 This is another schematic diagram illustrating the relationship between output current and output voltage disclosed in this application;
[0040] Figure 9 This is a schematic diagram showing the relationship between the open-circuit signal detection terminal voltage and the output voltage and time, respectively, in this application.
[0041] Figure 10 This is a schematic diagram showing the relationship between the short-circuit signal detection terminal voltage and the output voltage and time, respectively, in this application.
[0042] Figure 11 This is a schematic diagram of the temperature drift characteristics when the load resistance is 10kΩ as disclosed in this application.
[0043] Figure 12 This is a schematic diagram of the temperature drift characteristics when the load resistance is 100Ω as disclosed in this application.
[0044] Figure 13 This is a schematic diagram of the temperature drift characteristics when the load resistance is 5Ω as disclosed in this application.
[0045] Figure 14 This is a schematic diagram of one embodiment of a controller disclosed in this application. Detailed Implementation
[0046] The present application will be further described in detail below with reference to the accompanying drawings.
[0047] This application provides a current-limiting voltage regulator circuit and controller for protecting the load.
[0048] In devices such as cameras, antennas, or ultrasonic probes connected to an in-vehicle domain controller, current-limiting circuits are typically installed to ensure device safety. In existing current-limiting circuits, the main current-limiting switch is usually a MOSFET, with a current-limiting resistor and another MOSFET on the input side. The voltage is supplied to the load by controlling the MOSFET acting as the main switch. However, in existing solutions, when the load is short-circuited, both MOSFETs operate in the linear amplification region. The output current remains constant due to the current-limiting resistor, but the load still experiences output current flow, significantly increasing the likelihood of load burnout and reducing circuit reliability. Furthermore, the main switch operating in the linear amplification region results in high power consumption, and within a certain range, the output voltage decreases as the load resistance decreases, potentially causing abnormal power supply to the load-side devices. Moreover, existing solutions have poor temperature drift characteristics and require a current-limiting resistor, resulting in the output voltage being at least 0.7V lower than the input voltage. They also do not support open-circuit and short-circuit detection; achieving detection requires relying on relevant diagnostic fault codes, meaning the controller must be able to report the connection status of peripherals. Furthermore, existing solutions involve specialized components and chips with poor substitutability and high cost, causing inconvenience to users. To address these issues, this application provides a current-limiting voltage regulator circuit and controller. When the load experiences a short circuit or overcurrent, the output voltage and current values become zero, protecting the load. The circuit uses conventional components, resulting in low cost and high substitutability. Its small size reduces area, and it exhibits good temperature drift characteristics. Open-circuit and short-circuit detection can be implemented independently without software. The output voltage is close to the input voltage and does not change with current or load variations, improving circuit reliability. Additionally, the main switch operates only in the saturation or cutoff region, resulting in low power consumption and eliminating the need for a current-limiting resistor, ensuring stable output voltage. It is also compatible with different GPIO ports, providing significant convenience to users.
[0049] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.
[0050] The terms "first," "fourth," "fifth," "second," etc., used in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.
[0051] The following describes a current-limiting voltage regulator circuit according to this application. Please refer to... Figure 1 An embodiment of a current-limiting voltage regulator circuit of this application includes: a first semiconductor transistor, a second semiconductor transistor, a third semiconductor transistor and a first resistor, wherein the first semiconductor transistor is a first PNP transistor and is provided with an emitter, a collector and a base, the second semiconductor transistor is provided with an input terminal and an output terminal, and the third semiconductor transistor is a third switching transistor and is provided with a current input terminal, a current output terminal and a control terminal;
[0052] The emitter of the first PNP transistor is connected to the input terminal of the second semiconductor transistor, the collector of the first PNP transistor is connected to the control terminal of the third switch transistor, the base of the first PNP transistor is connected to the current input terminal of the third switch transistor, the output terminal of the second semiconductor transistor is connected to the current output terminal of the third switch transistor and one end of the first resistor, the other end of the first resistor is grounded, the emitter of the first PNP transistor is connected to the total input terminal of the circuit, and the collector of the first PNP transistor is connected to the total output terminal of the circuit.
[0053] The working principle of this embodiment will now be explained. When the load requires an output voltage, the third switch will cause the gate of the first PNP transistor to be at a low level, so the first PNP transistor is in the saturation region and is turned on. At this time, the input voltage is approximately equal to the output voltage. When the load needs overcurrent protection, the third switch will cause the gate of the first PNP transistor to be at a high level, so the first PNP transistor is turned off and the output voltage drops to zero.
[0054] In this embodiment, the current-limiting and voltage-regulating circuit includes a first PNP transistor, a second semiconductor transistor, and a third switching transistor. The first PNP transistor is the main switch, the second semiconductor transistor is on the input side, and the third switching transistor is on the output side. When the load experiences a short circuit and overcurrent, the third switching transistor enables the gate of the first PNP transistor to be at a high level, cutting off the first PNP transistor and thus making the output voltage and output current zero, protecting the load and improving the reliability of the circuit.
[0055] Please see Figures 2 to 13 Another embodiment of a current-limiting voltage regulator circuit of this application includes: a first semiconductor transistor, a second semiconductor transistor, a third semiconductor transistor, and a first resistor R1, wherein the first semiconductor transistor is a first PNP transistor Q1, which is provided with an emitter, a collector, and a base; the second semiconductor transistor is provided with an input terminal and an output terminal; and the third semiconductor transistor is a third switching transistor, which is provided with a current input terminal, a current output terminal, and a control terminal.
[0056] The emitter of the first PNP transistor Q1 is connected to the input terminal of the second semiconductor transistor. The collector of the first PNP transistor Q1 is connected to the control terminal of the third switching transistor. The base of the first PNP transistor Q1 is connected to the current input terminal of the third switching transistor. The output terminal of the second semiconductor transistor is connected to the current output terminal of the third switching transistor and one end of the first resistor R1. The other end of the first resistor R1 is grounded. The emitter of the first PNP transistor Q1 is connected to the total input terminal of the circuit, and the collector of the first PNP transistor Q1 is connected to the total output terminal of the circuit. Additionally, the external first power supply V1 is connected to the total input terminal.
[0057] If there is a resistor in the load (i.e., the second resistor R2) and no capacitive load, in order to power on the circuit, the circuit also includes: the first capacitor C1;
[0058] One end of the first capacitor C1 is connected to the input terminal of the second semiconductor transistor, and the other end of the first capacitor C1 is connected to the control terminal of the third switching transistor.
[0059] If the load includes not only the second resistor R2 but also a capacitive load (i.e., the second capacitor C2), please refer to [link to relevant documentation] for power-on instructions. Figure 3 The circuit also includes a ninth semiconductor transistor and a tenth semiconductor transistor, wherein both the ninth semiconductor transistor and the tenth semiconductor transistor are provided with input terminals and output terminals;
[0060] In this configuration, the emitter of the first PNP transistor Q1 is connected to the input terminal of the ninth semiconductor transistor, and the output terminal of the ninth semiconductor transistor is connected to the input terminal of the second semiconductor transistor, so that the emitter of the first PNP transistor Q1 is connected to the input terminal of the second semiconductor transistor.
[0061] In this configuration, the collector of the first PNP transistor Q1 is connected to the input terminal of the tenth semiconductor transistor, and the output terminal of the tenth semiconductor transistor is connected to the control terminal of the third switch transistor, so that the collector of the first PNP transistor Q1 is connected to the control terminal of the third switch transistor.
[0062] This embodiment is illustrated with the case where there is both a resistive load (second resistor R2) and a capacitive load (second capacitor C2).
[0063] The ninth semiconductor transistor can be implemented in at least two ways: It can be a ninth diode D9, with the anode of D9 serving as its input and the cathode as its output; or it can be a ninth transistor, with its base and collector connected, the collector serving as its input and the emitter as its output. This embodiment uses the ninth diode D9 as an example.
[0064] The tenth semiconductor transistor can be implemented in at least two ways: either the tenth semiconductor transistor is a tenth diode D10, with the anode of D10 serving as its input terminal and the cathode as its output terminal; or the tenth semiconductor transistor is a tenth thirteenth transistor, with its base and collector connected, the collector serving as its input terminal and the emitter as its output terminal. This embodiment uses the tenth diode D10 as an example.
[0065] It is understandable that the third switch can be externally powered on, and a resistor can be added to bias the first PNP transistor Q1 to achieve the foldback characteristic. For details, please refer to [link to relevant documentation]. Figure 4 The circuit also includes: a control module (not shown) and / or a twelfth resistor R12;
[0066] The control module is connected to the control terminal of the third switching transistor. The control module is used to control the third switching transistor to turn on or off, thereby powering on the third switching transistor.
[0067] In this configuration, the base of the first PNP transistor Q1 is connected to one end of the twelfth resistor R12, and the other end of the twelfth resistor R12 is connected to the current input terminal of the third switch transistor, so that the base of the first PNP transistor Q1 is connected to the current input terminal of the third switch transistor, thereby achieving the foldback characteristic.
[0068] exist Figure 3 and Figure 4 In the two corresponding implementation methods, this embodiment uses... Figure 3 Let's illustrate with examples.
[0069] The second semiconductor transistor can be implemented in at least three ways: 1) as a second diode, with the anode of the second diode serving as its input terminal and the cathode as its output terminal; 2) as a second NPN transistor Q2, with its base and collector connected, the collector serving as its input terminal and the emitter as its output terminal; 3) as a second Darlington transistor, with its base and collector connected, the collector serving as its input terminal and the emitter as its output terminal. This embodiment uses the second NPN transistor Q2 as an example.
[0070] The third switching transistor can be implemented in at least two ways: First, the third switching transistor is a third NPN transistor Q3, with its base serving as the control terminal, its collector as the current input terminal, and its emitter as the current output terminal. Second, the third switching transistor is a third Darlington transistor, with its base serving as the control terminal, its collector as the current input terminal, and its emitter as the current output terminal. This embodiment uses the third NPN transistor Q3 as an example.
[0071] For details on how to perform open-circuit detection, please refer to [link / reference]. Figure 5 The circuit also includes: a fourth semiconductor transistor, a fifth semiconductor transistor, a third resistor R3, a fourth resistor R4, and a detection module. The fourth semiconductor transistor is provided with an input terminal and an output terminal. The fifth semiconductor transistor is a fifth switching transistor and is provided with a current input terminal, a current output terminal, and a control terminal. The detection module is provided with an input terminal and an output terminal.
[0072] The input terminal of the fourth semiconductor transistor is connected to the total input terminal. The output terminal of the fourth semiconductor transistor is connected to the base of the fifth switching transistor and one end of the third resistor R3, respectively. The other end of the third resistor R3 is grounded. The current input terminal of the fifth switching transistor is connected to the total output terminal. The current output terminal of the fifth switching transistor is connected to the input terminal of the detection module and one end of the fourth resistor R4, respectively. The other end of the fourth resistor R4 is grounded. The output terminal of the detection module is connected to the open-circuit signal detection terminal OC_Int of the external device.
[0073] The detection module can be implemented in various ways, and no specific implementation is limited here. In one implementation, the detection module includes: a sixth PNP transistor Q6, a seventh NPN transistor Q7, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, and an eighth resistor R8.
[0074] The base of the sixth PNP transistor Q6 serves as the input terminal of the detection module. The emitter of Q6 is connected to the collector of the seventh NPN transistor Q7 via the eighth resistor R8. The emitter of Q6 is also connected to an external power supply module. The collector of Q6 is connected to one end of the fifth resistor R5 and one end of the sixth resistor R6, with the other end of R5 grounded. The other end of R6 is connected to the base of the seventh NPN transistor Q7 and one end of the seventh resistor R7, with the other end of R7 and the emitter of Q7 both grounded. The emitter of R6 is connected to an external second power supply V2.
[0075] The fourth semiconductor transistor can be implemented in at least three ways: 1) as a fourth diode, with the anode of the fourth diode serving as the input terminal and the cathode as the output terminal; 2) as a fourth PNP transistor Q4, with its base and collector connected, the collector serving as the output terminal and the emitter serving as the input terminal; 3) as a fourth Darlington transistor, with its base and collector connected, the collector serving as the output terminal and the emitter serving as the input terminal. This embodiment uses a fourth PNP transistor Q4 as an example.
[0076] The fifth switching transistor can be implemented in at least three ways: First, the fifth switching transistor is a fifth PNP transistor Q5, with its base serving as the control terminal, its collector as the current output terminal, and its emitter as the current input terminal. Second, the fifth switching transistor is a fifth Darlington transistor, with its base serving as the control terminal, its collector as the current output terminal, and its emitter as the current input terminal. This embodiment uses the fifth PNP transistor Q5 as an example.
[0077] For details on short-circuit detection, please refer to [link / reference]. Figure 6 The circuit also includes: the eighth NPN transistor Q8, the ninth resistor R9, the tenth resistor R10, and the eleventh resistor R11;
[0078] One end of the ninth resistor R9 is connected to the total output terminal. The other end of the ninth resistor R9 is connected to the base of the eighth NPN transistor Q8 and one end of the tenth resistor R10. The other end of the tenth resistor R10 and the emitter of the eighth NPN transistor Q8 are both grounded. The collector of the eighth NPN transistor Q8 is connected to the power supply module outside the circuit through the eleventh resistor R11. The collector of the eighth NPN transistor Q8 is connected to the short-circuit signal detection terminal SC_Int of the device outside the circuit.
[0079] Now, regarding this embodiment Figure 3The working principle is illustrated with an example. Diodes D9 and D10 are of the same model. On one hand, they isolate the total output terminal from the first capacitor C1, ensuring startup even with the second capacitor C2 present. On the other hand, they form a symmetrical structure with the second NPN transistor Q2 and the third NPN transistor Q3, providing an approximate voltage bias to ensure the output voltage is close to the input voltage. The first resistor R1 provides bias to prevent overcurrent. When the load requires power, the first power supply V1 supplies power, and a pulse is sent to the gate of the third NPN transistor Q3 through the first capacitor C1. The third NPN transistor Q3 conducts, and the second NPN transistor Q2 conducts. The first NPN transistor is in the saturation region and conducts. Because the second NPN transistor Q2 and the third NPN transistor Q3 are symmetrical, they form a comparator to compare the input and output voltages, so the input voltage is approximately equal to the output voltage. When the load experiences overcurrent, the third NPN transistor Q3 is turned off, and the first PNP transistor Q1 is also turned off, resulting in zero output voltage and zero output current.
[0080] Now, regarding this embodiment Figure 5 The working principle is illustrated with an example. The fourth and fifth NPN transistors form a symmetrical structure. When the load is open, the fifth NPN transistor is turned on, the sixth NPN transistor is turned off, and the seventh NPN transistor Q7 is also turned off. The open-circuit signal detection terminal OC_Int is at a high level. When the load is not open, the sixth NPN transistor is turned on, and then the seventh NPN transistor Q7 is turned on. The open-circuit signal detection terminal OC_Int is at a low level.
[0081] Now, regarding this embodiment Figure 6 The working principle is illustrated with an example. When the load is overcurrent, the output voltage is zero, and the short-circuit signal detection terminal SC_Int is at a high level. When the load is not overcurrent, the output voltage is not zero and is close to the input voltage, so the second NPN transistor is turned on, and the short-circuit signal detection terminal SC_Int is at a low level.
[0082] As can be seen, this embodiment has the following effects:
[0083] 1) Please refer to Figure 7 Due to its symmetrical design, the output voltage is essentially equal to the input voltage and will not drop significantly with increasing output current. The output voltage does not enter the uncertain region of the load power supply, ensuring the stability of the load-side equipment.
[0084] 2) Please refer to Figure 8 Due to the symmetrical design and the bias of the first resistor R1, when the load resistance decreases, the output current increases, and the output voltage moves linearly from point A to point B, reaching the current limiting protection threshold. When the load resistance decreases further, such as in the event of a short circuit, the voltage will jump directly from point B to point C (indicated by the thin line), the first PNP transistor Q1 will turn off, the output voltage will be zero, the output current will be zero, protecting the load and reducing the power consumption of the MOSFET.
[0085] 3) No current-limiting sampling resistor is required, making the output voltage approximately equal to the input voltage, which is closer to the ideal situation.
[0086] 4) Please refer to Figure 9 It supports open-circuit detection. When the second resistor R2 is 1000Ω, the open-circuit signal detection terminal OC_Int outputs a high level, and when the second resistor R2 is 100Ω, the open-circuit signal detection terminal OC_Int outputs a low level.
[0087] 5) Please refer to Figure 10 It supports short-circuit detection. When the second resistor R2 is 50Ω, the short-circuit signal detection terminal SC_Int outputs a low level. When the second resistor R2 is 5Ω, the short-circuit signal detection terminal SC_Int outputs a high level, and the output voltage drops to zero.
[0088] 6) Please refer to Figures 11 to 13 It exhibits good temperature drift characteristics under different load resistance values.
[0089] 7) The components involved in the circuit are low-cost and easily replaceable.
[0090] 8) Wide operating voltage range, applicable to 5V, 12V or 24V, etc.
[0091] In this embodiment, the current-limiting and voltage-regulating circuit includes a first PNP transistor Q1, a second semiconductor transistor, and a third switching transistor. The first PNP transistor Q1 is the main switch, the second semiconductor transistor is on the input side, and the third switching transistor is on the output side. When the load experiences a short circuit and overcurrent, the third switching transistor ensures that the gate of the first PNP transistor Q1 is at a high level, causing Q1 to be cut off. This results in zero output voltage and current, protecting the load and improving circuit reliability. It also enables open-circuit and short-circuit detection, ensuring circuit safety.
[0092] The above describes a current-limiting and voltage-regulating circuit according to an embodiment of this application. The following describes a controller according to an embodiment of this application. Please refer to... Figure 14 One embodiment of the controller in this application includes the current limiting and voltage regulating circuit described above, and further includes: a first power supply V1 and a second power supply V2;
[0093] The first power supply V1 is connected to the main input terminal of the current-limiting and voltage-regulating circuit, and the second power supply V2 is connected to the current-limiting and voltage-regulating circuit. The main output terminal of the current-limiting and voltage-regulating circuit is connected to the external load of the controller. The input voltages provided by the first power supply V1 and the second power supply V2 are different. The first power supply V1 can be 5V or 12V, etc., and the second power supply V2 can be 1.8V or 3.3V, etc., without being limited here.
[0094] The working principle of this embodiment will now be explained. Both the first power supply V1 and the second power supply V2 can supply power to the current limiting and voltage regulating circuit, which provides output voltage and output current to the load.
[0095] In this embodiment, the current-limiting and voltage-regulating circuit can provide output voltage, detect open circuits and short circuits, thereby improving the reliability of the controller.
[0096] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing embodiments, and will not be repeated here.
[0097] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces, or indirect coupling or communication connection between apparatuses or units, and may be electrical, mechanical, or other forms.
[0098] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.
[0099] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.
[0100] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit it. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this invention.
Claims
1. A current-limiting and voltage-regulating circuit, characterized in that, include: The transistor comprises a first semiconductor transistor, a second semiconductor transistor, a third semiconductor transistor, and a first resistor. The first semiconductor transistor is a first PNP transistor, which has an emitter, a collector, and a base. The second semiconductor transistor has an input terminal and an output terminal. The third semiconductor transistor is a third switching transistor, which has a current input terminal, a current output terminal, and a control terminal. The emitter of the first PNP transistor is connected to the input terminal of the second semiconductor transistor, the collector of the first PNP transistor is connected to the control terminal of the third switch transistor, the base of the first PNP transistor is connected to the current input terminal of the third switch transistor, the output terminal of the second semiconductor transistor is connected to the current output terminal of the third switch transistor and one end of the first resistor, the other end of the first resistor is grounded, the emitter of the first PNP transistor is connected to the total input terminal of the circuit, and the collector of the first PNP transistor is connected to the total output terminal of the circuit.
2. The current-limiting and voltage-regulating circuit according to claim 1, characterized in that, The circuit also includes: a first capacitor; One end of the first capacitor is connected to the input terminal of the second semiconductor transistor, and the other end of the first capacitor is connected to the control terminal of the third switching transistor.
3. The current-limiting and voltage-regulating circuit according to claim 2, characterized in that, The circuit further includes a ninth semiconductor transistor and a tenth semiconductor transistor, wherein both the ninth semiconductor transistor and the tenth semiconductor transistor are provided with an input terminal and an output terminal; Wherein, the emitter of the first PNP transistor is connected to the input terminal of the ninth semiconductor transistor, and the output terminal of the ninth semiconductor transistor is connected to the input terminal of the second semiconductor transistor, so that the emitter of the first PNP transistor is connected to the input terminal of the second semiconductor transistor. In this configuration, the collector of the first PNP transistor is connected to the input terminal of the tenth semiconductor transistor, and the output terminal of the tenth semiconductor transistor is connected to the control terminal of the third switch transistor, so that the collector of the first PNP transistor is connected to the control terminal of the third switch transistor.
4. The current-limiting and voltage-regulating circuit according to claim 3, characterized in that, The ninth semiconductor tube is a ninth diode, with the anode of the ninth diode serving as the input terminal and the cathode of the ninth diode serving as the output terminal; or, the ninth semiconductor tube is a ninth transistor, with the base and collector of the ninth transistor connected, the collector of the ninth transistor serving as the input terminal and the emitter of the ninth transistor serving as the output terminal. The tenth semiconductor transistor is a tenth diode, with its anode serving as the input terminal and its cathode serving as the output terminal; or, the tenth semiconductor transistor is a thirteenth diode, with its base and collector connected, its collector serving as the input terminal and its emitter serving as the output terminal.
5. The current-limiting and voltage-regulating circuit according to claim 1, characterized in that, The circuit also includes: a control module and / or a twelfth resistor; The control module is connected to the control terminal of the third switching transistor, and the control module is used to control the third switching transistor to turn on or off. The base of the first PNP transistor is connected to one end of the twelfth resistor, and the other end of the twelfth resistor is connected to the current input terminal of the third switch, so that the base of the first PNP transistor is connected to the current input terminal of the third switch.
6. The current-limiting and voltage-regulating circuit according to claim 1, characterized in that, The second semiconductor transistor is a second diode, with its anode serving as the input terminal and its cathode serving as the output terminal; or, the second semiconductor transistor is a second NPN transistor, with its base and collector connected, its collector serving as the input terminal and its emitter serving as the output terminal; or, the second semiconductor transistor is a second Darlington transistor, with its base and collector connected, its collector serving as the input terminal and its emitter serving as the output terminal. The third switching transistor is a third NPN transistor, with its base serving as the control terminal, its collector serving as the current input terminal, and its emitter serving as the current output terminal. Alternatively, the third switching transistor is a third Darlington transistor, with its base serving as the control terminal, its collector serving as the current input terminal, and its emitter serving as the current output terminal.
7. The current-limiting and voltage-regulating circuit according to claim 1, characterized in that, The circuit further includes: a fourth semiconductor transistor, a fifth semiconductor transistor, a third resistor, a fourth resistor, and a detection module. The fourth semiconductor transistor is provided with an input terminal and an output terminal. The fifth semiconductor transistor is a fifth switching transistor and is provided with a current input terminal, a current output terminal, and a control terminal. The detection module is provided with an input terminal and an output terminal. The input terminal of the fourth semiconductor transistor is connected to the total input terminal. The output terminal of the fourth semiconductor transistor is connected to the base of the fifth switching transistor and one end of the third resistor, respectively. The other end of the third resistor is grounded. The current input terminal of the fifth switching transistor is connected to the total output terminal. The current output terminal of the fifth switching transistor is connected to the input terminal of the detection module and one end of the fourth resistor, respectively. The other end of the fourth resistor is grounded. The output terminal of the detection module is connected to the open-circuit signal detection terminal of the external device.
8. The current-limiting and voltage-regulating circuit according to claim 7, characterized in that, The detection module includes: a sixth PNP transistor, a seventh NPN transistor, a fifth resistor, a sixth resistor, a seventh resistor, and an eighth resistor; The base of the sixth PNP transistor serves as the input terminal of the detection module. The emitter of the sixth PNP transistor is connected to the collector of the seventh NPN transistor via the eighth resistor. The emitter of the sixth PNP transistor is also connected to the power supply module outside the circuit. The collector of the sixth PNP transistor is connected to one end of the fifth resistor and one end of the sixth resistor, respectively. The other end of the fifth resistor is grounded. The other end of the sixth resistor is connected to the base of the seventh NPN transistor and one end of the seventh resistor, respectively. The other end of the seventh resistor and the emitter of the seventh NPN transistor are both grounded.
9. The current-limiting and voltage-regulating circuit according to claim 7, characterized in that, The fourth semiconductor transistor is a fourth diode, with its anode serving as the input terminal and its cathode serving as the output terminal; or, the fourth semiconductor transistor is a fourth PNP transistor, with its base and collector connected, its collector serving as the output terminal and its emitter serving as the input terminal; or, the fourth semiconductor transistor is a fourth Darlington transistor, with its base and collector connected, its collector serving as the output terminal and its emitter serving as the input terminal. The fifth switching transistor is a fifth PNP transistor, with its base serving as the control terminal, its collector serving as the current output terminal, and its emitter serving as the current input terminal. Alternatively, the fifth switching transistor is a fifth Darlington transistor, with its base serving as the control terminal, its collector serving as the current output terminal, and its emitter serving as the current input terminal.
10. The current-limiting and voltage-regulating circuit according to claim 1, characterized in that, The circuit also includes: an eighth NPN transistor, a ninth resistor, a tenth resistor, and an eleventh resistor; One end of the ninth resistor is connected to the total output terminal, and the other end of the ninth resistor is connected to the base of the eighth NPN transistor and one end of the tenth resistor. The other end of the tenth resistor and the emitter of the eighth NPN transistor are both grounded. The collector of the eighth NPN transistor is connected to the power supply module outside the circuit through the eleventh resistor. The collector of the eighth NPN transistor is connected to the short-circuit signal detection terminal of the device outside the circuit.
11. A controller, characterized in that, The circuit includes the current limiting and voltage regulating circuit as described in any one of claims 1 to 10, and further includes: a first power supply and a second power supply; The first power supply is connected to the total input terminal of the current limiting and voltage regulating circuit, the second power supply is connected to the current limiting and voltage regulating circuit, and the total output terminal of the current limiting and voltage regulating circuit is connected to the load outside the controller. The input voltages provided by the first power supply and the second power supply are different.