Nonvolatile memory device, memory system, and method for operating memory system

Abstract

The invention provides a nonvolatile memory device, a memory system, and an operating method of the memory system. The operating method includes loading first information data read (IDR) data stored in a non-volatile memory device into a memory controller when the memory system is powered on; opening the metadata by using the loaded first IDR data through the storage controller; checking environment information of each of the plurality of non-volatile memory devices; selecting subsequent IDR data corresponding to the detected environment information from the plurality of subsequent IDR data; and loading the subsequent IDR data from the non-volatile memory device into the memory controller.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2024-0062028, filed on May 10, 2024, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present invention relates to a storage system including a non-volatile memory device and a method of operating the storage system. Background Technology

[0003] A storage system is a memory device that can record data and retrieve data when needed, and may include a storage device and a storage controller. Data is recorded in the storage device, and the storage controller controls the overall operation of the storage device. The storage device may include non-volatile memory (NVM) in which the data stored does not disappear even when power is not supplied, and volatile memory (VM) in which the data stored disappears when power is not supplied.

[0004] In recent years, although research on improving the integration of storage devices has enabled high-density and large-capacity storage devices, the time required for initialization and setup operations has also increased. Summary of the Invention

[0005] One aspect of the present invention provides a storage device with a shortened startup time.

[0006] The invention also provides a storage device in which the startup operation is adapted differently depending on durability.

[0007] According to one aspect of this disclosure, a method of operating a storage system including a plurality of non-volatile memory devices is provided, the method comprising: when the storage system is powered on, loading first IDR (Information Data Readout) data stored in the non-volatile memory devices into a storage controller; opening metadata using the loaded first IDR data through the storage controller; checking environmental information of each of the plurality of non-volatile memory devices; selecting subsequent IDR data from a plurality of subsequent IDR data that corresponds to the checked environmental information, and loading the subsequent IDR data from the non-volatile memory devices into the storage controller.

[0008] According to another aspect of this disclosure, a storage system is provided, the storage system comprising: a storage controller; and a plurality of non-volatile memory devices driven by the storage controller, wherein any one of the non-volatile memory devices includes a user area for storing user data, a first meta-area for storing first IDR data, and a second meta-area for storing a plurality of subsequent IDR data, and the storage control unit performs initial settings using the first IDR data, and then updates the operating variables of the non-volatile memory devices using subsequent IDR data corresponding to environmental information from among the plurality of subsequent IDR data.

[0009] According to another aspect of this disclosure, a non-volatile memory device is provided, comprising: a memory cell array including a metadata region storing first IDR data and a plurality of subsequent IDR data and a user region storing user data; and peripheral circuitry accessing the memory cell array, wherein, while the peripheral circuitry is being started upon power-up under the control of a memory controller, the first IDR data is loaded into control logic to initialize the operating variables of the peripheral circuitry, a metadata open operation is performed based on the first IDR data, any subsequent IDR data is selected based on the environmental information of the non-volatile memory device and loaded into the control logic, and the peripheral circuitry updates the initialized operating variables.

[0010] However, the invention is not limited to the aspects set forth herein. The above and other aspects of the invention will become more apparent to those skilled in the art from the following detailed description of the invention. Attached Figure Description

[0011] The exemplary embodiments will become clearer from the following detailed description taken in conjunction with the accompanying drawings.

[0012] Figure 1 A diagram illustrating a storage system according to some embodiments is shown.

[0013] Figure 2 This is a block diagram illustrating a storage device according to some embodiments.

[0014] Figure 3 It is used for explanation Figure 2 A schematic block diagram of the storage device is shown in the figure.

[0015] Figure 4 It is used for explanation Figure 3 The diagram shows a memory cell array.

[0016] Figure 5 It is used for explanation Figure 3 The diagram shows a schematic of the meta-region of a memory cell array.

[0017] Figure 6 It is used to explain the storage according to some embodiments. Figure 5 A conceptual diagram of information data read (IDR) data in each of the partitioned regions.

[0018] Figure 7 It is used to explain the storage according to some embodiments. Figure 5 A conceptual diagram of IDR data in each of the partitioned regions.

[0019] Figure 8 This is a conceptual diagram used to explain multiple IDR data stored in a memory cell region according to some embodiments.

[0020] Figure 9 It is a timing diagram used to explain the operation of a storage system according to some embodiments.

[0021] Figure 10 This is a flowchart illustrating the operation method of a storage system 20 according to some embodiments.

[0022] Figure 11 This is a schematic block diagram of a computing system according to one embodiment. Detailed Implementation

[0023] In this specification, unless explicitly stated as “a” or “single,” expressions described in the singular are to be interpreted as either singular or plural. Terms including ordinal numbers such as first and second may be used to describe various components, but components are not limited to such terms. These terms may be used for the purpose of distinguishing one component from another.

[0024] According to some embodiments of the present invention, a non-volatile memory device, a storage device including a non-volatile memory device, and a method of operating the storage device can selectively use information data based on the user's durability requirements for the non-volatile memory device. Durability can be based on how many write / erase cycles the non-volatile memory device can perform before a failure occurs.

[0025] In the following text, the storage system according to some embodiments of the present invention will be referred to. Figures 1 to 11 To describe.

[0026] Figure 1 A diagram illustrating a storage system according to some embodiments is shown.

[0027] Reference Figure 1According to an embodiment of the present invention, the electronic system 1 includes a host 10 and a storage system 20. The electronic system 1 can be implemented as a PC (personal computer) or data server, a laptop computer, or a portable device. The portable device can be implemented as a mobile phone, smartphone, tablet PC, PDA (personal digital assistant), EDA (enterprise digital assistant), digital still camera, digital video camera, PMP (portable multimedia player), PND (personal navigation device or portable navigation device), handheld game console, or e-reader. The electronic system 1 can also be implemented as a system-on-a-chip (SoC).

[0028] Host 10 may request data processing operations (e.g., data read operations, data write (programming) operations, data erase operations, etc.) from storage system 20. For example, host 10 may be a central processing unit (CPU), graphics processing unit (GPU), microprocessor, or application processor (AP).

[0029] Storage system 20 includes storage controller 200 and storage device 100. Storage system 20 can be implemented as various types of storage devices (such as solid-state drive (SSD), embedded multimedia card (eMMC), universal flash storage device (UFS) or compact flash (CF), secure digital (SD), micro-secure digital (Micro-SD), mini-secure digital (Mini-SD), extreme digital (xD) or memory stick).

[0030] Storage controller 200 can be integrated with host 10 and storage system 20. Storage controller 200 can be configured to access storage device 100 in response to a request from host 10. For example, storage controller 200 can be implemented to control the overall operation of storage system 20. Storage controller 200 can perform various management operations, such as cache / buffer management, firmware management, garbage collection management, wear leveling management, data deduplication management, read refresh / reclaim management, bad block management, multi-stream management, host data and non-volatile memory mapping management, quality of service (QoS) management, system resource allocation management, non-volatile memory queue management, read level management, erase / programming management, hot / cold data management, power failure protection management, dynamic thermal management, and initialization management.

[0031] Although not clearly shown in the accompanying drawings, the storage controller 200 may be configured to provide an interface between the storage system 20 and the host 10. Furthermore, the storage controller 200 may be configured to drive firmware for controlling the storage system 20 upon request from the host 10, or to drive firmware for controlling the storage system 20 itself. For example, the storage controller 200 may also include known components such as a host control unit (HCORE) 210, a storage control unit (FCORE) 220, a memory 230, a host interface, and a memory interface.

[0032] The host control unit (HCORE) 210 controls the self-operation of the host 10 and the operation of the electronic system 1. The host control unit (HCORE) 210 generates commands for controlling the operation of the electronic system 1 and sends these commands to the electronic system 1. The host control unit (HCORE) 210 can, for example, execute the firmware's HIL (Hardware In the Loop) to perform conventional path processing of input / output (I / O) commands and administration commands. Conventional I / O paths refer to, for example, general I / O paths that do not use hardware automation, and administration commands refer to commands that monitor and analyze inputs and outputs through storage device initialization, reset, etc., to provide information to the core.

[0033] The storage control unit (FCORE) 220 performs the firmware's file transfer layer (FTL) and fault line (FIL).

[0034] The host interface of the storage controller 200 may include protocols for performing data exchange between the host 10 and the storage controller 200. As an example, the storage controller 200 may be configured to communicate with the host 10 via at least one of various interface protocols, such as Universal Serial Bus (USB) protocol, Multimedia Card (MMC) protocol, Peripheral Component Interconnect (PCI) protocol, PCI-express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, and Integrated Drive Electronics (IDE) protocol.

[0035] The memory interface of the memory controller 200 can send signals to and receive signals from the memory device 100 via multiple pins. For example, the multiple pins can respectively send DQ, DBI, DQS, RE, CE, ALE, CLE, and WE signals.

[0036] The DQ signal is a data signal, and commands (CMD), addresses (ADDR), and data (DATA) can be transmitted. The DQ signal can be transmitted via multiple data signal lines. The DBI signal is a data bus inversion signal, and the memory controller 200 and memory device 100 can send and receive data that has undergone data bus inversion calculations or data masking calculations. For example, data can be encrypted for security or privacy. The DQS signal is a data strobe signal, and the RE signal is a read enable signal, which can be input as a data output control signal when reading data from a non-volatile memory chip. The RE signal can be used to generate the DQS signal. The CE signal is a chip enable signal, and is the signal through which the memory controller 200 selectively activates and accesses at least one of the memory devices 100. The CLE signal is a command latch enable signal, and the ALE signal is an address latch enable signal. The CLE signal is enabled when the DQ signal includes a command (CMD), and the ALE signal is enabled when the DQ signal includes an address (ADDR). The CLE or ALE signal is disabled when general data is sent to the DQ signal. The WE signal is a write enable signal, and the storage controller 200 can send the data signal DQ, which includes the command CMD or address ADDR, and the switched write enable signal WE to the storage device 100.

[0037] For example, storage device 100 can perform programming / reading / erasing operations by latching the command CMD or address ADDR based on the CLE and ALE signals at the edge of the WE signal. For instance, during a read operation, the CE signal is activated, the CLE signal is activated in the command transmission segment, the ALE signal is activated in the address transmission segment, and the RE signal can be switched at the data transmission segment via the data signal line DQ. The DQS signal can be switched at a frequency corresponding to the data I / O speed. Read data can be sent sequentially and synchronously with the data strobe signal DQS.

[0038] At least one storage device 100 may include multiple planes 101, 102, ..., and 103, and the storage device 100 may support Plane Independent Command (PIC). The storage device 100 may also include peripheral circuitry (PERI) 300.

[0039] The memory 230 may be used as at least one of the operating memory of the host control unit (HCORE) 210 or the storage control unit (FCORE) 220, a cache memory between the storage system 20 and the host 10, and a buffer memory between the storage system 20 and the host 10, and may be implemented, for example, as random access memory (RAM). The storage control unit (FCORE) 220 can control the general operation of the storage controller 200.

[0040] Figure 2This is a block diagram illustrating a storage device according to some embodiments.

[0041] Reference Figure 2 The storage system 20 may include a storage device 100 and a storage controller 200. The storage system 20 may support multiple channels CH1 to CHm, and the storage device 100 and the storage controller 200 may be connected via multiple channels CH1 to CHm. For example, the storage system 20 may be implemented as a storage device (such as an SSD (Solid State Drive)).

[0042] The storage device 100 may include a plurality of non-volatile memory devices NVM11 to NVMmn. Each of the non-volatile memory devices NVM11 to NVMmn may be connected to one of a plurality of channels CH1 to CHm via a corresponding path. For example, non-volatile memory devices NVM11 to NVM1n may be connected to a first channel CH1 via paths W11 to W1n, and non-volatile memory devices NVM21 to NVM2n may be connected to a second channel CH2 via paths W21 to W2n. In an exemplary embodiment, each of the non-volatile memory devices NVM11 to NVMmn may be implemented in any memory cell capable of operating according to various instructions from the storage controller 200. For example, although each of the non-volatile memory devices NVM11 to NVMmn may be implemented as a chip or a die, the invention is not limited thereto.

[0043] The storage controller 200 can send signals to and receive signals from the storage device 100 via multiple channels CH1 to CHm. For example, the storage controller 200 can send commands CMDa to CMDm, addresses ADDRa to ADDRm, and data DATAa to DATAm to the storage device 100 via channels CH1 to CHm, and receive data DATAa to DATAm from the storage device 100.

[0044] The storage controller 200 can select one of the non-volatile memory devices NVM11 to NVM1n connected to the channel via each channel, and send signals to and receive signals from the selected non-volatile memory device. For example, the storage controller 200 can select the non-volatile memory device NVM11 connected to the first channel CH1 among the non-volatile memory devices NVM11 to NVM1n. The storage controller 200 can send command CMDa, address ADDRa, and data DATAa to the selected non-volatile memory device NVM11 via the first channel CH1, or receive data DATAa from the selected non-volatile memory device NVM11.

[0045] The storage controller 200 can send and receive signals in parallel with the storage device 100 through different channels. For example, the storage controller 200 can send the command CMDb to the storage device 100 through the second channel CH2, while simultaneously sending the command CMDa to the storage device 100 through the first channel CH1. For example, the storage controller 200 can receive data DATAb from the storage device 100 through the second channel CH2, while simultaneously receiving data DATAa from the storage device 100 through the first channel CH1.

[0046] The storage controller 200 controls the overall operation of the storage device 100. The storage controller 200 can control each of the non-volatile memory devices NVM11 to NVM1n connected to channels CH1 to CHm by sending signals to channels CH1 to CHm. For example, the storage controller 200 can send command CMDa and address ADDRa to the first channel CH1 to control a selection of non-volatile memory devices NVM11 to NVM1n.

[0047] Each of the non-volatile memory devices NVM11 to NVMmn can operate under the control of the memory controller 200. For example, non-volatile memory device NVM11 can program data DATAa according to the command CMDa and address ADDRa provided to the first channel CH1. For example, non-volatile memory device NVM21 can read data DATAb according to the command CMDb and address ADDRb provided to the second channel CH2, and send the read data DATAb to the memory controller 200.

[0048] although Figure 2 The storage device 100 communicates with the storage controller 200 through m channels CH1 to CHm, and the storage device 100 includes n non-volatile memory devices corresponding to each channel, but the number of channels and the number of non-volatile memory devices connected to a channel can be varied.

[0049] Figure 3 It is used for explanation Figure 2 The schematic block diagram of the storage device shown in the figure, and Figure 4 It is used for explanation Figure 3 The diagram shows a memory cell array.

[0050] Reference Figure 3The storage device 100 includes a memory cell array 400 and peripheral circuitry 300 connected to the memory cell array 400. The peripheral circuitry 300 may include a voltage generator 350, a row decoder 360, a page buffer 340, an I / O buffer 320, a cell counter 330, and control logic 310. The page buffer 340 may include multiple subpage buffers PB1, ..., PBn.

[0051] Reference Figure 3 The memory cell array 400 may include multiple memory blocks BLK1 to BLKz. Each of the memory blocks BLK1 to BLKz can be connected to the row decoder 360 via the word line WL, the serial select line SSL, and the ground select line GSL, and can be connected to the page buffer 340 via the bit line BL.

[0052] The memory cell array 400 may include multiple memory cells disposed in regions where multiple word lines WL intersect with multiple bit lines BL. Each memory cell may be formed in various cell types including single-level cell (SLC), multi-level cell (MLC), three-level cell (TLC), and four-level cell (QLC).

[0053] For example, each of the memory blocks BLK1 to BLKz can be formed in a three-dimensional structure on a substrate. (See reference...) Figure 4 The first memory block BLK1 may include multiple memory NAND strings NS11 to NS33 connected between multiple bit lines BL1 to BL3 and a common source line CSL. Each of the multiple memory NAND strings NS11 to NS33 may include a string select transistor SST, multiple memory cells MC, and a ground select transistor GST. Although Figure 4 The number of multiple bit lines BL1 to BL3 is shown to be three, the number of multiple memory NAND strings NS11 to NS33 is nine, and each of the multiple memory NAND strings NS11 to NS33 includes eight memory cells MC (memory cells MC1 to MC8), but this is not limited to this and can be implemented in different numbers according to embodiments.

[0054] The gate of the serial select transistor SST can be connected to the corresponding serial select lines SSL1 to SSL3. Multiple memory cells MC1 to MC8 can be connected to multiple gate lines GTL1 to GTL8 respectively. The multiple gate lines GTL1 to GTL8 can correspond to multiple word lines, and some of the gate lines GTL1 to GTL8 can correspond to dummy word lines. The gate of the ground select transistor GST can be connected to the corresponding ground select lines GSL1 to GSL3. The serial select transistor SST can be connected to the corresponding bit lines BL1 to BL3, and the ground select transistor GST can be connected to the common source line CSL.

[0055] In the first memory block BLK1, word lines of the same height (e.g., word line WL1) can be connected together, and ground select lines GSL1 to GSL3 and string select lines SSL1 to SSL3 can be separated from each other.

[0056] Return to reference Figure 3 The control logic 310 receives the command CMD and the address ADDR to generate control signals CTRL_vol for controlling the voltage generator 350 and control signals for controlling the page buffer 340, and can generate row address X_ADDR and column address Y_ADDR based on address ADDR. The control logic 310 can output row address X_ADDR to row decoder 360, and can output column address Y_ADDR to page buffer 340.

[0057] Voltage generator 350 receives power supply PWR, adjusts word line base voltage VWL for memory operation according to control signal CTRL_vol from control logic 310, and can provide word line base voltage VWL to memory cell array 400 through row decoder 360.

[0058] The row decoder 360 can be connected to the memory cell array 400 via the word line WL, the serial select line SSL, and the ground select line GSL. The row decoder 360 can decode the row address X_ADDR input from the control logic 310 to select at least one of a plurality of memory blocks BLK1 to BLKz. That is, the row decoder 360 can use the row address X_ADDR to select the word line WL, the serial select line SSL, and the ground select line GSL. The row decoder 360 can provide the word line basic voltage VWL supplied from the voltage generator 350 to the word line WL.

[0059] Page buffer 340 can be connected to memory cell array 400 via bit line BL, and can also be connected to I / O buffer 320. During programming operations, I / O buffer 320 can receive programming data DATA from memory controller 200, and provide the programming data DATA to page buffer 340 based on column address Y_ADDR provided from control logic 310. During read operations, I / O buffer 320 can provide read data DATA stored in page buffer 340 to memory controller 200 based on column address Y_ADDR provided from control logic 310.

[0060] Control logic 310 can control the overall operation of storage device 100 and output each control signal associated with memory operation. For example, control logic 310 can use internal control signals to control storage device 100 based on at least one of address ADDR, command CMD, and control signal CTRL received from storage controller 200.

[0061] The control logic 310 may also include a latch that reads setting data CDATA from a read-only memory (ROM), stores the setting data CDATA in the latch, and generates an internal control signal based on at least one of an address ADDR, a command CMD, and a control signal CTRL, as well as the stored setting data.

[0062] Figure 5 It is used for explanation Figure 3 A schematic diagram of the meta-region of the memory cell array 400 is shown in the figure. Figure 6 It is used to explain the storage according to some embodiments. Figure 5 A conceptual diagram of Information Data Read (IDR) data in each of the partitioned regions. Figure 7 It is used to explain the storage according to some embodiments. Figure 5 A conceptual diagram of IDR data in each of the partitioned regions. Figure 8 This is a conceptual diagram used to explain multiple IDR data stored in a memory cell region according to some embodiments.

[0063] Refer to together Figure 3 and Figure 5 The memory cell array 400 may include a meta region and a user region. The meta region and user region may be memory regions logically divided by namespaces of non-volatile memory devices NVM11 to NVMmn, etc. According to various embodiments, each of the meta region and user region may include a single-level cell, a multi-level cell, a three-level cell, etc.

[0064] The meta-area can store setup data (CDATA) required for the storage device 100 to operate. The setup data (CDATA) is used to initialize and set up the storage system 20 before the metadata open (Meta Open or Map Open) for memory operations, and can be pre-stored during the testing phase for a specific area of ​​the memory cell.

[0065] The user area can store user data that is entered or processed by the user through the host 10.

[0066] The meta-region may include at least a first region 410 and a second region 420. The division of the first region 410 and the second region 420 may be a variable and logical division, rather than a physical division. For example, the storage controller 200 may designate the first memory block BLK1 as the first region 410 and the remaining memory blocks BLK2 to BLKz as the second region 420. The storage controller 200 may designate and change the memory blocks belonging to each region according to the instructions of the host 10 or as needed (e.g., designating the first memory block BLK1 and the second memory block BLK2 as the first region 410 and the remaining memory blocks BLK3 to BLKz as the second region 420).

[0067] For example, the first region 410 may be implemented as a single-level unit, and the second region 420 may be implemented as including single-level units, multi-level units, or more. The first region 410 may be quickly accessible and may store initial setup data required for system startup, while the second region 420 may store remaining setup data in addition to the initial setup data.

[0068] The metadata enable operation can instruct the loading of metadata recorded before the power to storage system 20 was disconnected and the reconstruction of that metadata to the latest information. Storage controller 200 can use metadata to process requests from host 10. Metadata can be configuration information for each component in storage device 100.

[0069] Metadata may include IDR (Information Data Reader) data. IDR data is the data required to drive storage device 100 and may include, for example, data used for... Figure 2 Option information, column repair information, and bad block information for each of the non-volatile memory devices NVM11 to NVMmn.

[0070] Setup data can also be referred to as Information Data Read (IDR) data. Setup data represents the data required for the operation of a non-volatile memory device, and more specifically, may include option information, column repair information, and bad block information for each memory die. Setup data DC information may include setting conditions for operating the peripheral circuitry 300, pump circuitry, etc., of the non-volatile memory device.

[0071] According to some embodiments, when distortion occurs due to degradation of the metadata CDATA, there may be replicated metadata instead of the metadata CDATA that will be used. That is, IDR data may include multiple replicated IDR data. For example, IDR data may include first IDR data and first replicated IDR data.

[0072] According to an embodiment, the memory cell array 400 may include multiple planes ( Figure 1(Plane 101, 102, and 103). (Refer to...) Figure 6 The first region 410 may include a first plane (plane 1) 401 and a second plane (plane 2) 402. The first plane 401 is the primary plane where metadata is first accessed, and the second plane 402 may be a replica plane storing the same data as the data in the first plane 401. Multiple replica metadata entries for each plane may be stored as data to prepare for failures of the bit line BL.

[0073] The previous IDR data (i.e., IDR_P) and the previous copied IDR data (IDR_P) are stored in planes of first regions 411 and 412, respectively. Subsequent IDR data (IDR_A, IDR_B, and IDR_C) and subsequent copied IDR data are stored in planes of second regions 421 and 422, respectively. For example, the first IDR data (IDR_A and the IDR master block) is stored in the first plane 401 belonging to the second region 421, and the first copied IDR data (IDR_A and the IDR copy block) may be stored in the second plane 402 belonging to the second region 422. Similarly, the second IDR data (IDR_B and the IDR master block) is stored in the first plane 401 of the second region 421, and the second copied IDR data (IDR_B and the IDR copy block) may be stored in the second plane 402. For example, the third IDR data (IDR_C and IDR master block) is stored in the first plane 401 of the second region 421, and the third replicated IDR data (IDR_C and IDR replicated block) can be stored in the second plane 402.

[0074] The third area, 431 and 432, is the user area and can store user data.

[0075] According to some embodiments, each of the IDR_A data, IDR_B data, and IDR_C data may include an operational variable setting value within a threshold range associated with the operational reliability of the storage device 100. For example, the IDR_A data may have a first threshold range, the IDR_B data may have a second threshold range different from the first threshold range, and the IDR_C data may have a third threshold range different from the first and second threshold ranges.

[0076] According to some embodiments, each of the IDR_A data, IDR_B data, and IDR_C data may be data having operation variable settings for different cores based on erase count levels for each die of the storage device 100 (or having different operation variable settings for the peripheral circuitry 300 of the storage device 100). For example, the IDR_A data may include operation variable settings for a first die, the IDR_B data may include operation variable settings for a second die, and the IDR_C data may include operation variable settings for a third die. The first, second, and third dies may be dies located at different positions from each other.

[0077] For example, the storage control unit may collect erase counts associated with the degradation of storage device 100 as environmental information. As an example, if the collected erase count is 3.5k and falls within a first threshold range, storage device 100 may be configured to store previous IDR data (IDR_P), and this configuration may be updated with subsequent IDR data (IDR_A, IDR_B, IDR_C) after a metadata open operation.

[0078] During operation of the storage system 20, the storage controller 200 collects environmental information of the storage device 100, and upon restart, compares the previously collected environmental information with a first threshold range, a second threshold range, and a third threshold range to select IDR data corresponding to the threshold range to which the environmental information belongs.

[0079] When the storage device 100 is driven, the storage system 20 loads the initial IDR data (previous IDR data (IDR_P) and IDR master block) and operates. However, if the first IDR data cannot be read due to a bit line fault in the first plane 401 or if there is an error in the first IDR data, the storage system 20 may load the first replicated IDR data (IDR_A and IDR replica block) in the second plane 402.

[0080] For example, during initial operation, storage device 100 performs a metadata opening operation after high-speed setup using previous IDR data, and loads and operates on first subsequent IDR data (IDR_A) after the metadata opening is completed. The storage control unit may load and operate on second subsequent IDR data (IDR_B) or third subsequent IDR data (IDR_C) considering the degree of degradation of storage device 100 after a specific period of use. In the illustrated example, subsequent IDR data with different values ​​are shown as IDR_A, IDR_B, and IDR_C; however, according to various embodiments, storage device 100 may store multiple pieces of subsequent IDR data (e.g., three or more pieces of IDR data).

[0081] Reference Figure 7According to an embodiment, each of the first subsequent IDR data (IDR_A) and the first subsequent replicated IDR data (IDR_A) can be implemented on a unit of SSL lines. For example, the first subsequent IDR data can be stored in a memory cell where the first unit string 401 of the first SSL (master SSL) intersects with the IDR word line (IDR WL), and the first subsequent replicated IDR data can be stored in a memory cell where the second unit string 402 of the second SSL (replicated SSL) intersects with the IDR word line (IDR WL). In this case, the IDR word line intersecting with each of the first unit string 401 and the second unit string 402 can be the same word line. Furthermore, the first unit string 401 of the first SSL can also be connected to the string select line SSL. <0> 、Word line WL <n-1>And the ground selection line GSL intersects, and the second unit string 402 of the second SSL can also be connected to the string selection line SSL. <k>、Word line WL <n-1>And the ground selection line GSL intersects.

[0082] When the storage system 20 operates the storage device 100, the storage system 20 loads the first subsequent IDR data (IDR_A and IDR main block) for operation. However, if the first subsequent IDR data cannot be read due to the failure of the first SSL (main SSL) or if there is an error in the first IDR data, the storage system 20 may load the first subsequent replicated IDR data (IDR_A) of the second SSL (replicated SSL).

[0083] According to various embodiments, a first IDR word line may be connected to a memory cell in which first subsequent IDR data (IDR_A) and first subsequent copy IDR data are stored, and a second IDR word line may be connected to a memory cell in which second subsequent IDR data (IDR_B) and second subsequent copy IDR data are stored.

[0084] Together Figure 6 and Figure 7 Refer to together Figure 8 The storage device 100 can store previous IDR data (IDR_P) in the first memory cells connected to word lines WLm to WLm+3 in the first region 410 inside the memory cell array 400 (m is an integer equal to or greater than 0). The previous IDR data (IDR_P) can be, for example, 1M bytes of information.

[0085] Storage device 100 can store subsequent IDR data (IDR_A) in second memory cells connected to word lines WLn to WLn+3 (where n is an integer equal to or greater than 0) in a second region 420 within memory cell array 400. The subsequent IDR data (IDR_A) can be, for example, 3 M bytes of information.

[0086] The initial IDR data (IDR_P) is the initial IDR data and may only include some setup data required for the initial startup of storage system 20. For example, the initial IDR data (IDR_P) may be loaded to quickly set up only the non-volatile memory devices (i.e., non-volatile memory devices NVM11 to NVMmn) where the master metadata is stored. Therefore, the initial IDR data (IDR_P) may be data with a smaller size than the subsequent IDR data (IDR_A, IDR_B, IDR_C).

[0087] Storage system 20 can shorten startup time and save power consumed during startup by preferentially performing setup operations using only some setup data of small size during initial setup. For example, storage device 100 can read previous IDR data (IDR_P) for SLC operation and perform setup operations.

[0088] Previous IDR data (IDR_P) and subsequent IDR data (IDR_A) can be accessed via different commands. The storage controller can access the previous IDR data (IDR_P) stored in the first memory cell by sending the first command CMD1 under the initial drive of the non-volatile memory device after the storage system 20 is powered on. Subsequently, during the metadata open operation of the storage system 20, the storage controller 200 collects environmental information related to the durability and reliability of the storage device 100.

[0089] Then, upon restarting, the storage controller 200 sends a second command CMD2 for multi-IDR access to the storage device 100 based on the collected environmental information. The storage device 100 can access subsequent (e.g., second) IDR data (IDR_A) stored in a second memory cell in response to the second command CMD2. The subsequent IDR data (e.g., IDR_A) can be subsequent setting data selected in response to environmental information for each chip (or die) of the non-volatile memory device. The subsequent IDR data can be all the data including operational variable setting values ​​enhanced according to the environmental information. That is, the subsequent IDR data can be data with a larger size than the previous IDR data (IDR_P).

[0090] The non-volatile memory device sends accessed previous IDR data (IDR_P) or subsequent IDR data (e.g., IDR_A) to the memory controller 200 via page buffer 340 and I / O buffer 320, and the memory controller 200 controls control logic 310 such that each component of the peripheral circuitry 300 operates using a setting value based on the selected IDR data.

[0091] For example, the accessed IDR data is stored in an electric fuse latch in control logic 310, and the peripheral circuitry 300 can operate using the IDR data stored in the electric fuse latch.

[0092] Figure 9 It is a timing diagram used to explain the operation of a storage system according to some embodiments.

[0093] Reference Figure 9 When the power supply to the storage system 20 is turned on, the host control unit (HCORE) 210 of the storage controller 200 accesses the memory 230 and loads the accessed initial setup data into the boot loader of the memory 230. Based on the loaded initial setup data, the storage controller 200 performs an initialization operation in the host control unit (HCORE) 210 and the storage control unit (FCORE) 220, and controls the general operation of the storage device 100 after the initialization is completed.

[0094] Initialization operations based on configuration data, such as loading initial IDR data (e.g., previous IDR data (IDR_P)) of each non-volatile memory device NVM11 to NVMmn connected to each road (way0, way1, ..., wayN) from ROM into the boot region starting from time t0, and performing a metadata open operation (MetaOpen) when all initial IDR data has been loaded.

[0095] Metadata open operations instruct the reconstruction of metadata recorded just before the power to storage system 20 was disconnected, using the latest information (e.g., initial IDR data). Metadata open operations may include read operations. For example, a read operation may be an SLC read. An SLC read may be an operation that reads data from a memory cell using a voltage. When power is restored after a sudden power outage (SPO), metadata open operations may also include erase and programming operations.

[0096] When the metadata open operation is completed, the storage controller 200 can perform a setup operation on the storage device 100 for general operation. The setup operation includes subsequent processing (such as sensing for reading IDR data CDATA of the second region 420 using page buffer 340, storing the setup data CDATA stored in page buffer 340 as a sensing result in a latch of control logic 310 after verifying validity, and setting conditions for operation of the storage device 100 based on the IDR data CDATA stored in the latch). For example, control logic 310 can perform the setup operation by sending IDR data stored in the latch to each of components 320 to 350 to set operation variables. Subsequent processing may include setting the DC level of the operation voltage or performing a WOR (Write-Operation-Read) scan of the buffer to exclude bad columns using column repair information.

[0097] When a fault occurs during a WOR scan, storage device 100 can perform setup operations using the replicated data. That is, when a fault occurs in the IDR data (CDATA) recorded in the primary plane and primary SSL, storage device 100 can perform setup operations using the replicated IDR data recorded in the replication plane and primary SSL.

[0098] Simultaneously, the Storage Control Unit (FCORE) 220 checks the environmental information collected just before the power to the storage system 20 is disconnected. The FCORE 220 can scan the metadata header corresponding to the environmental information checked after initial startup. The FCORE 220 accesses the scanned metadata (i.e., the new IDR data IDR_A), loads the scanned metadata into the latches of the control logic, and updates the operation variables set in the initial IDR data. Then, the FCORE 220 can execute the firmware file transfer layer (FTL Open) after a waiting period.

[0099] According to some embodiments, the environmental information may be an erase count. For example, the storage control unit (FCORE) 220 may... Figure 2 During operation of storage device 100, erase counts (hereinafter referred to as ECs) are collected for each of the non-volatile memory devices NVM11 to NVMmn (i.e., implemented as chips or dies) connected to each channel CHm. After storage system 20 is started, the previously collected ECs are checked, and a threshold criterion is compared with the checked ECs to determine whether to retain the initial IDR data or update the initial IDR data with new IDR data. For example, if the checked ECs exceed the threshold count (nC>Th), storage controller 200 decides to update with new IDR data, and storage device 100 loads the scanned new IDR data IDR_A into a latch in control logic 310.

[0100] When the storage system 20 is operated in this manner, the storage system 20 can be configured to operate to a degree suitable for the use of the storage device 100, and the peripheral circuitry 300 of the storage device 100 is a newly updated operating variable, and therefore, the reliability of the storage system 20 can be improved.

[0101] Even if the new IDR data is as follows Figure 8 The storage system 20 loads new IDR data after the metadata opening is completed at time t2, and updates the storage device 100 with new operation variables without wasting the initial setup time (t0 to t1) and metadata opening time of the storage device 100, thereby improving the performance of the storage device 100.

[0102] Furthermore, storage system 20 can load IDR data that matches the environmental conditions of host 10 and non-volatile memory devices without separate hardware changes or software updates, even when operating conditions differ for each host 10, and update the operating variables of storage system 20, thereby improving performance while ensuring the reliability of the storage system.

[0103] Figure 10 This is a flowchart illustrating the operation method of a storage system 20 according to some embodiments.

[0104] Reference Figure 10 When the storage system 20 is powered on (S10), the storage controller 200 performs startup (S11).

[0105] The storage controller 200 initiates the initialization of the storage control unit (FCORE) 220 and the host control unit (HCORE) 210, and loads system setting data into the memory 230 (e.g., ROM (Read-Only Memory)). The storage device 100 can perform the initialization operation and the setting operation IDR_A (S12) in response to a first command from the storage controller 200. After loading the system setting data, the storage controller 200 loads only the initial setting data (previous IDR data (IDR_P)) required to access the storage device 100 into the control logic 310, and the setting operation IDR_A, based on the setting data, can be executed for the operation most needed by the storage device 100.

[0106] Mapping open (or metadata open) is performed (S13). After mapping open, storage controller 200 checks environmental information (e.g., erase count) collected before the previous power was disconnected (S14). Storage controller 200 selects and loads IDR data corresponding to the checked erase count from the IDR data stored in the second region 420 of the non-volatile memory device via a second command (S15).

[0107] The storage controller 200 can perform a selected setup operation IDR_A for the remaining subsequent operations of the storage device 100. The storage controller 200 loads the selected IDR_A data to update the operation variables of the storage device 100 (S16). The selected IDR_A data at this time can be used to update the operation variables of the entire storage device 100, or it can be used to update the operation variables of specific non-volatile memory devices NVM11 to NVMmn or any block of the storage device 100. The operations of steps S15 and S16 can be performed as background operations of the storage device 100.

[0108] Storage controller 200 performs general operations (such as accessing storage device 100) based on operation variables updated during runtime (S17), and storage device 100 collects erase counts and / or P / E (programming / erasing) cycle counts in real time while performing step S17 (S18). If host 10 or user subsequently receives a restart command (S19, yes), processing returns to step S11 to perform a restart, and subsequent steps (S12 and subsequent steps) are executed. If the command is neither a restart command (S19, no) nor a power-off command (S20, no), operations after the runtime of step S17 are executed continuously. If a power-off is performed (S20, yes), the erase counts collected in step S18 are stored, and storage system 20 terminates.

[0109] Figure 11 This is a schematic block diagram of a computing system according to one embodiment.

[0110] Reference Figure 11 The computing system 1000 can be a mobile device, computer, etc. The computing system 1000 may include a host 1010, RAM 1020, device driver 1030, memory system 1040, communication interface 1050, and bus 1060. The host 1010, RAM 1020, device driver 1030, memory system 1040, and communication interface 1050 may each be electrically connected to the bus 1060. The computing system 1000 may also include other general-purpose components.

[0111] The host 1010 controls the overall operation of each component of the computing system 1000. The host 1010 can be a central processing unit (CPU), graphics processing unit (GPU), microprocessor, application processor (AP), etc.

[0112] RAM 1020 can be used as data storage for host 1010.

[0113] The host 1010 can write data to or read data from the memory system 1040 via the device driver 1030. The data may include setting data and user data. According to an embodiment, the device driver 1030 may be implemented within the host 1010.

[0114] The memory system 1040 can be implemented as non-volatile memory. The memory system 1040 may include a memory controller and a memory device. The memory system 1040 can be connected to a device driver 1030. The memory system 1040 can perform operations related to… Figure 1 The storage system 20 has basically the same functions.

[0115] Bus 1060 provides communication functionality between components of computing system 1000. Bus 1360 may include at least one type of bus according to a communication protocol between components.

[0116] In some embodiments, refer to Figures 1 to 11 Each component described, or a combination of two or more components, can be implemented as a digital circuit, a programmable or non-programmable logic device or array, an application-specific integrated circuit (ASIC), etc.

[0117] Although embodiments of the present disclosure have been described above with reference to the accompanying drawings, the present disclosure is not limited to the above embodiments and can be made in various different forms. Those skilled in the art will understand that aspects of the invention may be embodied in other specific forms without altering the technical spirit or essential features of the present disclosure. Therefore, the above embodiments should be understood in all respects as illustrative rather than restrictive. < / k>

Claims

1. A method of operating a storage system, the storage system comprising a plurality of non-volatile memory devices, the method comprising: When the storage system is powered on, the first information data stored in the plurality of non-volatile memory devices is loaded into the storage controller; The storage controller reads data and opens metadata using the first loaded information data; Check the environmental information of each of the plurality of non-volatile memory devices; as well as Select the subsequent information data that corresponds to the detected environmental information from among multiple subsequent information data reads, and load the subsequent information data reads from the non-volatile memory device into the memory controller.

2. The method of operating the storage system as described in claim 1, wherein, The first piece of information data to be read is data that is smaller than the data read in subsequent pieces of information data.

3. The method of operating the storage system as described in claim 1, wherein, Each of the plurality of subsequent information data reads has a different threshold range for environmental information and includes different operating variable setting values ​​for the peripheral circuits of the plurality of non-volatile memory devices.

4. The method of operating the storage system as described in claim 3, wherein, The step of selecting and loading subsequent information data is based on the environmental information collected for each non-volatile memory device, and selects the subsequent information data to be read corresponding to the environmental information of each non-volatile memory device.

5. The method of operating the storage system as described in claim 1, wherein, Each of the plurality of non-volatile memory devices includes: The user area stores user data; The first element region stores the first information data and reads the data; and The second region stores the multiple subsequent information data read data.

6. The method of operating the storage system as described in claim 5, wherein, The steps of loading selected subsequent information data and reading data are performed in the background operation of the plurality of non-volatile memory devices.

7. The method of operating the storage system as described in claim 1, wherein, The storage system outputs a second command, different from the first command used to access the first information data, to the non-volatile memory device, and accesses subsequent information data.

8. The method of operating the storage system as described in claim 1, wherein, Environmental information includes values ​​that change based on the durability of the non-volatile memory device.

9. The method of operating the storage system as described in claim 8, wherein, Environmental information includes erase counts and / or programming / erase cycle counts for non-volatile memory devices.

10. The method of operating the storage system as described in claim 1, wherein, When the storage system is restarted: The storage system uses the first information data to read and configure the plurality of non-volatile memory devices. The storage system performs an open metadata operation, and The storage system loads subsequent information data corresponding to the environmental information collected before the storage system was restarted.

11. A storage system, comprising: Storage controller; as well as Multiple non-volatile memory devices are driven by a memory controller. Any of the plurality of non-volatile memory devices includes: a user area for storing user data, a first sub-area for storing first information data read data, and a second sub-area for storing a plurality of subsequent information data read data, and The storage controller uses the first information data to read data to perform initial settings, and then uses the subsequent information data corresponding to the environmental information among the multiple subsequent information data to update the operating variables of the multiple non-volatile memory devices.

12. The storage system of claim 11, wherein, The first information data read data and the plurality of subsequent information data read data are stored in different planes compared to the first copied information data read data and the plurality of subsequent copied information data read data.

13. The storage system of claim 11, wherein, The environmental information is the erase count and / or programming / erasing cycle count of the non-volatile memory device.

14. The storage system of claim 11, wherein, When the storage system is powered on, the storage controller sends a first command to the plurality of non-volatile memory devices to load first information data, read data, and perform initial settings for the non-volatile memory devices. During runtime, the memory controller sends a second command, different from the first command, to the non-volatile memory device, and The storage controller selects and loads any one of the subsequent information data reads corresponding to the environmental information to update the settings of the plurality of non-volatile memory devices.

15. The storage system of claim 11, wherein, The first element region includes single-level units, and the second element region includes single-level units and / or multi-level units.

16. The storage system of claim 11, wherein, The first information data read has a smaller size than the plurality of subsequent information data reads.

17. The storage system of claim 11, wherein, Subsequent information data reads corresponding to environmental information are selected for each die based on environmental information collected for the non-volatile memory device.

18. A non-volatile memory device, the non-volatile memory device comprising a memory system, including: The memory cell array includes a meta-region for storing first information data read data and multiple subsequent information data read data, and a user region for storing user data; as well as Peripheral circuitry, accessing the memory cell array. During the power-on process, as the peripheral circuits are being started under the control of the storage controller, the first information data is loaded into the control logic to initialize the operating variables of the peripheral circuits. The metadata open operation is performed based on the first information data reading. Any one of the environmental information from the plurality of subsequent information data reads, based on a non-volatile memory device, is selected and loaded into the control logic, and The external circuit updates the operation variables after initialization.

19. The non-volatile memory device of claim 18, wherein, The meta-region includes: a first meta-region, which stores first information data and reads data; the first meta-region includes a single-level unit; and The second element region stores the multiple subsequent information data read data, and the second element region includes single-level units and / or multi-level units.

20. The non-volatile memory device of claim 19, wherein, When the first command is received from the storage controller, the first information data is read from the first metadata area and sent to the control logic, and When the second command is received from the storage controller, the subsequent information data corresponding to the environmental information among the plurality of subsequent information data read data is sent to the control logic.

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