Processor and floating-point number processing method, storage medium, program product

Abstract

The embodiment of the present disclosure discloses a processor and a floating point number processing method, a storage medium and a program product, wherein the processor comprises: a multiply-add operation unit; the multiply-add operation unit is configured to, in response to a first signal for a target floating point number, determine a state of multiply-add operation matched with the target floating point number based on a size relationship between the target floating point number and a floating point number threshold in a case where the target floating point number does not satisfy a preset condition; and output a decimal part of the target floating point number based on the state of the multiply-add operation. In this way, the processing of FRC operation is realized by multiplexing the calculation path of the multiply-add operation unit, the circuit area consumption when the FRC calculation unit is separately set and the calculation power consumption when the FRC operation is performed are saved, and the processing efficiency is improved.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to, but is not limited to, the technical field of computer technology, and particularly relates to a processor, a floating-point number processing method, a storage medium and a program product. BACKGROUND

[0002] The FRC operation is an instruction for performing mathematical operation on a floating-point number, which is used to obtain the decimal part of the floating-point number, i.e., the decimal part between 0.0 and 1.0.

[0003] In the related art, an FRC calculation unit is separately arranged in an arithmetic and logic unit (ALU) to complete the calculation of the FRC function, the FRC calculation unit and other calculation units in the ALU are processed in parallel, and a selector selects one from the calculation results of the FRC calculation unit and the calculation results of the other calculation units for output.

[0004] However, the separate arrangement of the FRC calculation unit causes an increase in circuit area, and increases the calculation power consumption and reduces the calculation efficiency. SUMMARY

[0005] Therefore, the embodiments of the present disclosure at least provide a processor, a floating-point number processing method, a storage medium and a program product.

[0006] The technical solutions of the embodiments of the present disclosure are implemented as follows.

[0007] In one aspect, the embodiments of the present disclosure provide a processor, which comprises: a multiply-add operation unit; the multiply-add operation unit is configured to, in response to a first signal for a target floating-point number, determine a state of multiply-add operation matched with the target floating-point number based on a size relationship between the target floating-point number and a floating-point number threshold in a case where the target floating-point number does not satisfy a preset condition; and output a decimal part of the target floating-point number based on the state of the multiply-add operation.

[0008] In some embodiments, the multiply-add operation unit comprises: a window state detection module; the window state detection module is configured to output a first target state of the multiply-add operation in a case where the target floating-point number is greater than a first floating-point number threshold and less than a second floating-point number threshold; the floating-point number threshold comprises the first floating-point number threshold and the second floating-point number threshold; and a calculation window in the first target state contains a mantissa of the target floating-point number.

[0009] In some embodiments, the window state detection module is further configured to, in a case that at least one of the target floating-point number is less than the first floating-point number threshold and the target floating-point number is greater than the second floating-point number threshold exists, and the right shift number is less than the bit number threshold, output a state of the multiply-add operation as a second target state; the calculation window in the second target state contains effective values of a tail number part of the tail number of the target floating-point number corresponding to an exponent less than or equal to 0.

[0010] In some embodiments, the window state detection module is further configured to, in a case that at least one of the target floating-point number is less than the first floating-point number threshold and the target floating-point number is greater than the second floating-point number threshold exists, and the right shift number is greater than or equal to the bit number threshold, output a state of the multiply-add operation as a third target state; the calculation window in the third target state does not contain effective values of a tail number part of the tail number of the target floating-point number corresponding to an exponent less than or equal to 0.

[0011] In some embodiments, the multiply-add operation unit comprises: a bit shift value calculation unit; an input port of the bit shift value calculation unit is connected with an input port of the multiply-add operation unit, and an output port of the bit shift value calculation unit is connected with an input port of the window state detection module; the bit shift value calculation unit is configured to determine a right shift number of the target floating-point number based on a tail number bit width of the target floating-point number, the tail number of the target floating-point number, an exponent offset of the target floating-point number, and a first bit width threshold.

[0012] In some embodiments, the multiply-add operation unit further comprises: an addition exponent calculation module; an input port of the addition exponent calculation module is connected with an output port of the window state detection module; the addition exponent calculation module is configured to determine an addition exponent based on a state of the multiply-add operation; the addition exponent is used to determine a decimal part of the target floating-point number; in a case that the state of the multiply-add operation is the first target state, the addition exponent is an exponent of the target floating-point number; in a case that the state of the multiply-add operation is the second target state or the third target state, the addition exponent is determined based on the exponent offset of the target floating-point number.

[0013] In some embodiments, the multiply-add operation unit further comprises: a sum tail calculation module; an input port of the sum tail calculation module is connected to an input port of the sum exponent calculation module in parallel to an output port of the window state detection module; the sum tail calculation module is configured to determine a sum tail based on the state of the multiply-add operation; the sum tail is used to determine a decimal part of the target floating-point number; when the state of the multiply-add operation is a first target state, the sum tail is determined based on a first summand and a second summand of a calculation window in the first target state; in the first target state, the first summand is the first floating-point number value, and the second summand is a tail of the target floating-point number placed to the highest bit of the calculation window and truncated from the highest bit downward by a first number of bits; the first number of bits is determined based on a bit width of the calculation window in the first target state; when the state of the multiply-add operation is a second target state or a third target state, the sum tail is determined based on the tail of the target floating-point number placed according to the right shift number of the target floating-point number and a sign bit of the target floating-point number.

[0014] In some embodiments, the processor further comprises: a selector; the selector is connected to an input of the processor and an output of the multiply-add operation unit respectively; the selector is configured to output a floating-point number value corresponding to the target floating-point number when the target floating-point number satisfies a preset condition; and output a decimal part of the target floating-point number when the target floating-point number does not satisfy the preset condition.

[0015] In another aspect, the embodiments of the present disclosure provide a floating-point number processing method, which comprises: in response to a first signal for a target floating-point number, determining a state of a multiply-add operation matched with the target floating-point number based on a size relationship between the target floating-point number and a floating-point number threshold when the target floating-point number does not satisfy a preset condition; and outputting a decimal part of the target floating-point number based on the state of the multiply-add operation.

[0016] In some embodiments, the determination of the state of the multiply-add operation matched with the target floating-point number based on the size relationship between the target floating-point number and the floating-point number threshold comprises at least one of the following steps: determining that the state of the multiply-add operation is a first target state when the target floating-point number is greater than a first floating-point number threshold and less than a second floating-point number threshold; the floating-point number threshold comprises the first floating-point number threshold and the second floating-point number threshold; a calculation window in the first target state contains a tail of the target floating-point number; determining the state of the multiply-add operation based on a size relationship between a right shift number of the target floating-point number and a bit number threshold when at least one of the target floating-point number is less than the first floating-point number threshold and the target floating-point number is greater than the second floating-point number threshold exists; the right shift number is used to retain a tail part corresponding to an exponent less than or equal to 0 in the tail of the target floating-point number in the calculation window.

[0017] In some embodiments, the determining the state of the multiply-add operation based on the size relationship between the target floating-point number and the bit-width threshold includes: determining a right shift number of the target floating-point number based on a mantissa bit-width of the target floating-point number, a mantissa of the target floating-point number, an exponent offset of the target floating-point number, and a first bit-width threshold; outputting the state of the multiply-add operation as a second target state in a case where the right shift number is less than the bit-width threshold; the calculation window in the second target state containing valid values of the mantissa part corresponding to an exponent less than or equal to 0; outputting the state of the multiply-add operation as a third target state in a case where the right shift number is greater than or equal to the bit-width threshold; the calculation window in the third target state not containing valid values of the mantissa part corresponding to the exponent less than or equal to 0.

[0018] In some embodiments, the outputting the fractional part of the target floating-point number based on the state of the multiply-add operation includes: determining an addition mantissa and an addition exponent based on the state of the multiply-add operation; and outputting the fractional part of the target floating-point number based on a sign bit of the target floating-point number, the addition mantissa, and the addition exponent.

[0019] In some embodiments, the determining the addition mantissa and the addition exponent based on the state of the multiply-add operation includes: in a case where the state of the multiply-add operation is the first target state, assigning a first floating-point value to a first addend of the calculation window in the first target state; placing the mantissa of the target floating-point number to the highest bit of the calculation window in the first target state, and assigning a first number of bits from the highest bit downwards to a second addend of the calculation window in the first target state; the first number of bits being determined based on a bit-width of the calculation window in the first target state, the calculation window in the first target state containing the mantissa of the target floating-point number; determining the addition mantissa based on the first addend and the second addend; and assigning the exponent of the target floating-point number as the addition exponent.

[0020] In some embodiments, the determining the addition mantissa and the addition exponent based on the state of the multiply-add operation includes: in a case where the state of the multiply-add operation is the second target state, placing the mantissa of the target floating-point number to the calculation window in the second target state according to the right shift number of the target floating-point number; determining the addition mantissa based on the placed mantissa of the target floating-point number and a sign bit of the target floating-point number; and determining the addition exponent based on an exponent offset of the target floating-point number.

[0021] In some embodiments, the determining the addition mantissa based on the placed mantissa of the target floating-point number and the sign bit of the target floating-point number includes: in a case where the target floating-point number is determined to be negative based on the sign bit of the target floating-point number, assigning a third floating-point value to a first addend of the calculation window in the second target state; assigning a second number of bits from the placed mantissa of the target floating-point number downwards to a second addend of the calculation window in the second target state; and performing subtraction on the first addend and the second addend to obtain the addition mantissa.

[0022] In some embodiments, the determining the addend exponent based on the state of the multiply-add operation comprises: in a case that the state of the multiply-add operation is the third target state, determining the addend exponent based on the exponent offset of the target floating-point number.

[0023] In some embodiments, the determining the addend exponent based on the state of the multiply-add operation comprises: in a case that the state of the multiply-add operation is the third target state, determining the addend exponent based on the exponent offset of the target floating-point number.

[0024] In some embodiments, the floating-point number processing method further comprises: in a case that the target floating-point number satisfies a preset condition, outputting a floating-point number value corresponding to the target floating-point number.

[0025] In some embodiments, the floating-point number processing method further comprises: in a case that the target floating-point number is 0, or the target floating-point number has no valid value in the fractional part but has a valid value in the integer part, determining that the target floating-point number satisfies a first preset condition; in a case that the target floating-point number is infinity INF, or the target floating-point number is not a number NaN, determining that the target floating-point number satisfies a second preset condition; the preset condition comprises at least one of the first preset condition and the second preset condition.

[0026] In some embodiments, the outputting the floating-point number value corresponding to the target floating-point number in a case that the target floating-point number satisfies a preset condition comprises at least one of: in a case that the target floating-point number satisfies a first preset condition, outputting a first floating-point number value; in a case that the target floating-point number satisfies a second preset condition, outputting a second floating-point number value.

[0027] In another aspect, the embodiments of the present disclosure provide a computer device, comprising a memory and a processor, wherein the memory stores a computer program capable of running on the processor, and the processor implements part or all of the steps of the above method when executing the program.

[0028] In another aspect, the embodiments of the present disclosure provide a computer readable storage medium, which stores a computer program capable of being executed by a processor to implement part or all of the steps of the above method.

[0029] In yet another aspect, the embodiments of the present disclosure provide a computer program, comprising computer readable code which, when run in a computer device, causes a processor in the computer device to perform some or all of the steps of the above method.

[0030] In yet another aspect, the embodiments of the present disclosure provide a computer program product, comprising a computer program which, when read and executed by a computer, implements some or all of the steps of the above method.

[0031] In the embodiments of the present disclosure, in the case that the target floating-point number does not satisfy the preset condition, the state of the multiply-add operation is reused to implement the processing of the FRC operation for obtaining the decimal part of the floating-point number. In this way, the calculation path of the multiply-add operation is reused to implement the processing of the FRC operation, thereby saving the circuit area consumption when the FRC calculation unit is separately arranged; the calculation power consumption of the FRC operation is saved by directly reusing the calculation path of the multiply-add operation, thereby improving the processing efficiency. Moreover, when the state of the multiply-add operation is reused to implement the processing of the FRC operation, the size relationship between the target floating-point number and the floating-point number threshold is considered, and the processing accuracy of the FRC operation can be improved.

[0032] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, but not limiting the technical solutions of the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0033] The accompanying drawings, which are incorporated into and form part of the specification, illustrate embodiments consistent with the present disclosure and, together with the specification, serve to explain the technical solutions of the present disclosure.

[0034] Figure 1 A constituent structure diagram of a floating-point number provided by the embodiments of the present disclosure;

[0035] Figure 2 A structure diagram of a separately configured FRC calculation unit provided by the embodiments of the present disclosure;

[0036] Figure 3 A structure diagram of a multiply-add operation unit provided by the embodiments of the present disclosure;

[0037] Figure 4 A calculation window diagram of a multiply-add operation unit provided by the embodiments of the present disclosure;

[0038] Figure 5 An implementation flowchart of a floating-point number processing method provided by the embodiments of the present disclosure Figure 1 ;

[0039] Figure 6An implementation flowchart of a floating-point number processing method provided by an embodiment of the present disclosure Figure 2 ;

[0040] Figure 7 An implementation flowchart of an addition mantissa in a floating-point number processing method provided by an embodiment of the present disclosure

[0041] Figure 8 An implementation flowchart of a processor provided by an embodiment of the present disclosure Figure 1 ;

[0042] Figure 9 An implementation flowchart of a processor provided by an embodiment of the present disclosure Figure 2 ;

[0043] Figure 10 A hardware entity diagram of a computer device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0044] In order to make the objects, technical solutions and advantages of the present disclosure clearer, the technical solutions of the present disclosure are further described in detail below in combination with the drawings and embodiments, and the described embodiments should not be regarded as limiting the present disclosure, and all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present disclosure.

[0045] In the following description, “some embodiments” are described, which describe a subset of all possible embodiments, but it can be understood that “some embodiments” can be the same subset or different subsets of all possible embodiments, and can be combined with each other without conflict.

[0046] The terms “first / second / third” involved only distinguish similar objects, and do not represent a specific order of the objects, and it can be understood that “first / second / third” can interchange specific order or sequence as allowed, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0047] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. The terms used herein are only for the purpose of describing the present disclosure, and are not intended to limit the present disclosure.

[0048] In order to better understand the floating-point number processing method provided by the embodiments of the present disclosure, the solutions in the related art will be described first.

[0049] A floating point number is composed of 1 sign bit, n exponent bits, and m mantissa bits. The sign bit indicates whether the floating point number is positive or negative. For example, a sign bit of 0 indicates a positive number, and a sign bit of 1 indicates a negative number. The exponent bits indicate the range of the value. The mantissa bits indicate the precision of the value, i.e., the fractional part of the value. Both n and m are positive integers greater than or equal to 1. For example, as shown in FIG. 1, a 32-bit floating point number (FP32) includes 23 mantissa bits (bits 0-23), 8 exponent bits (bits 24-30), and 1 sign bit (bit 31) in a 32-bit width. Figure 1

[0050] FRC is a commonly used floating point instruction, whose behavior is to input any floating point number x and output the fractional part of x as a floating point number. If x is equal to INF or NAN, then FRC(x) is equal to NAN.

[0051] The following formula describes the calculation method when x is not equal to INF or NAN:

[0052] FRC(x) = x - FLOOR(x);

[0053] where FLOOR is a floor function. The following examples show several typical FRC function calculation methods.

[0054] 1. x = +3.0f, FLOOR(x) = +3.0f, FRC(x) = x - FLOOR(x) = +0.0f, indicating that the fractional part of x is 0.

[0055] 2. x = -5.0f, FLOOR(x) = -5.0f, FRC(x) = x - FLOOR(x) = +0.0f, indicating that the fractional part of x is 0.

[0056] 3. x = +3.8f, FLOOR(x) = +3.0f, FRC(x) = x - FLOOR(x) = +0.8f.

[0057] 4. x = -3.8f, FLOOR(x) = -4.0f, FRC(x) = x - FLOOR(x) = +0.2f. Note that the FRC result is always positive, so x < 0 means that x is composed of a negative integer and a positive fraction.

[0058] 5. x = ±0.0f, FLOOR(x) = ±0.0f, FRC(x) = x - FLOOR(x) = +0.0f.

[0059] ​6、x = inf, FLOOR(x) = inf, FRC(x) = x - FLOOR(x) = NAN.

[0060] 7、x = NAN, FLOOR(x) = NAN, FRC(x) = x - FLOOR(x) = NAN.

[0061] In the related art, as shown in FIG. 1, a FRC calculation unit is separately arranged in an ALU to complete the calculation of the FRC function, and a selector selects one of the calculation result of the FRC calculation unit and the calculation result of other calculation units to output. Figure 2

[0062] The independent FRC calculation unit in the related art has the following problems:

[0063] 1. The independent FRC calculation unit leads to an increase in circuit area;

[0064] 2. A selector is added on the critical path, which makes the calculation time longer;

[0065] 3. The independent FRC calculation unit leads to an increase in the calculation power consumption of Fused Multiply-Add (FMA).

[0066] Embodiments of the present disclosure provide a floating-point number processing method, which reuses the calculation path of a multiply-add operation unit (the multiply-add operation unit is used for FMA operation) when calculating, and can realize the processing of FRC operation without increasing the calculation power consumption and circuit overhead. The multiply-add operation unit is described first.

[0067] Suppose that the multiply-add operation unit to be designed is used to calculate the multiply-add operation of three floating-point numbers. The three floating-point numbers are src0, src1 and src2, and the calculation mode is specified as src0*src1+src2. Correspondingly, the sign bits of the three floating-point numbers are named as sgn0, sgn1 and sgn2, the exponents of the three floating-point numbers are named as exp0, exp1 and exp2, and the mantissas of the three floating-point numbers are named as mat0, mat1 and mat2.

[0068] Figure 3 The FMA path in the multiply-add operation unit supports the mixed operation of FP32 (32-bit floating-point number) and FP16 (16-bit floating-point number), and the specific content is as follows:

[0069] Figure 3 The source operand extraction module in the multiply-add operation unit is used to extract the data of FP32 or FP16 to be calculated from each input source operand.

[0070] Figure 3 ​an exponent adjustment module in the exponent adjustment module, configured to adjust an exponent offset of each source operand according to a data format of the source operand, so as to unify different formats of floating-point numbers under the FP32 format.

[0071] Figure 3 a leading zero detection module in the leading zero detection module, configured to calculate a number of leading zeros of a mantissa of the src2.

[0072] Figure 3 an exponent subtraction module in the exponent subtraction module, configured to calculate a difference between the exp2 and exp01 (a sum of the exp0 and the exp1).

[0073] Figure 3 a window state detection module in the window state detection module, configured to detect whether the current instruction is running in the state one, the state two, the state three or the state four.

[0074] Figure 3 a mantissa bit shift module in the mantissa bit shift module, configured to right shift the mat2 according to the window state and the difference between the exp2 and the exp01.

[0075] Figure 3 a mantissa multiplication module in the mantissa multiplication module, configured to calculate the mat0*mat1 to obtain the mat01.

[0076] Figure 3 an addition exponent calculation module in the addition exponent calculation module, configured to select the exp2 or the exp01 as an exponent after the exponent alignment, i.e., the exp_add, according to the window state.

[0077] Figure 3 a window selection module in the window selection module, configured to select the addin0 and the addin1 to be calculated by addition or subtraction from the bit-shifted mat2 and the mat01 according to the window state.

[0078] Figure 3 a mantissa addition module in the mantissa addition module, configured to calculate the addin0 and the addin1 by addition or subtraction.

[0079] Figure 3 a leading zero prediction module in the leading zero prediction module, configured to calculate a number of leading zeros of a result of the addition or subtraction of the addin0 and the addin1.

[0080] Figure 3 a normalization operation module in the normalization operation module, configured to perform a normalization operation on the exponent and the mantissa after the addition.

[0081] wherein a total bit width of the calculation window is mat_width_tmp*4+7 bits, a bit width of the addition window in the states of the state one and the state two of the multiply-add operation is mat_width_tmp*2+6 bits, and a bit width of the addition window in the states of the state three and the state four of the multiply-add operation is mat_width_tmp*2+6 bits.

[0082] As Figure 4 shown, taking single-precision floating-point numbers as an example, mat_width_tmp is 23, the total bit width of the calculation window is 99 bits at this time, the bit width of the addition window in the state one and the state two of the multiply-add operation is 52 bits, and the bit width of the addition window in the state three and the state four of the multiply-add operation is also 52 bits. From high to low, the calculation window is divided into three parts, and the length of each part is 26 bits (the highest part), 50 bits (the second highest part) and 23 bits in turn.

[0083] In the initial state, mat2 is placed at the highest bit of the highest part of the calculation window, and mat01 is placed at the highest bit of the second highest part of the calculation window. Then, mat2 is shifted downward in the calculation window according to the size relationship between exp2 and the multiply-add operation unit.

[0084] If exp01+27-exp2<0, it is considered that exp2 is much larger than exp01, mat2 is not shifted, otherwise mat2 needs to be right shifted by exp01+27-exp2 bits. After the shift, the addition mantissa mat_add is calculated.

[0085] State one: if 0>exp01+27-exp2, addin0=0 is set, mat2 in the highest part and the second highest part of the shifted window with a total of 51 bits is taken as addin1, and then the addition or subtraction operation of addin0 and addin1 is performed to obtain mat_add. All mat01 is regarded as sticky bit. Correspondingly, the addition exponent is selected as exp_add=exp2.

[0086] State two: if 26>exp01+27-exp2>=0, mat01 in the highest part and the second highest part of the shifted window with a total of 51 bits is taken as addin0=0, and mat2 in the highest part and the second highest part of the shifted window with a total of 51 bits is taken as addin1, and then the addition or subtraction operation of addin0 and addin1 is performed to obtain mat_add. The mat01 in the second highest part that is not taken is regarded as sticky bit. Correspondingly, the addition exponent is selected as exp_add=exp01+27. Mat2 in the highest part and the second highest part of the shifted window with a total of 51 bits is taken as addin1, that is, addin1=shf_mat2[mat_width_tmp*4+6: mat_width_tmp*2+2] at this time.

[0087] State 3: If 76 > exp01 + 27 - exp2 >= 26, then truncate the second-highest portion of the window after displacement (50 bits total, mat01) as addin0, and truncate the second-highest portion of the window after displacement (50 bits total, mat2) as addin1. Then perform addition or subtraction operations on addin0 and addin1 to obtain mat_add. Treat mat2 in the lowest part of the window as sticky bits. And correspondingly, choose the addition exponent as exp_add = exp01.

[0088] State 4: If exp01 + 27 - exp2 >= 76, then extract the second-highest portion of the window after displacement, totaling 50 bits (mat01), as addin0, and set addin1 = 0. Then, perform addition or subtraction operations on addin0 and addin1 to obtain mat_add. Treat all mat2 bits as sticky bits. Correspondingly, select the addition exponent as exp_add = exp01.

[0089] Finally, after checking for leading zeros in the mantissa of the addition, the mantissa and exponent of the addition are adjusted according to the specific situation to obtain the floating-point result after normalization.

[0090] The floating-point number processing method provided in the embodiments of this disclosure will be described in detail below.

[0091] This disclosure provides a floating-point number processing method, which can be executed by a processor of a computer device. The computer device refers to a device with data processing capabilities, such as a server, laptop, tablet, desktop computer, smart TV, set-top box, or mobile device (e.g., mobile phone, portable video player, personal digital assistant, dedicated messaging device, portable gaming device). Figure 5 This is a schematic diagram illustrating the implementation flow of a floating-point number processing method provided in an embodiment of this disclosure, as shown below. Figure 5 As shown, the method includes the following steps 501 to 502:

[0092] Step 501: In response to the first signal for the target floating-point number, if the target floating-point number does not meet the preset conditions, determine the state of the multiplication-addition operation that matches the target floating-point number based on the size relationship between the target floating-point number and the floating-point number threshold.

[0093] The first signal is used to obtain the fractional part of the target floating-point number. For example, the first signal can be a signal used to perform an FRC operation on the target floating-point number. The target floating-point number is any floating-point number that needs to be processed.

[0094] The preset condition is used to determine whether the floating point number value corresponding to the floating point number can be directly output. For example, the floating point number value can include 0 and NAN. NAN represents not a number, i.e., not a valid number value. This situation usually occurs in some mathematical operations, such as 0 divided by 0, or some illegal mathematical operations, and the result is NAN.

[0095] In a possible implementation, the preset condition can include a condition for determining whether 0 is directly output, and a condition for determining whether the special value NAN is directly output.

[0096] The target floating point number does not satisfy the preset condition, which means that the target floating point number is neither 0, INF, NaN, nor a pure integer; that is, the target floating point number can be a pure decimal number, or a floating point number with both integer and decimal parts. The floating point number threshold is used to determine the state of the multiplication-addition operation matched with the floating point number.

[0097] In some embodiments, the specific implementation of step 501 can be: if the target floating point number satisfies the floating point number threshold, it is determined that the target floating point number meets the state one of the multiplication-addition operation; if the target floating point number does not satisfy the floating point number threshold, the right shift number of the target floating point number is determined; and the state of the multiplication operation matched with the target floating point number is determined according to the right shift number.

[0098] In some embodiments, the specific implementation of "determining the state of the multiplication operation matched with the target floating point number according to the right shift number" can be: determining the state of the multiplication operation matched with the target floating point number according to the size relationship between the right shift number and the bit threshold.

[0099] Further, the specific implementation of "determining the state of the multiplication operation matched with the target floating point number according to the size relationship between the right shift number and the bit threshold" can be: in the case that the right shift number satisfies the bit threshold, determining that the state of the multiplication operation matched with the target floating point number is the second target state; and in the case that the right shift number does not satisfy the bit threshold, determining that the state of the multiplication operation matched with the target floating point number is the third target state.

[0100] Step 502: outputting the decimal part of the target floating point number based on the state of the multiplication-addition operation.

[0101] In some embodiments, the specific implementation of step 502 can be: if the target floating-point number satisfies the floating-point number threshold, determining that it meets the state one of the multiply-add operation, processing the target floating-point number according to the state one of the multiply-add operation, and outputting the fractional part of the target floating-point number. If the target floating-point number does not satisfy the floating-point number threshold, determining the right shift number of the target floating-point number; determining the state of the product operation matched with the target floating-point number according to the right shift number; processing the target floating-point number according to the state of the product operation matched with the target floating-point number, and outputting the fractional part of the target floating-point number.

[0102] In the embodiments of the present disclosure, in the case that the target floating-point number does not satisfy the preset condition, the state of the multiply-add operation is reused to implement the processing of the FRC operation for obtaining the fractional part of the floating-point number. In this way, the processing of the FRC operation is implemented by reusing the calculation path of the multiply-add operation, thereby saving the circuit area consumption when the FRC calculation unit is separately set; by directly reusing the calculation path of the multiply-add operation, the calculation power consumption of the FRC operation is saved, and the processing efficiency is improved. Moreover, when the state of the multiply-add operation is reused to implement the processing of the FRC operation, the size relationship between the target floating-point number and the floating-point number threshold is considered, and the processing accuracy of the FRC operation can be improved.

[0103] The embodiments of the present disclosure provide a floating-point number processing method, which can be executed by a processor of a computer device. As shown in Figure 6 The method includes the following steps 601 to 603:

[0104] Step 601, in response to a first signal for a target floating-point number, in the case that the target floating-point number does not satisfy the preset condition, determining the state of the multiply-add operation matched with the target floating-point number based on the size relationship between the target floating-point number and a floating-point number threshold.

[0105] Step 602, outputting the fractional part of the target floating-point number based on the state of the multiply-add operation.

[0106] Here, steps 601 to 602 correspond to the aforementioned steps 501 to 502 respectively, and in implementation, the specific implementation of the aforementioned steps 501 to 502 can be referred to.

[0107] Step 603, in the case that the target floating-point number satisfies the preset condition, outputting the floating-point number value corresponding to the target floating-point number.

[0108] In some embodiments, the specific implementation of determining whether the target floating-point number satisfies the preset condition can be: determining that the target floating-point number satisfies a first preset condition in a case where the target floating-point number is 0, or the decimal part of the target floating-point number has no valid value but the integer part has a valid value; determining that the target floating-point number satisfies a second preset condition in a case where the target floating-point number is infinity INF, or the target floating-point number is not a number NaN; and the preset condition includes the first preset condition and the second preset condition.

[0109] The decimal part of the target floating-point number has no valid value but the integer part has a valid value, which means that the target floating-point number is a pure integer.

[0110] The first preset condition is a condition for judging whether 0 can be directly output. For example, the first preset condition can be whether the floating-point number is 0, or the floating-point number is a pure integer. If the target floating-point number is 0, it is determined that the target floating-point number satisfies the first preset condition; if the target floating-point number is a pure integer, it is determined that the target floating-point number satisfies the first preset condition.

[0111] The second preset condition is a condition for judging whether to directly output NaN. For example, the second preset condition can be whether the floating-point number is INF (infinity) or NaN (not a number). If the target floating-point number is INF, it is determined that the target floating-point number satisfies the second preset condition; if the target floating-point number is NaN, it is determined that the target floating-point number satisfies the second preset condition.

[0112] In some embodiments, the specific implementation of judging whether the target floating-point number is 0 can be: if the mantissa and the exponent of the target floating-point number are both equal to 0, it is determined that the target floating-point number is 0.

[0113] In some embodiments, the specific implementation of judging whether the target floating-point number is a pure integer can be: if the target floating-point number is greater than an exponent threshold, it is determined that the target floating-point number is a pure integer; wherein the exponent threshold is determined based on the exponent bit width and the mantissa bit width of the data format of the floating-point number supported by the multiplication and addition operation.

[0114] For example, if the multiplication and addition operation supports the calculation of single-precision floating-point numbers (FP32), the exponent of the single-precision floating-point number has 8 bits, and the mantissa bit width is 23 bits, then the exponent offset of the target floating-point number is 2 8 -1, and the exponent threshold is 2 8 -1+23-1=149. If the exponent of the target floating-point number is greater than 149 (the exponent threshold), it is determined that the integer part of the target floating-point number has a valid value but the decimal part has no valid value; that is, it is determined that the target floating-point number is a pure integer.

[0115] In some embodiments, the specific implementation of step 503 can be: outputting a first floating-point number value if the target floating-point number satisfies the first preset condition; outputting a second floating-point number value if the target floating-point number satisfies the second preset condition.

[0116] The first floating-point number value is 0.0, and the second floating-point number value is NaN.

[0117] For example, if the target floating-point number is 0 or a pure integer, 0 is directly output. If the target floating-point number is INF or NaN, NaN is directly output.

[0118] In the embodiments of the present disclosure, the processing of the FRC operation for obtaining the decimal part of the floating-point number is divided into two cases: a case where a constant corresponding to the floating-point number can be directly output, and a case where the processing needs to reuse the multiply-add module. The two cases are distinguished by a preset condition. In the case where the target floating-point number satisfies the preset condition, the constant corresponding to the target floating-point number is directly output. In the case where the target floating-point number does not satisfy the preset condition, the processing of the FRC operation is implemented by reusing the state of the multiply-add operation. In this way, the processing of the FRC operation is implemented by reusing the calculation path of the multiply-add operation, thereby saving the circuit area consumption when a separate FRC calculation unit is set. In the processing, the separate FRC calculation unit is not used, and the calculation path of the multiply-add operation is directly reused. This process saves the calculation power consumption of the FRC operation and improves the processing efficiency. Moreover, when the processing of the FRC operation is implemented by reusing the state of the multiply-add operation, both the size relationship between the target floating-point number and the floating-point number threshold and the size relationship between the right shift number of the target floating-point number and the bit number threshold are considered, thereby further improving the processing accuracy of the FRC operation.

[0119] In some embodiments, the "determining a state of a multiply-add operation matched with the target floating-point number based on a size relationship between the target floating-point number and a floating-point number threshold" in step 601 can be implemented by the following step 6011 or step 6012:

[0120] Step 6011: determining that the state of the multiply-add operation is a first target state if the target floating-point number is greater than a first floating-point number threshold and less than a second floating-point number threshold.

[0121] The floating-point number threshold includes the first floating-point number threshold and the second floating-point number threshold. The calculation window in the first target state includes the mantissa of the target floating-point number.

[0122] The first floating-point number threshold is 0.0, and the second floating-point number threshold is 1.0. The first target state refers to Figure 4 the state of the multiply-add operation is one. From Figure 4As can be seen from the data, the first target state includes all the mantissas of the target floating-point number. The target floating-point number is greater than the first floating-point threshold and less than the second floating-point threshold, indicating that the target floating-point threshold meets the floating-point threshold requirements.

[0123] For example, if 0.0f < target floating-point number < +1.0f, then the target floating-point number is determined to be a decimal, and should be output as is. Therefore, the state of the multiplication-addition operation matching the target floating-point number is the first target state. Figure 4 (State 1 in the middle).

[0124] Step 6012: If at least one of the target floating-point number being less than the first floating-point number threshold and the target floating-point number being greater than the second floating-point number threshold exists, determine the state of the multiplication-addition operation based on the relationship between the number of bits shifted right of the target floating-point number and the number of bits threshold.

[0125] The right shift bit is used to retain the mantissa portion of the target floating-point number whose exponent is less than or equal to 0 in the calculation window.

[0126] If the target floating-point number is less than the first floating-point threshold or greater than the second floating-point threshold, it means that the target floating-point number does not meet the floating-point threshold. The right shift bits are used both to determine the status of the multiplication-addition operation that matches the target floating-point number and to retain the mantissa portion of the target floating-point number whose exponent is less than or equal to 0 in the calculation window.

[0127] Based on the above technical solution, the first floating-point threshold and the second floating-point threshold can be used to determine whether the target floating-point number is a decimal. If the target floating-point number is greater than the first floating-point threshold and less than the second floating-point threshold, it is determined that the target floating-point number is a decimal. In this case, the target floating-point number should be output as is, and the state of the multiplication-addition operation should be considered the first target state. Figure 4 In state one, the target floating-point number is processed. If the target floating-point number is less than the first floating-point threshold or greater than the second floating-point threshold, it is determined that the target floating-point number is not entirely a decimal. In this case, the state of the multiplication-accumulation operation corresponding to the target floating-point number needs to be further determined based on the relationship between the number of bits shifted right and the bit threshold. In this way, determining the state of the multiplication-accumulation operation hierarchically can improve the processing efficiency of FRC operations.

[0128] In some implementations, step 6012 can be achieved by the following steps 6012a to 6012c:

[0129] Step 6012a: Determine the number of bits to right shift the target floating-point number based on the mantissa width of the target floating-point number, the mantissa of the target floating-point number, the exponent offset of the target floating-point number, and the first bit width threshold.

[0130] During multiplication and addition operations, mat2 is shifted to the right based on the state of the calculation window; similarly, when reusing the calculation path of multiplication and addition operations to process FRC operations, the target floating-point number also needs to be shifted to the right.

[0131] like Figure 4 As shown, in the initial state, mat2 is placed in the highest position of the calculation window, and then the right shift number is calculated according to the value of exp2, so as to retain the mantissa part of the target floating-point number whose exponent is less than or equal to 0 in the calculation window.

[0132] In some implementations, the specific method for "determining the number of right shifts of the target floating-point number based on the mantissa width of the target floating-point number, the mantissa of the target floating-point number, the exponent offset of the target floating-point number, and the first width threshold" can be as follows: adjust the mantissa of the target floating-point number according to the exponent offset of the target floating-point number to obtain the first right shift; perform an addition operation on the mantissa width and the first width threshold of the target floating-point number to obtain the second right shift; and perform a subtraction operation on the second right shift and the first right shift to obtain the third right shift.

[0133] For example, using single-precision floating-point numbers as an example, refer to... Figure 4 The mantissa width of the target floating-point number is 23, the first bit width threshold is the extended bit width of 3, and the exponent offset of the target floating-point number is 2. 8 -1; At this point, the number of bits shifted to the right should be 23 + 3 - (exp2 - (2 8 -1))=153-exp2.

[0134] In some implementations, the bit width threshold can be determined by performing an addition operation on the bit width of the calculation window in states one and two, and the bit width of the calculation window in states three and four, and then removing the overlapping bit width of the two calculation windows to obtain the bit width threshold.

[0135] For example, using single-precision floating-point numbers as an example, refer to... Figure 4 The bit width of the calculation window in states one and two, and the bit width of the calculation window in states three and four are all 23*2+6. The bit width of the two windows overlaps by 28. At this time, the bit threshold is: (23*2+6)*2-28=76.

[0136] Step 6012b: If the number of right shifts is less than the number of bits threshold, output the state of the multiplication-addition operation as the second target state; the calculation window in the second target state contains the valid value of the mantissa portion of the corresponding exponent which is less than or equal to 0.

[0137] The second target state refers to Figure 4 State three of the multiplication and addition operation.

[0138] If the right shift bits are less than the bit threshold, it means that after the target floating-point number is right-shifted by the number of bits, states three and four will still contain the mantissa of the target floating-point number. Figure 7 State 3 is shown; at this time, the calculation window under State 3 and State 4 contains the valid values ​​of the mantissa portion of the corresponding exponent less than or equal to 0 (exp≤0).

[0139] For example, taking a single-precision floating-point number as an example, the right shift bits are 153 - exp2, and the bit threshold is 76. If the right shift bits are less than 76, then the state of the multiply-accumulate operation that matches the target floating-point number is determined to be state three (second target).

[0140] Step 6012c: If the number of right shifts is greater than or equal to the number of bits threshold, output the state of the multiplication-addition operation as the third target state; the calculation window in the third target state does not contain the valid value of the mantissa part with the corresponding exponent less than or equal to 0.

[0141] The third objective state refers to Figure 4 State four of multiplication and addition operations.

[0142] If the right shift bits are greater than or equal to the bit threshold, it means that after right shifting the target floating-point number by the specified number of bits, states three and four do not contain the mantissa of the target floating-point number. Figure 7 State four is shown.

[0143] For example, taking a single-precision floating-point number as an example, the right shift bits are 153 - exp2, and the bit threshold is 76. If the right shift bits are greater than or equal to 76, then the state of the multiplication-addition operation that matches the target floating-point number is determined to be state three (second target).

[0144] Based on the above technical solution, the state of the multiplication and addition operation corresponding to the target floating-point number can be clearly determined according to the relationship between the number of bits shifted to the right of the target floating-point number and the bit threshold. Then, the FRC operation on the target floating-point number can be realized based on the state of the multiplication and addition operation corresponding to the target floating-point number.

[0145] In some implementations, step 602 above can be achieved by the following steps 6021 to 6022:

[0146] Step 6021: Based on the state of the multiplication-addition operation, determine the mantissa and exponent of the addition.

[0147] In some implementations, step 6021 can be specifically implemented as follows: when the target floating-point number is a pure decimal (the target floating-point number is greater than the first floating-point number threshold and less than the second floating-point number threshold), the target floating-point number is processed according to the state one of multiplication and addition to obtain the addition mantissa; the exponent of the target floating-point number is used as the addition exponent.

[0148] In some implementations, step 6021 can also be implemented as follows: when the target floating-point number is less than the first floating-point number threshold and the number of bits shifted to the right is less than the number of bits threshold, the target floating-point number is processed according to the state three of the multiplication-addition operation to obtain the mantissa of the addition; the exponent offset of the target floating-point number is used as the addition exponent.

[0149] In some implementations, step 6021 can also be implemented as follows: when the target floating-point number is greater than the first floating-point number threshold and the number of bits shifted to the right is less than the number of bits threshold, the target floating-point number is processed according to the state three of the multiplication-addition operation to obtain the mantissa of the addition; the exponent offset of the target floating-point number is used as the addition exponent.

[0150] In some implementations, step 6021 can also be implemented as follows: when the target floating-point number is less than the first floating-point number threshold and the number of bits shifted to the right is greater than the number of bits threshold, the target floating-point number is processed according to the state four of the multiplication-addition operation to obtain the mantissa of the addition; the exponent offset of the target floating-point number is used as the addition exponent.

[0151] In some implementations, step 6021 can also be implemented as follows: when the target floating-point number is greater than the first floating-point number threshold and the number of bits shifted to the right is greater than the number of bits threshold, the target floating-point number is processed according to the state four of the multiplication-addition operation to obtain the mantissa of the addition; the exponent offset of the target floating-point number is used as the addition exponent.

[0152] Step 6022: Based on the sign bit of the target floating-point number, the mantissa of the addition, and the exponent of the addition, output the fractional part of the target floating-point number.

[0153] In one feasible implementation, the sign bit, mantissa, and exponent of the target floating-point number are organized into a floating-point data format through a normalization module to obtain the output result of the target instruction.

[0154] In some embodiments, when the state of the multiplication-addition operation is the first target state, the above step 6021 can be implemented by the following steps A1 to A4:

[0155] Step A1: When the state of the multiplication-addition operation is the first target state, assign the first floating-point value to the first addend of the calculation window in the first target state.

[0156] The first floating-point value is 0. For example, the state in the multiplication-addition operation is the first target state ( Figure 4 In state one, assign 0 to Figure 4 In state one, addmin0 (the first addend).

[0157] Step A2: Place the mantissa of the target floating-point number in the highest bit of the calculation window in the first target state, and truncate the first bit from the highest bit and assign it to the second addend of the calculation window in the first target state; the first bit is determined based on the bit width of the calculation window in the first target state, and the calculation window in the first target state contains the mantissa of the target floating-point number.

[0158] The first digit is used to extract the valid part of the mantissa of the target floating-point number after it has been arranged.

[0159] Taking single-precision floating-point numbers as an example, when the state of the multiplication and addition operation that matches the target floating-point number is state one, the truncation bits of addin1 are 51 bits from high to low in the calculation window of the first target state.

[0160] For example, such as Figure 7 The state shown is the first target state in the multiplication-addition operation. Figure 4 In state one, the mantissa of the target floating-point number is placed as mat2 in the highest bit of the calculation window, and 51 bits are truncated from the highest bit and assigned to it. Figure 4 In state one, addmin1 (the second addend).

[0161] Step A3: Determine the mantissa based on the first addend and the second addend.

[0162] In some implementations, the state during the multiplication-addition operation is the first target state ( Figure 4 In state one, the first addend and the second addend are added to obtain the mantissa.

[0163] For example, the state in the multiplication-addition operation is the first target state ( Figure 4 In state one, the first addend is 0, the second addend is mat2, and the mantissa of the addition is mat2+0.

[0164] Step A4: Use the exponent of the target floating-point number as the addition exponent.

[0165] For example, the state in the multiplication-addition operation is the first target state ( Figure 4 In state one, set the addition exponent exp_add=exp2.

[0166] The FRC operation operates on a single floating-point number, while the multiply-accumulate operation operates on three floating-point numbers. During processing, the FRC operation's operand is treated as the third floating-point number in the multiply-accumulate operation. Figure 3 In src2), the first floating-point number ( Figure 3 src0 in the second floating-point number ( Figure 3In the implementation, if the target floating-point number is a pure decimal, then the state of the multiplication-addition operation is state one (…). Figure 4 In the method described in State 1, addin0=0 is set, the target floating-point number is placed in the highest bit of the calculation window in State 1, and mat2 within the first 51 bits is used as addin1. Then, the addition operation of addin0 and addin1 is performed to obtain mat_add (the mantissa of the addition). Here, all mat01 are regarded as sticky bits, and the addition exponent is selected as exp_add=exp2.

[0167] In some embodiments, when the multiplication-addition operation is in the second target state, step 6021 can be implemented by the following steps B1 to B3:

[0168] Step B1: When the multiplication-addition operation is in the second target state, the mantissa of the target floating-point number is placed in the calculation window of the second target state according to the number of right shifts of the target floating-point number.

[0169] If the target floating-point number is less than the first floating-point threshold and the number of right shift bits is less than the number of bits threshold, or if the target floating-point number is greater than the first floating-point threshold and the number of right shift bits is less than the number of bits threshold, then it is processed according to the state of multiplication and addition operation as state three. The processing logic is to extract only the valid value of the mantissa part of mat2 whose exponent is less than or equal to 0 (exp≤0) through the calculation window, and assign the first addend of the calculation window according to the size relationship between the number of right shift bits and the number of bits threshold.

[0170] like Figure 7 As shown in state three, based on the number of right shifts of the target floating-point number, the mantissa of the target floating-point number is placed in the calculation window under the second target state (state three), so that the bit corresponding to the exponent 0 in mat2 is shifted to the highest bit of the calculation window under the second target state. At this time, the calculation window under the second target state only retains the valid value of the mantissa part corresponding to the exponent of mat2 that is less than or equal to 0 (exp≤0).

[0171] Step B2: Determine the addition mantissa based on the mantissa of the target floating-point number after placement and the sign bit of the target floating-point number.

[0172] In some implementations, when the target floating-point number is negative, step B2 can be implemented as follows: if the target floating-point number is determined to be negative based on the sign bit of the target floating-point number, the third floating-point value is assigned to the first addend of the calculation window in the second target state; the second digit of the mantissa of the target floating-point number after placement is truncated from the high digit downwards and assigned to the second addend of the calculation window in the second target state; the first addend and the second addend are subtracted to obtain the mantissa.

[0173] The third floating-point value is 1 << 49. The second bit is the second highest 50 bits.

[0174] For example, when the target floating-point number is negative, set addin0 to 1<<49, extract all 50 bits of the second highest part of mat2 after it is right-shifted within the calculation window, and subtract addin1 from addin0 to obtain the mantissa of the addition.

[0175] In some implementations, when the target floating-point number is positive, step B2 can be implemented as follows: if the target floating-point number is determined to be positive based on the sign bit of the target floating-point number, the first floating-point value is assigned to the first addend of the calculation window in the second target state; the second bit excluding the highest bit of the mantissa of the target floating-point number after it is placed is truncated from the high bit downwards and assigned to the second addend of the calculation window in the second target state; the first addend and the second addend are added to obtain the mantissa.

[0176] The first floating-point value is 0. The third bit is the lower 49 bits of the second-highest part (the highest bit is discarded).

[0177] For example, when the target floating-point number is positive, set addin0 to 0, extract the lower 49 bits of the second highest part of mat2 after it is right-shifted within the calculation window, and then addin0+addin1 to obtain the mantissa of the addition.

[0178] Step B3: Determine the addition exponent based on the exponent offset of the target floating-point number.

[0179] In some implementations, step B3 can be specifically implemented by using the exponent offset of the target floating-point number as the addition exponent.

[0180] In some embodiments, when the multiplication-addition operation is in the third target state, step 6021 can be implemented by the following steps C1 to C3:

[0181] Step C1: When the multiplication-addition operation is in the third target state, the mantissa of the target floating-point number is placed in the calculation window of the third target state according to the number of right shifts of the target floating-point number.

[0182] If the target floating-point number is less than the first floating-point threshold and the number of bits shifted to the right is greater than the number of bits threshold, or if the target floating-point number is greater than the first floating-point threshold and the number of bits shifted to the right is greater than the number of bits threshold, then it is processed according to the state of multiplication and addition operation as state four. The processing logic is that mat2 is very small at this time, which has exceeded the calculation window under state four, and can be regarded as 0; however, at this time, it is still necessary to assign a value to the first addend of the calculation window according to the relationship between the number of bits shifted to the right and the number of bits threshold.

[0183] like Figure 7 As shown in state four, after right-shifting the target floating-point number according to the number of right shifts, the mantissa of the target floating-point number will exceed the calculation window under the third target state (state four).

[0184] Step C2: Determine the addition mantissa based on the mantissa of the target floating-point number after placement and the sign bit of the target floating-point number.

[0185] In some implementations, when the target floating-point number is negative, step B2 can be implemented as follows: if the target floating-point number is determined to be negative based on the sign bit of the target floating-point number, assign the third floating-point value to the first addend of the calculation window in the third target state; truncate the second digit of the mantissa of the target floating-point number after placement from the high bit downwards, and assign it to the second addend of the calculation window in the third target state; perform subtraction on the first addend and the second addend to obtain the mantissa.

[0186] For example, such as Figure 7 In the fourth state shown, when the multiplication and addition operation matching the target floating-point number is in the third target state (state four), the placed target floating-point number has exceeded the calculation window under state four. At this time, the second addend addedin1 is 0. When the target floating-point number is negative, addin0 is set to 1<<49, and addin0-addin1 is performed to obtain the mantissa of the addition.

[0187] In some implementations, when the target floating-point number is positive, step B2 can be implemented as follows: if the target floating-point number is determined to be positive based on the sign bit of the target floating-point number, the first floating-point value is assigned to the first addend of the calculation window in the third target state; the second bit excluding the highest bit of the mantissa of the target floating-point number after it is placed is truncated from the high bit downwards and assigned to the second addend of the calculation window in the third target state; the first addend and the second addend are added to obtain the mantissa.

[0188] For example, such as Figure 7 In the fourth state shown, when the multiplication and addition operation matching the target floating-point number is in the third target state (state four), the placed target floating-point number has exceeded the calculation window under state four. At this time, the second addend addedin1 is 0. When the target floating-point number is positive, the first addend addedin0 is set to 0, and addin0+addin1 is performed to obtain the mantissa of the addition.

[0189] Step C3: Determine the addition exponent based on the exponent offset of the target floating-point number.

[0190] In some implementations, step C3 can be specifically implemented by using the exponent offset of the target floating-point number as the addition exponent.

[0191] This disclosure provides a processor, such as... Figure 8 and Figure 9 As shown, Figure 8 The diagram mainly illustrates the various units required to implement FRC operations by using the multiplexing multiplication-addition computational path. Figure 9 The main focus is on a more specific structural configuration, whereby the processor includes: a multiply-accumulate unit;

[0192] The multiply-accumulate unit is used to determine the state of the multiply-accumulate operation that matches the target floating-point number based on the size relationship between the target floating-point number and the floating-point number threshold when the target floating-point number does not meet the preset conditions; and to output the decimal part of the target floating-point number based on the state of the multiply-accumulate operation.

[0193] In some embodiments, such as Figure 8 and Figure 9 As shown, the multiply-accumulate operation unit includes: a window state detection module;

[0194] The window state detection module is used to output the state of the multiplication-addition operation as a first target state when the target floating-point number is greater than a first floating-point number threshold and less than a second floating-point number threshold; the floating-point number threshold includes the first floating-point number threshold and the second floating-point number threshold; the calculation window in the first target state includes the mantissa of the target floating-point number.

[0195] In some embodiments, the window state detection module is further configured to output the state of the multiplication-addition operation as a second target state when at least one of the target floating-point number being less than the first floating-point number threshold and the target floating-point number being greater than the second floating-point number threshold exists, and the number of right shift bits is less than the number of bits threshold; the calculation window in the second target state contains the valid values ​​of the mantissa portion of the target floating-point number whose exponent is less than or equal to 0.

[0196] In some embodiments, the window state detection module is further configured to output the state of the multiplication-addition operation as a third target state when at least one of the target floating-point number being less than the first floating-point number threshold and the target floating-point number being greater than the second floating-point number threshold exists, and the number of right shift bits is greater than or equal to the number of bits threshold; the calculation window in the third target state does not contain a valid value of the mantissa portion of the target floating-point number whose corresponding exponent is less than or equal to 0.

[0197] In some embodiments, such as Figure 8 and Figure 9 As shown, the processor includes: a displacement value calculation unit; the input port of the displacement value calculation unit is connected to the input port of the multiply-accumulate operation unit, and the output port of the displacement value calculation unit is connected to the input port of the window state detection module; the displacement value calculation unit is used to determine the number of right shifts of the target floating-point number based on the mantissa bit width of the target floating-point number, the mantissa of the target floating-point number, the exponent offset of the target floating-point number, and the first bit width threshold.

[0198] In some embodiments, such as Figure 8 and Figure 9 As shown, the multiplication-addition unit further includes: an addition exponent calculation module; the input port of the addition exponent calculation module is connected to the output port of the window state detection module; the addition exponent calculation module is used to determine the addition exponent based on the state of the multiplication-addition operation; the addition exponent is used to determine the fractional part of the target floating-point number; when the state of the multiplication-addition operation is a first target state, the addition exponent is the exponent of the target floating-point number; when the state of the multiplication-addition operation is a second target state or a third target state, the addition exponent is determined based on the exponent offset of the target floating-point number.

[0199] In some embodiments, such asFigure 8 and Figure 9 As shown, the multiplication-addition unit further includes: an addition mantissa calculation module; the input port of the addition mantissa calculation module and the input port of the addition exponent calculation module are connected in parallel to the output port of the window state detection module; the addition mantissa calculation module is used to determine the addition mantissa based on the state of the multiplication-addition operation; the addition mantissa is used to determine the fractional part of the target floating-point number; when the state of the multiplication-addition operation is a first target state, the addition mantissa is determined based on the first addend and the second addend of the calculation window in the first target state; in the first target state, the first addend is a first floating-point value, and the second addend is the first number of bits truncated from the highest bit after the mantissa of the target floating-point number is placed in the highest bit of the calculation window; the first number of bits is determined based on the bit width of the calculation window in the first target state; when the state of the multiplication-addition operation is a second target state or a third target state, the addition mantissa is determined based on the mantissa of the target floating-point number after placement and the sign bit of the target floating-point number, and the mantissa of the target floating-point number after placement is placed in the calculation window according to the right shift of the target floating-point number.

[0200] In some embodiments, such as Figure 8 and Figure 9 As shown, the processor further includes: a selector; the selector is connected to the input of the processor and the output of the multiply-accumulate unit respectively; the selector is used to output the floating-point value corresponding to the target floating-point number when the target floating-point number meets the preset condition; and to output the decimal part of the target floating-point number when the target floating-point number does not meet the preset condition.

[0201] The following describes the application of the floating-point number processing method provided in this disclosure in a real-world scenario, using single-precision floating-point numbers as an example.

[0202] The embodiments disclosed herein embed FRC operations into the algorithm of FMA instructions, implementing both FRC and FMA instructions with the same set of circuitry without increasing power consumption or circuit overhead.

[0203] In this embodiment, the src2 of the FMA is used as the input to the FRC operation, and src0 and src1 are set to 0. The FRC operation is calculated using the FMA path according to the following method:

[0204] If both exp2 and mat2 are equal to 0, then src2 is determined to be equal to 0, and 0 is output directly.

[0205] Otherwise, if src2 is INF or NAN, then simply output NAN.

[0206] If all the corresponding exponents of mat2 are greater than or equal to 0, it is considered that this floating-point number has no fractional part, and 0 can be directly output. Taking single-precision floating-point numbers as an example, if exp2 > 149, it is determined that src2 has no fraction, and 0 is directly output.

[0207] For cases other than the above three, the FRC result needs to be calculated by reusing the FMA path.

[0208] If 0.0f < src2 < +1.0f, that is, all of src2 are fractions, src2 should be output as it is. Therefore, mat2 is placed at the highest bit of the calculation window, the right shift bit number of mat2 is set to 0, and the addition exponent exp_add = exp2 is set, and it is determined that it belongs to the first state of the FMA calculation path. Intercept according to the first state of the FMA calculation path. After interception, addin0 is equal to 0, that is, the mantissa addition is mat2 + 0, and after normalization, src2 will be output as it is finally.

[0209] If it is not 0.0f < src2 < +1.0f, it is necessary to determine that it belongs to the third or fourth state of the FMA calculation path, and it is stipulated that the highest bit corresponding exponent of the calculation window intercepted according to the third or fourth state of the FMA calculation path is 0. According to the requirement that the high-order exponent of the calculation window is 0, mat2 needs to be right-shifted to achieve exponent alignment. In the initial state, mat2 is placed at the highest bit of the calculation window, and then the right shift bit number is calculated according to the value of exp2. Taking single-precision floating-point numbers as an example, the right shift bit number should be equal to 153 - exp2. If the right shift bit number is less than 76, the window is set to the third state, otherwise the window is set to the fourth state. Whether it is the third state or the fourth state, exp_add needs to be set to 127 (corresponding to the real exponent of 0). After the right shift of mat2, the part where the corresponding exponent of mat2 is greater than 0 is left at the highest part of the window, and through window interception, only the part where the corresponding exponent of mat2 is less than or equal to 0 is retained.

[0210] If src2 is a positive number, according to the window interception methods of the third and fourth states, addin0 is intercepted as 0, addin1 is intercepted as the lower 49 bits (discarding the highest bit) of the second-highest part of mat2 after right shift in the window, and addition is performed. After the normalization operation, the FRC calculation result is obtained.

[0211] If src2 is a negative number, according to the window interception methods of the third and fourth states, addin1 is intercepted as all 50 bits of the second-highest part of mat2 after right shift in the window, and addin0 is set to 1 << 49, and addin0 - addin1 is performed by subtraction. After the normalization operation, the FRC calculation result is obtained.

[0212] In summary, the approach to implementing FRC operations in this disclosed embodiment involves the following steps:

[0213] 1. Determine if src2 is a special value that can be directly output, such as 0, NAN, INF, or a pure positive number. If so, directly output the corresponding floating-point value.

[0214] 2. Set src0 and src1 to 0, and place mat2 at the highest position in the window.

[0215] 3. If src2 is a positive decimal, then no shifting is required.

[0216] 4. If src2 is not a positive decimal, set the highest exponent of the second-highest part of the window to 0, and shift mat2 to the right to align the exponent.

[0217] 5. If src2 is positive, the lower 49 bits of the second highest part of the window are truncated for addition and subtraction calculations. If src2 is negative, all 50 bits of the second highest part of the window are truncated, and addin0 is set to 1<<49 before the addin0-addin1 operation is performed.

[0218] 6. After setting up exp_add, perform the normalization operation.

[0219] In order to Figure 3 FRC operations are embedded in the FMA pathway in this disclosure embodiment. Figure 3 The circuit structure shown has the following modules added, such as Figure 8 and Figure 9 As shown.

[0220] The FRC operation floating-point value output detection module is used to detect whether src2 is 0, NaN, or INF. If src2 is 0, then 0 should be output. If src2 is NaN or INF, then NaN should be output.

[0221] The selector is used to select the corresponding floating-point value for output when the floating-point value output detection module of the FRC operation detects that a floating-point value needs to be output; otherwise, it selects the result from the normalization module. In fact, the FMA instruction usually also needs to output floating-point values ​​such as 0, INF, and NAN, and this selector does not add any circuit overhead.

[0222] The FRC operation displacement calculation module calculates the value of right shifting mat2 in the FRC operation. If mat2 is a positive decimal, it sets s2_pos_frc=1 and outputs frc_shf_val=0; otherwise, it outputs frc_shf_val=153-exp2. It also sends s2_pos_frc and frc_shf_val to the window detection module to modify the window detection result. The sign bit s2_sgn of src2 is sent to the window selection module to set addin0 and addin1. When performing the FRC operation, the window state detection module sets the window state to state one upon receiving s2_pos_frc=1; otherwise, if frc_shf_val<76, it sets the window state to state three; if frc_shf_val>=76, it sets the window state to state four. When performing the FRC operation, the addition exponent calculation module sets exp_add = exp2 upon receiving s2_pos_frc=1; otherwise, it sets exp_add=127. When performing FRC operations, if s2_pos_frc=1, then mat2 is not shifted to the right; otherwise, the mantissa shifting module shifts mat2 to the right according to frc_shf_val.

[0223] It should be noted that the embodiments disclosed herein can achieve at least the following technical effects:

[0224] 1. The embodiments of this disclosure save the area of ​​a separate FRC computing unit by embedding FRC operations into the FMA path.

[0225] 2. In this embodiment of the present disclosure, since a separate FRC calculation unit is not used, the power consumption of this part of the circuit is saved when calculating FRC operations.

[0226] It should be noted that, in the embodiments of this disclosure, if the above-described floating-point number processing method is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiments of this disclosure, or the part that contributes to related technologies, can be embodied in the form of a software product. This software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the methods described in the various embodiments of this disclosure. The aforementioned storage medium includes various media capable of storing program code, such as a USB flash drive, external hard drive, read-only memory (ROM), magnetic disk, or optical disk. Thus, the embodiments of this disclosure are not limited to any specific hardware, software, or firmware, or any combination of hardware, software, and firmware.

[0227] This disclosure provides a computer device including a memory and a processor. The memory stores a computer program that can run on the processor. When the processor executes the program, it implements some or all of the steps in the above-described method.

[0228] This disclosure provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements some or all of the steps in the above-described method. The computer-readable storage medium may be transient or non-transient.

[0229] This disclosure provides a computer program including computer-readable code, wherein when the computer-readable code is executed in a computer device, a processor in the computer device performs some or all of the steps in the above-described method.

[0230] This disclosure provides a computer program product comprising a computer program that, when read and executed by a computer, implements some or all of the steps in the above-described method. The computer program product can be implemented specifically through hardware, software, or a combination thereof. In some embodiments, the computer program product is specifically embodied in a computer storage medium; in other embodiments, the computer program product is specifically embodied in a software product, such as a software development kit (SDK), etc.

[0231] It should be noted that the descriptions of the various embodiments above tend to emphasize the differences between them, while their similarities or commonalities can be referenced interchangeably. The descriptions of the above embodiments of the device, storage medium, computer program, and computer program product are similar to the descriptions of the above method embodiments and have similar beneficial effects. For technical details not disclosed in the embodiments of the device, storage medium, computer program, and computer program product of this disclosure, please refer to the descriptions of the method embodiments of this disclosure for understanding.

[0232] It should be noted that, Figure 10 This is a schematic diagram of a hardware entity of a computer device in an embodiment of this disclosure, such as... Figure 10 As shown, the hardware entity of the computer device 1000 includes: a processor 1001, a communication interface 1002, and a memory 1003, wherein:

[0233] Processor 1001 typically controls the overall operation of computer device 1000.

[0234] The communication interface 1002 enables computer devices to communicate with other terminals or servers via a network.

[0235] The memory 1003 is configured to store instructions and applications executable by the processor 1001, and can also cache data to be processed or already processed (e.g., image data, audio data, voice communication data, and video communication data) in the processor 1001 and various modules in the computer device 1000. It can be implemented using flash memory or random access memory (RAM). Data transfer between the processor 1001, the communication interface 1002, and the memory 1003 can be performed via bus 1004.

[0236] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above steps / processes do not imply a sequential order of execution; the execution order of each step / process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above embodiments of this disclosure are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0237] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0238] In the several embodiments provided in this disclosure, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components may be combined, or integrated into another system, or some features may be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed may be through some interfaces, and the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0239] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units. They may be located in one place or distributed across multiple network units. Some or all of the units may be selected to achieve the purpose of this embodiment according to actual needs.

[0240] In addition, each functional unit in the various embodiments of this disclosure can be integrated into one processing unit, or each unit can be a separate unit, or two or more units can be integrated into one unit; the integrated unit can be implemented in hardware or in the form of hardware plus software functional units.

[0241] Those skilled in the art will understand that all or part of the steps of the above method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it performs the steps of the above method embodiments. The aforementioned storage medium includes various media that can store program code, such as mobile storage devices, read-only memory (ROM), magnetic disks, or optical disks.

[0242] Alternatively, if the integrated units described above are implemented as software functional modules and sold or used as independent products, they can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this disclosure, or the part that contributes to related technologies, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the methods described in the various embodiments of this disclosure. The aforementioned storage medium includes various media capable of storing program code, such as mobile storage devices, ROM, magnetic disks, or optical disks.

[0243] The above description is merely an embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A processor, comprising: The processor comprises a multiply-add operation unit; The multiply-add operation unit is configured to, in response to a first signal for a target floating-point number, determine a state of multiply-add operation matched with the target floating-point number based on a size relationship between the target floating-point number and a floating-point number threshold in a case where the target floating-point number does not satisfy a preset condition, and output a fractional part of the target floating-point number based on the state of multiply-add operation to implement FRC operation of the target floating-point number through a calculation channel of multiply-add operation.

2. The processor of claim 1, wherein the multiply-add unit comprises: A window state detection module; The window state detection module is configured to output the state of multiply-add operation as a first target state in a case where the target floating-point number is greater than a first floating-point number threshold and less than a second floating-point number threshold, the floating-point number threshold comprises the first floating-point number threshold and the second floating-point number threshold, and a calculation window in the first target state contains a mantissa of the target floating-point number.

3. The processor of claim 2, wherein The window state detection module is further configured to output the state of multiply-add operation as a second target state in a case where at least one of the target floating-point number being less than the first floating-point number threshold and the target floating-point number being greater than the second floating-point number threshold exists, and a right shift number is less than a bit number threshold, and a calculation window in the second target state contains significant values of a mantissa part corresponding to an exponent less than or equal to 0 in the mantissa of the target floating-point number.

4. The processor of claim 2, wherein The window state detection module is further configured to output the state of multiply-add operation as a third target state in a case where at least one of the target floating-point number being less than the first floating-point number threshold and the target floating-point number being greater than the second floating-point number threshold exists, and the right shift number is greater than or equal to the bit number threshold, and a calculation window in the third target state does not contain the significant values of the mantissa part corresponding to the exponent less than or equal to 0 in the mantissa of the target floating-point number.

5. The processor of claim 3 or 4, characterized in that the processor comprises: A bit shift value calculation unit; An input port of the bit shift value calculation unit is connected with an input port of the multiply-add operation unit, and an output port of the bit shift value calculation unit is connected with an input port of the window state detection module; The bit shift value calculation unit is configured to determine a right shift number of the target floating-point number based on a mantissa bit width of the target floating-point number, a mantissa of the target floating-point number, an exponent offset of the target floating-point number, and a first bit width threshold.

6. The processor of any one of claims 2-4, wherein the multiply-add unit further comprises: An addition exponent calculation module; An input port of the addition exponent calculation module is connected with an output port of the window state detection module; The addition exponent calculation module is configured to determine an addition exponent based on the state of multiply-add operation, and the addition exponent is used to determine the fractional part of the target floating-point number; In a case where the state of multiply-add operation is the first target state, the addition exponent is the exponent of the target floating-point number; In a case where the state of multiply-add operation is the second target state or the third target state, the addition exponent is determined based on the exponent offset of the target floating-point number.

7. The processor of any one of claims 2-4, wherein the multiply-add unit further comprises: An addition mantissa calculation module; The input port of the addition mantissa calculation module is connected to the output port of the window state detection module in parallel with the input port of the addition exponent calculation module; The addition mantissa calculation module is configured to determine an addition mantissa based on the state of the multiply-add operation; the addition mantissa is used to determine a decimal part of a target floating-point number; When the state of the multiply-add operation is a first target state, the addition mantissa is determined based on a first addend and a second addend of a calculation window in the first target state; in the first target state, the first addend is a first floating-point number value, and the second addend is a mantissa of the target floating-point number placed to the highest bit of the calculation window and then truncated from the high bit to a first number of bits; the first number of bits is determined based on a bit width of the calculation window in the first target state; When the state of the multiply-add operation is a second target state or a third target state, the addition mantissa is determined based on the mantissa of the target floating-point number after placement and a sign bit of the target floating-point number; the mantissa of the target floating-point number after placement is placed in a calculation window according to a right shift number of the target floating-point number.

8. The processor of any one of claims 2-4, further comprising: A selector; The selector is connected to the input of the processor and the output of the multiply-add operation unit, respectively; The selector is configured to output a floating-point number value corresponding to the target floating-point number when the target floating-point number satisfies the preset condition, and output a decimal part of the target floating-point number when the target floating-point number does not satisfy the preset condition.

9. A method of floating-point number processing, characterized by, The floating-point number processing method further includes: In response to a first signal for a target floating-point number, determining a state of a multiply-add operation matched with the target floating-point number based on a size relationship between the target floating-point number and a floating-point number threshold when the target floating-point number does not satisfy a preset condition; Outputting a decimal part of the target floating-point number based on the state of the multiply-add operation, so as to realize FRC operation of the target floating-point number through a calculation path of the multiply-add operation.

10. The floating-point number processing method according to claim 9, wherein, The determination of the state of the multiply-add operation matched with the target floating-point number based on the size relationship between the target floating-point number and the floating-point number threshold includes at least one of the following steps: When the target floating-point number is greater than a first floating-point number threshold and less than a second floating-point number threshold, outputting the state of the multiply-add operation as a first target state; the floating-point number threshold includes the first floating-point number threshold and the second floating-point number threshold; a calculation window in the first target state contains a mantissa of the target floating-point number; When at least one of the target floating-point number being less than the first floating-point number threshold and the target floating-point number being greater than the second floating-point number threshold exists, determining the state of the multiply-add operation based on a size relationship between a right shift number of the target floating-point number and a bit number threshold; the right shift number is used to retain a mantissa part corresponding to an exponent less than or equal to 0 in the mantissa of the target floating-point number in a calculation window.

11. The floating-point number processing method according to claim 10, wherein, The determination of the state of the multiply-add operation based on the size relationship between the right shift number of the target floating-point number and the bit number threshold includes: determining a right shift number of the target floating-point number based on a mantissa bit width of the target floating-point number, a mantissa of the target floating-point number, an exponent offset of the target floating-point number, and a first bit width threshold; in a case where the right shift number is less than a bit number threshold, outputting a state of the multiply-add operation as a second target state; a calculation window in the second target state containing valid values of a mantissa part corresponding to an exponent less than or equal to 0; in a case where the right shift number is greater than or equal to the bit number threshold, outputting the state of the multiply-add operation as a third target state; a calculation window in the third target state not containing valid values of the mantissa part corresponding to the exponent less than or equal to 0.

12. The floating-point number processing method according to any one of claims 9 to 11, characterized by, the outputting the fractional part of the target floating-point number based on the state of the multiply-add operation comprises: determining an addition mantissa and an addition exponent based on the state of the multiply-add operation; outputting the fractional part of the target floating-point number based on a sign bit of the target floating-point number, the addition mantissa and the addition exponent.

13. The floating-point number processing method according to claim 12, wherein, the determining the addition mantissa and the addition exponent based on the state of the multiply-add operation comprises: in a case where the state of the multiply-add operation is the first target state, assigning a first floating-point value to a first addend of the calculation window in the first target state; placing a mantissa of the target floating-point number to a highest bit of the calculation window in the first target state, and assigning a first bit number of the mantissa from a high bit downwards to a second addend of the calculation window in the first target state; the first bit number being determined based on a bit width of the calculation window in the first target state, the calculation window in the first target state containing the mantissa of the target floating-point number; determining the addition mantissa based on the first addend and the second addend; assigning an exponent of the target floating-point number as the addition exponent.

14. The floating-point number processing method according to claim 12, wherein, the determining the addition mantissa and the addition exponent based on the state of the multiply-add operation comprises: in a case where the state of the multiply-add operation is the second target state, placing the mantissa of the target floating-point number to the calculation window in the second target state according to the right shift number of the target floating-point number; determining the addition mantissa based on the placed mantissa of the target floating-point number and a sign bit of the target floating-point number; determining the addition exponent based on the exponent offset of the target floating-point number.

15. The floating-point number processing method according to claim 14, wherein, the determining the addition mantissa based on the placed mantissa of the target floating-point number and the sign bit of the target floating-point number comprises: in a case where it is determined that the target floating-point number is negative based on the sign bit of the target floating-point number, assigning a third floating-point value to the first addend of the calculation window in the second target state; assigning a second bit number of the placed mantissa of the target floating-point number from a high bit downwards to the second addend of the calculation window in the second target state; performing subtraction processing on the first addend and the second addend to obtain the addition mantissa.

16. The floating-point number processing method according to claim 14, wherein, the determining the addition mantissa based on the placed mantissa of the target floating-point number and the sign bit of the target floating-point number comprises: In a case where it is determined, based on a sign bit of the target floating-point number, that the target floating-point number is a positive number, assigning a first floating-point number value to a first addend of a calculation window in the second target state; truncating, from the highest bit downward, a third number of bits other than the highest bit in the mantissa of the target floating-point number after the placement and assigning the third number of bits to a second addend of the calculation window in the second target state; performing addition processing on the first addend and the second addend to obtain an addition mantissa.

17. The floating-point number processing method according to claim 12, wherein, The determining, based on the state of the multiply-add operation, of the addition mantissa and the addition exponent includes: In a case where the state of the multiply-add operation is a third target state, placing a mantissa of the target floating-point number to a calculation window in the third target state according to a right shift number of the target floating-point number; determining the addition mantissa based on the placed mantissa of the target floating-point number and a sign bit of the target floating-point number; determining the addition exponent based on an exponent offset of the target floating-point number.

18. The floating-point number processing method according to claim 9, wherein, The floating-point number processing method further includes: In a case where the target floating-point number satisfies the preset condition, outputting a floating-point number value corresponding to the target floating-point number.

19. The floating-point number processing method according to claim 18, wherein, The floating-point number processing method further includes: In a case where the target floating-point number is 0, or the target floating-point number has no valid value in a fractional part but has a valid value in an integer part, determining that the target floating-point number satisfies a first preset condition; In a case where the target floating-point number is infinity INF, or the target floating-point number is not a number NaN, determining that the target floating-point number satisfies a second preset condition; the preset condition includes at least one of the first preset condition and the second preset condition.

20. The floating-point number processing method according to claim 18, wherein, The outputting, in the case where the target floating-point number satisfies the preset condition, of the floating-point number value corresponding to the target floating-point number includes at least one of: In a case where the target floating-point number satisfies the first preset condition, outputting a first floating-point number value; In a case where the target floating-point number satisfies the second preset condition, outputting a second floating-point number value.

21. A computer readable storage medium having stored thereon a computer program, characterized in that, The computer program, when executed by a processor, implements the steps of the method of any one of claims 9 to 20.

22. A computer program product, characterised in that, The computer program product includes a computer program that, when read and executed by a computer, implements the steps of the method of any one of claims 9 to 20.

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