Register allocation method and device, electronic equipment and computer storage medium

Abstract

The invention provides a register allocation method and device, electronic equipment and a computer storage medium, and belongs to the technical field of register allocation, and the register allocation method comprises the steps that on the basis of the use position of a to-be-allocated SSA variable, a to-be-allocated register demand block needed by the to-be-allocated SSA variable is split into target sub-demand blocks; and executing a register allocation operation based on the target sub-demand block. Limited physical registers can be utilized to a greater extent.

Description

Technical Field

[0001] This disclosure relates to the field of register allocation technology, and in particular to a register allocation method, apparatus, electronic device, and computer storage medium. Background Technology

[0002] There is no limit to the number of Static Single Assignment (SSA) variables. SSA variables require storage space, and register allocation determines which SSA variables are stored in registers, overflowing into memory when registers are insufficient. Since register access is significantly faster than memory access, SSA variables are usually stored in registers first.

[0003] However, since there are a large number of SSA variables and limited physical register resources, how to reasonably allocate register resources to each SSA variable becomes the key to improving program performance. Summary of the Invention

[0004] This disclosure provides a register allocation method, apparatus, electronic device, and computer storage medium that can maximize the use of limited physical registers.

[0005] The technical solution disclosed herein is implemented as follows: In a first aspect, this disclosure provides a register allocation method, which includes: splitting the register requirement block required by the SSA variable to be allocated into target sub-requirement blocks based on the usage location of the SSA variable to be allocated; and performing register allocation operations based on the target sub-requirement blocks.

[0006] Secondly, this disclosure provides a register allocation apparatus, which includes a splitting module and an execution module; the splitting module is configured to split the register requirement block required by the SSA variable to be allocated into target sub-requirement blocks based on the usage location of the SSA variable to be allocated; the execution module is configured to perform register allocation operations based on the target sub-requirement blocks.

[0007] Thirdly, this disclosure provides an electronic device including a processor, a memory, and a program or instructions stored in the memory and executable on the processor, wherein the program or instructions, when executed by the processor, implement the steps of the register allocation method as described in the first aspect.

[0008] Fourthly, this disclosure provides a computer-readable storage medium on which a program or instructions are stored, which, when executed by a processor, implement the steps of the register allocation method as described in the first aspect.

[0009] Fifthly, this disclosure provides a computer program product, wherein the computer program product includes a computer program or instructions, which, when run on a processor, cause the processor to execute the computer program or instructions to implement the steps of the register allocation method as described in the first aspect.

[0010] In a sixth aspect, this disclosure provides a chip including a processor and a communication interface coupled to the processor, the processor being used to run programs or instructions to implement the register allocation method as described in the first aspect.

[0011] This disclosure provides a register allocation method that splits a register requirement block to be allocated into target sub-requirement blocks before performing register allocation operations. The lifetime of the SSA variable corresponding to the target sub-requirement block after splitting is shorter than the lifetime of the SSA variable to be allocated. That is, the range of consecutive instruction positions occupied by the target sub-requirement block is significantly reduced. The target sub-requirement block can make full use of the scattered short free spaces in the register resource matrix, maximize the use of limited register resources, and using the usage position as the split point can also avoid the invalid occupation of register resources. Attached Figure Description

[0012] Figure 1 This is a schematic diagram of a register resource matrix provided in this disclosure.

[0013] Figure 2 This is a flowchart illustrating a register allocation method provided in this disclosure.

[0014] Figure 3 A schematic diagram of the splitting points provided in this disclosure.

[0015] Figure 4 A flowchart illustrating another register allocation method provided in this disclosure.

[0016] Figure 5 This is a schematic diagram of the splitting process provided in this disclosure.

[0017] Figure 6 This is a flowchart illustrating yet another register allocation method provided in this disclosure.

[0018] Figure 7 A schematic diagram of the register allocation process provided in this disclosure.

[0019] Figure 8 A schematic diagram of the register allocation results provided in this disclosure.

[0020] Figure 9 This is a schematic diagram of the overall process of register allocation provided in this disclosure.

[0021] Figure 10This is a structural block diagram of a register allocation device provided in this disclosure.

[0022] Figure 11 This is a schematic diagram of the hardware structure of an electronic device provided in this disclosure. Detailed Implementation

[0023] The technical solutions in the embodiments of this disclosure will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure are within the scope of protection of this disclosure.

[0024] In the field of compiler optimization, the Single-Assigned Variable (SSA) form is widely used due to its explicit definition of variable lifetime. As an intermediate representation for the compiler, SSA requires that each variable be defined (assigned) only once, but can be used multiple times. When a program involves multiple assignments, the compiler converts them into independent SSA variables. For example, if the program gives: variable x = 2 (x is assigned a value for the first time), x = x + 1 (x is assigned a value for the second time), the compiler converts it to the SSA form: x1 = 2, x2 = x1 + 1, thus decomposing the original variable into multiple single-assignment variables, significantly simplifying data flow analysis.

[0025] Each SSA variable must be stored in physical storage, which can be either memory or a physical register. Given that register access is much faster than memory access, compilers typically prioritize allocating SSA variables to physical registers to optimize performance.

[0026] All SSA variables are used in different instructions of the program. These instructions, executed in the order they appear, form an instruction sequence. Each instruction in the sequence is uniquely identified by its instruction location. The instruction location where an SSA variable is assigned a value corresponds to the SSA variable's definition location. The instruction location where an SSA variable is last used corresponds to the SSA variable's end location. The instruction location where an SSA variable is actually used corresponds to the SSA variable's usage location. The lifetime of an SSA variable is defined from its definition location to its end location.

[0027] Since instruction location reflects the order in which a particular SSA variable is used in a program, physical register resources can be constructed as a two-dimensional discretized register resource matrix, such as... Figure 1 As shown, the vertical axis represents the register number (i.e., how many physical registers there are), and the horizontal axis represents the instruction position of each instruction in the instruction sequence. Each cell records the occupancy status of a specific register at a specific instruction position, with 0 indicating that it is not occupied (idle state) and 1 indicating that it is occupied by a certain SSA variable.

[0028] The register requirement block (i.e., lifetime and number of registers occupied) for each SSA variable can be represented by a triple (s, e, c), denoted as STR, where s is the definition location of the SSA, e is the end location of the SSA, and c is the number of consecutive registers required to store the SSA. For example, c = 2 means that two consecutive registers are needed to store the SSA variable.

[0029] In related technologies, the register requirement block needed by the SSA variable is treated as a whole, and resources are allocated for it in the register resource matrix. That is, the register resource matrix is ​​found by identifying consecutive unoccupied cells from the definition position of the SSA variable to its end position. For example, if STR is (1, 7, 1), and the usage positions are instruction positions 5 and 6, then the corresponding SSA variable is not used in the interval from instruction position 2 to instruction position 4. Figure 1 The grid-filled cells shown are cells occupied by SSA variables that are not used. Cells occupied by instructions that do not use SSA variables are recorded as invalid occupancy.

[0030] This kind of invalid occupancy will occupy a large amount of register resources, resulting in waste of register resources and low utilization.

[0031] Based on this, the present disclosure aims to provide a register allocation method that can efficiently utilize limited register resources. The register allocation method provided by the present disclosure will be described in detail below with reference to the accompanying drawings, through specific embodiments and application scenarios.

[0032] like Figure 2 As shown, the register allocation method provided in this disclosure may include the following steps S101 to S102.

[0033] In step S101, based on the usage location of the SSA variable to be allocated, the register requirement block required by the SSA variable to be allocated is split into target sub-requirement blocks.

[0034] Based on the usage location of the SSA variable to be allocated, the register requirement block required by the SSA variable to be allocated is split into target sub-requirement blocks.

[0035] In step S102, a register allocation operation is performed based on the target sub-requirement block.

[0036] The core purpose of the splitting operation is to divide the register request block to be allocated into multiple target sub-request blocks, where the lifetime of the SSA variable corresponding to each target sub-request block is shorter than the lifetime of the SSA variable to be allocated. Each target sub-request block is independently eligible during the register allocation process. Since the SSA variable to be allocated cannot be stored in the register for its entire lifetime, a portion of the SSA variable is stored in memory; that is, the splitting operation corresponds to overflowing a portion of the SSA variable to be allocated into memory. Because the SSA needs to be stored in memory after splitting and needs to be read from memory before use, this process increases memory read / write latency. Each split corresponds to an increase in memory read / write latency. Therefore, a reasonable splitting strategy (i.e., a reasonable overflow strategy) can reduce the number of splits, thereby reducing memory read / write latency.

[0037] When a non-used location is chosen as the split point, a load instruction inserted before the split point immediately creates a new SSA variable and binds it to a physical register, but this SSA has no actual reference in the subsequent non-used location range. This results in the register being in an invalid occupied state between the load instruction before the split point and the first used location thereafter, i.e., forming unnecessary occupancy in the register resource matrix (from the location of the load instruction to the first used location thereafter), wasting register resources. Therefore, by using one of the various used locations as the split point, the new SSA variable generated by the load instruction is used immediately after its definition location, ensuring that the occupied range of the physical register precisely matches the actual data flow requirements, eliminating invalid resource occupancy, and ensuring that the lifetime of the target sub-requirement block after splitting exhibits a compact and continuous characteristic in the resource matrix, ultimately achieving optimal time and space efficiency in register allocation.

[0038] For example, such as Figure 3 As shown, the two used positions of STR (3, 10, 1) are instruction position 4 and instruction position 9. The blank area in the middle means that the register resources are not occupied. Using the used position as the split point can make the split target sub-requirement block not include the blank area. However, using any instruction position in the blank area as the split point will make the split sub-target requirement block still include the blank area, that is, there is an invalid occupation of register resources in the sub-target requirement block.

[0039] In this disclosure, the lifetime of the SSA variable corresponding to the target sub-requirement block generated by the splitting operation is shortened compared to the lifetime of the SSA variable to be allocated. That is, the range of consecutive instruction positions occupied by the target sub-requirement block is significantly reduced. The target sub-requirement block can make full use of the scattered short free spaces in the register resource matrix, maximize the use of limited register resources, and use the usage position as the splitting point to avoid the invalid occupation of register resources.

[0040] In some embodiments, step S101 above, which splits the register requirement block required by the SSA variable to be allocated into target sub-requirement blocks based on the usage location of the SSA variable to be allocated, includes: when the register requirement block to be allocated does not meet the insertion condition, splitting the register requirement block to be allocated into target sub-requirement blocks based on the usage location of the SSA variable to be allocated.

[0041] The insertion conditions include: being able to fit in the free space of the register resource matrix, or being able to fit in the free gap of the allocated register demand block.

[0042] Free space refers to all unoccupied resources. If there is enough contiguous free space in the register resource matrix to cover the block of registers to be allocated, and the number of contiguous free registers meets the requirement for the number of registers to be allocated, then the block of registers to be allocated can be accommodated in the free space of the register resource matrix. The required number refers to the number of contiguous registers needed.

[0043] An allocated register request block refers to a block for which registers have already been allocated in the register resource matrix, meaning it occupies at least one cell in the matrix. A free gap refers to the invalid occupied interval between adjacent usage positions of SSA variables within an allocated request block. If, at any adjacent key position of the SSA variable corresponding to the allocated register request block, the preceding key position is earlier than the definition position of the SSA variable corresponding to the pending allocated register request block, and the subsequent key position is later than the end position of the SSA variable corresponding to the pending allocated register request block, and the number of consecutive free registers between these adjacent key positions meets the requirement for the number of available registers in the pending allocated register request block, then the pending allocated register request block can be accommodated in the free space of the register resource matrix. Adjacent key positions include: definition position, usage position, and end position.

[0044] If the free space in the register resource matrix cannot accommodate the register request block to be allocated, the allocated register request block is split first. If the free space of the allocated register request block can accommodate the register request block to be allocated, the process only needs to split the allocated register request block once to provide register resources for the register request block to be allocated.

[0045] If the free space in the register resource matrix cannot accommodate the register request block to be allocated, and the register request block to be allocated is split first, one case is that both target sub-request blocks after splitting can be accommodated in the free space of the register resource matrix, then only one split is needed; the other case is that one of the two target sub-request blocks after splitting can be accommodated in the free space, and the other can be accommodated in the free gap of the already allocated register request block, then the already allocated register request block needs to be split again, so two splits are required.

[0046] Therefore, when the free space in the register resource matrix cannot accommodate the register request block to be allocated, the allocated register request block is split first. When the free space of the allocated register request block cannot accommodate the register request block to be allocated, the number of splits of the register request block to be allocated is minimized, thus the memory read and write latency caused by splitting is also lower.

[0047] In this disclosure, when the free space in the register resource matrix and the free gap between the allocated register demand blocks are both insufficient to accommodate the register demand blocks to be allocated, the register demand blocks to be allocated are then split. This splitting strategy can avoid redundant splitting operations.

[0048] In some embodiments, combined with Figure 2 ,like Figure 4 As shown, step S101 above splits the required register block for the SSA variable to be allocated into target sub-requirement blocks based on the usage location of the SSA variable to be allocated. Specifically, this can be achieved through steps S101a to S101d.

[0049] In S101a, the usage position adjacent to the end position of the SSA variable to be assigned is determined as a candidate split point.

[0050] In S101b, a splitting operation is performed on the block of register requirements to be allocated based on the candidate splitting point, resulting in two candidate sub-requirement blocks.

[0051] In S101c, when a candidate sub-requirement block that includes the definition location of the SSA variable to be assigned does not meet the insertion condition, the usage location adjacent to the candidate split point is determined as the candidate split point.

[0052] Continue to execute the splitting operation in step S101b.

[0053] In S101d, when the candidate sub-requirement blocks that include the definition positions of the SSA variables to be assigned meet the insertion conditions, the two candidate sub-requirement blocks are determined as the target sub-requirement blocks.

[0054] The usage location adjacent to the end position is the usage location closest to the end position of the SSA. For example, such as Figure 3 As shown, the closest usage position to the end position 10 of the SSA is instruction position 9. In each loop, the candidate split point is a usage position that gradually approaches the definition position; that is, the first candidate split point is the usage position adjacent to the end position of the SSA variable to be allocated, the next candidate split point is the usage position adjacent to the first candidate split point and close to the definition position of the SSA variable, and so on.

[0055] Since SSA variables are not reassigned, the two candidate sub-requirement blocks after splitting are two different SSA variables, each with independent eligibility during allocation. For candidate sub-requirement blocks that include the definition location after splitting, they are designated as the first candidate sub-requirement block, and their values ​​are not lost. However, for candidate sub-requirement blocks that do not include the definition location after splitting, they are designated as the second sub-requirement block, and the value of the SSA variable cannot be determined at subsequent usage locations. Therefore, for candidate sub-requirement blocks that do not include the definition location after splitting, a load instruction needs to be added before the split point; this load instruction represents the definition location of the candidate sub-requirement block.

[0056] Specifically, in some embodiments, when the definition location of the SSA variable to be allocated is not a load instruction, a store instruction is added at an adjacent position after the definition location; a load instruction is added on the side adjacent to the split point and close to the definition location of the SSA variable; the area from the definition location of the SSA variable to the usage location adjacent to the load instruction and close to the definition location is determined as a candidate sub-requirement block; the area from the load instruction to the end position of the SSA is determined as another candidate sub-requirement block. When the definition location of the SSA variable to be allocated is a load instruction, no store instruction needs to be added. The store instruction stores the value of the SSA variable to be allocated into memory, and the load instruction reads the value of the SSA variable to be allocated from memory. This process is equivalent to overflowing a portion of the lifetime of the SSA variable to be allocated into memory. It should be noted that the split point in this embodiment is the candidate split point corresponding to the aforementioned target sub-requirement block.

[0057] The store instruction is used to store the value of the SSA variable into memory, and the load instruction is used to retrieve the stored value of the SSA variable from memory.

[0058] For example, such as Figure 5As shown, the SSA variable to be allocated is defined at position 3 and ends at position 10. The two usage positions are instruction positions 4 and 9. Instruction position 9 is used as the split point. A store instruction is inserted after the definition position to overflow the SSA value into memory for storage, ensuring that the value is not lost later. Since the instruction sequence is sequential, after inserting the store instruction, the instruction positions originally following the inserted store instruction are all shifted one position to the right. That is, instruction position 4 becomes instruction position 5, instruction position 9 becomes instruction position 10, and instruction position 10 becomes instruction position 11. A load instruction is added before the split point to ensure that the SSA value can be correctly obtained at the usage positions after splitting. Similarly, after adding the load instruction, the original instruction positions after the load instruction are all shifted one position to the right. The candidate demand blocks after splitting are (3, 5, 1) and (10, 12, 1). These two candidate demand blocks represent register demands corresponding to two different SSA variables. The definition location of the SSA variable to be allocated is a load instruction, indicating that the value of the SSA variable is already stored in memory. Therefore, no additional load instruction is needed. Only a load instruction needs to be added before the split point to ensure that the value of the SSA variable can be correctly obtained at the usage location after splitting. The candidate demand blocks after splitting are (3, 4, 1) and (9, 11, 1). This disclosure immediately stores the current value of the SSA variable in memory, which can prevent the risk of value loss during subsequent splitting processes. Inserting a load instruction before the split point ensures that the latest value of the new SSA variable is loaded immediately before use.

[0059] If the contiguous free space in the register resource matrix can cover the lifetime of the SSA variable corresponding to the first candidate sub-requirement block, and the number of contiguous free registers meets the requirement of the first candidate sub-requirement block, then the first candidate sub-requirement block can be accommodated in the free space of the register resource matrix.

[0060] If, at any adjacent critical position of the SSA variable corresponding to the allocated register demand block, the preceding critical position is earlier than the definition position of the SSA variable corresponding to the first candidate sub-demand block, and the following critical position is later than the end position of the SSA corresponding to the first candidate sub-demand block, and the number of consecutive free registers between these adjacent critical positions meets the demand quantity requirement of the first candidate sub-demand block, then it is determined that the first candidate sub-demand block can be accommodated in the free space of the register resource matrix.

[0061] If the first candidate sub-requirement block meets the insertion condition, the two candidate sub-requirement blocks are determined as target sub-requirement blocks; otherwise, the candidate splitting point is re-determined and the blocks are split again; if no target sub-requirement block that meets the insertion condition is found after traversing all available positions, the register allocation is determined to have failed.

[0062] The reason for determining whether the first candidate sub-requirement block meets the insertion condition after splitting is that the register allocation process in this disclosure is carried out in the order of its defined positions. Once it is determined that the first candidate sub-requirement block meets the insertion condition, it will definitely be allocated space after subsequent splitting. However, even if it is determined that the second candidate sub-requirement block meets the insertion condition after splitting, there may be unallocated SSA variables in the list of unallocated register requirement blocks whose defined positions are before the defined positions of the SSA variables corresponding to the second candidate sub-requirement block. These unallocated SSA variables will be allocated to register resources before the second candidate sub-requirement block, which may result in the second candidate sub-requirement block still not being allocated register resources.

[0063] The splitting process begins from the usage position closest to the end position, ensuring that the lifetime of candidate sub-requirement blocks, including the definition position, is as long as possible, thus minimizing the number of splits and balancing splitting granularity and instruction overhead. Compared to related technologies that insert storage instructions directly after the definition position and load instructions at each usage position, resulting in a surge in instruction overhead and the number of splits, leading to increased memory read / write operations and latency, this disclosure prioritizes the usage position closest to the end position, ensuring that the sub-STRs containing the definition position maintain the maximum contiguous lifetime, thereby reducing the number of subsequent reloads.

[0064] In some embodiments, combined with Figure 4 ,like Figure 6 As shown, step S102 above performs register allocation operation based on the target sub-requirement block, which can be implemented through the following steps S102a to S102e.

[0065] In step S102a, when the free space of the register resource matrix can accommodate the target sub-requirement block, the target sub-requirement block is added to the free space of the register resource matrix.

[0066] In step S102b, when the free space cannot accommodate the target sub-requirement block, and the target free gap of the allocated register requirement block can accommodate the target sub-requirement block, a splitting operation is performed on the target allocated register requirement block where the target free gap is located according to the target free gap, resulting in two reallocated sub-requirement blocks.

[0067] Specifically, in some embodiments, when the definition location of the SSA variable corresponding to the target allocated register demand block is not a load instruction, a store instruction is added at an adjacent position after the definition location; a load instruction is added on the side adjacent to the split point and close to the definition location of the SSA variable; the area from the definition location of the SSA variable to the usage position adjacent to the load instruction and close to the definition location is determined as a reallocation sub-demand block; the area from the load instruction to the end position of the SSA variable is determined as another reallocation sub-demand block. When the definition location of the SSA in the target allocated register demand block is a load instruction, no store instruction needs to be added. A detailed description of the splitting operation can be found in the above description of splitting the register demand block to be allocated, and will not be repeated here. It should be noted that the splitting point in this embodiment is the usage position adjacent to the target free gap and close to the end position.

[0068] In step S102c, the space occupied by the target allocated register request block and subsequent allocated register request blocks in the register resource matrix is ​​released.

[0069] If a target allocated register demand block that has already occupied resources in the register resource matrix is ​​split into two reallocation sub-demand blocks, then the space occupied by the target allocated register demand block and its subsequent allocated register demand blocks in the register resource matrix needs to be released, and register resources need to be reallocated.

[0070] Specifically, the original occupied area of ​​the target allocated register request block in the register resource matrix is ​​released, and its instruction location range and consecutive register lines are reset to 0. All other allocated register request blocks whose defined locations follow the defined location of the target allocated register request block also have their corresponding register occupied cells set to 0 simultaneously.

[0071] In step S102d, the list of register requirement blocks to be allocated is updated based on the target allocated register requirement block and subsequent allocated register requirement blocks.

[0072] In step S102e, resources are allocated in the register resource matrix for the register request blocks in the list of register request blocks to be allocated.

[0073] After the release operation, the two reallocation sub-requirement blocks obtained from the split, along with the other released allocated register requirement blocks, are added back to the list of register requirement blocks to be allocated. Register resources are then reassigned to the register requirement blocks in the list according to the order in which their corresponding SSA variables are defined.

[0074] The list of register request blocks to be allocated stores register request blocks of multiple SSAs waiting to be allocated register resources. Each element in the list is sorted in ascending order according to the definition position of its corresponding SSA variable. Specifically, the order of each register request block in the list is determined by the definition position of its corresponding SSA variable, with the request block with the smaller definition position at the front of the list and the larger request blocks at the back. The register request block with the smallest definition position (0, 1, 2) is at the first position, the register request block with the second smallest definition position (1, 7, 1) is at the second position, and the register request block with the largest definition position (2, 5, 1) is at the last position. This sorting rule ensures that the allocation process proceeds according to the temporal order defined by the SSA variables, consistent with the static execution order of the program instruction flow.

[0075] It should be noted that since the splitting operation inserts instructions (store instructions, load instructions), and the instruction positions are sequential, the instruction positions after the inserted instructions will all be affected. Each instruction position determines the number of instructions inserted before it, and it is shifted backward by that number of instruction positions.

[0076] For example, such as Figure 7 As shown, the list of register request blocks to be allocated includes: (0, 1, 2), (1, 7, 1), (2, 5, 1), (3, 10, 1), (4, 8, 1), (5, 9, 1), (6, 9, 1), (7, 9, 1). Register resources are allocated sequentially in the register resource matrix. The dashed lines in the request blocks in the figure indicate the usage position. Filled request blocks indicate allocated register request blocks, and unfilled request blocks indicate register request blocks to be allocated. Since instruction position 6 of each register in the register resource matrix is ​​occupied, (6, 9, 1) cannot be accommodated in the register resource matrix or the free gap of the allocated register demand block. (6, 9, 1) is split at instruction position 8, with the previous used position being instruction position 7, resulting in (6, 8, 1) and (9, 11, 1). After splitting, due to the addition of store and load instructions, the list of register demand blocks to be allocated is updated to: (0, 1, 2), (1, 8, 1), (2, 5, 1), (3, 12, 1), (4, 10, 1), (5, 11, 1), (6, 8, 1), (8, 11, 1), (9, 11, 1). Register resources are allocated to (6, 8, 1) according to the defined position order, but (6, 8, 1) cannot be accommodated in the register resource matrix. A search is conducted in the allocated register demand block to find a free gap that can accommodate (6, 8, 1), and it is determined that the free gap of (3, 12, 1) can accommodate (6, 8, 1). Therefore, the instruction is split at (3, 12, 1), with the split point being instruction position 9. The preceding position is instruction position 4. (See reference...) Figure 4The split yields two redistributable sub-demand blocks: (3, 5, 1) and (12, 14, 1). The updated list of register demand blocks to be allocated includes: (0, 1, 2), (1, 9, 1), (2, 6, 1), (3, 5, 1), (5, 11, 1), (6, 13, 1), (7, 9, 1), (9, 13, 1), (10, 13, 1), (12, 14, 1). Resources are then allocated again to each register demand block according to the updated list of register demand blocks to be allocated, and the allocation result is as follows. Figure 8 As shown. Through the above register allocation operations, the register resource matrix is ​​utilized more efficiently while ensuring minimal overflow.

[0077] In some embodiments, the register allocation method further includes: when the adjacent usage positions of multiple register demand blocks to be split in the allocated register demand block all meet the gap condition, the register demand block to be split with the smallest overflow cost is determined as the target allocated register demand block.

[0078] Overflow cost refers to the overall performance loss caused when a split, reallocated sub-demand block is forced to be stored in memory due to insufficient register resources. Overflow cost includes: the more registers the SSA variable corresponding to the register demand block to be split occupies, the more insert instructions are needed, the longer the free gap, and the higher the execution frequency. The more registers the SSA variable corresponding to the register demand block to be split occupies, the greater the number of insert instructions, the higher the execution frequency, and the shorter the free gap, the higher the overflow cost. The number of insert instructions corresponds to two cases: if the definition location is not a load instruction, then one load instruction and one store instruction are needed per loop; if the definition location is a load instruction, then one load instruction is needed per loop. Execution frequency refers to the number of times the SSA variable is used.

[0079] Specifically, the overflow cost = number of registers occupied × (store instruction weight × number of store instructions + load instruction weight × number of load instructions) × execution frequency + (1 / length of the free gap) × gap weight).

[0080] For example, the storage instruction weight, load instruction weight, and gap weight are 0.6, 0.3, and 0.1, respectively. The lifetime of the SSA variable corresponding to the register demand block A to be split is 5, the execution frequency is 100 times, one additional load instruction is required, and the length of the free gap is 2. The lifetime of the SSA variable corresponding to the register demand block B to be split is 10, the execution frequency is 50 times, one additional storage instruction and one additional load instruction are required, and the length of the free gap is 4. The overflow cost of the register demand block A to be split is 5×(0.3×1)×100+1 / 2×0.1 =150.05. The overflow cost of the register demand block B to be split is 10×(0.6×1+0.3×1)×50+1 / 4×0.1 =450.0225. It is determined that the register demand block A to be split with the lower overflow cost is selected as the target allocated register demand block.

[0081] This disclosure comprehensively evaluates memory access overhead, execution frequency, and critical path impact. This mechanism ensures that, in resource contention scenarios, the register demand block to be split is automatically selected for splitting with the least overall performance loss, thereby minimizing the negative impact of splitting operations on program execution efficiency.

[0082] like Figure 9 The diagram shows the overall process steps of the register allocation method provided in this disclosure, including steps S901 to S914.

[0083] S901. Obtain the register demand block pointed to by the allocation pointer from the list of register demand blocks to be allocated.

[0084] S902. Determine if the required block of the register to be allocated exists.

[0085] If yes, proceed to step S903; otherwise, the register allocation process ends.

[0086] S903. Determine whether the free space of the register resource matrix can accommodate the register request block to be allocated.

[0087] If yes, proceed to step S904; otherwise, proceed to step S905.

[0088] S904. Allocate register resources for the block of registers to be allocated and move the allocation pointer to the next block of registers to be allocated.

[0089] S905. Determine whether the free gap of the allocated register demand block can accommodate the unallocated register demand block.

[0090] If yes, proceed to steps S906 to S908; otherwise, proceed to step S909.

[0091] S906. Split the first allocated register demand block into two first sub-demand blocks by splitting the free gap to accommodate the register demand block to be allocated.

[0092] S907. Release the space occupied by the first allocated register request block and subsequent allocated register request blocks in the register resource matrix.

[0093] S908. Based on the first allocated register demand block and subsequent allocated register demand blocks, update the list of register demand blocks to be allocated, and move the allocation pointer to the first allocated register demand block. Return to step S901.

[0094] S909. The position adjacent to the end position of the SSA variable to be assigned is determined as the candidate split position.

[0095] S910: Based on the candidate splitting position, perform a splitting operation on the block of register requirements to be allocated, and obtain two candidate sub-requirement blocks.

[0096] S911. When a candidate sub-requirement block that includes the definition location of the SSA variable to be assigned does not meet the insertion condition, the usage location adjacent to the candidate split point will be determined as the candidate split point.

[0097] Continue to execute the splitting operation in step S910.

[0098] S912. When the candidate sub-requirement block, including the definition location of the SSA variable to be allocated, satisfies the insertion condition, the register requirement block to be allocated is split to obtain two second sub-requirement blocks.

[0099] S913. Add the two second sub-requirement blocks to the list of register request blocks to be allocated. Return to step S901.

[0100] S914. If there is no adjacent usage location on the side of the candidate split point near the defined location, the register allocation will fail.

[0101] In this disclosure, the register allocation problem is modeled as a constrained two-dimensional "rectangular bar" packing problem. The register allocation process is transformed into loading "rectangular bars" into "containers," where the "container" is the register resource matrix, which is virtualized as a two-dimensional spatiotemporal grid of register lifetimes (time dimension) and register requirements (spatial dimension). The "rectangular bars" are the register requirement blocks to be allocated. If a "rectangular bar" cannot find a place in the free space of the "container," firstly, the allocated register requirement blocks are split, and a portion of the lifetime of the corresponding SSA variable of the allocated register requirement block is stored in memory, thereby freeing up some space in the allocated register requirement blocks for the "rectangular bars" to use. This process only requires one split, ensuring low memory read and write latency. Secondly, if the free space of the allocated register requirement blocks also cannot accommodate the "rectangular bar," the "rectangular bar" is split to obtain "sub-rectangular bars," i.e., target sub-requirement blocks, so that smaller "sub-rectangular bars" can find a place in the "container" or find a place in the free space of the allocated register requirement blocks. This ensures that limited physical registers are utilized to the greatest extent possible with as few splitting operations as possible (resulting in lower memory read / write latency).

[0102] This disclosure also provides a register allocation device, such as Figure 10 As shown, the register allocation device 100 includes: a splitting module 1001 and an execution module 1002; the splitting module 1001 is configured to split the register requirement block required by the SSA variable to be allocated into target sub-requirement blocks based on the usage location of the SSA variable to be allocated; the execution module 1002 is configured to perform register allocation operations based on the target sub-requirement blocks.

[0103] In some embodiments, the splitting module 1001 is configured to split the register requirement block required by the SSA variable to be allocated into target sub-requirement blocks based on the usage location of the SSA variable to be allocated when the register requirement block to be allocated does not meet the insertion conditions. The insertion conditions include: being able to be accommodated in the free space of the register resource matrix, or being able to be accommodated in the free gap of the allocated register requirement block.

[0104] In some embodiments, the splitting module 1001 is configured to determine the adjacent usage position of the end position of the SSA variable to be allocated as a candidate splitting point; perform a splitting operation on the register requirement block to be allocated based on the candidate splitting point to obtain two candidate sub-requirement blocks; when the candidate sub-requirement block including the definition position of the SSA variable to be allocated does not meet the insertion condition, determine the adjacent usage position of the candidate splitting point as a candidate splitting point, return to perform the splitting operation, until the candidate sub-requirement block including the definition position of the SSA variable to be allocated meets the insertion condition, and determine the two candidate sub-requirement blocks as the target sub-requirement blocks.

[0105] In some embodiments, the register allocation device 100 further includes a determination module; the determination module is configured to determine that a demand block can be accommodated in an empty gap of an allocated register demand block when any adjacent key position of the SSA variable corresponding to the allocated register demand block meets a gap condition. The gap condition is that the preceding key position of the adjacent key positions is earlier than the definition position of the SSA variable corresponding to the demand block, and the following key position is later than the end position of the SSA variable corresponding to the demand block. The demand block is a register demand block to be allocated or a candidate sub-demand block, and the key positions include a definition position, a usage position, and an end position.

[0106] In some embodiments, the execution module 1002 is configured to add the target sub-requirement block to the free space of the register resource matrix when the free space of the register resource matrix can accommodate the target sub-requirement block; when the free space cannot accommodate the target sub-requirement block, and the target free gap of the allocated register requirement block can accommodate the target sub-requirement block, perform a splitting operation on the target allocated register requirement block where the target free gap is located according to the target free gap to obtain two reallocated sub-requirement blocks; release the space occupied by the target allocated register requirement block and subsequent allocated register requirement blocks in the register resource matrix; update the list of register requirement blocks to be allocated based on the target allocated register requirement block and subsequent allocated register requirement blocks; and allocate resources in the register resource matrix for the register requirement blocks to be allocated in the list of register requirement blocks to be allocated in turn.

[0107] In some embodiments, the splitting operation includes: when the definition location of the SSA variable corresponding to the register demand block to be split is not a load instruction, adding a storage instruction at an adjacent position after the definition location; adding a load instruction on the side adjacent to the splitting point and close to the definition location of the SSA variable; determining a sub-demand block from the definition location of the SSA variable to the usage location adjacent to the load instruction and close to the definition location; determining a sub-demand block from the load instruction to the end position of the SSA variable, wherein the register demand block to be split is a target allocated register demand block or a register demand block to be allocated.

[0108] In some embodiments, the determining module is further configured to determine the register demand block to be split with the minimum overflow cost as the target allocated register demand block when the adjacent usage positions of the SSA variables corresponding to multiple register demand blocks to be split in the allocated register demand block all meet the gap condition.

[0109] In this embodiment, each module can implement the register allocation method provided in the above method embodiments and achieve the same technical effect. To avoid repetition, it will not be described again here.

[0110] Please refer to Figure 11This illustration shows a schematic diagram of the hardware structure of an electronic device provided in an exemplary embodiment of this disclosure. In some examples, the electronic device may be at least one of devices such as a smartphone, smartwatch, desktop computer, laptop, virtual reality terminal, augmented reality terminal, wireless terminal, and laptop computer. The electronic device has communication capabilities and can access wired or wireless networks. The term "electronic device" can refer to one of multiple terminals; those skilled in the art will understand that the number of terminals may be more or less. Figure 11 As shown, the electronic device in this disclosure may include one or more of the following components: processor 1110 and memory 1120.

[0111] Optionally, the processor 1110 connects various parts within the electronic device using various interfaces and lines. It executes various functions and processes data by running or executing instructions, programs, code sets, or instruction sets stored in the memory 1120, and by calling data stored in the memory 1120. Optionally, the processor 1110 can be implemented using at least one hardware form of Digital Signal Processing (DSP), Field Programmable Gate Array (FPGA), or Programmable Logic Array (PLA). The processor 1110 can integrate one or more of the following: Central Processing Unit (CPU), Graphics Processing Unit (GPU), Neural-network Processing Unit (NPU), and baseband chip. Specifically, the CPU primarily handles the operating system, user interface, and applications; the GPU is responsible for rendering and drawing the content displayed on the touchscreen; the NPU implements Artificial Intelligence (AI) functions; and the baseband chip handles wireless communication. It is understandable that the aforementioned baseband chip may not be integrated into the processor 1110, but may be implemented using a separate chip.

[0112] The memory 1120 may include random access memory (RAM) or read-only memory (ROM). Optionally, the memory 1120 may include a non-transitory computer-readable storage medium. The memory 1120 may be used to store instructions, programs, code, code sets, or instruction sets. The memory 1120 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for at least one function (such as touch function, sound playback function, image playback function, etc.), instructions for implementing the various method embodiments described above, etc.; the data storage area may store data created based on the use of the electronic device, etc.

[0113] In addition, those skilled in the art will understand that the structure of the electronic device shown in the above figures does not constitute a limitation on the electronic device. The electronic device may include more or fewer components than shown, or combine certain components, or have different component arrangements. For example, the electronic device may also include a display screen, camera assembly, microphone, speaker, radio frequency circuit, input unit, sensors (such as accelerometer, angular velocity sensor, light sensor, etc.), audio circuit, WiFi module, power supply, Bluetooth module, etc., which will not be described in detail here.

[0114] This disclosure also provides a computer-readable storage medium storing at least one instruction that is executed by a processor to implement the register allocation method described in the above embodiments.

[0115] This disclosure also provides a computer program product including computer instructions stored in a computer-readable storage medium; a processor of an electronic device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the electronic device to perform the register allocation method described in the above embodiments.

[0116] This disclosure also provides a chip, which includes a processor and a communication interface. The communication interface is coupled to the processor. The processor is used to run programs or instructions to implement the various processes of the above-described register allocation method embodiments and achieve the same technical effect. To avoid repetition, it will not be described again here.

[0117] It should be understood that the chip mentioned in the embodiments of this disclosure may also be referred to as a system-on-a-chip, system chip, chip system, or system-on-a-chip, etc.

[0118] In the several embodiments provided in this disclosure, it should be understood that the disclosed systems, apparatuses, servers, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection between apparatuses or units through some interfaces, and may be electrical, mechanical, or other forms.

[0119] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0120] Furthermore, the functional units in the various embodiments of this disclosure can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0121] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this disclosure, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this disclosure. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, ROM, RAM, magnetic disks, or optical disks.

[0122] Those skilled in the art will recognize that the functions described in this disclosure in one or more of the examples above can be implemented using hardware, software, firmware, or any combination thereof. When implemented in software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or code on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein communication media include any medium that facilitates the transfer of a computer program from one place to another. Storage media can be any available medium accessible to a general-purpose or special-purpose computer.

[0123] It should be noted that the technical solutions described in this disclosure can be combined arbitrarily as long as they do not conflict.

[0124] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A register allocation method, characterized in that, The register allocation method includes: Based on the usage location of the static single-assignment (SSA) variable to be allocated, the register requirement block required by the SSA variable to be allocated is split into target sub-requirement blocks. Based on the target sub-requirement block, perform register allocation operation.

2. The register allocation method according to claim 1, characterized in that, The step of splitting the required register block for the SSA variable to be allocated into target sub-requirement blocks based on the usage location of the SSA variable to be allocated includes: When the register demand block to be allocated does not meet the insertion condition, the register demand block to be allocated for the SSA variable to be allocated is split into target sub-demand blocks based on the usage position of the SSA variable to be allocated. The insertion condition includes: it can be accommodated in the free space of the register resource matrix, or it can be accommodated in the free gap of the allocated register demand block.

3. The register allocation method according to claim 2, characterized in that, The step of splitting the required register block for the SSA variable to be allocated into target sub-requirement blocks based on the usage location of the SSA variable to be allocated includes: The usage position adjacent to the end position of the SSA variable to be assigned is determined as the candidate split point; Based on the candidate splitting points, the block of register requirements to be allocated is split to obtain two candidate sub-requirement blocks; When a candidate sub-requirement block including the definition location of the SSA variable to be assigned does not meet the insertion condition, the usage location adjacent to the candidate split point is determined as the candidate split point, and the split operation is returned to be executed until the candidate sub-requirement block including the definition location of the SSA variable to be assigned meets the insertion condition, and the two candidate sub-requirement blocks are determined as the target sub-requirement blocks.

4. The register allocation method according to claim 3, characterized in that, The register allocation method further includes: When any adjacent key position of the SSA variable corresponding to the allocated register demand block satisfies the gap condition, it is determined that the demand block can be accommodated in the free gap of the allocated register demand block. The gap condition is that the preceding key position is earlier than the definition position of the SSA variable corresponding to the demand block, and the following key position is later than the end position of the SSA variable corresponding to the demand block. The demand block is: the register demand block to be allocated or the candidate sub-demand block. The key positions include: definition position, usage position, and end position.

5. The register allocation method according to claim 1, characterized in that, The step of performing register allocation operation based on the target sub-requirement block includes: When the free space of the register resource matrix can accommodate the target sub-requirement block, the target sub-requirement block is added to the free space of the register resource matrix; When the free space cannot accommodate the target sub-requirement block, and the target free gap of the allocated register requirement block can accommodate the target sub-requirement block, a splitting operation is performed on the target allocated register requirement block where the target free gap is located according to the target free gap, resulting in two reallocated sub-requirement blocks. Release the space occupied by the target allocated register request block and subsequent allocated register request blocks in the register resource matrix; Update the list of register requirement blocks to be allocated based on the target allocated register requirement blocks and subsequent allocated register requirement blocks; The register request blocks in the list of register request blocks to be allocated are allocated resources in the register resource matrix in sequence.

6. The register allocation method according to claim 3 or 5, characterized in that, The splitting operation includes: When the definition location of the SSA variable corresponding to the register demand block to be split is not a load instruction, a storage instruction is added in the adjacent position after the definition location; Add a load instruction on the side adjacent to the split point, near the definition location of the SSA variable; The location from the definition position of the SSA variable to the usage position adjacent to and close to the definition position of the load instruction is defined as a sub-requirement block; The position from the load instruction to the end of the SSA variable is defined as a sub-requirement block, and the register requirement block to be split is either the target allocated register requirement block or the register requirement block to be allocated.

7. The register allocation method according to claim 5, characterized in that, The register allocation method further includes: When the adjacent usage positions of SSA variables corresponding to multiple register demand blocks to be split in the allocated register demand block all meet the gap condition, the register demand block to be split with the smallest overflow cost is determined as the target allocated register demand block.

8. A register allocation device, characterized in that, The register allocation device includes: a splitting module and an execution module; The splitting module is configured to split the register requirement block required by the SSA variable to be allocated into target sub-requirement blocks based on the usage location of the SSA variable to be allocated. The execution module is configured to perform register allocation operations based on the target sub-requirement block.

9. An electronic device, characterized in that, It includes a processor, a memory, and a program or instructions stored in the memory and executable on the processor, wherein the program or instructions, when executed by the processor, implement the steps of the register allocation method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a program or instructions that, when executed by a processor, implement the steps of the register allocation method as described in any one of claims 1 to 7.

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