Processor supporting data multiplexing and instruction multiplexing and data multiplexing method

Abstract

The invention provides a processor supporting data multiplexing and instruction multiplexing, which is used for supporting multiplexing of operands and instructions of a previous calculation task in a later-executed calculation task, and realizes operand multiplexing and instruction multiplexing based on configuration information stored by a host control module connected with the processor. The processor comprises a configuration information caching module used for storing a storage offset and a storage offset use mark which are acquired from configuration information and correspond to each instruction in each calculation task; the base address dynamic generation module is used for storing a data cache index address of each calculation task and generating a real base address of each instruction in each calculation task; and the calculation module is used for acquiring an operand to execute each calculation task based on the real base address of each instruction in each calculation task generated by the base address dynamic generation module.

Description

Technical Field

[0001] This invention relates to processors, more specifically to processor instruction-data optimization, and more specifically, to a processor and a data multiplexing method that support data multiplexing and instruction multiplexing. Background Technology

[0002] In high-performance computing fields such as scientific computing, big data processing, and artificial intelligence, applications generally place stringent requirements on processing systems, including high computing power, low latency, high throughput, high concurrency, and the ability to handle diverse application types.

[0003] However, current mainstream processor architectures generally face a key bottleneck: the actual efficiency of computing units is often difficult to fully realize. The core issue lies in the data processing flow itself. Specifically, such as... Figure 1 As shown, executing a complete computation task requires first moving the source data and instructions to be processed from off-chip memory to on-chip cache. Then, by reading instructions, the required data is moved from the on-chip cache to registers or local memory units directly accessible by the computation unit for computation. After the computation is completed, the computation result is written back to the on-chip cache, and finally, the computation result is sent back to off-chip memory. To alleviate the processor's idle waiting during data movement, on-chip caches often adopt a Ping-Pong double buffer structure, aiming to achieve parallel operation of the data transmission path and memory / computation units—that is, while one side operates on one buffer, the other side operates on another buffer, thereby improving overall parallelism.

[0004] While the Ping-Pong double-buffered architecture used in the on-chip cache of the processor improves data parallelism, this mechanism still suffers from significant performance overhead. Firstly, the repeated data transfers and memory accesses between memory levels (off-chip -> on-chip cache -> compute unit registers -> on-chip cache -> off-chip) consume considerable time. Secondly, each time the processor starts executing a new task, it needs to transfer a complete instruction set from off-chip memory to the processor's internal instruction memory location to guide the memory access and other operations required by the task, which also consumes a significant amount of time. The time consumed by these data transfers (including instructions and data themselves) is not only limited by the finite off-chip to on-chip transfer bandwidth, but more seriously, this bandwidth is often orders of magnitude slower than the processor's high-speed memory access and computation.

[0005] In summary, current processors spend a significant amount of time on data preparation (transfer and memory access) and instruction updates, rather than on the core computing itself. This results in a severe mismatch between the processor's powerful computing capabilities and its relatively slow data supply capabilities, greatly limiting the processor's overall execution efficiency and performance ceiling.

[0006] It should be noted that the background information presented here is only for illustrating relevant information about the present invention to aid in understanding the technical solutions of the present invention, and does not imply that the relevant information is necessarily prior art. In the absence of evidence indicating that the relevant information was disclosed before the filing date of this invention, the relevant information should not be considered prior art. Summary of the Invention

[0007] Therefore, the purpose of this invention is to overcome the shortcomings of the prior art and provide a processor that supports data multiplexing and instruction multiplexing, and a data multiplexing method.

[0008] The objective of this invention is achieved through the following technical solutions.

[0009] According to a first aspect of the present invention, a processor supporting data reuse and instruction reuse is provided, for supporting the reuse of operands and instructions of a previous computational task by a subsequently executed computational task. The processor implements operand reuse and instruction reuse based on configuration information stored in a host control module to which it is connected. The processor includes: a configuration information cache module for storing the storage offset corresponding to each instruction in each computational task and a storage offset usage flag obtained from the configuration information; wherein the storage offset represents the address offset between the expected memory access address or the actual memory access address of the operand corresponding to a specific instruction in the computational task and the actual memory access address of the operand corresponding to the specific instruction in the previous computational task; the storage offset usage flag indicates whether the storage offset is used; the expected memory access address represents the address to be stored, and the actual memory access address represents the address to be actually stored; and a base address dynamic generation module for storing the data cache index address of each computational task. The system generates the actual base address for each instruction in each computation task. The data cache index address is used to locate the expected base address of the operand, where the expected base address represents the expected base address, and the actual base address represents the actual base address. The dynamic base address generation module is configured to add the storage offset corresponding to each instruction in each computation task to the data cache index address of that computation task to obtain the offset index address of each instruction in each computation task, and use the storage offset usage flag to determine the actual base address of each instruction in each computation task. Specifically, when the storage offset usage flag indicates the use of a storage offset, the offset index address of the instruction is used as the actual base address of that instruction; otherwise, the data cache index address corresponding to the instruction is used as the actual base address of that instruction. The computation module is used to obtain operands to execute each computation task based on the actual base address of each instruction in each computation task generated by the dynamic base address generation module.

[0010] In some embodiments of the present invention, the configuration information caching module includes two registers, one register for storing the storage offset corresponding to each instruction in each computation task obtained from the configuration information of the host control module; the other register for storing the storage offset usage flag corresponding to each instruction in each computation task obtained from the configuration information of the host control module.

[0011] In some embodiments of the present invention, the base address dynamic generation module includes a storage offset register, a storage offset usage flag register, a first multiplexer, a base address calculator, and a second multiplexer, wherein: the storage offset register is used to store the storage offset corresponding to each instruction in each computation task obtained from the configuration information cache module; the storage offset usage flag register is used to store the storage offset usage flag corresponding to each instruction in each computation task obtained from the configuration information cache module; the base address calculator is used to store the data cache index address of each computation task, and adds the storage offset corresponding to each instruction in the computation task stored in the storage offset register to the data cache index address of the computation task to obtain each instruction in each computation task. The offset index address; wherein, both the data cache index address and the offset index address include multiple address indices, each address index being used to locate the base address; the first multiplexer is used to select the storage offset usage flag corresponding to each instruction in each computation task from the storage offset usage flag register; the second multiplexer is used to determine the actual base address corresponding to each instruction in each computation task based on the storage offset usage flag corresponding to each instruction in each computation task selected by the first multiplexer; wherein, when the storage offset usage flag indicates that the storage offset is used, the offset index address of the instruction is used as the actual base address of the instruction, and when the storage offset usage flag indicates that the storage offset is not used, the data cache index address corresponding to the instruction is used as the actual base address of the instruction.

[0012] In some embodiments of the present invention, the computing module includes a real base address register, an instruction register, an instruction fetch unit, a third multiplexer, an adder, an on-chip data cache unit, and a memory access unit, wherein: the real base address register is used to store the real base address corresponding to each instruction in each computing task generated by the base address dynamic generation module; the instruction register is used to store multiple instructions for each computing task transferred from outside the processor, and / or one or more instructions from the previous computing task reused in this computing task; the instruction fetch unit is used to fetch each instruction in each computing task from the instruction register; wherein each instruction includes flag information, an immediate number field, and an instruction opcode; the flag information represents the address index corresponding to the instruction, the immediate number field represents the address offset relative to the real base address corresponding to the instruction, and the instruction opcode indicates that the instruction is a load data operation or a write-back data operation; the third multiplexer is used to select the address index corresponding to each instruction in each computing task from the real base address corresponding to each instruction in each computing task stored in the real base address register based on the flag information corresponding to each instruction in each computing task obtained by the instruction fetch unit; the adder... The adder is used to add the address index selected by the third multiplexer to the immediate number field obtained by the instruction fetch unit to obtain the target memory access address for each instruction in each computation task; wherein, the target memory access address is used to locate the storage address of the on-chip data cache unit; the memory access unit is used to store the operands and computation results of each computation task passed by the on-chip data cache unit; the memory access unit is configured to read the memory access address of each instruction in each computation task stored in the on-chip data cache unit based on the instruction opcode corresponding to each instruction in each computation task obtained by the instruction fetch unit and the target memory access address obtained by the adder. The on-chip data cache unit is used to store the operands of two consecutive computation tasks transferred from outside the processor, as well as the computation results of each computation task transferred by the memory access unit. When the instruction opcode indicates a write-back operation, the computation result of the corresponding computation task is transferred to the memory address located by the target memory access address in the on-chip data cache unit. When the instruction opcode indicates a load data operation, the operands in the on-chip data cache unit are obtained according to the memory access address and stored. The on-chip data cache unit is used to store the operands required for two consecutive computation tasks transferred from outside the processor, as well as the computation results of each computation task transferred by the memory access unit.

[0013] In some embodiments of the present invention, the memory access unit is provided with two data buffers, one of which is used to store the operands of each computation task obtained from the on-chip data cache unit, and the other is used to store the computation result of each computation task.

[0014] In some embodiments of the present invention, the on-chip data cache unit is provided with two on-chip data buffers to store operands required for two consecutive computation tasks. One on-chip data buffer is used to store operands required for the previously executed computation task that are moved from outside the processor, as well as the computation result of the previously executed computation task passed by the memory access unit. The other on-chip data buffer is used to store operands required for the subsequently executed computation task that are moved from outside the processor, the computation result of the subsequently executed computation task passed by the memory access unit, and operands of the previous computation task reused in the previously executed computation task.

[0015] According to a second aspect of the present invention, a data reuse method applied to the processor described in the first aspect of the present invention is provided, for supporting the reuse of operands and instructions of a previous computational task by a subsequently executed computational task. The method involves configuring the processor to execute each computational task according to the following steps: Step S1: A configuration information cache module reads and stores the storage offset corresponding to each instruction in each computational task and a storage offset usage flag from configuration information; wherein, the storage offset represents the address offset between the expected memory access address or the actual memory access address of the operand corresponding to a specific instruction in the computational task and the actual memory access address of the operand corresponding to the specific instruction in the previous computational task; the storage offset usage flag indicates whether the storage offset is used; the expected memory access address represents the address to be stored, and the actual memory access address represents the address to be actually stored. The storage address; Step S2: The base address dynamic generation module adds the storage offset corresponding to each instruction in each computation task to the data cache index address of the computation task stored in itself to obtain the offset index address of each instruction in each computation task, and uses the storage offset usage flag to determine the real base address of each instruction in each computation task; wherein, when the storage offset usage flag indicates that the storage offset is used, the offset index address of the corresponding instruction is used as the real base address of the instruction, and when the storage offset usage flag indicates that the storage offset is not used, the corresponding data cache index address is used as the real base address of the instruction; Step S3: The computation module obtains operands to execute each computation task based on the real base address of each instruction in each computation task generated by the base address dynamic generation module.

[0016] In some embodiments of the present invention, in step S2, the configuration base address dynamic generation module generates the actual base address of each instruction in each computation task according to the following steps: the storage offset register reads and stores the storage offset corresponding to each instruction in each computation task from the configuration information cache module; the storage offset usage flag register reads and stores the storage offset usage flag corresponding to each instruction in each computation task from the configuration information cache module; the base address calculator, based on its own stored data cache index address for each computation task, adds the storage offset corresponding to each instruction in the computation task stored in the storage offset register to the data cache index address of the computation task to obtain the offset index address of each instruction in each computation task. The data cache index address and offset index address each include multiple address indices, each used to locate the storage address. The first multiplexer selects the storage offset usage flag corresponding to each instruction in each computation task from the storage offset usage flag register. The second multiplexer determines the actual base address corresponding to each instruction in each computation task based on the storage offset usage flag corresponding to each instruction in each computation task selected by the first multiplexer. Specifically, when the storage offset usage flag indicates that a storage offset is used, the offset index address of the instruction is used as the actual base address of the instruction; when the storage offset usage flag indicates that a storage offset is not used, the data cache index address corresponding to the instruction is used as the actual base address of the instruction.

[0017] Compared with the prior art, the advantages of the present invention are: the processor is equipped with a configuration information cache module and a base address dynamic generation module, which enables the processor to support the reuse of operands and instructions of the previous calculation task in subsequent calculation tasks, thereby reducing unnecessary data transfer time and instruction transfer time, and thus effectively improving the overall performance of the processor. Attached Figure Description

[0018] The embodiments of the present invention will be further described below with reference to the accompanying drawings, wherein:

[0019] Figure 1 This is a schematic diagram of the data processing flow of an existing processor;

[0020] Figure 2 A schematic diagram of the processor composition according to an embodiment of the present invention.

[0021] Figure 3 This is a schematic diagram of the composition of a computing module according to an embodiment of the present invention. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the invention.

[0023] As mentioned in the background section, current processors spend a significant amount of time on data preparation (transfer and memory access) and instruction updates, rather than on the core computing itself. This results in a severe mismatch between the processor's powerful computing capabilities and its relatively slow data supply capabilities, greatly limiting the processor's overall execution efficiency and performance ceiling.

[0024] To address the aforementioned issues, the inventors analyzed the data preparation and instruction update processes during processor computational tasks and discovered significant feasibility in data and instruction reuse. Therefore, the inventors proposed optimizing these processes to allow subsequent computational tasks to reuse operands and instructions from previous tasks. This reduces unnecessary data and instruction transfer time, thereby effectively improving the overall performance of the processor.

[0025] Based on this, the present invention provides a processor capable of data and instruction multiplexing. The processor includes a configuration information cache module, a base address dynamic generation module, and a computation module. The configuration information cache module stores the storage offset and storage offset usage flag corresponding to each instruction in each computation task, obtained from the configuration information. The base address dynamic generation module generates the actual base address of each instruction in each computation task based on the storage offset and storage offset usage flag. The computation module obtains operands based on the actual base address of each instruction in each computation task to execute each computation task. The base address dynamic generation module determines the actual base address of each instruction in each computation task, ensuring that the processor can address both multiplexed operands and operands corresponding to multiplexed instructions, as well as non-multiplexed operands and operands corresponding to non-multiplexed instructions. This allows the processor to flexibly access memory to target addresses and data, thereby reducing unnecessary data and instruction transport time and improving overall processor performance.

[0026] In summary, such as Figure 2As shown, a processor supporting data reuse and instruction reuse is provided to support the reuse of operands and instructions from a previous computational task in subsequent executions. The processor implements operand reuse and instruction reuse based on configuration information stored in a connected host control module. The processor includes: a configuration information cache module for storing the storage offset corresponding to each instruction in each computational task and a storage offset usage flag obtained from the configuration information; wherein, the storage offset represents the address offset between the expected memory access address or actual memory access address of the operand corresponding to a specific instruction in the computational task and the actual memory access address of the operand corresponding to a specific instruction in the previous computational task; the storage offset usage flag indicates whether the storage offset is used; the expected memory access address represents the address to be stored, and the actual memory access address represents the address to be actually stored; and a base address dynamic generation module for storing the data cache index address of each computational task and generating... The base address is the actual base address of each instruction in each computation task; the data cache index address is used to locate the expected base address of the operand, where the expected base address represents the expected base address and the actual base address represents the actual base address; the base address dynamic generation module is configured to add the storage offset corresponding to each instruction in each computation task to the data cache index address of that computation task to obtain the offset index address of each instruction in each computation task, and use the storage offset usage flag to determine the actual base address of each instruction in each computation task; where, when the storage offset usage flag indicates that the storage offset is used, the offset index address of the instruction is used as the actual base address of the instruction, otherwise, the data cache index address corresponding to the instruction is used as the actual base address of the instruction; the computation module is used to obtain the operand to execute each computation task based on the actual base address of each instruction in each computation task generated by the base address dynamic generation module.

[0027] Before describing the embodiments of the present invention in detail, some of the terms used therein are explained as follows:

[0028] Base address: Indicates the starting position of a storage area, used to locate the starting point of the final memory access address.

[0029] To better understand the present invention, each module in the processor will be described in detail below with reference to specific embodiments.

[0030] I. Configuration Information Caching Module

[0031] The configuration information caching module is used to store the storage offset and storage offset usage flag corresponding to each instruction in each computing task obtained from the configuration information stored in the host control module. The storage offset represents the address offset between the expected memory access address or the actual memory access address of the operand corresponding to a specific instruction in the computing task and the actual memory access address of the operand corresponding to a specific instruction in the previous computing task. The storage offset usage flag indicates whether the storage offset is used. The expected memory access address represents the address that is expected to be stored, and the actual memory access address represents the address that is actually stored.

[0032] According to one embodiment of the present invention, the configuration information caching module includes two registers, one register for storing the storage offset corresponding to each instruction in each computation task obtained from the configuration information of the host control module; the other register for storing a storage offset usage flag corresponding to each instruction in each computation task obtained from the configuration information of the host control module. Wherein, as... Figure 2 As shown, register 0 is used to store the storage offset corresponding to the instruction, and register 1 is used to store the corresponding storage offset usage flag.

[0033] The memory offset, denoted as BaseAddrConfig, represents the address offset between the expected or actual memory access address of the operand corresponding to a specific instruction in a computation task and the actual memory access address of the operand corresponding to the same instruction in the previous computation task. For example, suppose an instruction in a later-executed computation task corresponds to operand A, and an instruction in an earlier-executed computation task corresponds to operand B. The corresponding memory offset could be: BaseAddrConfig_AB = F_ADDR_preB - F_ADDR_preA, where F_ADDR_preA represents the expected memory access address of operand A, and F_ADDR_preB represents the actual memory access address of operand B.

[0034] The storage offset usage flag is either 0 or 1. When the flag is 0, the corresponding storage offset is used; when it is 1, the corresponding storage offset is not used. It's important to note that the memory addresses of the operands and results used in the previously executed computation task on the on-chip cache are fixed, as are the off-chip addresses of the operands used in that task. Similarly, the off-chip addresses of the operands required in subsequent computation tasks are also fixed. Therefore, by analyzing whether the off-chip addresses of the operands required in two consecutive computation tasks are the same, we can determine whether the operands in the subsequent task can be reused from the previous task. If the off-chip addresses are the same, the operands are identical and can be reused, and the corresponding storage offset usage flag is set to 0. If the off-chip addresses are different, the operands are different and cannot be reused, and the corresponding storage offset usage flag is set to 1.

[0035] II. Base Address Dynamic Generation Module

[0036] The dynamic base address generation module is used to store the data cache index address for each computation task and to generate the actual base address for each instruction in each computation task. The data cache index address is used to locate the expected base address of the operand, where the expected base address represents the expected base address and the actual base address represents the actual base address. The dynamic base address generation module is configured to add the storage offset corresponding to each instruction in each computation task to the data cache index address of that computation task to obtain the offset index address of each instruction in each computation task, and to determine the actual base address of each instruction in each computation task using the storage offset usage flag. Specifically, when the storage offset usage flag indicates that a storage offset is used, the offset index address of the instruction is used as the actual base address of the instruction; otherwise, the data cache index address corresponding to the instruction is used as the actual base address of the instruction.

[0037] According to one embodiment of the present invention, such as Figure 2 As shown, the base address dynamic generation module includes a storage offset register, a storage offset usage flag register, a first multiplexer, a base address calculator, and a second multiplexer.

[0038] The storage offset register is used to store the storage offset corresponding to each instruction in each computation task obtained from the configuration information cache module.

[0039] The storage offset uses a flag register to store the storage offset usage flag corresponding to each instruction in each computation task, obtained from the configuration information cache module.

[0040] The base address calculator is used to store the data cache index address for each calculation task, and adds the storage offset corresponding to each instruction in the calculation task stored in the storage offset register to the data cache index address of the calculation task to obtain the offset index address of each instruction in each calculation task; wherein, both the data cache index address and the offset index address include multiple address indices, and each address index is used to locate the base address.

[0041] The first multiplexer is used to select the memory offset usage flag corresponding to each instruction in each computation task from the memory offset usage flag register.

[0042] The second multiplexer is used to determine the actual base address of each instruction in each computation task based on the storage offset usage flag corresponding to each instruction in each computation task selected by the first multiplexer; wherein, when the storage offset usage flag indicates that the storage offset is used, the offset index address of the instruction is used as the actual base address of the instruction, and when the storage offset usage flag indicates that the storage offset is not used, the data cache index address corresponding to the instruction is used as the actual base address of the instruction.

[0043] To better understand this invention, the following is combined with... Figure 2 This will explain how the dynamic base address generation module generates the actual base address for each instruction.

[0044] Depend on Figure 2 It can be seen that the base address dynamic generation module is configured to generate the actual base address of each instruction in the following manner: the storage offset register first obtains the storage offset corresponding to the current instruction; the base address calculator then adds the storage offset corresponding to the instruction to the data cache index address (offset0~3) of the computation task to obtain the offset index address (Wh_Addr0~3, Wh_Addr0~3=offset0~3+BaseAddrConfig); the first multiplexer then selects the storage offset usage flag corresponding to the instruction from the storage offset usage flag register; finally, the second multiplexer determines the actual base address corresponding to the instruction based on the storage offset usage flag (0 or 1) selected by the first multiplexer; wherein, when the storage offset usage flag is 0, the offset index address (Wh_Addr0~3) of the instruction is used as the actual base address of the instruction, and when the storage offset usage flag is 1, the data cache index address (offset0~3) corresponding to the instruction is used as the actual base address of the instruction. Here, offset0, offset1, offset2, and offset3 are address indices in the data cache index address, and Wh_Addr0, Wh_Addr1, Wh_Addr2, and Wh_Addr3 are address indices in the offset index address. These address indices are used to locate the base address.

[0045] It should be noted that the base address dynamic generation module can also be configured with a base address register to store the actual base address of each instruction generated by the module. For example, ... Figure 2 As shown, Dym_addr0~3 are set in the base address dynamic generation module to store the actual base address of each instruction.

[0046] III. Calculation Module

[0047] The calculation module is used to obtain operands to execute each calculation task based on the real base address of each instruction in each calculation task generated by the base address dynamic generation module.

[0048] According to one embodiment of the present invention, such as Figure 3 As shown, the computing module includes a real base address register, an instruction register, an instruction fetch unit, a third multiplexer, an adder, an on-chip data cache unit, and a memory access unit.

[0049] The real base address register is used to store the real base address corresponding to each instruction in each computation task generated by the base address dynamic generation module.

[0050] The instruction register (Instruction Buffer) is used to store multiple instructions for each computation task transferred from outside the processor, and / or one or more instructions from the previous computation task reused in the current computation task.

[0051] The instruction fetch unit is used to fetch each instruction in each computation task from the instruction register; wherein each instruction includes flag information, an immediate number field and an instruction opcode; the flag information indicates the address index corresponding to the instruction, the immediate number field indicates the address offset relative to the actual base address corresponding to the instruction, and the instruction opcode indicates whether the instruction is a load data operation or a write-back data operation.

[0052] The third multiplexer is used to select the address index corresponding to each instruction in each computation task from the real base address corresponding to each instruction in each computation task stored in the real base address register, based on the flag information corresponding to each instruction in each computation task obtained by the instruction fetch unit.

[0053] The adder is used to add the address index selected by the third multiplexer to the immediate number field obtained by the instruction fetch unit to obtain the target memory access address of each instruction in each computation task; wherein, the target memory access address is used to locate the storage address of the on-chip data cache unit.

[0054] The memory access unit is used to store the operands and calculation results of each computation task passed by the on-chip data cache unit. The memory access unit is configured to read the operands of each computation task stored in the on-chip data cache unit or pass the calculation results of each computation task to the on-chip data cache unit based on the instruction opcode corresponding to each instruction in each computation task obtained by the instruction fetch unit and the target memory access address obtained by the adder. Specifically, when the instruction opcode indicates a write-back operation, the calculation result of the corresponding computation task is passed to the storage address located by the target memory access address in the on-chip data cache unit. When the instruction opcode indicates a load operation, the operands in the on-chip data cache unit are obtained and stored according to the storage address located by the target memory access address.

[0055] According to one embodiment of the present invention, the memory access unit is provided with two data buffers, one data buffer for storing operands for each computation task obtained from the on-chip data cache unit, and the other data buffer for storing the computation result of each computation task. Wherein, as... Figure 3 As shown, the data buffer Buffer2Data is used to store the operands of each computation task obtained from the on-chip data cache unit, and the data buffer Data2Buffer is used to store the computation result of each computation task.

[0056] The on-chip data cache unit is used to store the operands required for two consecutive computation tasks transferred from outside the processor, as well as the computation results of each computation task passed by the memory access unit.

[0057] According to one embodiment of the present invention, the on-chip data cache unit is provided with two on-chip data buffers (BUF0 and BUF1) to store operands required for two consecutive computation tasks. One on-chip data buffer is used to store operands required for the previously executed computation task that are transferred from outside the processor, as well as the computation result of the previously executed computation task passed by the memory access unit. The other on-chip data buffer is used to store operands required for the subsequently executed computation task that are transferred from outside the processor, the computation result of the subsequently executed computation task passed by the memory access unit, and operands of the previous computation task reused in the previously executed computation task.

[0058] To better understand this invention, the following is combined with... Figure 3 This explains how the computation module processes each instruction based on the actual base address of each instruction in each computation task generated by the dynamic base address generation module.

[0059] like Figure 3It can be seen that the computation module (PE) is configured to process each instruction as follows: the instruction fetch unit first fetches an instruction from the instruction buffer for the current computation task. This instruction includes flag information, an immediate number field (addr_imm), and an opcode. The third multiplexer then selects the address index corresponding to the instruction (e.g., Base_addr0, where Base_addr0 = offset0 or Wh_Addr0) from the real base address register based on the flag information (flag) of the instruction fetched by the instruction fetch unit. The adder then adds the address index (Base_addr0) selected by the third multiplexer to the immediate number field (addr_imm) fetched by the instruction fetch unit to obtain the target memory access address (F) of the instruction. Finally, the memory access unit receives the instruction opcode and the target memory access address (F_ADDR) obtained by the adder and executes the corresponding operation. When the instruction opcode indicates a write-back operation, the calculation result of the corresponding calculation task is passed to the corresponding address space in BUF0 or BUF1 located at the target memory access address (F_ADDR) in the on-chip data cache unit. When the instruction opcode indicates a load operation, the operands in the corresponding address space in BUF0 or BUF1 are obtained according to the memory address located at the target memory access address (F_ADDR) and stored in the data buffer Buffer2Data for later use.

[0060] As can be seen from the foregoing embodiments, unlike the prior art, the present invention sets up a configuration information cache module and a base address dynamic generation module in the processor, so that the base address dynamic generation module can generate the actual base address corresponding to each instruction based on the data stored in the configuration information cache module. In turn, the calculation module can determine the target memory access address of each instruction based on the actual base address and the flag information and immediate number field in the instruction. This enables the processor to flexibly access the target address and data according to the target memory access address, thereby reducing unnecessary data and instruction transfer time and improving the overall performance of the processor.

[0061] Based on the foregoing embodiments, the present invention also proposes a data reuse method for the processor described in the foregoing embodiments, used to support the reuse of operands and instructions from the previous computation task by a later-executed computation task. The method involves configuring the processor to execute each computation task according to the following steps: Step S1: A configuration information cache module reads and stores the storage offset corresponding to each instruction in each computation task and a storage offset usage flag from the configuration information; wherein, the storage offset represents the address offset between the expected memory access address or actual memory access address of the operand corresponding to a specific instruction in the computation task and the actual memory access address of the operand corresponding to a specific instruction in the previous computation task; the storage offset usage flag indicates whether the storage offset is used; the expected memory access address represents the address to be stored, and the actual memory access address represents the actual memory access address. The address; Step S2: The base address dynamic generation module adds the storage offset corresponding to each instruction in each computation task to the data cache index address of the computation task stored in itself to obtain the offset index address of each instruction in each computation task, and uses the storage offset usage flag to determine the real base address of each instruction in each computation task; wherein, when the storage offset usage flag indicates that the storage offset is used, the offset index address of the corresponding instruction is used as the real base address of the instruction, and when the storage offset usage flag indicates that the storage offset is not used, the corresponding data cache index address is used as the real base address of the instruction; Step S3: The computation module obtains operands to execute each computation task based on the real base address of each instruction in each computation task generated by the base address dynamic generation module.

[0062] According to an embodiment of the present invention, in step S2, the configuration base address dynamic generation module generates the actual base address of each instruction in each computation task according to the following steps: the storage offset register reads and stores the storage offset corresponding to each instruction in each computation task from the configuration information cache module; the storage offset usage flag register reads and stores the storage offset usage flag corresponding to each instruction in each computation task from the configuration information cache module; the base address calculator, based on its own stored data cache index address for each computation task, adds the storage offset corresponding to each instruction in the computation task stored in the storage offset register to the data cache index address of the computation task to obtain the offset index address of each instruction in each computation task. The data cache index address and offset index address each include multiple address indices, each used to locate the storage address. The first multiplexer selects the storage offset usage flag corresponding to each instruction in each computation task from the storage offset usage flag register. The second multiplexer determines the actual base address corresponding to each instruction in each computation task based on the storage offset usage flag corresponding to each instruction in each computation task selected by the first multiplexer. Specifically, when the storage offset usage flag indicates that a storage offset is used, the offset index address of the instruction is used as the actual base address of the instruction; when the storage offset usage flag indicates that a storage offset is not used, the data cache index address corresponding to the instruction is used as the actual base address of the instruction.

[0063] To better understand this invention, the following specific operand reuse example illustrates how the data reuse method proposed in this invention achieves operand reuse.

[0064] Suppose there are two computational tasks, TASK0 and TASK1. TASK0 corresponds to element-wise addition: A1 + B1, with operands A1 and B1 stored in the on-chip data buffer BUF0. TASK1 corresponds to element-wise multiplication: A2 * B1, with operands A2 and B1 stored in the on-chip data buffer BUF1. In this case, TASK1 can reuse operand B1 stored in the on-chip data buffer BUF0 (by offsetting the address from BUF1 to BUF0 during memory access), only requiring operand A2 to be moved to the on-chip data buffer BUF1 for storage. The execution process of TASK1 is described in detail below.

[0065] First, the configuration information caching module reads and stores the storage offsets and storage offset usage flags corresponding to the A2 operand loading instruction, B1 operand loading instruction, and calculation result storage instruction in TASK1 from the configuration information.

[0066] In this context, the storage offset corresponding to the A2 operand load instruction is 0, and the storage offset usage flag is 1. The storage offset corresponding to the B1 operand load instruction is BaseAddrConfig_B1, and the storage offset usage flag is 0. This storage offset is the address offset between the expected memory access address F_ADDR_preB1 of operand B1 in the on-chip data buffer BUF1 and the actual memory access address F_ADDR_tureB1 of operand B1 in the on-chip data buffer BUF0, i.e., BaseAddrConfig_B1 = F_ADDR_tureB1 - F_ADDR_preB1. The storage offset corresponding to the result storage instruction is 0, and the storage offset usage flag is 1.

[0067] Then, the base address dynamic generation module generates the actual base addresses of the A2 operand load instruction, the B1 operand load instruction, and the calculation result storage instruction in sequence according to the instruction execution order.

[0068] For the A2 operand load instruction, the corresponding storage offset is 0 and the storage offset usage flag is 1. In this case, the data cache index address offset_TASK1_0~3 corresponding to TASK1 can be directly used as the real base address of the instruction.

[0069] For the B1 operand load instruction, its corresponding storage offset is BaseAddrConfig_B1, and the storage offset usage flag is 0. At this time, the data cache index address offset_TASK1_0~3 corresponding to TASK1 needs to be added to the storage offset BaseAddrConfig_B1 to obtain the offset index address Wh_Addr_B1_0~3 corresponding to the instruction (Wh_Addr_B1_0~3=offset_TASK1_0~3+ BaseAddrConfig_B1), and the offset index address Wh_Addr_B1_0~3 is used as the actual base address of the instruction.

[0070] For the instruction to store the calculation result, its corresponding storage offset is 0 and the storage offset usage flag is 1. In this case, the data cache index address offset_TASK1_0~3 corresponding to TASK1 can be directly used as the real base address of the instruction.

[0071] Finally, the calculation module retrieves operand A2 from the on-chip data buffer BUF1 and operand B1 from the on-chip data buffer BUF0 based on the A2 operand load instruction generated by the base address dynamic generation module to perform element-wise multiplication calculation, and writes the calculation result back to the on-chip data buffer BUF1 based on the real base address of the calculation result storage instruction.

[0072] For the A2 operand load instruction, the fetch unit in the calculation module first retrieves the A2 operand load instruction from the instruction buffer. The third multiplexer then selects the address index corresponding to the instruction (e.g., Base_addr1, Base_addr1 = offset_TASK1_1) from the real base address register based on the flag information corresponding to the A2 operand load instruction retrieved by the fetch unit. The adder then adds the address index (Base_addr1) selected by the third multiplexer to the immediate number field (addr_imm_A2) retrieved by the fetch unit to obtain the target memory access address of the instruction (F_ADDR_A2, F_ADDR_A2 = Base_addr1 + ...). (addr_imm_A2); The memory access unit receives the instruction opcode corresponding to the instruction and the target memory access address (F_ADDR_A2) obtained by the adder. Based on the memory address located by the target memory access address (F_ADDR_A2), it obtains the operand A2 in the corresponding address space in BUF1 and stores it in the data buffer Buffer2Data for later use.

[0073] For the B1 operand load instruction, the fetch unit in the computation module first retrieves the B1 operand load instruction from the instruction register (InstructionBuffer). The third multiplexer then selects the address index corresponding to the instruction (e.g., Base_addr_0, Base_addr0 = Wh_Addr_B1_0) from the real base address register based on the flag information corresponding to the B1 operand load instruction retrieved by the fetch unit. The adder then adds the address index (Base_addr0) selected by the third multiplexer to the immediate number field (addr_imm_B1) retrieved by the fetch unit to obtain the target memory access address of the instruction (F_ADDR_B1, F_ADDR_B1 = Base_addr0 + ...). (addr_imm_B1); The memory access unit receives the instruction opcode corresponding to the instruction and the target memory access address (F_ADDR_B1) obtained by the adder. Based on the memory address located by the target memory access address (F_ADDR_B1), it obtains the operand B1 in the corresponding address space in BUF0 and stores it in the data buffer Buffer2Data for later use.

[0074] For the instruction to store the computation result, the instruction fetch unit in the computation module first retrieves the instruction from the instruction buffer. The third multiplexer then selects the address index corresponding to the instruction (e.g., Base_addr2, Base_addr2 = offset_TASK1_2) from the real base address register based on the flag information (flag) corresponding to the instruction retrieved by the instruction fetch unit. The adder then adds the address index (Base_addr2) selected by the third multiplexer to the immediate number field (addr_imm_T1) retrieved by the instruction fetch unit to obtain the target memory access address (F_ADDR_T1, F_ADDR_T1 = Base_addr2 + addr_imm_T1). Finally, the memory access unit receives the instruction opcode and the target memory access address (F_ADDR_T1) obtained by the adder and passes the computation result of TASK1 to the address space corresponding to BUF1 located at the target memory access address (F_ADDR_T1).

[0075] To better understand this invention, the following specific example of instruction multiplexing illustrates how the data multiplexing method proposed in this invention achieves instruction multiplexing.

[0076] Suppose we have two computational tasks, TASK2 and TASK3. TASK2 performs element-wise addition: A0 + B0, with operands A0 and B0 stored in on-chip data buffer BUF1. TASK3 performs element-wise addition: A3 + B3, with operands A3 and B3 stored in on-chip data buffer BUF0. In this case, TASK3 is essentially executing TASK2 again. Therefore, the instructions and corresponding data cache index address of TASK2 can be reused. During memory access, the address only needs to be offset from on-chip data buffer BUF1 to on-chip data buffer BUF0 to retrieve operands A3 and B3. The execution process of TASK3 is described in detail below.

[0077] First, the configuration information caching module reads and stores the storage offsets and storage offset usage flags corresponding to the A0 operand loading instruction, B0 operand loading instruction, and calculation result storage instruction in TASK2 reused by TASK3 from the configuration information.

[0078] The storage offset corresponding to the A0 operand load instruction is BaseAddrConfig_A0, and the storage offset usage flag is 0. This storage offset is equal to the address offset between the actual memory access address F_ADDR_tureA3 of operand A3 in on-chip data buffer BUF0 and the actual memory access address F_ADDR_tureA0 of operand A0 in on-chip data buffer BUF1, that is, BaseAddrConfig_A0 = F_ADDR_tureA3 - F_ADDR_tureA0.

[0079] The memory offset corresponding to the B0 operand load instruction is BaseAddrConfig_B0, and the memory offset usage flag is 0. This memory offset is equal to the address offset between the actual memory access address F_ADDR_tureB3 of operand B3 in the on-chip data buffer BUF0 and the actual memory access address F_ADDR_tureB0 of operand B0 in the on-chip data buffer BUF1, that is, BaseAddrConfig_B0 = F_ADDR_tureB3 - F_ADDR_tureB0.

[0080] The storage offset corresponding to the calculation result storage instruction is BaseAddrConfig_T2, and the storage offset usage flag is 0. This storage offset is equal to the address offset between the actual memory access address F_ADDR_tureT3 of the operand corresponding to the TASK3 calculation result storage instruction in the on-chip data buffer BUF0 and the actual memory access address F_ADDR_tureT2 of the operand corresponding to the TASK2 calculation result storage instruction in the on-chip data buffer BUF1, that is, BaseAddrConfig_T2 = F_ADDR_tureT3 - F_ADDR_tureT2.

[0081] Then, the base address dynamic generation module generates the actual base addresses of the A0 operand load instruction, the B0 operand load instruction, and the calculation result storage instruction in sequence according to the instruction execution order.

[0082] For the A0 operand load instruction, its corresponding storage offset is BaseAddrConfig_A0, and the storage offset usage flag is 0. At this point, the data cache index address offset_TASK2_0~3 corresponding to TASK2 needs to be added to the storage offset BaseAddrConfig_A0 to obtain the offset index address Wh_Addr_A0_0~3 corresponding to this instruction (Wh_Addr_A0_0~3 = offset_TASK2_0~3 + BaseAddrConfig_A0), and this offset index address Wh_Addr_A0_0~3 is used as the actual base address of this instruction.

[0083] For the B0 operand load instruction, its corresponding storage offset is BaseAddrConfig_B0, and the storage offset usage flag is 0. At this point, the data cache index address offset_TASK2_0~3 corresponding to TASK2 needs to be added to the storage offset BaseAddrConfig_B0 to obtain the offset index address Wh_Addr_B0_0~3 corresponding to this instruction (Wh_Addr_B0_0~3 = offset_TASK2_0~3 + BaseAddrConfig_B0), and this offset index address Wh_Addr_B0_0~3 is used as the actual base address of this instruction.

[0084] For the instruction that stores the calculation result, its corresponding storage offset is BaseAddrConfig_T2, and the storage offset usage flag is 0. At this point, the data cache index address offset_TASK2_0~3 corresponding to TASK2 needs to be added to the storage offset BaseAddrConfig_T2 to obtain the offset index address Wh_Addr_T2_0~3 corresponding to the instruction (Wh_Addr_T2_0~3 = offset_TASK2_0~3 + BaseAddrConfig_T2), and the offset index address Wh_Addr_T2_0~3 is used as the actual base address of the instruction.

[0085] Finally, based on the real base addresses of the A0 operand load instruction, the B0 operand load instruction, and the calculation result storage instruction generated by the base address dynamic generation module, the calculation module obtains operands A3 and B3 from the on-chip data buffer BUF0 to perform element-wise addition calculation, and writes the calculation result back to the on-chip data buffer BUF0 based on the real base address of the calculation result storage instruction.

[0086] For the A0 operand load instruction, the fetch unit in the calculation module first retrieves the A0 operand load instruction from the instruction buffer. The third multiplexer then selects the address index corresponding to the instruction (e.g., Base_addr1, Base_addr1 = Wh_Addr_A0_1) from the real base address register based on the flag information corresponding to the A0 operand load instruction retrieved by the fetch unit. The adder then adds the address index (Base_addr1) selected by the third multiplexer to the immediate number field (addr_imm_A0) retrieved by the fetch unit to obtain the target memory access address of the instruction (F_ADDR_A3, F_ADDR_A3 = Base_addr1 + ...). (addr_imm_A0); The memory access unit receives the instruction opcode corresponding to the instruction and the target memory access address (F_ADDR_A3) obtained by the adder. Based on the memory address located by the target memory access address (F_ADDR_A3), it obtains the operand A3 in the corresponding address space in BUF0 and stores it in the data buffer Buffer2Data for later use.

[0087] For the B0 operand load instruction, the fetch unit in the computation module first retrieves the B0 operand load instruction from the instruction register (InstructionBuffer). The third multiplexer then selects the address index corresponding to the instruction from the real base address register based on the flag information (flag) obtained by the fetch unit (e.g., Base_addr_0, Base_addr0 = Wh_Addr_B1_0). The adder then adds the address index (Base_addr0) selected by the third multiplexer to the immediate number field (addr_imm_B0) obtained by the fetch unit to obtain the target memory access address of the instruction (F_ADDR_B3, F_ADDR_B3 = Base_addr0 + ...). (addr_imm_B0); The memory access unit receives the instruction opcode corresponding to the instruction and the target memory access address (F_ADDR_B3) obtained by the adder. Based on the memory address located by the target memory access address (F_ADDR_B3), it obtains the operand B3 in the corresponding address space in BUF0 and stores it in the data buffer Buffer2Data for later use.

[0088] For the instruction to store the computation result, the instruction fetch unit in the computation module first retrieves the instruction from the instruction register (InstructionBuffer). The third multiplexer then selects the address index corresponding to the instruction (e.g., Base_addr2, Base_addr2 = Wh_Addr_T2_2) from the real base address register based on the flag information (flag) corresponding to the instruction obtained by the instruction fetch unit. The adder then adds the address index (Base_addr2) selected by the third multiplexer to the immediate number field (addr_imm_T2) obtained by the instruction fetch unit to obtain the target memory access address (F_ADDR_T3, F_ADDR_T3 = Base_addr2 + addr_imm_T2). Finally, the memory access unit receives the instruction opcode corresponding to the instruction and the target memory access address (F_ADDR_T3) obtained by the adder, and passes the computation result of TASK3 stored in the data buffer Data2Buffer to the address space corresponding to BUF0 located at the target memory access address (F_ADDR_T3).

[0089] The beneficial effects of this invention are as follows: by setting up a configuration information cache module and a base address dynamic generation module in the processor, the processor can support the reuse of operands and instructions of the previous calculation task in subsequent calculation tasks, thereby reducing unnecessary data transfer time and instruction transfer time, and thus effectively improving the overall performance of the processor.

[0090] It should be noted that although the steps are described in a specific order above, it does not mean that the steps must be executed in the above specific order. In fact, some of these steps can be executed concurrently or even in a different order, as long as the required function can be achieved.

[0091] This invention can be a system, method, and / or computer program product. A computer program product may include a computer-readable storage medium having computer-readable program instructions loaded thereon for causing a processor to implement various aspects of the invention.

[0092] Computer-readable storage media can be tangible devices that hold and store instructions for use by an instruction execution device. Computer-readable storage media can include, for example, but not limited to, electrical storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination thereof. More specific examples (a non-exhaustive list) of computer-readable storage media include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital multifunction disc (DVD), memory sticks, floppy disks, mechanical encoding devices, such as punch cards or recessed protrusions storing instructions thereon, and any suitable combination thereof.

[0093] The various embodiments of the present invention have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or technical improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A processor supporting data reuse and instruction reuse, used to support the reuse of operands and instructions of a previous computational task by a subsequently executed computational task, characterized in that, The processor implements operand multiplexing and instruction multiplexing based on configuration information stored in the host control module it is connected to. The processor includes: The configuration information caching module is used to store the storage offset and storage offset usage flag for each instruction in each computation task obtained from the configuration information. The storage offset represents the address offset between the expected memory access address or the actual memory access address of the operand corresponding to a specific instruction in the computation task and the actual memory access address of the operand corresponding to a specific instruction in the previous computation task. The storage offset usage flag indicates whether the storage offset is used. The expected memory access address represents the address that is expected to be stored, and the actual memory access address represents the address that is actually stored. The base address dynamic generation module is used to store the data cache index address for each computation task and generate the actual base address for each instruction in each computation task. The data cache index address is used to locate the expected base address of the operand, where the expected base address represents the expected base address, and the actual base address represents the actual base address. The base address dynamic generation module is configured to add the storage offset corresponding to each instruction in each computation task to the data cache index address of that computation task to obtain the offset index address of each instruction in each computation task, and use the storage offset usage flag to determine the actual base address of each instruction in each computation task. Specifically, when the storage offset usage flag indicates that the storage offset is used, the offset index address of the instruction is used as the actual base address of the instruction; otherwise, the data cache index address corresponding to the instruction is used as the actual base address of the instruction. The calculation module is used to obtain operands to execute each calculation task based on the actual base address of each instruction in each calculation task generated by the base address dynamic generation module.

2. The processor according to claim 1, characterized in that, The configuration information caching module includes two registers. One register stores the storage offset corresponding to each instruction in each computation task obtained from the configuration information of the host control module. The other register stores the storage offset usage flag corresponding to each instruction in each computation task obtained from the configuration information of the host control module.

3. The processor according to claim 2, characterized in that, The base address dynamic generation module includes a storage offset register, a storage offset usage flag register, a first multiplexer, a base address calculator, and a second multiplexer, wherein: The storage offset register is used to store the storage offset corresponding to each instruction in each calculation task obtained from the configuration information cache module; The storage offset uses a flag register to store the storage offset usage flag corresponding to each instruction in each computation task, obtained from the configuration information cache module; The base address calculator is used to store the data cache index address of each calculation task, and adds the storage offset corresponding to each instruction in the calculation task stored in the storage offset register to the data cache index address of the calculation task to obtain the offset index address of each instruction in each calculation task; wherein, both the data cache index address and the offset index address include multiple address indices, and each address index is used to locate the base address; The first multiplexer is used to select the memory offset usage flag corresponding to each instruction in each computation task from the memory offset usage flag register; The second multiplexer is used to determine the actual base address of each instruction in each computation task based on the storage offset usage flag corresponding to each instruction in each computation task selected by the first multiplexer; wherein, when the storage offset usage flag indicates that the storage offset is used, the offset index address of the instruction is used as the actual base address of the instruction, and when the storage offset usage flag indicates that the storage offset is not used, the data cache index address corresponding to the instruction is used as the actual base address of the instruction.

4. The processor according to claim 3, characterized in that, The computing module includes a real base address register, an instruction register, an instruction fetch unit, a third multiplexer, an adder, an on-chip data cache unit, and a memory access unit, wherein: The real base address register is used to store the real base address corresponding to each instruction in each computation task generated by the base address dynamic generation module; The instruction register is used to store multiple instructions for each computation task transferred from outside the processor, and / or one or more instructions from the previous computation task reused in the current computation task. The instruction fetch unit is used to fetch each instruction in each computation task from the instruction register; wherein, each instruction includes flag information, an immediate number field and an instruction opcode; the flag information indicates the address index corresponding to the instruction, the immediate number field indicates the address offset relative to the actual base address corresponding to the instruction, and the instruction opcode indicates whether the instruction is a load data operation or a write-back data operation; The third multiplexer is used to select the address index corresponding to each instruction in each computation task from the real base address corresponding to each instruction in each computation task stored in the real base address register, based on the flag information corresponding to each instruction in each computation task obtained by the instruction fetch unit. The adder is used to add the address index selected by the third multiplexer to the immediate number field obtained by the instruction fetch unit to obtain the target memory access address of each instruction in each computation task; wherein, the target memory access address is used to locate the storage address of the on-chip data cache unit; The memory access unit is used to store the operands and calculation results of each computation task passed by the on-chip data cache unit. The memory access unit is configured to read the operands of each computation task stored in the on-chip data cache unit or pass the calculation results of each computation task to the on-chip data cache unit based on the instruction opcode corresponding to each instruction in each computation task obtained by the instruction fetch unit and the target memory access address obtained by the adder. Specifically, when the instruction opcode indicates a write-back operation, the calculation result of the corresponding computation task is passed to the storage address located by the target memory access address in the on-chip data cache unit; when the instruction opcode indicates a load operation, the operands in the on-chip data cache unit are obtained and stored according to the storage address located by the target memory access address. The on-chip data cache unit is used to store the operands required for two consecutive computation tasks transferred from outside the processor, as well as the computation results of each computation task passed by the memory access unit.

5. The processor according to claim 4, characterized in that, The memory access unit is equipped with two data buffers. One data buffer is used to store the operands of each computation task obtained from the on-chip data cache unit, and the other data buffer is used to store the computation result of each computation task.

6. The processor according to claim 5, characterized in that, The on-chip data cache unit is provided with two on-chip data buffers to store the operands required for two consecutive computation tasks. One on-chip data buffer is used to store the operands required for the previously executed computation task that are moved from outside the processor, as well as the computation result of the previously executed computation task passed by the memory access unit. The other on-chip data buffer is used to store the operands required for the subsequently executed computation task that are moved from outside the processor, the computation result of the subsequently executed computation task passed by the memory access unit, and the operands of the previous computation task reused in the previously executed computation task.

7. A data reuse method applied to the processor of any one of claims 1-6, for supporting the reuse of operands and instructions of a previous computational task by a subsequently executed computational task, characterized in that, The method involves configuring the processor to execute each computation task according to the following steps: Step S1: The configuration information caching module reads and stores the storage offset and storage offset usage flag corresponding to each instruction in each computation task from the configuration information. The storage offset represents the address offset between the expected memory access address or the actual memory access address of the operand corresponding to a specific instruction in the computation task and the actual memory access address of the operand corresponding to a specific instruction in the previous computation task. The storage offset usage flag indicates whether the storage offset is used. The expected memory access address represents the address that is expected to be stored, and the actual memory access address represents the address that is actually stored. Step S2: The base address dynamic generation module adds the storage offset corresponding to each instruction in each computation task to the data cache index address of the computation task stored in itself to obtain the offset index address of each instruction in each computation task, and uses the storage offset usage flag to determine the real base address of each instruction in each computation task; wherein, when the storage offset usage flag indicates that the storage offset is used, the offset index address of the corresponding instruction is used as the real base address of the instruction, and when the storage offset usage flag indicates that the storage offset is not used, the corresponding data cache index address is used as the real base address of the instruction. Step S3: The calculation module obtains operands to execute each calculation task based on the real base address of each instruction in each calculation task generated by the base address dynamic generation module.

8. The method according to claim 7, characterized in that, In step S2, the configuration base address dynamic generation module generates the actual base address of each instruction in each computation task according to the following steps: The storage offset register reads from the configuration information cache module and stores the storage offset corresponding to each instruction in each computation task; The storage offset uses a flag register to read and store the storage offset flag corresponding to each instruction in each computation task from the configuration information cache module; The base address calculator, based on the data cache index address stored in its own memory for each computation task, adds the storage offset corresponding to each instruction in the computation task stored in the storage offset register to the data cache index address of that computation task to obtain the offset index address of each instruction in each computation task; wherein, both the data cache index address and the offset index address include multiple address indices, each address index being used to locate the storage address; The first multiplexer selects the memory offset usage flag corresponding to each instruction in each computation task from the memory offset usage flag register; The second multiplexer determines the actual base address of each instruction in each computation task based on the storage offset usage flag corresponding to each instruction in each computation task selected by the first multiplexer. Specifically, when the storage offset usage flag indicates that a storage offset is used, the offset index address of the instruction is used as the actual base address of the instruction; when the storage offset usage flag indicates that a storage offset is not used, the data cache index address corresponding to the instruction is used as the actual base address of the instruction.

9. A computer-readable storage medium, characterized in that, It stores a computer program that can be executed by a processor to implement the steps of the method of any one of claims 7-8.

10. An electronic device, characterized in that, include: One or more processors as described in any one of claims 1-6, and a memory.

Images