Efficiency optimization method and system for core particle cooperative processing

Abstract

The invention provides a core particle cooperative processing efficiency optimization method and system, and the method comprises the steps: obtaining the current operation information of each core particle of a chip, a target processing task, and a working region where each core particle is located, and recognizing the core particle state of each core particle and the current core particle processing information; based on the target processing task of the chip, identifying a current processing flow of the chip and task distribution information of each working area, and identifying core particle function evaluation information of each core particle of each working area through a core particle state evaluation strategy; and querying and based on the task criticality and the task type corresponding to the target processing task and the core particle function evaluation information of each core particle, adapting each current target core particle of each working area through a core particle adaptation strategy, so as to generate a cooperative working task of each working area, and aiming at each working area, generating a cooperative working task of each working area according to the task criticality and the task type corresponding to the target processing task and the core particle function evaluation information of each core particle. And generating a cooperative task scheme of each current target core particle. By adopting the scheme, the core particle cooperative processing effect of different tasks can be improved.

Description

Technical Field

[0001] This invention relates to the field of chip integration and collaborative interaction technology, and in particular to an efficiency optimization method and system for chip collaborative processing. Background Technology

[0002] Multi-chiplet integration technology refers to the technology of integrating modular chiplets into a multi-chiplet integrated system using advanced packaging technology. When multiple chiplets are operating, they often need to work collaboratively to effectively improve the processing efficiency and accuracy of complex tasks. However, since the collaborative control between multiple chiplets requires not only controlling the functions of each chiplet but also real-time monitoring of the operating status of different chiplets to ensure efficient task processing, improving the collaborative task processing efficiency of multiple chiplets is a current research focus.

[0003] Traditional multi-chip collaborative processing involves issuing collaborative tasks to the working areas of each chip to control collaborative processing between these areas. However, in multi-chip integrated chips, each working area contains multiple chips. The above method is too one-sided and cannot maximize the collaborative performance between multiple chips. Furthermore, different tasks require different amounts of performance resources, resulting in poor collaborative processing performance for different tasks. Summary of the Invention

[0004] The main objective of this invention is to provide an efficiency optimization method and system for chip-to-chip co-processing, which aims to solve the problem that in the prior art, since each working area of ​​a multi-chip integrated chip has multiple chips, the above methods take too one-sided a perspective and cannot bring out the highest performance of the co-processing between multiple chips. Furthermore, different tasks have different supply of performance resources, resulting in poor chip-to-chip co-processing effect for different tasks.

[0005] To achieve the above objectives, the present invention provides an efficiency optimization method for co-processing of core and particle components, the method comprising:

[0006] The current operating information of each chip, the target processing task of the chip, and the working area of ​​each chip are obtained. Based on the current operating information of each chip, the chip state and the current chip processing information of each chip are identified.

[0007] Based on the target processing task of the chip, the current processing flow of the chip and the task allocation information of the chip to each working area are identified. Based on the chip state of each chip and the current chip processing information of each chip, the chip function evaluation information of each chip in each working area is identified through the chip state evaluation strategy.

[0008] The task criticality and task type corresponding to the target processing task are queried. Based on the task criticality, task type, and core function evaluation information of each core in each work area, the current target core in each work area is adapted through a core adaptation strategy.

[0009] Based on the chip's current processing flow, the chip's task allocation information for each working area, and each current target chip in each working area, a collaborative work task for each working area is generated. Furthermore, for each working area, based on the current chip processing information of each current target chip in the working area and the collaborative work task of each current target chip, a collaborative task scheme for each current target chip is generated.

[0010] Optionally, the step of identifying the current processing flow of the chip and the task allocation information of the chip to each working area based on the target processing task of the chip includes:

[0011] Based on the target processing task of the chip, the processing flow corresponding to the target processing task and the task requirement information of the target processing task are queried in the task database, and the processing flow corresponding to the target processing task is used as the current processing flow of the chip.

[0012] Based on the task requirement information of the target processing task, identify the requirement information of the target processing task for each processing function, as well as the process nodes corresponding to each processing function, and obtain the functional application scope of each work area.

[0013] Based on the target processing task's requirements for each processing function and the functional application scope of each work area, the target work area corresponding to each processing function is identified, and the processing functions corresponding to each work area and the process nodes of each processing function corresponding to each work area are used as the task allocation information for each work area.

[0014] Optionally, the step of identifying the core function evaluation information of each core in each working area based on the core state of each core and the current core processing information of each core, through a core state evaluation strategy, includes:

[0015] For each core, based on the core state of the core, the core state type of the core is identified, and based on the current core processing information of the core, the current occupancy level of each core function of the core and the current task processing progress of the core are identified.

[0016] Based on the state type of the core particle, the state threshold evaluation strategy corresponding to the core particle is screened in the state evaluation database. Based on the current occupancy level of each core particle function and the current task processing progress of the core particle, the current performance evaluation value of each core particle function and the current task timeliness evaluation value of the core particle are identified through the state threshold evaluation strategy corresponding to the core particle.

[0017] The current performance evaluation value of each core function and the current task timeliness evaluation value of the core are used as the core function evaluation information of the core.

[0018] Optionally, based on the task criticality corresponding to the target processing task, the task type corresponding to the target processing task, and the core function evaluation information of each core in each work area, the core adaptation strategy is used to adapt each current target core in each work area, including:

[0019] Based on the task type corresponding to the target processing task, identify the task level corresponding to the target processing task, and based on the task level, query the core function evaluation range of each working area adapted to the target processing task in the task adaptation database.

[0020] Based on the core particle function evaluation range of each working region and the core particle function evaluation information of each core particle in each working region, the current initial target core particle adapted to each working region is selected.

[0021] Based on the core function evaluation information of the current initial target core adapted to each of the work areas, and the task criticality corresponding to the target processing task, each current target core in each of the work areas is selected through a criticality-first screening strategy.

[0022] Optionally, the step of generating collaborative work tasks for each work area based on the current processing flow of the chip, the task allocation information of the chip to each work area, and each current target chip in each work area includes:

[0023] For each working area, based on the processing function corresponding to the working area and the current performance evaluation value of each function of each current target core, a target processing core that matches each processing function is selected from the current target cores in the working area through a performance priority strategy.

[0024] Each target processing core adapted to a processing function is used as a collaborative task in the work area.

[0025] Optionally, for each working area, generating a collaborative task scheme for each current target core based on the current core processing information of each current target core in the working area and the collaborative work tasks of each current target core includes:

[0026] Based on the current chip processing information of each target processing chip in the working area, the task start time of each target processing chip is identified;

[0027] Based on the task start time of each target processing chip, the processing function corresponding to each target processing chip, and the process node corresponding to each processing function, the node start time of each process node in the current processing flow of the chip and the collaborative interaction task of each target processing chip are identified.

[0028] The node start time of each process node in the current processing flow of the chip, and the collaborative interaction tasks of each target processing chip, are used as the collaborative task scheme of each target processing chip.

[0029] Furthermore, to achieve the above objectives, the present invention also provides an efficiency optimization system for chip-particle co-processing, the efficiency optimization system for chip-particle co-processing comprising:

[0030] The acquisition module is used to acquire the current operating information of each chip in the chip, the target processing task of the chip, and the working area of ​​each chip in the chip, and based on the current operating information of each chip, to identify the chip state of each chip and the current chip processing information of each chip.

[0031] The identification module is used to identify the current processing flow of the chip and the task allocation information of the chip to each working area based on the target processing task of the chip, and to identify the chip function evaluation information of each chip in each working area based on the chip state and the current chip processing information of each chip through the chip state evaluation strategy.

[0032] The adaptation module is used to query the task criticality and task type corresponding to the target processing task, and based on the task criticality, task type, and core function evaluation information of each core in each work area, adapt each current target core in each work area through a core adaptation strategy.

[0033] The generation module is used to generate collaborative work tasks for each work area based on the current processing flow of the chip, the task allocation information of the chip to each work area, and each current target chip in each work area, and to generate collaborative task schemes for each current target chip for each work area based on the current chip processing information of each current target chip in the work area and the collaborative work tasks of each current target chip.

[0034] Optionally, the identification module is specifically used for:

[0035] Based on the target processing task of the chip, the processing flow corresponding to the target processing task and the task requirement information of the target processing task are queried in the task database, and the processing flow corresponding to the target processing task is used as the current processing flow of the chip.

[0036] Based on the task requirement information of the target processing task, identify the requirement information of the target processing task for each processing function, as well as the process nodes corresponding to each processing function, and obtain the functional application scope of each work area.

[0037] Based on the target processing task's requirements for each processing function and the functional application scope of each work area, the target work area corresponding to each processing function is identified, and the processing functions corresponding to each work area and the process nodes of each processing function corresponding to each work area are used as the task allocation information for each work area.

[0038] Optionally, the identification module is specifically used for:

[0039] For each core, based on the core state of the core, the core state type of the core is identified, and based on the current core processing information of the core, the current occupancy level of each core function of the core and the current task processing progress of the core are identified.

[0040] Based on the state type of the core particle, the state threshold evaluation strategy corresponding to the core particle is screened in the state evaluation database. Based on the current occupancy level of each core particle function and the current task processing progress of the core particle, the current performance evaluation value of each core particle function and the current task timeliness evaluation value of the core particle are identified through the state threshold evaluation strategy corresponding to the core particle.

[0041] The current performance evaluation value of each core function and the current task timeliness evaluation value of the core are used as the core function evaluation information of the core.

[0042] Optionally, the adapter module is specifically used for:

[0043] Based on the task type corresponding to the target processing task, identify the task level corresponding to the target processing task, and based on the task level, query the core function evaluation range of each working area adapted to the target processing task in the task adaptation database.

[0044] Based on the core particle function evaluation range of each working region and the core particle function evaluation information of each core particle in each working region, the current initial target core particle adapted to each working region is selected.

[0045] Based on the core function evaluation information of the current initial target core adapted to each of the work areas, and the task criticality corresponding to the target processing task, each current target core in each of the work areas is selected through a criticality-first screening strategy.

[0046] Optionally, the generation module is specifically used for:

[0047] For each working area, based on the processing function corresponding to the working area and the current performance evaluation value of each function of each current target core, a target processing core that matches each processing function is selected from the current target cores in the working area through a performance priority strategy.

[0048] Each target processing core adapted to a processing function is used as a collaborative task in the work area.

[0049] Optionally, the generation module is specifically used for:

[0050] Based on the current chip processing information of each target processing chip in the working area, the task start time of each target processing chip is identified;

[0051] Based on the task start time of each target processing chip, the processing function corresponding to each target processing chip, and the process node corresponding to each processing function, the node start time of each process node in the current processing flow of the chip and the collaborative interaction task of each target processing chip are identified.

[0052] The node start time of each process node in the current processing flow of the chip, and the collaborative interaction tasks of each target processing chip, are used as the collaborative task scheme of each target processing chip.

[0053] Thirdly, this application provides a computer device. The computer device includes a memory and a processor, the memory storing a computer program, and the processor executing the computer program to implement the steps of the method described in any one of the first aspects.

[0054] Fourthly, this application provides a computer-readable storage medium having a computer program stored thereon that, when executed by a processor, implements the steps of the method described in any one of the first aspects.

[0055] Fifthly, this application provides a computer program product. The computer program product includes a computer program that, when executed by a processor, implements the steps of the method described in any one of the first aspects.

[0056] This invention provides an efficiency optimization method and system for chip-to-chip co-processing. The method includes: acquiring the current operating information of each chip, the target processing task of the chip, and the working area of ​​each chip; identifying the chip state and current chip processing information of each chip based on the current operating information of each chip; identifying the current processing flow of the chip and the task allocation information of the chip to each working area based on the target processing task of the chip; and identifying the chip function evaluation information of each chip in each working area based on the chip state and the current chip processing information of each chip through a chip state evaluation strategy; and querying the task criticality corresponding to the target processing task. The system utilizes the target processing task and the task type corresponding to the target processing task. Based on the task criticality, the task type, and the chip function evaluation information of each chip in each work area, a chip adaptation strategy is used to adapt each current target chip in each work area. Based on the chip's current processing flow, the chip's task allocation information for each work area, and each current target chip in each work area, a collaborative work task is generated for each work area. For each work area, a collaborative task scheme for each current target chip is generated based on the current chip processing information of each current target chip in the work area and the collaborative work task of each current target chip. This solution evaluates and analyzes the current state and processing information of each chip to identify its functional evaluation information. Then, it analyzes the target processing tasks of the chip to identify task criticality and type, adapting the chip to the current target chips in each work area. Compared to traditional solutions, this solution can adapt different chips to different target processing tasks, ensuring that the task requirements are met while improving the resource utilization of each chip and increasing the accuracy of resource adaptation for different target processing tasks. After adapting the current target chips for each target processing task, this solution generates collaborative work tasks and collaborative work schemes for each work area, based on the current processing flow of each current target chip. This effectively improves task processing efficiency and resource utilization in each work area, thereby comprehensively improving the collaborative processing effect of chips for different tasks. Attached Figure Description

[0057] To more clearly illustrate the solutions in this application, the accompanying drawings used in the description of the embodiments of this application will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0058] Figure 1 This is a flowchart of the efficiency optimization method for chip-particle co-processing provided in an embodiment of the present invention;

[0059] Figure 2 This is a schematic diagram of the efficiency optimization system for chip-particle co-processing provided in an embodiment of the present invention;

[0060] Figure 3 An internal structural diagram of a computer device provided in an embodiment of the present invention. Detailed Implementation

[0061] The chip-particle coprocessing efficiency optimization method provided in this invention is applied to a chip-particle coprocessing efficiency optimization system. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this application. The terms "comprising" and "having," and any variations thereof, in the specification, claims, and accompanying drawings of this application are intended to cover non-exclusive inclusion. The terms "first," "second," etc., in the specification, claims, or accompanying drawings of this application are used to distinguish different objects, not to describe a particular order.

[0062] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0063] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings.

[0064] The chip-level collaborative processing efficiency optimization method provided in this application embodiment can be applied to chip-level collaborative processing efficiency optimization application environments. This method can be applied to terminals, servers, or systems including both terminals and servers, and is implemented through interaction between the terminal and server. The terminal can be, but is not limited to, various personal computers, laptops, etc. The terminal evaluates and analyzes the current state and processing information of each chip to identify the chip's functional evaluation information. Then, it performs task analysis on the chip's target processing task to identify the task criticality and task type, adapting it to each current target chip in each working area. Compared to traditional technical solutions, this solution can adapt different chips to different target processing tasks, ensuring that the task requirements of the target processing task are met while improving the resource utilization of each chip and enhancing the accuracy of resource adaptation for different target processing tasks. Then, after adapting to the current target particles of each target processing task, this solution generates collaborative work tasks for each work area and collaborative work schemes for each current target particle in each work area, based on the current processing flow of each current target particle. This effectively improves the task processing efficiency and resource utilization in each work area, thereby comprehensively improving the collaborative processing effect of particles for different tasks.

[0065] In one embodiment, such as Figure 1 As shown, an efficiency optimization method for chip-particle co-processing is provided. Taking the application of this method to a terminal as an example, the method includes the following steps:

[0066] Step S101: Obtain the current operating information of each chip, the target processing task of the chip, and the working area of ​​each chip. Based on the current operating information of each chip, identify the chip status of each chip and the current chip processing information of each chip.

[0067] In this embodiment, the terminal obtains the current operating information of each chip, the target processing task of the chip, and the working area of ​​each chip through a preset chip detection program. The different working areas of each chip result in different chip functions. For example, a chip may include functions such as data processing, data analysis, data computation, data transmission, data aggregation, and data distribution. Working area A, however, only handles data integration computation; therefore, the chips in working area A only have data integration computation-related data computation, data processing, and data aggregation functions enabled. Then, based on the current operating information of each chip, the terminal identifies the chip status and current chip processing information of each chip.

[0068] Step S102: Based on the target processing task of the chip, identify the current processing flow of the chip and the task allocation information of the chip to each working area. Based on the chip state of each chip and the current chip processing information of each chip, identify the chip function evaluation information of each chip in each working area through the chip state evaluation strategy.

[0069] In this embodiment, the terminal identifies the chip's current processing flow and task allocation information for each working area based on the chip's target processing task. Based on the chip's chip state and current processing information, a chip state evaluation strategy is used to identify the chip function evaluation information for each chip in each working area. The task allocation information for each working area includes the processing functions and process nodes corresponding to each function. The chip state of each chip characterizes whether the chip can operate normally or its operational level. This operational state includes, for example, normal operation, inoperable operation, faulty operation (i.e., some functions are unavailable), and inefficient operation (i.e., low efficiency and long runtime, often caused by chip updates, chip overload, or chip malfunction). The chip state evaluation strategy includes multiple state threshold evaluation strategies to assess the chip's functionality and its ability to handle new tasks in a timely manner. Different chip state types correspond to different state threshold evaluation strategies. The specific evaluation process will be described in detail later.

[0070] Step S103: Query the task criticality and task type corresponding to the target processing task. Based on the task criticality, task type, and core function evaluation information of each core in each work area, adapt each current target core in each work area through a core adaptation strategy.

[0071] In this embodiment, the terminal queries the task criticality and task type corresponding to the target processing task. Based on the task criticality, task type, and core function evaluation information of each core in each work area, the terminal adapts each current target core in each work area using a core adaptation strategy. The currently adapted target cores are those with the highest core function evaluation information among the cores that can be adapted to based on the task criticality and task type of the target processing task.

[0072] Step S104: Based on the chip's current processing flow, the chip's task allocation information for each working area, and each current target chip in each working area, generate a collaborative work task for each working area. For each working area, based on the current chip processing information of each current target chip in the working area and the collaborative work task of each current target chip, generate a collaborative task scheme for each current target chip.

[0073] In this embodiment, the terminal generates collaborative work tasks for each work area based on the chip's current processing flow, the chip's task allocation information for each work area, and the current target chips in each work area. Furthermore, for each work area, based on the current chip processing information of each current target chip and the collaborative work tasks of each current target chip, a collaborative task scheme for each current target chip is generated. The specific generation process will be described in detail later. The collaborative work tasks for each current target chip are the running tasks adapted to each target chip based on the task allocation information of that work area. The collaborative task scheme for each current target chip is a task execution sequence obtained by sorting the running tasks of each target chip according to the start time of the node that can execute the running task for each current target chip.

[0074] Based on the above scheme, by evaluating and analyzing the current state and processing information of each chip, the functional evaluation information of each chip is identified. Then, task analysis is performed on the target processing tasks of the chip to identify the task criticality and task type, so as to adapt to each current target chip in each working area. Compared with traditional technical solutions, this scheme can adapt different chips to different target processing tasks, thereby ensuring that the task requirements of the target processing task can be met, while improving the resource utilization of each chip in the chip and improving the accuracy of resource adaptation for different target processing tasks. After adapting to the current target chips of each target processing task, this scheme generates collaborative work tasks for each working area and collaborative work schemes for each current target chip in each working area, based on the current processing flow of each current target chip. This effectively improves the task processing efficiency and resource utilization in each working area, thereby comprehensively improving the collaborative processing effect of chips for different tasks.

[0075] Optionally, based on the target processing task of the chip, the current processing flow of the chip and the task allocation information of the chip to each working area are identified, including: based on the target processing task of the chip, querying the processing flow corresponding to the target processing task and the task requirement information of the target processing task in the task database, and taking the processing flow corresponding to the target processing task as the current processing flow of the chip; based on the task requirement information of the target processing task, identifying the requirement information of the target processing task for each processing function and the process nodes corresponding to each processing function, and obtaining the functional application scope of each working area; based on the requirement information of the target processing task for each processing function and the functional application scope of each working area, identifying the target working area corresponding to each processing function, and taking the processing functions corresponding to each working area and the process nodes of each processing function corresponding to each working area as the task allocation information of each working area.

[0076] In this embodiment, the terminal, based on the target processing task of the chip, queries the task database for the processing flow corresponding to the target processing task and the task requirement information of the target processing task, and uses the processing flow corresponding to the target processing task as the current processing flow of the chip. The task requirement information refers to the functional requirements that the chip needs to process for the target processing task.

[0077] Then, based on the task requirement information of the target processing task, the terminal identifies the requirement information of the target processing task for each processing function, as well as the process nodes corresponding to each processing function, and obtains the functional application scope of each work area. Among them, the process nodes corresponding to each processing function are the nodes in the processing flow that need to apply that processing function.

[0078] Next, based on the target processing task's requirements for each processing function and the functional application scope of each work area, the terminal identifies the target work area corresponding to each processing function and uses the processing functions and process nodes corresponding to each processing function in each work area as the task allocation information for each work area. Specifically, the terminal presets the core functional range of each work area. The terminal filters the target work areas corresponding to each processing function through range adaptation. Then, the terminal uses the adapted processing functions and corresponding process nodes for each work area as the task allocation information for each work area.

[0079] Based on the above scheme, by breaking down the target processing tasks into process steps and analyzing the processing functions, the task allocation information suitable for each work area can be identified, thereby improving the accuracy of task allocation identification for each work area.

[0080] Optionally, based on the core state and current core processing information of each core, a core function evaluation information for each core in each work area is identified through a core state evaluation strategy. This includes: for each core, identifying the core state type based on its core state, and identifying the current occupancy level and current task processing progress of each core function based on its current core processing information; based on the core state type, selecting the corresponding state threshold evaluation strategy from the state evaluation database, and identifying the current performance evaluation value and current task timeliness evaluation value of each core function based on the current occupancy level and current task processing progress of each core function through the corresponding state threshold evaluation strategy; and using the current performance evaluation value and current task timeliness evaluation value of each core function as the core function evaluation information.

[0081] In this embodiment, for each core, the terminal identifies the core state type based on the core state and identifies the current occupancy level of each core function and the current task processing progress based on the current core processing information. Specifically, the occupancy level of the core functions required by the current task when the core is executing the current task can be reflected in the detection results obtained by detecting each core using a core detection program.

[0082] Then, based on the core's current state type, the terminal filters the corresponding state threshold evaluation strategy from the state evaluation database. Based on the current occupancy level of each core function and the current task processing progress, the terminal identifies the current performance evaluation value and the current task timeliness evaluation value of each core function using the corresponding state threshold evaluation strategy. Each state threshold evaluation strategy includes the correspondence between the current occupancy range of each core function and its current performance evaluation value, as well as the correspondence between the current task processing progress range and its current task timeliness evaluation value. The terminal uses these correspondences to identify the current performance evaluation value and the current task timeliness evaluation value of each core function.

[0083] Finally, the terminal uses the current performance evaluation value of each core function and the current task timeliness evaluation value of the core as the core function evaluation information.

[0084] Based on the above scheme, by evaluating the state type of the combined core particles, the functions of each core particle and the timeliness of the current task can be evaluated, thereby improving the comprehensiveness of the evaluation of core particle functions.

[0085] Optionally, based on the task criticality corresponding to the target processing task, the task type corresponding to the target processing task, and the core function evaluation information of each core in each work area, a core adaptation strategy is used to adapt each current target core in each work area. This includes: identifying the task level corresponding to the target processing task based on the task type corresponding to the target processing task, and querying the core function evaluation range of each work area adapted to the target processing task in the task adaptation database based on the task level; filtering the current initial target core adapted to each work area based on the core function evaluation range of each work area and the core function evaluation information of each core in each work area; and filtering each current target core in each work area based on the core function evaluation information of the current initial target core adapted to each work area and the task criticality corresponding to the target processing task, using a criticality-first filtering strategy.

[0086] In this embodiment, the terminal identifies the task level corresponding to the target processing task based on the task type, and then queries the task adaptation database to find the core function evaluation range of each working area adapted to the target processing task. Each task level corresponds to a task type range, and the terminal identifies the task level corresponding to the target processing task through range adaptation. Different task levels have limited adaptable psychological function evaluation ranges; the higher the task level, the larger the adaptable core function evaluation range, and vice versa. Task levels can be divided into A-level tasks, B-level tasks, C-level tasks, D-level tasks, etc., in order from most important to least important.

[0087] The terminal filters the current initial target particles adapted to each working area based on the particle function evaluation range of each working area and the particle function evaluation information of each particle in each working area. Then, based on the particle function evaluation information of the current initial target particles adapted to each working area and the task criticality corresponding to the target processing task, the terminal filters each current target particle in each working area using a criticality-first filtering strategy. The criticality-first filtering strategy involves the terminal identifying the sub-particle function evaluation range adapted to the particle function evaluation range corresponding to the target processing task based on the task criticality. Each task criticality corresponds to a sub-particle function evaluation range within the particle function evaluation range; the higher the task criticality, the higher the sub-particle function evaluation range that the target processing task can adapt to, and vice versa. Finally, the terminal filters the particles belonging to the sub-particle function evaluation range corresponding to the task criticality from the particle function evaluation information of each particle in the working area, and uses these as the current target particles for that working area.

[0088] Based on the above scheme, by classifying the target processing tasks and then dividing them by criticality, the current target core is adapted to each working area, thereby improving the accuracy of core adaptation for different target processing tasks.

[0089] Optionally, based on the chip's current processing flow, the chip's task allocation information for each working area, and each current target chip in each working area, a collaborative work task for each working area is generated. This includes: for each working area, based on the processing function corresponding to the working area and the current performance evaluation value of each chip function of each current target chip, selecting target processing chips that are compatible with each processing function from among the current target chips in the working area through a performance priority strategy; and using the target processing chips that are compatible with each processing function as the collaborative work task for the working area.

[0090] In this embodiment, for each working area, the terminal, based on the processing function corresponding to the working area and the current performance evaluation value of each function of each current target core, selects the target processing core that matches each processing function from among the current target cores in the working area through a performance priority strategy. Specifically, the terminal presets the correspondence between each processing function and core function, where one processing function can correspond to one or more core functions. Based on the current performance evaluation value of each function of each current target core, the terminal selects the current target core with the highest current performance evaluation value among the multiple core functions corresponding to each processing function in each current target core, and uses it as the target processing core corresponding to that processing function.

[0091] Finally, the terminal will adapt each processing function to the target processing core as a collaborative task in the working area.

[0092] Based on the above scheme, by adapting the target processing chip corresponding to each processing function, the processing efficiency and quality of each processing function are improved. While ensuring that the requirements of the processing function are met, the processing efficiency and quality of the processing function are improved.

[0093] Optionally, for each working area, based on the current chip processing information of each current target chip in the working area and the collaborative work tasks of each current target chip, a collaborative task scheme for each current target chip is generated, including: identifying the task start time of each target processing chip based on the current chip processing information of each target processing chip in the working area; identifying the node start time of each process node in the current processing flow of the chip and the collaborative interaction tasks of each target processing chip based on the task start time of each target processing chip, the processing function corresponding to each target processing chip, and the process node corresponding to each processing function; and using the node start time of each process node in the current processing flow of the chip and the collaborative interaction tasks of each target processing chip as the collaborative task scheme for each target processing chip.

[0094] In this embodiment, the terminal identifies the task start time of each target processing chip based on the current chip processing information of each target processing chip in the working area. Then, based on the task start time of each target processing chip, the processing function corresponding to each target processing chip, and the process node corresponding to each processing function, the terminal identifies the node start time of each process node in the current processing flow of the chip, as well as the collaborative interaction task of each target processing chip. The collaborative interaction task of the target processing chip is the interaction flow of each processing function within the task flow of that target processing task.

[0095] Finally, the terminal uses the node start time of each process node in the current processing flow of the chip, as well as the collaborative interaction tasks of each target processing chip, as the collaborative task scheme of each target processing chip.

[0096] Based on the above scheme, by transforming the task flow into collaborative interaction tasks of target processing particles in different work areas, it is possible not only to effectively improve the accuracy of operation control of each particle, but also to maximize the task completion effect of each work area.

[0097] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0098] Based on the same inventive concept, this application also provides a chip-particle coprocessing efficiency optimization system for implementing the above-described chip-particle coprocessing efficiency optimization method. The solution provided by this system is similar to the implementation described in the above method; therefore, the specific limitations of one or more chip-particle coprocessing efficiency optimization system embodiments provided below can be found in the limitations of the chip-particle coprocessing efficiency optimization method described above, and will not be repeated here.

[0099] Further reference Figure 2 As a response to the above Figure 1 The present application provides an embodiment of a chip-particle co-processing efficiency optimization system 200, which includes an acquisition module 210, an identification module 220, an adaptation module 230, and a generation module 240, wherein:

[0100] The acquisition module 210 is used to acquire the current running information of each chip of the chip, the target processing task of the chip, and the working area of ​​each chip of the chip, and based on the current running information of each chip, to identify the chip state of each chip and the current chip processing information of each chip.

[0101] The identification module 220 is used to identify the current processing flow of the chip and the task allocation information of the chip to each working area based on the target processing task of the chip, and to identify the chip function evaluation information of each chip in each working area based on the chip state and the current chip processing information of each chip through a chip state evaluation strategy.

[0102] The adaptation module 230 is used to query the task criticality and the task type corresponding to the target processing task, and based on the task criticality, the task type, and the core function evaluation information of each core in each work area, adapt each current target core in each work area through a core adaptation strategy.

[0103] The generation module 240 is used to generate collaborative work tasks for each work area based on the current processing flow of the chip, the task allocation information of the chip to each work area, and each current target chip in each work area, and to generate collaborative task schemes for each current target chip for each work area based on the current chip processing information of each current target chip in the work area and the collaborative work tasks of each current target chip.

[0104] Optionally, the identification module 220 is specifically used for:

[0105] Based on the target processing task of the chip, the processing flow corresponding to the target processing task and the task requirement information of the target processing task are queried in the task database, and the processing flow corresponding to the target processing task is used as the current processing flow of the chip.

[0106] Based on the task requirement information of the target processing task, identify the requirement information of the target processing task for each processing function, as well as the process nodes corresponding to each processing function, and obtain the functional application scope of each work area.

[0107] Based on the target processing task's requirements for each processing function and the functional application scope of each work area, the target work area corresponding to each processing function is identified, and the processing functions corresponding to each work area and the process nodes of each processing function corresponding to each work area are used as the task allocation information for each work area.

[0108] Optionally, the identification module 220 is specifically used for:

[0109] For each core, based on the core state of the core, the core state type of the core is identified, and based on the current core processing information of the core, the current occupancy level of each core function of the core and the current task processing progress of the core are identified.

[0110] Based on the state type of the core particle, the state threshold evaluation strategy corresponding to the core particle is screened in the state evaluation database. Based on the current occupancy level of each core particle function and the current task processing progress of the core particle, the current performance evaluation value of each core particle function and the current task timeliness evaluation value of the core particle are identified through the state threshold evaluation strategy corresponding to the core particle.

[0111] The current performance evaluation value of each core function and the current task timeliness evaluation value of the core are used as the core function evaluation information of the core.

[0112] Optionally, the adapter module 230 is specifically used for:

[0113] Based on the task type corresponding to the target processing task, identify the task level corresponding to the target processing task, and based on the task level, query the core function evaluation range of each working area adapted to the target processing task in the task adaptation database.

[0114] Based on the core particle function evaluation range of each working region and the core particle function evaluation information of each core particle in each working region, the current initial target core particle adapted to each working region is selected.

[0115] Based on the core function evaluation information of the current initial target core adapted to each of the work areas, and the task criticality corresponding to the target processing task, each current target core in each of the work areas is selected through a criticality-first screening strategy.

[0116] Optionally, the generation module 240 is specifically used for:

[0117] For each working area, based on the processing function corresponding to the working area and the current performance evaluation value of each function of each current target core, a target processing core that matches each processing function is selected from the current target cores in the working area through a performance priority strategy.

[0118] Each target processing core adapted to a processing function is used as a collaborative task in the work area.

[0119] Optionally, the generation module 240 is specifically used for:

[0120] Based on the current chip processing information of each target processing chip in the working area, the task start time of each target processing chip is identified;

[0121] Based on the task start time of each target processing chip, the processing function corresponding to each target processing chip, and the process node corresponding to each processing function, the node start time of each process node in the current processing flow of the chip and the collaborative interaction task of each target processing chip are identified.

[0122] The node start time of each process node in the current processing flow of the chip, and the collaborative interaction tasks of each target processing chip, are used as the collaborative task scheme of each target processing chip.

[0123] Each module in the aforementioned chip-particle co-processing efficiency optimization system can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in a computer device, or stored in the computer device's memory as software, so that the processor can invoke and execute the corresponding operations of each module.

[0124] In one embodiment, a computer device is provided, which may be a terminal, and its internal structure diagram may be as follows: Figure 3As shown, the computer device includes a processor, memory, communication interface, display screen, and input system connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, mobile cellular networks, NFC (Near Field Communication), or other technologies. When the computer program is executed by the processor, it implements an efficiency optimization method for chip-to-chip co-processing. The display screen can be an LCD screen or an e-ink display screen. The input system can be a touch layer covering the display screen, buttons, a trackball, or a touchpad on the computer device's casing, or an external keyboard, touchpad, or mouse.

[0125] Those skilled in the art will understand that Figure 3 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0126] In one embodiment, a computer device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the method described in any one of the first aspects.

[0127] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the steps of the method described in any one of the first aspects.

[0128] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps of the method described in any one of the first aspects.

[0129] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties.

[0130] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments described above. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.

[0131] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0132] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A method for optimizing the efficiency of core-particle co-processing, characterized in that, The method includes: The current operating information of each chip, the target processing task of the chip, and the working area of ​​each chip are obtained. Based on the current operating information of each chip, the chip state and the current chip processing information of each chip are identified. Based on the target processing task of the chip, the current processing flow of the chip and the task allocation information of the chip to each working area are identified. Based on the chip state of each chip and the current chip processing information of each chip, the chip function evaluation information of each chip in each working area is identified through the chip state evaluation strategy. The task criticality and task type corresponding to the target processing task are queried. Based on the task criticality, task type, and core function evaluation information of each core in each work area, the current target core in each work area is adapted through a core adaptation strategy. Based on the chip's current processing flow, the chip's task allocation information for each working area, and each current target chip in each working area, a collaborative work task for each working area is generated. Furthermore, for each working area, based on the current chip processing information of each current target chip in the working area and the collaborative work task of each current target chip, a collaborative task scheme for each current target chip is generated.

2. The method according to claim 1, characterized in that, The target processing task based on the chip identifies the current processing flow of the chip and the task allocation information of the chip to each working area, including: Based on the target processing task of the chip, the processing flow corresponding to the target processing task and the task requirement information of the target processing task are queried in the task database, and the processing flow corresponding to the target processing task is used as the current processing flow of the chip. Based on the task requirement information of the target processing task, identify the requirement information of the target processing task for each processing function, as well as the process nodes corresponding to each processing function, and obtain the functional application scope of each work area. Based on the target processing task's requirements for each processing function and the functional application scope of each work area, the target work area corresponding to each processing function is identified, and the processing functions corresponding to each work area and the process nodes of each processing function corresponding to each work area are used as the task allocation information for each work area.

3. The method according to claim 1, characterized in that, Based on the core state of each core and the current core processing information of each core, the core state evaluation strategy identifies the core function evaluation information of each core in each working area, including: For each core, based on the core state of the core, the core state type of the core is identified, and based on the current core processing information of the core, the current occupancy level of each core function of the core and the current task processing progress of the core are identified. Based on the state type of the core particle, the state threshold evaluation strategy corresponding to the core particle is screened in the state evaluation database. Based on the current occupancy level of each core particle function and the current task processing progress of the core particle, the current performance evaluation value of each core particle function and the current task timeliness evaluation value of the core particle are identified through the state threshold evaluation strategy corresponding to the core particle. The current performance evaluation value of each core function and the current task timeliness evaluation value of the core are used as the core function evaluation information of the core.

4. The method according to claim 2, characterized in that, The process, based on the task criticality of the target processing task, the task type of the target processing task, and the core function evaluation information of each core in each work area, uses a core adaptation strategy to adapt each current target core in each work area, including: Based on the task type corresponding to the target processing task, identify the task level corresponding to the target processing task, and based on the task level, query the core function evaluation range of each working area adapted to the target processing task in the task adaptation database. Based on the core particle function evaluation range of each working region and the core particle function evaluation information of each core particle in each working region, the current initial target core particle adapted to each working region is selected. Based on the core function evaluation information of the current initial target core adapted to each of the work areas, and the task criticality corresponding to the target processing task, each current target core in each of the work areas is selected through a criticality-first screening strategy.

5. The method according to claim 2, characterized in that, The generation of collaborative work tasks for each work area based on the chip's current processing flow, the chip's task allocation information for each work area, and each current target chip in each work area includes: For each working area, based on the processing function corresponding to the working area and the current performance evaluation value of each function of each current target core, a target processing core that matches each processing function is selected from the current target cores in the working area through a performance priority strategy. Each target processing core adapted to a processing function is used as a collaborative task in the work area.

6. The method according to claim 5, characterized in that, For each working area, based on the current core processing information of each current target core in the working area and the collaborative working tasks of each current target core, a collaborative task scheme for each current target core is generated, including: Based on the current chip processing information of each target processing chip in the working area, the task start time of each target processing chip is identified; Based on the task start time of each target processing chip, the processing function corresponding to each target processing chip, and the process node corresponding to each processing function, the node start time of each process node in the current processing flow of the chip and the collaborative interaction task of each target processing chip are identified. The node start time of each process node in the current processing flow of the chip, and the collaborative interaction tasks of each target processing chip, are used as the collaborative task scheme of each target processing chip.

7. An efficiency optimization system for core-particle co-processing, characterized in that, The system includes: The acquisition module is used to acquire the current operating information of each chip in the chip, the target processing task of the chip, and the working area of ​​each chip in the chip, and based on the current operating information of each chip, to identify the chip state of each chip and the current chip processing information of each chip. The identification module is used to identify the current processing flow of the chip and the task allocation information of the chip to each working area based on the target processing task of the chip, and to identify the chip function evaluation information of each chip in each working area based on the chip state and the current chip processing information of each chip through the chip state evaluation strategy. The adaptation module is used to query the task criticality and task type corresponding to the target processing task, and based on the task criticality, task type, and core function evaluation information of each core in each work area, adapt each current target core in each work area through a core adaptation strategy. The generation module is used to generate collaborative work tasks for each work area based on the current processing flow of the chip, the task allocation information of the chip to each work area, and each current target chip in each work area, and to generate collaborative task schemes for each current target chip for each work area based on the current chip processing information of each current target chip in the work area and the collaborative work tasks of each current target chip.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 6.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 6.

10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 6.

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