Memory stress testing method and electronic device

Abstract

The application discloses a memory stress test method and electronic equipment, and relates to the technical field of computers, and comprises the following steps: in the case that the error times of a to-be-tested memory are higher than the corresponding error threshold, obtaining stress test information of the to-be-tested memory, determining a first target memory and a second target memory from the to-be-tested memory according to the stress test information of the to-be-tested memory, testing the first target memory by using a preset deep test strategy, testing the second target memory by using a preset lightweight test strategy, determining an error memory and a memory position corresponding to the error memory according to a test result; determining a corresponding error type according to the memory position corresponding to the error memory, determining a processing strategy corresponding to the error memory according to the corresponding error type, and processing the error memory based on the processing strategy corresponding to the error memory, so that the problem of low memory stress test efficiency is solved, and the performance and reliability of the memory stress test are significantly improved.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and more particularly to a memory stress testing method and electronic device. Background Technology

[0002] In cloud computing and big data application scenarios, with the exponential growth of server load, the stability of memory modules has become a key bottleneck affecting the reliability of data centers. The current industry-wide passive recording mechanism of operating system logs (Correctable Error / Uncorrectable Error) has the following technical defects: (1) Delayed fault response: CE (Correctable Error) / UCE (Uncorrectable Error) errors need to accumulate until they trigger the ECC (Error-Correcting Code memory) correction limit or cause a crash before they are processed, and the mean time to repair (MTTR) exceeds the requirements of business continuity; (2) Discontinuity in detection cycle: The memory initialization stage (POST-Bootloader transition period) during system restart lacks an error information inheritance mechanism; (3) Bottleneck in operation and maintenance efficiency: The fault diagnosis mode that relies on manual inspection generates a false negative rate of up to 37% in ultra-large-scale clusters.

[0003] The relevant technology uses a static stress test triggering mechanism for stress testing: it uses the BIOS (Basic Input Output System) preset options to force full memory stress testing. Its test triggering is decoupled from the actual health status of the memory. This solution has the problem of mismatch between test conditions and fault characteristics. For example, redundant testing is performed on memory modules without CE records, and the test coverage is inversely proportional to the memory capacity.

[0004] However, the relevant technologies have the following drawbacks: (1) The boot time is extended. The memory stress test time increases with the increase of memory capacity. If the stress test is enabled by default, the boot time will be extended due to memory detection every time the machine is turned on, which will affect the operation and maintenance efficiency; (2) The test efficiency is low. If manual judgment and manual switching of the stress test option are adopted, not only is the operation cumbersome, but also the response delay and resource waste will be caused by relying on manual intervention. Summary of the Invention

[0005] This invention provides a memory stress testing method and electronic device, which significantly improves the performance and reliability of memory stress testing by addressing problems such as mismatch between test conditions and fault characteristics, low test coverage, and low test efficiency in at least related technologies.

[0006] This invention provides a memory stress testing method, comprising the following steps:

[0007] Determine whether the number of errors in the memory under test exceeds the corresponding error threshold;

[0008] If the number of errors in the memory under test is higher than the corresponding error threshold, then the stress test information of the memory under test is obtained, and the first target memory and the second target memory are determined from the memory under test based on the stress test information of the memory under test;

[0009] A first test result is obtained by testing the first target memory using a preset deep testing strategy, and a second test result is obtained by testing the second target memory using a preset lightweight testing strategy. The error memory and the memory location corresponding to the error memory are determined based on the first test result and the second test result.

[0010] The error type corresponding to the reported memory is determined based on the memory location of the reported memory, and the processing strategy corresponding to the reported memory is determined based on the error type of the reported memory. The reported memory is then processed based on the processing strategy corresponding to the reported memory.

[0011] The present invention also provides a memory stress testing device, comprising:

[0012] The judgment module is used to determine whether the number of errors in the memory under test is higher than the corresponding error threshold;

[0013] The acquisition module is used to acquire the stress test information of the memory under test when the number of errors of the memory under test is higher than the corresponding error threshold, and to determine the first target memory and the second target memory from the memory under test based on the stress test information of the memory under test;

[0014] The testing module is used to test the first target memory using a preset deep testing strategy to obtain a first test result, and to test the second target memory using a preset lightweight testing strategy to obtain a second test result, and to determine the erroneous memory and the memory location corresponding to the erroneous memory based on the first test result and the second test result;

[0015] The processing module is used to determine the error type corresponding to the error memory based on the memory location corresponding to the error memory, determine the processing strategy corresponding to the error memory based on the error type corresponding to the error memory, and process the error memory based on the processing strategy corresponding to the error memory.

[0016] The present invention also provides an electronic device, including: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the memory stress testing method as described in the above embodiments.

[0017] The present invention also provides a computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps of any of the above-described memory stress tests.

[0018] The present invention also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of any of the above-described memory stress tests.

[0019] This invention determines whether the number of errors in the memory under test exceeds a corresponding error threshold. If the number of errors exceeds the threshold, stress testing information for the memory under test is obtained. Based on this information, a first target memory and a second target memory are identified. A preset deep testing strategy is used to test the first target memory to obtain a first test result, and a preset lightweight testing strategy is used to test the second target memory to obtain a second test result. Based on the first and second test results, faulty memory and its corresponding memory location are determined. The error type of the faulty memory is determined based on its location, and a processing strategy is determined based on its error type. The faulty memory is then processed according to the processing strategy. This solves problems such as mismatch between test conditions and fault characteristics, low test coverage, and low test efficiency in related technologies, significantly improving the performance and reliability of memory stress testing. Attached Figure Description

[0020] To more clearly illustrate the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 A flowchart of a memory stress testing method provided in an embodiment of the present invention;

[0022] Figure 2 A flowchart illustrating a memory stress testing method provided in one embodiment of the present invention;

[0023] Figure 3 This is a block diagram of a memory stress testing device provided in an embodiment of the present invention;

[0024] Figure 4 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0025] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present invention.

[0026] It should be noted that, in the description of this invention, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., used in this invention are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0027] To enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0028] The embodiments of the present invention provide a memory stress testing method, and the method is described in detail in conjunction with the execution flow of the memory stress testing method.

[0029] Specifically, Figure 1 This is a flowchart illustrating a memory stress testing method provided in an embodiment of the present invention.

[0030] like Figure 1 As shown, this memory stress test method includes the following steps:

[0031] In step S101, it is determined whether the number of errors in the memory to be tested is higher than the corresponding error threshold.

[0032] According to one embodiment of the present invention, before determining whether the number of errors of the memory under test is higher than the corresponding error threshold, the method includes: acquiring usage data of the memory under test, wherein the usage data includes at least one of usage duration, operating temperature, and historical error rate trend; and determining the error threshold corresponding to the memory under test based on the usage data.

[0033] It should be noted that the data used in this embodiment of the invention refers to multi-dimensional information reflecting the operating status and history of the memory module, continuously collected and recorded by the Baseboard Management Controller (BMC) during normal server operation. This data includes at least: usage time (cumulative working time of the memory since installation or power-on), operating temperature (real-time and historical temperature of the memory module during operation), and historical error rate trend (a curve showing the frequency of correctable errors (CEs) over time, such as a steady, slow, or rapid increase). The "error threshold" is the criterion for triggering subsequent deep stress testing in the BIOS phase; that is, when the cumulative number of CE errors in the memory reaches or exceeds this value, the system will initiate a pre-check process.

[0034] Specifically, in one embodiment of the present invention, the decision-making process for determining whether the memory under test needs to undergo BIOS stress testing is further optimized. This process no longer relies on a fixed global threshold, but instead first acquires the aforementioned usage data of the memory module before determining whether the number of errors exceeds the limit. Subsequently, the system (usually executed by the BMC) dynamically calculates or adjusts the error threshold corresponding to the specific memory module based on this dynamic usage data. For example, for a memory module with a consistently high operating temperature or long usage history, even if its CE error rate trend is flat, the system may set a lower threshold to reflect its higher potential risk; conversely, for a newly installed memory module in a good operating environment, even if a small number of CE errors occur, the system may set a higher threshold to avoid oversensitivity.

[0035] Therefore, by introducing data to dynamically determine the error threshold, the fault early warning mechanism is made more intelligent and precise. Its technical effect is that it significantly improves the accuracy and rationality of risk assessment.

[0036] In step S102, if the number of errors in the memory to be tested is higher than the corresponding error threshold, the stress test information of the memory to be tested is obtained, and the first target memory and the second target memory are determined from the memory to be tested based on the stress test information of the memory to be tested.

[0037] The first target memory is the memory containing correctable errors, and the second target memory is the memory without correctable errors.

[0038] It should be noted that stress test information refers to information generated by the Baseboard Management Controller (BMC) and transmitted to the Basic Input / Output System (BIOS) to guide memory stress testing during the BIOS phase. This stress test information includes health status data of the memory under test, such as records of correctable errors. The "first target memory" refers to memory modules that were detected and had CE errors recorded by the BMC during the server's previous operation; these are high-risk objects with potential failures. The "second target memory" refers to other memory modules in the same system that did not have CE errors recorded and are considered relatively healthy, low-risk objects.

[0039] Specifically, in an embodiment of the present invention, when the BMC determines that the number of CE errors of a memory module under test exceeds its dynamic or preset threshold, it will enter a more refined stress test preparation stage. The BMC will compile detailed CE records of all memory modules in its logs and send them to the BIOS. After obtaining this stress test information, the BIOS will parse and classify it: memory modules with CE error records will be identified and marked as "first target memory," which are the objects that need to be given special attention; at the same time, memory modules without CE error records will be identified and marked as "second target memory." This distinction is the basis for the subsequent implementation of differentiated and graded stress test strategies, enabling the BIOS to adopt different test intensities for memory modules with different risk levels.

[0040] Therefore, by classifying memory risks and clearly distinguishing between the first and second target memory, a foundation is laid for accurate and efficient testing, enabling refined management of memory health screening.

[0041] In step S103, a preset deep testing strategy is used to test the first target memory to obtain a first test result, and a preset lightweight testing strategy is used to test the second target memory to obtain a second test result. Based on the first test result and the second test result, the erroneous memory and the memory location corresponding to the erroneous memory are determined.

[0042] Among them, the preset deep testing strategy and the preset lightweight testing strategy can be preset by relevant personnel. The deep testing strategy is a high coverage and high time consumption stress testing method, which usually includes a variety of complex testing algorithms and a high number of loops, aiming to fully expose the potential hardware defects of memory. The lightweight testing strategy is a fast and low-overhead detection method, which usually only includes basic test modes and has very few loops, and is used to quickly screen obvious faults.

[0043] Specifically, in this embodiment of the invention, the BIOS executes differentiated testing procedures based on the first target memory and the second target memory determined in step S102. For the "first target memory" marked as high-risk, the BIOS calls a preset deep testing strategy to perform a thorough and comprehensive test to verify its reliability to the greatest extent possible and generates a first test result. For the second target memory marked as low-risk, the BIOS applies a preset lightweight testing strategy for quick spot checks to confirm its basic functionality at a lower cost and generates a second test result. The BIOS summarizes all test results, and if an error message occurs, it returns the error address information, parses and determines the specific error memory and its physical memory location.

[0044] Therefore, by implementing a tiered testing strategy, a balance between fault detection efficiency and accuracy was achieved, significantly shortening the overall testing time for the BIOS stage while ensuring the detection rate of critical faults.

[0045] Alternatively, the embodiments of the present invention can provide another implementation method, for example, pre-building a load testing configuration table, which includes: memory target identifier, test level and test parameters.

[0046] The memory target identifier identifies the memory to be tested. Test levels include: Level 1, which performs a full, multi-loop, multi-algorithm test on memory modules with CE (Continuous Error Correction) records; Level 2, which performs a fast, single-loop, basic algorithm test on other memory modules located under the same memory controller as the faulty memory module; and Level 3, which skips tests on memory modules located far from the faulty area and with a good historical record. Test parameters can include the test algorithm, test program, and number of tests.

[0047] In this embodiment of the invention, after obtaining the stress test information of the memory to be tested, the test level of the memory to be tested can be determined based on the pre-built stress test configuration table, and the corresponding test content can be called according to the test level.

[0048] In step S104, the error type corresponding to the error memory is determined according to the memory location corresponding to the error memory, and the processing strategy corresponding to the error memory is determined according to the error type corresponding to the error memory. The error memory is then processed based on the processing strategy corresponding to the error memory.

[0049] Specifically, after identifying the memory location corresponding to the reported memory error, this application can determine the error type based on that location. For example, if the error is highly concentrated on one or a few memory modules under the same memory controller, the system will infer that the problem likely stems from hardware failure of these specific memory modules. The determined "handling strategy" in this case is targeted in-depth testing and isolation: the BIOS can immediately perform more stringent, specific-mode stress tests on these faulty memory modules to confirm the fault and remove them from the system memory mapping, while simultaneously prompting the user to replace the specified memory modules via BMC alarms. If the error is widely distributed across multiple different memory modules, the system will infer that the problem is more likely system-level, with the root cause possibly being the CPU memory controller, motherboard wiring, unstable power supply, or a BIOS firmware defect, rather than the memory modules themselves. The determined "handling strategy" in this case is comprehensive diagnosis and system-level alarms: the system will instruct for more comprehensive memory testing and generate high-level alarms, prompting the administrator that the problem may not be with the memory hardware, but requires checking the CPU, power supply, motherboard, or updating the BIOS, preventing users from blindly replacing multiple memory modules.

[0050] Therefore, by analyzing the distribution pattern of the error-reporting memory to distinguish the error type, a preliminary intelligent diagnosis of the root cause of the fault is achieved, which greatly improves the accuracy and efficiency of fault handling and avoids misjudgment and waste of resources.

[0051] According to one embodiment of the present invention, after obtaining the stress test information of the memory to be tested, the method further includes: obtaining the physical memory information of the memory to be tested, and parsing the stress test information to obtain the stress test program and the number of stress tests; determining the starting address of the physical address of the memory to be tested based on the physical memory information, and performing stress test on the memory to be tested based on the starting address, the stress test program, and the number of stress tests to obtain the stress test result.

[0052] Among them, physical memory information refers to the physical characteristics of the memory module; the stress test program is the specific program or script used to perform stress tests; the number of stress tests is the number of times the stress test program needs to be executed. The number of stress tests can be preset by the user, obtained through a limited number of experiments, or obtained through a limited number of computer simulations. No specific limitation is made here. Preferably, the number of stress tests is 3.

[0053] It is understood that, in addition to classifying memory tests according to memory risks, the embodiments of the present invention can also perform comprehensive memory tests.

[0054] Specifically, during the server boot process, the BIOS obtains stress test information from the preset controller side through shared memory. This stress test information includes whether memory stress testing is required, as well as configuration information such as the stress test program and the number of loops.

[0055] Then, this embodiment of the invention obtains physical memory information, determines the physical address range of the memory to be tested, and finds the starting address. The starting address is the starting point of the test and is used to identify the beginning position of the memory region to be tested. Subsequently, based on this starting address, combined with the previously parsed stress test program and the number of stress tests, the system performs stress tests on the memory. The stress test program will start at the specified starting address and test the memory according to the preset test logic and number of tests. During the test, the system will collect memory performance data in real time and finally generate stress test results. These results will be used to evaluate the performance and stability of the memory and help users understand the actual working state of the memory.

[0056] Therefore, through precise testing and comprehensive performance evaluation, this invention enables the system to more effectively identify potential memory failure points and performance bottlenecks. This helps enhance the overall reliability of the system, reduce the risk of system failures and data loss due to memory issues, and improve system stability and security.

[0057] According to one embodiment of the present invention, stress test results are obtained by stress testing the memory to be tested based on a starting address, according to a stress testing program and a number of stress tests, including: segmenting the memory to be tested based on the starting address to obtain at least a portion of the memory segments to be tested; performing stress tests on the at least a portion of the memory segments to be tested using a stress testing program, and obtaining stress test information of the at least a portion of the memory segments to be tested when the current number of tests reaches the number of stress tests; and obtaining stress test results based on the stress test information of the at least a portion of the memory segments to be tested.

[0058] The memory segment under test is a series of small memory regions obtained by segmenting the memory under test; the stress test value is the performance data obtained for each memory segment under test during the stress test.

[0059] It is understood that the embodiments of this application can employ parallel testing, for example, using a multi-core processor to test multiple memory segments simultaneously, or sequentially testing each memory segment one by one.

[0060] For example, in this embodiment of the invention, physical memory is segmented, and the parallel computing capabilities of multi-core processors are utilized to simultaneously launch multiple test threads or tasks. Each thread is responsible for stress testing an independent memory segment, thereby achieving parallelization and significantly shortening the overall test time.

[0061] Specifically, embodiments of the present invention can segment the memory to be tested based on a starting address to obtain multiple memory segments. This segmentation process divides a large block of memory into multiple smaller blocks, facilitating separate testing. A load testing program calls the corresponding memory load testing function to perform load testing on at least a portion of the memory segments to be tested. During the load testing of each memory segment, the system records the current number of tests. When the current number of tests reaches a preset load testing count, the system collects the load test value for that memory segment. Based on the load test values ​​of all memory segments to be tested, the system finally obtains the load test result.

[0062] Therefore, by segmenting the memory under test and stress testing each segment separately, memory performance can be evaluated more precisely. In addition, segmented testing allows the system to adjust the testing strategy according to the characteristics of different memory segments. Furthermore, segmented testing can be performed in parallel, and multiple memory segments can be stress tested simultaneously, thereby significantly improving testing efficiency.

[0063] According to one embodiment of the present invention, after segmenting the memory to be tested based on the starting address to obtain at least a portion of the memory segments to be tested, the method further includes: testing the at least portion of the memory segments to be tested using a load testing program according to a preset load testing order, and obtaining load testing information of the at least portion of the memory segments to be tested when the current number of tests reaches the load testing number; and obtaining a stress test result based on the load testing information of the at least portion of the memory segments to be tested.

[0064] The preset stress test sequence can be pre-set by relevant personnel.

[0065] Specifically, in one embodiment of the present invention, after obtaining the starting address of the memory under test and completing segmentation, the BIOS organizes the test process according to a pre-set stress test order. The system performs stress tests on each memory segment under test sequentially according to the preset stress test order. For the memory segment currently being tested, the stress test program starts a loop counter and repeatedly executes the preset test algorithm. Only when the "current test count" of the memory segment successfully reaches the preset "stress test count" (for example, completing 3 complete March C tests) does the system consider the segment test complete and record the complete stress test information. If an error occurs in any loop, the failure information is immediately recorded and subsequent loops for that segment are terminated. After all memory segments have completed their specified stress test counts in sequence, the BIOS integrates and analyzes all collected stress test information, ultimately generating an overall stress test result to determine the health status of the system memory.

[0066] This enables the memory stress testing process to be ordered, controllable, and standardized, ensuring the stability and predictability of the testing process.

[0067] According to one embodiment of the present invention, after determining the starting address of the physical address of the memory to be tested based on the physical memory information, the method further includes: selecting a preset space from the memory to be tested as a temporary cache area based on the starting address, wherein the temporary cache area is used to store the stress test results.

[0068] The preset space is a pre-defined area in memory used as a temporary cache; the temporary cache is an area used to temporarily store stress test results.

[0069] Specifically, in this embodiment of the invention, a preset space is selected from the memory to be tested as a temporary cache area based on the starting address. The size and location of the temporary cache area can be preset according to actual needs. During the stress test, the test results will be stored in this temporary cache area in real time.

[0070] In actual execution, embodiments of the present invention obtain the starting address of the physical address based on the physical memory information (Memory map) and request a segment of memory of a specified size as a temporary buff, i.e., a temporary cache area.

[0071] Therefore, the embodiments of the present invention ensure that test results can be stored and retrieved quickly and accurately, avoiding the impact of data storage and retrieval delays on test efficiency and accuracy during the test process. The temporary cache can be cleared or retained after the test is completed for subsequent analysis and processing.

[0072] According to one embodiment of the present invention, after performing stress testing on the memory to be tested according to the stress testing program and the number of stress tests to obtain the stress test result, the method further includes: determining whether the stress test result meets the preset stress test conditions; if the stress test result does not meet the preset stress test conditions, generating current error information based on the stress test result, and sending the current error information to the first preset terminal.

[0073] The preset stress test conditions are used to determine whether the stress test results meet the expected performance requirements. The preset stress test conditions are set in advance by relevant personnel or generated by the system, and are not specifically limited here. Preferably, in this embodiment of the invention, the preset stress test conditions are that the stress test results do not have error information; the current error information is detailed error information generated based on the stress test results; the first preset terminal can be any device that can receive or process error information, such as a computer, a computer, a tablet, etc.

[0074] Specifically, in this embodiment of the invention, the stress test result is first determined to meet the preset stress test conditions. If the stress test result does not meet the preset stress test conditions, it indicates that there is a potential problem with the memory. The system will generate current error information based on the stress test result. This information describes in detail the type and location of the error. The generated current error information will be sent to a first preset terminal. The first preset terminal can be a maintenance personnel's workstation or a monitoring system, used to promptly notify relevant personnel of the memory problem so that they can take measures to deal with it quickly.

[0075] For example, if the stress test fails, the BIOS will parse the specific memory error type and memory location based on the error message and the IMC register, and send the error information to the BMC through shared memory. The user can then confirm the memory that needs to be replaced through the BMC log and replace it. If the stress test results meet the preset stress test conditions, the system will continue to boot.

[0076] Therefore, by sending the current error message to the first preset terminal, the system can promptly notify maintenance personnel of memory problems. This ensures that problems can be quickly detected and resolved, reducing potential risks caused by delayed detection.

[0077] According to one embodiment of the present invention, after sending the current error information to a first preset terminal, the method includes: generating an error reminder instruction based on the current error information, and performing optical and / or acoustic reminders based on the error reminder instruction.

[0078] Among them, the error alert instruction is an instruction generated based on the current error information; the optical alert is to remind the user of a memory error through light signals (such as flashing indicator lights, warning icons on the display screen, etc.); and the acoustic alert (AcousticAlert) is to remind the user of a memory error through sound signals (such as alarm sounds, voice prompts, etc.).

[0079] Specifically, based on the received error message, the system generates a corresponding error alert instruction. This instruction includes specific information triggering the alert, such as the type of alert (optical or acoustic), the frequency of the alert, and the duration of the alert. The system then executes the optical or / or acoustic alert based on the instruction. For example, the system might illuminate a red indicator light and sound an alarm, or display a warning icon on the screen and play a voice prompt. These alert methods can be used individually or in combination to ensure that users notice the error message promptly.

[0080] Therefore, through optical and / or acoustic alerts, the system can promptly notify users of memory errors, ensuring that users can quickly notice the problem and reducing potential risks caused by delayed detection.

[0081] According to one embodiment of the present invention, before performing stress tests on at least a portion of the memory segments to be tested using a stress testing program, the process includes: obtaining test requirements, writing test cases based on the test requirements, and generating a stress testing program based on the test cases. This allows users to customize the stress testing program according to their own needs, enhancing the flexibility of stress testing.

[0082] In summary, this invention achieves the following technical effects by obtaining specific stress test information from the BMC via shared memory during the BIOS stage, acquiring physical memory information through the HOB, calling the stress test function to perform stress tests on the physical memory, and analyzing and reporting error information to the BMC: 1. Fault prevention: By moving the memory quality verification window forward to the maintenance stage, the UCE error rate in the production environment is reduced by more than 90%; 2. Efficiency improvement: Through intelligent decision-making stress testing by the BMC, invalid detection is avoided, shortening the maintenance cycle by 30%-50%; 3. Reduced maintenance costs for manual troubleshooting and emergency memory replacement, extending the hardware lifecycle. Therefore, this invention is suitable for scenarios with stringent memory reliability requirements, such as cloud computing data centers and financial core systems, providing a highly available, low-cost standardized solution for server memory health management.

[0083] To enable those skilled in the art to further understand the memory stress testing method of the present invention, the following description is provided in conjunction with specific embodiments.

[0084] like Figure 2 As shown, Figure 2 This is a flowchart of a memory stress testing method provided according to an embodiment of the present invention.

[0085] When the server is running user services under the system, if a memory error (CE) reaches a threshold, it will be reported to the BMC. When the server is undergoing maintenance and restarting, the BIOS obtains information from the BMC via shared memory to determine whether a memory stress test is needed. If the BIOS detects a memory error, it obtains the current memory capacity, memory attributes, and other initialization information via the Hob. The BIOS calls the memory test function integrated in the code to perform a stress test on all actual physical memory. If a memory error is found during the stress test, the specific memory module location is parsed from the error message, and the information of the faulty memory module is reported to the BMC. The user then replaces the memory module according to the location of the memory module in the alarm information in the BMC.

[0086] This invention constructs a BIOS-BMC deep collaborative architecture, which achieves the following functions: (1) Dynamic error capture: memory CE event logs are obtained through the BMC real-time monitoring interface; (2) Intelligent pre-detection trigger: during system maintenance restart, the BIOS actively calls the MemTest customized test case; (3) Risk pre-isolation: pre-operating system level isolation is implemented for faulty DIMMs to block the transmission of errors to the business system. This invention advances the fault detection node from runtime to pre-boot, thereby increasing the memory fault detection rate to 99.2% (laboratory test data) and significantly reducing the risk of business interruption caused by memory faults.

[0087] Therefore, the embodiments of the present invention have the following beneficial effects:

[0088] (1) Risk prediction. For CE error memory reported during business operation, intelligently distinguish between occasional software errors and potential hardware failures. Verify memory reliability through customized stress testing at the BIOS stage, intercept problematic memory in advance, and prevent it from flowing back into the production environment and causing serious failures.

[0089] (2) Dynamic load testing triggering mechanism. The BMC shared memory communication technology is adopted to dynamically determine whether to start the load test and select the test strategy based on the CE error record, avoiding the startup delay caused by the default full detection, and realizing fully automated operation and maintenance without manual intervention.

[0090] (3) Lossless business isolation. The test runs entirely at the BIOS layer, with zero intrusion into the user's operating system and business environment. No additional agent or downtime deployment is required, ensuring that the testing process is completely decoupled from the business.

[0091] (4) Flexible and scalable architecture. Supports on-demand customization of load testing programs (such as load mode, duration threshold), adapts to different memory types and business scenario requirements, and improves detection accuracy and efficiency.

[0092] According to the memory stress testing method proposed in this embodiment of the invention, the method determines whether the number of errors in the memory under test exceeds a corresponding error threshold. If the number of errors in the memory under test exceeds the corresponding error threshold, the method acquires the stress testing information of the memory under test. Based on the stress testing information, a first target memory and a second target memory are determined from the memory under test. A preset deep testing strategy is used to test the first target memory to obtain a first test result, and a preset lightweight testing strategy is used to test the second target memory to obtain a second test result. Based on the first test result and the second test result, the method determines the faulty memory and its corresponding memory location, determines the error type of the faulty memory based on its memory location, determines the processing strategy for the faulty memory based on its error type, and processes the faulty memory based on the processing strategy. This solves the problems of mismatch between test conditions and fault characteristics, low test coverage, and low test efficiency in related technologies, significantly improving the performance and reliability of memory stress testing.

[0093] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0094] Embodiments of the present invention also provide a memory stress testing device.

[0095] Figure 3 This is a block diagram of a memory stress testing device according to an embodiment of the present invention.

[0096] like Figure 3 As shown, the memory stress testing device 10 includes: a judgment module 100, an acquisition module 200, a testing module 300, and a processing module 400.

[0097] The judgment module 100 is used to determine whether the number of errors in the memory to be tested is higher than the corresponding error threshold.

[0098] The acquisition module 200 is used to acquire the stress test information of the memory under test when the number of errors in the memory under test is higher than the corresponding error threshold, and to determine the first target memory and the second target memory from the memory under test based on the stress test information.

[0099] The testing module 300 is used to test the first target memory using a preset deep testing strategy to obtain a first test result, and to test the second target memory using a preset lightweight testing strategy to obtain a second test result. Based on the first test result and the second test result, the error memory and the memory location corresponding to the error memory are determined.

[0100] The processing module 400 is used to determine the error type corresponding to the erroneous memory based on the memory location corresponding to the erroneous memory, determine the processing strategy corresponding to the erroneous memory based on the error type corresponding to the erroneous memory, and process the erroneous memory based on the processing strategy corresponding to the erroneous memory. According to an embodiment of the present invention, after obtaining the stress test information of the memory to be tested, the acquisition module 200 further includes: a first acquisition unit and a testing unit.

[0101] The first acquisition unit is used to acquire the physical memory information of the memory to be tested and parse the load test information to obtain the load test program and the number of load tests.

[0102] The test unit is used to determine the starting address of the physical address of the memory to be tested based on the physical memory information, and to perform stress testing on the memory to be tested based on the starting address, the stress testing program and the number of stress tests to obtain the stress test results.

[0103] According to one embodiment of the present invention, the test unit includes: a segmentation subunit, a test subunit, and a generation subunit.

[0104] The segmentation subunit is used to segment the memory to be tested based on the starting address to obtain at least a portion of the memory segment to be tested.

[0105] The test subunit is used to perform stress tests on at least a portion of the memory segments to be tested using a stress testing program, and to obtain stress test information for at least a portion of the memory segments to be tested when the current number of tests reaches the stress test count.

[0106] Generate sub-units to obtain stress test results based on stress test information from at least a portion of the memory segment under test.

[0107] According to one embodiment of the present invention, after segmenting the memory to be tested based on the starting address to obtain at least a portion of the memory to be tested, the segmentation subunit further includes: a test subunit and a generation subunit.

[0108] The test sub-component is used to test at least a portion of the memory segments to be tested according to a preset load test sequence using a load test program, and to obtain load test information for at least a portion of the memory segments to be tested when the current test count reaches the load test count.

[0109] Generate sub-components to obtain stress test results based on stress test information from at least a portion of the memory segment under test.

[0110] According to one embodiment of the present invention, after determining the starting address of the physical address of the memory to be tested based on the physical memory information, the test unit further includes:

[0111] The selection sub-component is used to select a preset space from the memory to be tested as a temporary cache area based on the starting address. The temporary cache area is used to store the stress test results.

[0112] According to an embodiment of the present invention, after stress testing the memory to be tested according to the stress testing program and the number of stress tests to obtain the stress test results, the test unit further includes: a judgment subunit and an error reporting subunit.

[0113] The judgment subunit is used to determine whether the pressure test results meet the preset pressure test conditions.

[0114] The error reporting subunit is used to generate current error information based on the stress test results if the stress test results do not meet the preset stress test conditions, and then send the current error information to the first preset terminal.

[0115] According to an embodiment of the present invention, before determining whether the number of errors in the memory to be tested is higher than the corresponding error threshold, the determination module 100 includes: a second acquisition unit and a determination unit.

[0116] The second acquisition unit is used to acquire usage data of the memory to be tested, wherein the usage data includes at least one of usage duration, operating temperature, and historical error rate trend.

[0117] The determination unit is used to determine the error threshold corresponding to the memory to be tested based on the usage data.

[0118] According to one embodiment of the present invention, the first target memory is memory with correctable errors, and the second target memory is memory without correctable errors.

[0119] According to one embodiment of the present invention, after sending the current error information to the first preset terminal, the error reporting subunit includes: a reminder sub-component.

[0120] The reminder sub-component is used to generate an error reminder command based on the current error information, and to provide optical and / or acoustic reminders based on the error reminder command.

[0121] In summary, the descriptions of the features in the embodiments corresponding to the memory stress testing device can be found in the relevant descriptions of the embodiments corresponding to the memory stress testing method, and will not be repeated here.

[0122] Embodiments of the present invention also provide an electronic device, which may include:

[0123] The memory 401, the processor 402, and the computer program stored on the memory 401 and capable of running on the processor 402.

[0124] When processor 402 executes the program, it performs the memory stress test provided in the above embodiments.

[0125] Furthermore, electronic devices also include:

[0126] Communication interface 403 is used for communication between memory 401 and processor 402.

[0127] The memory 401 is used to store computer programs that can run on the processor 402.

[0128] Memory 401 may include high-speed RAM memory, and may also include non-volatile memory, such as at least one disk storage device.

[0129] If the memory 401, processor 402, and communication interface 403 are implemented independently, then the communication interface 403, memory 401, and processor 402 can be interconnected via a bus to complete communication between them. The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized into address buses, data buses, control buses, etc. For ease of representation, Figure 4 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0130] Optionally, in a specific implementation, if the memory 401, processor 402, and communication interface 403 are integrated on a single chip, then the memory 401, processor 402, and communication interface 403 can communicate with each other through an internal interface.

[0131] Processor 402 may be a central processing unit (CPU), an application specific integrated circuit (ASIC), or one or more integrated circuits configured to implement embodiments of the present invention.

[0132] Embodiments of the present invention also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above-described memory stress testing method embodiments when running.

[0133] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0134] Embodiments of the present invention also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above-described memory stress testing method embodiments.

[0135] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0136] The memory stress testing method provided by this invention has been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this invention. The descriptions of the embodiments above are only for the purpose of helping to understand the method and core ideas of this invention. It should be noted that those skilled in the art can make several improvements and modifications to this invention without departing from the principles of this invention, and these improvements and modifications also fall within the protection scope of the claims of this invention.

Claims

1. A memory stress testing method, characterized by, The method comprises the following steps: determining whether the error number of the to-be-tested memory is higher than the corresponding error threshold value; if the error number of the to-be-tested memory is higher than the corresponding error threshold value, obtaining stress test information of the to-be-tested memory, determining a first target memory and a second target memory from the to-be-tested memory according to the stress test information of the to-be-tested memory; using a preset deep test strategy to test the first target memory to obtain a first test result, and using a preset lightweight test strategy to test the second target memory to obtain a second test result, determining an error memory and a memory position corresponding to the error memory according to the first test result and the second test result; determining an error type corresponding to the error memory according to the memory position corresponding to the error memory, and determining a processing strategy corresponding to the error memory according to the error type corresponding to the error memory, and processing the error memory based on the processing strategy corresponding to the error memory, the first target memory is a memory with correctable errors, and the second target memory is a memory without the correctable errors; if the memory positions corresponding to the error memory are concentrated in the same memory bank or part of the memory banks under the same memory controller, it is determined that the error type corresponding to the error memory is memory bank hardware damage, and the processing strategy is to retest or isolate the memory bank with hardware damage; if the memory positions corresponding to the error memory are scattered in multiple different memory banks, it is determined that the error type corresponding to the error memory is system failure, and the processing strategy is to comprehensively diagnose and alarm the central processing unit, power supply, motherboard or basic input / output system.

2. The method of claim 1, wherein, After obtaining the stress test information of the to-be-tested memory, the method further comprises: obtaining physical memory information of the to-be-tested memory, and parsing the stress test information to obtain a stress test program and a stress test number; determining a starting address of a physical address of the to-be-tested memory according to the physical memory information, and performing stress testing on the to-be-tested memory based on the starting address, the stress test program and the stress test number to obtain a stress test result.

3. The method of claim 2, wherein, The stress testing on the to-be-tested memory based on the starting address, the stress test program and the stress test number to obtain a stress test result comprises: segmenting the to-be-tested memory based on the starting address to obtain at least part of to-be-tested memory segments; performing stress testing on at least part of the to-be-tested memory segments using the stress test program, and obtaining stress test information of the at least part of the to-be-tested memory segments when the current test number reaches the stress test number; obtaining the stress test result according to the stress test information of the at least part of the to-be-tested memory segments.

4. The method of claim 3, wherein, After segmenting the to-be-tested memory based on the starting address to obtain at least part of to-be-tested memory segments, the method further comprises: testing the at least part of the to-be-tested memory segments using the stress test program in a preset stress test order, and obtaining stress test information of the at least part of the to-be-tested memory segments when the current test number reaches the stress test number; obtaining the stress test result according to the stress test information of the at least part of the to-be-tested memory segments.

5. The method of claim 2, wherein, After determining the start address of the physical address of the memory to be tested according to the physical memory information, the method further comprises: selecting a preset space from the memory to be tested as a temporary cache area based on the start address, wherein the temporary cache area is used to store the stress test result.

6. The method of claim 2, wherein, After obtaining the stress test result by performing stress test on the memory to be tested according to the stress test program and the stress test times, the method further comprises: determining whether the stress test result meets a preset stress test condition; if the stress test result does not meet the preset stress test condition, generating current error information based on the stress test result, and sending the current error information to a first preset terminal.

7. The method of claim 1, wherein, Before determining whether the error times of the memory to be tested is higher than the corresponding error threshold, the method comprises: obtaining usage data of the memory to be tested, wherein the usage data comprises at least one of usage duration, working temperature, and historical error rate trend; determining the error threshold corresponding to the memory to be tested according to the usage data.

8. The method of claim 6, wherein, After sending the current error information to the first preset terminal, the method comprises: generating an error reminding instruction according to the current error information, and performing optical reminding and / or acoustic reminding according to the error reminding instruction.

9. An electronic device, comprising: The method comprises: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the steps of the memory stress test method according to any one of claims 1 to 8.

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