Dynamic reconfigurable chip implementation method based on data stream architecture

Abstract

The invention discloses a dynamic reconfigurable chip implementation method based on a data flow framework, which belongs to the technical field of integrated circuit design, and comprises the following steps: firstly, receiving a top-layer user program by a software programming framework, and splitting the top-layer user program into operator levels to form a program operator data flow diagram; analyzing the number of data elements and the number of program operators executed by the program in parallel; reading the configurable depth and the number of processable parallel elements of a computing unit in the reconfigurable chip; according to the parameters, determining a data flow link length, an operation updating frequency and an operation grouping mode which are executed by the program in parallel according to a corresponding formula; reading the number and the positions of idle computing units in the reconfigurable chip, and determining the computing mode and the data flow direction of the computing units; and completing operator function configuration writing and data transmission configuration writing according to the operator data flow diagram in the data flow link. According to the invention, the instruction scheduling overhead is effectively saved, the execution power consumption of the computing unit is guaranteed, and the power consumption density of the whole chip is reduced.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and more specifically to a method for implementing a dynamically reconfigurable chip based on a dataflow architecture. Background Technology

[0002] In the current field of integrated circuit design and heterogeneous computing, traditional computing chips face two major challenges:

[0003] One reason is the inherent defects of instruction-driven architecture: existing heterogeneous computing processing cores generally adopt the instruction-driven mode. The pipeline mechanism of instruction reading, decoding and execution leads to a lot of ineffective power consumption. Especially when processing computationally intensive tasks (such as neural networks and matrix operations), the instruction scheduling overhead can account for more than 30%, which seriously restricts the improvement of computing power utilization.

[0004] On the other hand, there is the contradiction between energy consumption and versatility: to balance computing efficiency and versatility, traditional chips often adopt complex instruction set architecture (CISC) or heterogeneous multi-core combinations, resulting in increased chip area and power density. For example, in AI inference scenarios, the energy efficiency ratio (TOPS / W) of mainstream GPUs has long stagnated in the 10-50 range, making it difficult to meet the low power consumption requirements of edge computing devices. Summary of the Invention

[0005] The technical objective of this invention is to address the above-mentioned shortcomings by providing a dynamic reconfigurable chip implementation method based on a dataflow architecture, which effectively eliminates instruction scheduling overhead, ensures the execution power consumption of the computing unit, and reduces the overall chip power density.

[0006] The technical solution adopted by this invention to solve its technical problem is:

[0007] A method for implementing a dynamically reconfigurable chip based on a dataflow architecture parses user programs through a software programming framework and uses data as a driver to guide the execution of computing units. The specific implementation includes the following steps:

[0008] The software programming framework first receives the top-level user program and breaks it down into operator levels, forming a program operator data flow graph.

[0009] Analyze the number of data elements and program operators that are executed in parallel.

[0010] Read the configurable depth of computing units and the number of parallel elements that can be processed in a reconfigurable chip;

[0011] Based on the above parameters, the data stream link length, operation update frequency, and operation grouping method for parallel execution of the program are determined according to the corresponding formulas.

[0012] Read the number and location of idle computing units in the reconfigurable chip to determine the computing mode and data flow of the computing units;

[0013] Based on the operator data flow diagram in the data flow chain, complete the writing of operator function configuration and data transmission configuration.

[0014] Furthermore, the user program includes conventional computing tasks, control tasks, and computationally intensive tasks including artificial intelligence, neural networks, etc.

[0015] Furthermore, the reconfigurable chip supports a wide range of underlying operators, including basic addition, subtraction, multiplication, and division operators, activation function operators, matrix operators, convolution operators, pooling operators, normalization operators, tensor operators, and many others.

[0016] Furthermore, let the number of data elements executed in parallel by the analysis program be Npn and the number of program operators be Npc; read the configurable depth of the computing unit in the reconfigurable chip as Ncc and the number of parallel elements that can be processed as Ncn;

[0017] The data flow link length Lc for parallel execution of the program is determined by the formula Lc=(Npn*Npc) / (Ncc*Ncn). This length represents the number of computing units that need to be continuously occupied in order to achieve parallel execution of the program in a reconfigurable chip.

[0018] The operation update frequency and operation grouping method are determined according to the formula Fc = Npc / Ncc. The operation update frequency represents the number of times the computing unit configuration information is updated during program execution. The operators are grouped according to the number of computing units required, so as to facilitate efficient execution on the computing units.

[0019] The number of times the software programming framework needs to send data to the reconfigurable chip is determined by the formula Dc = Npn / Ncn.

[0020] Furthermore, the dynamic reconfigurable chip hardware operator mapping process based on the dataflow architecture is as follows:

[0021] The software programming framework first reads the state of the computing units in the reconfigurable chip to determine the location and number of idle computing units;

[0022] Based on the number of computing units required by the current user program and the location of available computing units, determine the location of the computing units to be executed by the current user program and the direction of data flow.

[0023] After determining the location of the computing unit and the direction of data flow, the data composition of the configuration register stack in the selected computing unit is determined according to the operation grouping method.

[0024] Furthermore, the order of selection for computing units is as follows:

[0025] (1) Prioritize allocation to computational units in the top-level row;

[0026] (2) If it is necessary to use a row of calculation units whose first column is empty, the calculation units are selected in a right-up-left sequence;

[0027] (3) If multiple rows with empty first columns are required, the selection of calculation units is also performed in the same right-up-left sequence.

[0028] Furthermore, the hardware execution process of the dynamically reconfigurable chip based on the dataflow architecture is as follows:

[0029] First, the reconfigurable chip receives configuration information from the software programming framework and performs internal hardware configuration, including: receiving a computing unit selection signal from the software programming framework to select the computing units participating in the current application computation; receiving data flow direction information from the software programming framework to configure the router corresponding to the computing unit to enable the data link in the corresponding direction and close the routing path in other directions; receiving computation configuration information for each computing unit from the software programming framework to configure the configuration register stack in the computing unit and determine the configuration register stack data update frequency Fc.

[0030] Subsequently, the software programming framework sends operation data to the initial calculation unit in sequence according to the Dc data; after receiving the data, the calculation unit begins to execute the operation.

[0031] For each computing unit participating in the calculation, after receiving the strobe signal sent by the software programming framework, it will configure and start the corresponding computing operator according to the internal configuration register stack information.

[0032] After the initial calculation unit receives the data sent by the software programming framework, it passes the data into the configuration register stack for information configuration, starts the corresponding calculation operator to complete the calculation, and directly sends the data to the determined next-level calculation unit after the calculation is completed. It also determines whether the selected calculation operator needs to be changed according to the configuration register stack data update frequency Fc. After the currently selected calculation operator completes Fc calculations, it switches to the calculation operator mode defined by the next configuration register stack data.

[0033] After the next-level computing unit receives the input data from the starting computing unit, it also inputs the data into its own selected computing operator to complete the calculation; at the same time, the starting computing unit receives the subsequent data sent by the software programming framework and completes synchronous calculation.

[0034] After the data is transmitted to the last calculation unit of the data flow, the last calculation unit completes the calculation defined by the internal configuration register stack and feeds the calculation result back to the starting calculation unit (at this time, the starting calculation unit has generally completed the iteration of the calculation operator).

[0035] In this mode, the data will be continuously calculated in the selected computing units until all operators defined in their respective configuration register stacks are completed, and then the data will be fed back to the software programming framework.

[0036] Furthermore, within the computing unit, each computing operator is driven by a gating circuit. That is, when it is not enabled, the corresponding computing module does not participate in the calculation and does not generate power consumption. This is the low-power design of this method.

[0037] The present invention also claims a dynamically reconfigurable chip implementation device based on a dataflow architecture, comprising: at least one memory and at least one processor;

[0038] The at least one memory is used to store a machine-readable program;

[0039] The at least one processor is used to call the machine-readable program to implement the above method.

[0040] The present invention also claims a computer-readable medium storing computer instructions that, when executed by a processor, implement the above-described method.

[0041] Compared with existing technologies, the dynamic reconfigurable chip implementation method based on dataflow architecture of the present invention has the following advantages:

[0042] This invention addresses the inherent shortcomings of instruction-driven architecture chips by proposing a dynamically reconfigurable chip architecture based on data flow. It uses a software programming framework to parse user programs and replaces instructions with data to drive the execution of computing units, effectively eliminating instruction scheduling overhead. Simultaneously, addressing the issue of excessively high energy consumption in existing chips, this invention uses a clock-gating circuit as a basis to dynamically configure the operation types of computing units in the data flow path, ensuring the execution power consumption of computing units and reducing the overall chip power density. Attached Figure Description

[0043] Figure 1 This is a schematic diagram of the execution process of a dynamically reconfigurable chip software compilation framework based on a dataflow architecture, provided in an embodiment of the present invention.

[0044] Figure 2 This is a schematic diagram of the user program splitting process in a dynamically reconfigurable chip software compilation framework provided by an embodiment of the present invention;

[0045] Figure 3 This is a schematic diagram of the overall architecture of a dynamically reconfigurable chip based on a dataflow architecture, provided in one embodiment of the present invention. Detailed Implementation

[0046] The present invention will be further described below with reference to specific embodiments.

[0047] This invention provides a method for implementing a dynamically reconfigurable chip based on a dataflow architecture. Addressing the inherent limitations of instruction-driven chip architectures, the dataflow-based dynamically reconfigurable chip architecture parses user programs through a software programming framework, replacing instructions with data to drive the execution of computing units, effectively eliminating instruction scheduling overhead. Simultaneously, addressing the issue of excessively high energy consumption in existing chips, it uses a clock-gating circuit as a basis to dynamically configure the operation types of computing units in the dataflow path, ensuring the execution power consumption of computing units and reducing the overall chip power density.

[0048] like Figure 1 The diagram shows the execution process of a dynamically reconfigurable chip software compilation framework based on a dataflow architecture. The specific implementation process is as follows:

[0049] S01: In this method, the software programming framework first receives the top-level user program and breaks it down into a sequential execution process diagram of the underlying operators supported by the reconfigurable chip. The user program can be a regular computational task, a control task, or a computationally intensive task such as artificial intelligence or neural networks. The underlying operators supported by the reconfigurable chip include basic addition, subtraction, multiplication, and division operators, activation function operators, matrix operators, convolution operators, pooling operators, normalization operators, tensor operators, and many other operators. The specific program decomposition process is as follows: Figure 2 As shown.

[0050] S02: After the software programming framework receives and decomposes the top-level user program, it then analyzes the operator parallelism and counts the total number of operator operations. Specifically, the dynamically reconfigurable chip software compilation framework analyzes the number of data elements (Npn) executed in parallel, which represents the number of data elements processed simultaneously in a single parallel computation, such as the number of matrix elements in a single parallel computation in matrix multiplication; and counts the number of program operators (Npc), i.e., the total number of operators in the program's operator data flow graph. Figure 2 Taking user program A as an example, user program A requires a total of 3 operator operations. The number of operations executed in parallel for each operator is the number of elements in the data preprocessing operation, the number of elements in the tensor computation, and the number of elements in the format conversion operation.

[0051] S03: After the software programming framework completes the parsing of the user program, it will continue to read the configurable depth (Ncc) and the number of parallel elements that can be processed (Ncn) of the computing unit in the reconfigurable chip. The configurable depth (Ncc) represents the maximum number of different computing states that the computing unit can be configured with, and the number of parallel elements that can be processed (Ncn) represents the number of data elements that the computing unit can process in parallel within a single computing cycle. These parameters can be read through the chip's configuration registers or specific interfaces, providing the basic data for subsequent resource calculations.

[0052] S04: After the software programming framework completes the reading of the Npn, Npc, Ncc, and Ncn parameters from the user program and the reconfigurable chip, it determines the data flow link length Lc for parallel execution of the program according to the formula Lc = (Npn * Npc) / (Ncc * Ncn). This length represents the number of computing units that need to be continuously occupied in the reconfigurable chip to achieve parallel execution of the program. The operation update frequency and operation grouping method are determined according to the formula Fc = Npc / Ncc. The operation update frequency represents the number of times the computing unit configuration information is updated during program execution. The operator grouping arranges the required computing units sequentially to facilitate efficient execution on the computing units. The number of times the software programming framework needs to send data to the reconfigurable chip is determined according to the formula Dc = Npn / Ncn. The values ​​of Lc and Fc for Ncc = 50 and Ncn = 100 are shown in Table 1.

[0053] Table 1: Examples of Update Frequency and Operation Grouping Calculations in Dynamically Reconfigurable Chip Software Compilation Frameworks

[0054]

[0055] S05: After the software programming framework determines the number of computing units and the configuration of the computing mode, it then reads the location and quantity information of idle computing units in the reconfigurable chip, selects computing units that meet the user program's requirements, and determines the data flow and operator configuration of each computing unit. For details, see the hardware operator mapping process for dynamically reconfigurable chips based on a dataflow architecture.

[0056] S06: After the software programming framework determines the data flow direction and operator configuration of the computing unit, it first writes the operator configuration information and data flow direction information into the routing node and computing unit in the reconfigurable chip, and then sends the computing data to start the computing.

[0057] The dynamic reconfigurable chip hardware operator mapping process based on the dataflow architecture is as follows:

[0058] The overall architecture diagram of the dynamically reconfigurable chip based on the dataflow architecture is as follows: Figure 3As shown, a combined architecture of routing nodes and computing chips is adopted. The routing nodes are responsible for receiving data from five directions: East, South, West, North, and Local. Based on the routing order determined by the software programming framework, they send data from a specific direction to the corresponding target computing unit. The computing unit is configured with various computing operator cores, supporting basic addition, subtraction, multiplication, and division operators, activation function operators, matrix operators, convolution operators, tensor operators, and many other low-level operators. Each low-level operator corresponds to an enable code, which is determined by a configuration register stack with a depth of Ncc. Taking a reconfigurable chip with a 5x5 routing topology as an example, the specific hardware operator mapping process is as follows:

[0059] First, the software programming framework reads the state of the computing units in the reconfigurable chip to determine the location and number of idle computing units, in order to... Figure 3 For example, only five computing units are in a busy state, while the remaining computing units can be assigned computing tasks by the software programming framework.

[0060] Subsequently, the software programming framework determines the location of the computational units and the data flow direction for the current user program based on the number of computational units (Lc) required by the current user program and the location of available computational units. Using the lower left computational unit as the (1,1) coordinate, the order of computational unit selection is as follows:

[0061] (1) Prioritize the allocation of computation units in the top row. That is, if the current user program needs 1-3 computation units to participate in the computation, then select the computation unit with coordinates (3-5, 5) in the top row, and the data flow is (3, 5) → (4, 5) → (5, 5) → (3, 5); if the current user program needs 4 computation units to participate in the computation, then select the computation unit with coordinates (3-5, 5) in the top row, plus the computation unit with coordinates (5, 4) in the second row, and the data flow is (3, 5) → (4, 5) → (5, 5) → (5, 4) → (3, 5).

[0062] (2) If a row of calculation units with an empty first column is needed, the calculation units are selected in a right-up-left sequence. That is, if the current user program needs 5 calculation units to participate in the calculation, the calculation unit with the coordinates (3-5, 3) in the third row is selected to participate in the calculation, and the data flow is (1, 3) → (2, 3) → (3, 3) → (4, 3) → (5, 3) → (1, 3). If the current user program requires 6 computational units to participate in the calculation, then the computational unit with coordinates (3-5, 3) in the third row is selected, plus the computational unit with coordinates (5, 4) in the second row. The data flow is (1, 3) → (2, 3) → (3, 3) → (4, 3) → (5, 3) → (5, 4) → (1, 3). If the current user program requires 7 computational units to participate in the calculation, then five computational units with coordinates (3-5, 3) in the third row are selected, plus the computational unit with coordinates (5, 4) in the second row and the computational unit with coordinates (5, 5) in the first row. The data flow is ( 1,3)→(2,3)→(3,3)→(4,3)→(5,3)→(5,4)→(5,5)→(1,3); If the current user program requires 8-9 calculation units to participate in the calculation, then select the five calculation units with coordinates (3-5,3) in the third row, plus the calculation unit with coordinates (5,4) in the second row and the calculation unit with coordinates (3-5,5) in the first row to participate in the calculation. The data flow is (1,3)→(2,3)→(3,3)→(4,3)→(5,3)→(5,4)→(5,5)→(4,5)→(3,5)→(1,3).

[0063] (3) If multiple rows with empty first columns are required, the selection of calculation units is also performed in the same right-up-left sequence.

[0064] Subsequently, based on the determined locations of the computational units and the data flow, the software programming framework determines the data structure of the configuration register stack in the selected computational units according to the operation grouping method. Taking a user program requiring four computational units to participate in the computation as an example, the data structure of the configuration register stack in the selected computational units is as follows:

[0065] by Figure 3 Taking the reconfigurable chip state as an example, the four computational unit positions required by the user program are (3, 5), (4, 5), (5, 5), and (5, 4), and the data flow is (3, 5) → (4, 5) → (5, 5) → (5, 4) → (3, 5). Therefore, the data configuration in the configuration register is written sequentially according to the data flow and the gating values ​​of the user program's underlying operator graph, which is divided into parts of the software programming framework. Figure 2Taking the splitting operator of the user program C as an example, the data preprocessing operator enable number is first written into the configuration register stack of the (3, 5) bit computation unit, the matrix multiplication operator number is written into the configuration register stack of the (4, 5) bit computation unit, the activation function operator number is written into the configuration register stack of the (5, 5) bit computation unit, the branch judgment operator number is written into the configuration register stack of the (5, 5) bit computation unit, the basic multiplication operator number is written into the configuration register stack of the (5, 4) bit computation unit, and the branch merging operator number is written into the configuration register stack of the (3, 5) bit computation unit, and so on.

[0066] In this method, the dynamic reconfigurable chip hardware execution process based on the dataflow architecture is as follows:

[0067] First, the reconfigurable chip receives configuration information from the software programming framework and performs internal hardware configuration, which specifically includes: receiving a computing unit selection signal from the software programming framework to select the computing units participating in the current application computation; receiving data flow direction information from the software programming framework to configure the router corresponding to the computing unit to enable the data link in the corresponding direction and close the routing path in other directions; receiving the computation configuration information of each computing unit from the software programming framework to configure the configuration register stack in the computing unit and determine the configuration register stack data update frequency Fc.

[0068] Subsequently, the software programming framework sends operation data to the initial calculation unit sequentially based on the DC data. Once the calculation unit receives the data, it begins execution.

[0069] For each computing unit participating in the computation, upon receiving the strobe signal sent by the software programming framework, it will configure and start the corresponding computation operator according to the internal configuration register stack information. It is worth noting that within the computing unit, each computation operator is driven by a gating circuit. That is, when not enabled, the corresponding computing module does not participate in the computation and does not generate power consumption. This is the low-power design of this method.

[0070] After the initial computation unit receives the data sent by the software programming framework, it will pass the data into the configuration register stack to configure and start the corresponding computation operator to complete the computation. After the computation is completed, the data will be sent directly to the determined next-level computation unit. The unit will determine whether to change the selected computation operator based on the configuration register stack data update frequency Fc. After the currently selected computation operator completes Fc calculations, it will switch to the next computation operator mode defined by the configuration register stack data.

[0071] After the next-level computing unit receives the data from the starting computing unit, it also passes the data to its selected computing operator to complete the calculation. At the same time, the starting computing unit receives subsequent data sent by the software programming framework and completes synchronous calculation.

[0072] After the data is transmitted to the last calculation unit in the data flow, the last calculation unit completes the calculation defined in its internal configuration register stack and then feeds the result back to the starting calculation unit (at this time, the starting calculation unit has generally completed the iteration of the calculation operators). In this mode, the data will continuously cycle through the selected calculation units until all the operators defined in their respective configuration register stacks are completed, and then the data will be fed back to the software programming framework.

[0073] This invention also provides a dynamically reconfigurable chip implementation device based on a dataflow architecture, comprising: at least one memory and at least one processor;

[0074] The at least one memory is used to store a machine-readable program;

[0075] The at least one processor is used to call the machine-readable program to implement the dynamically reconfigurable chip implementation method based on dataflow architecture described in the above embodiments.

[0076] This invention also provides a computer-readable medium storing computer instructions. When executed by a processor, the computer instructions cause the processor to perform the dynamically reconfigurable chip implementation method based on a dataflow architecture described in the above embodiments. Specifically, a system or apparatus equipped with a storage medium storing software program code that implements the functions of any of the embodiments described above can be provided, and the computer (or CPU or MPU) of the system or apparatus can read and execute the program code stored in the storage medium.

[0077] In this case, the program code read from the storage medium can itself implement the function of any of the above embodiments, and therefore the program code and the storage medium storing the program code constitute part of the present invention.

[0078] Examples of storage media used to provide program code include floppy disks, hard disks, magneto-optical disks, optical disks (such as CD-ROM, CD-R, CD-RW, DVD-ROM, DVD-RAM, DVD-RW, DVD+RW), magnetic tapes, non-volatile memory cards, and ROMs. Alternatively, program code can be downloaded from a server computer via a communication network.

[0079] Furthermore, it should be clear that not only can the program code read by the computer be executed, but also the operating system or other components operating on the computer can be instructed based on the program code to perform some or all of the actual operations, thereby realizing the function of any of the embodiments described above.

[0080] Furthermore, it is understood that the program code read from the storage medium is written to the memory set in the expansion board inserted into the computer or to the memory set in the expansion unit connected to the computer. Then, based on the instructions of the program code, the CPU or other components installed on the expansion board or expansion unit execute some and all of the actual operations, thereby realizing the function of any of the embodiments described above.

[0081] The present invention has been shown and described in detail above with reference to the accompanying drawings and preferred embodiments. However, the present invention is not limited to these disclosed embodiments. Based on the above embodiments, those skilled in the art will know that more embodiments of the present invention can be obtained by combining the code review methods in the different embodiments. These embodiments are also within the protection scope of the present invention.

Claims

1. A method for implementing a dynamically reconfigurable chip based on a dataflow architecture, characterized in that, The user program is parsed through a software programming framework, and the execution of the computing unit is driven by data. The specific implementation includes the following steps: The software programming framework first receives the top-level user program and breaks it down into operator levels, forming a program operator data flow graph. Analyze the number of data elements and program operators that are executed in parallel. Read the configurable depth of computing units and the number of parallel elements that can be processed in a reconfigurable chip; Based on the above parameters, the data stream link length, operation update frequency, and operation grouping method for parallel execution of the program are determined according to the corresponding formulas. Read the number and location of idle computing units in the reconfigurable chip to determine the computing mode and data flow of the computing units; Based on the operator data flow diagram in the data flow chain, complete the writing of operator function configuration and data transmission configuration.

2. The method for implementing a dynamically reconfigurable chip based on a dataflow architecture according to claim 1, characterized in that, The user program includes regular computing tasks, control tasks, and computationally intensive tasks including artificial intelligence and neural networks.

3. The method for implementing a dynamically reconfigurable chip based on a dataflow architecture according to claim 1, characterized in that, The underlying operators supported by the reconfigurable chip include basic addition, subtraction, multiplication, and division operators, activation function operators, matrix operators, convolution operators, pooling operators, normalization operators, and tensor operators.

4. The method for implementing a dynamically reconfigurable chip based on a dataflow architecture according to claim 1, characterized in that, Let the number of data elements executed in parallel by the analysis program be Npn and the number of program operators be Npc; read the configurable depth of the computing unit in the reconfigurable chip be Ncc and the number of parallel elements that can be processed be Ncn. The data flow link length Lc for parallel execution of the program is determined by the formula Lc=(Npn*Npc) / (Ncc*Ncn). This length represents the number of computing units that need to be continuously occupied in order to achieve parallel execution of the program in a reconfigurable chip. The operation update frequency and operation grouping method are determined according to the formula Fc = Npc / Ncc. The operation update frequency represents the number of times the computing unit configuration information is updated during program execution; the operators are grouped according to the number of computing units required. The number of times the software programming framework needs to send data to the reconfigurable chip is determined by the formula Dc = Npn / Ncn.

5. A method for implementing a dynamically reconfigurable chip based on a dataflow architecture according to claim 1 or 4, characterized in that, The hardware operator mapping process for dynamically reconfigurable chips based on a dataflow architecture is as follows: The software programming framework first reads the state of the computing units in the reconfigurable chip to determine the location and number of idle computing units; Based on the number of computing units required by the current user program and the location of available computing units, determine the location of the computing units to be executed by the current user program and the direction of data flow. After determining the location of the computing unit and the direction of data flow, the data composition of the configuration register stack in the selected computing unit is determined according to the operation grouping method.

6. The method for implementing a dynamically reconfigurable chip based on a dataflow architecture according to claim 5, characterized in that, The order of selection for computing units is as follows: (1) Prioritize allocation to computational units in the top-level row; (2) If it is necessary to use a row of calculation units whose first column is empty, the calculation units are selected in a right-up-left sequence; (3) If multiple rows with empty first columns are required, the selection of calculation units is also performed in the same right-up-left sequence.

7. The method for implementing a dynamically reconfigurable chip based on a dataflow architecture according to claim 4, characterized in that, The hardware execution process of a dynamically reconfigurable chip based on a dataflow architecture is as follows: First, the reconfigurable chip receives configuration information from the software programming framework and performs internal hardware configuration, including: receiving a computing unit selection signal from the software programming framework and selecting the computing unit to participate in the current application computation; receiving data flow direction information from the software programming framework and configuring the router corresponding to the computing unit to enable the data link in the corresponding direction and close the routing path in other directions. Receive the computing configuration information of each computing unit sent by the software programming framework, configure the configuration register stack in the computing unit, and determine the configuration register stack data update frequency Fc; Subsequently, the software programming framework sends operation data to the initial calculation unit sequentially based on the Dc data; Once the computing unit receives the data, it begins actual execution. For each computing unit participating in the calculation, after receiving the strobe signal sent by the software programming framework, it will configure and start the corresponding computing operator according to the internal configuration register stack information. After the initial calculation unit receives the data sent by the software programming framework, it passes the data into the configuration register stack for information configuration, starts the corresponding calculation operator to complete the calculation, and directly sends the data to the determined next-level calculation unit after the calculation is completed. It also determines whether the selected calculation operator needs to be changed according to the configuration register stack data update frequency Fc. After the currently selected calculation operator completes Fc calculations, it switches to the calculation operator mode defined by the next configuration register stack data. When the next-level computing unit receives the input data from the starting computing unit, it also inputs the data into the computing operator it has selected to complete the calculation; At the same time, the initial computing unit receives subsequent data sent by the software programming framework and completes synchronous computing; After the data is transmitted to the last calculation unit of the data flow, the last calculation unit completes the calculation defined by the internal configuration register stack and then feeds the calculation result back to the starting calculation unit. In this mode, the data is processed cyclically in the selected computing units until all operators defined in their respective configuration register stacks are completed, and then the data is fed back to the software programming framework.

8. The method for implementing a dynamically reconfigurable chip based on a dataflow architecture according to claim 7, characterized in that, Inside the computing unit, each computing operator is driven by a gating circuit, meaning that when it is not enabled, the corresponding computing module does not participate in the calculation and does not generate power consumption.

9. A dynamically reconfigurable chip implementation device based on a dataflow architecture, characterized in that, include: At least one memory and at least one processor; The at least one memory is used to store a machine-readable program; The at least one processor is configured to invoke the machine-readable program to implement the method according to any one of claims 1 to 8.

10. A computer-readable medium, characterized in that, The computer-readable medium stores computer instructions that, when executed by a processor, implement the method described in any one of claims 1 to 8.

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