A circuit reduction method, apparatus, electronic device, and medium

Abstract

This application provides a circuit reduction method, apparatus, electronic device, and medium. The method includes: eliminating a large number of internal nodes mathematically at once through matrix operations based on nodal admittance matrices and boundary admittance vectors, and calculating the precise equivalent admittance to be added between port nodes, thereby generating a reduced circuit composed of equivalent circuit elements. This significantly reduces the order of the circuit model, greatly reducing the complexity and computational resource consumption of subsequent circuit simulations. Furthermore, because the equivalent admittance is derived from rigorous mathematical derivation and mapped to physical elements, it ensures that the reduced model can accurately reproduce the electrical characteristics of the original circuit in the DC and low-frequency domains, ensuring the reliability and stability of the simulation results.

Description

Technical Field

[0001] This disclosure belongs to the technical field of integrated circuit design automation, and particularly relates to a circuit reduction method, apparatus, electronic device and medium. Background Technology

[0002] With the continuous advancement of integrated circuit technology, the scale of circuits inside modern chips is becoming increasingly larger, involving complex interconnect structures and coupling behaviors. To ensure the reliability and functional correctness of the design, engineers typically need to model the entire system, extract parasitic parameters of interconnects, and perform time-domain simulations after the circuit design is completed to verify whether its delay characteristics, stability, and other properties meet the specifications. This process is a key step in the "integrated circuit design automation" workflow and a significant bottleneck restricting the efficiency of large-scale circuit design.

[0003] To meet the demands of very large-scale integrated circuit (VLSI) design, the equivalent circuit networks generated by parasitic parameter extraction are becoming increasingly large. Traditional simulation programs with integrated circuit emulation (SPICE) exhibit a superlinear relationship between computational complexity and circuit size, making it difficult to meet modern design cycle requirements in terms of simulation timeliness. Therefore, effectively reducing the order of these large-scale circuit networks while ensuring undistorted electrical characteristics has become a crucial technical challenge in the automated back-end design of integrated circuits. Summary of the Invention

[0004] This invention provides a circuit reduction method, apparatus, electronic device, and medium, aiming to solve the problems of high computational complexity and poor parallelism in large-scale integrated circuit simulation.

[0005] The first aspect of this disclosure provides a circuit reduction method, comprising: identifying port nodes and internal nodes in a target circuit; wherein, the port nodes are circuit nodes directly connected to an external circuit, and the internal nodes are nodes in the target circuit other than the port nodes, connected between the port nodes through electrical components; constructing a node admittance matrix based on the electrical connection relationship between the internal nodes; constructing a port admittance relationship representation based on the electrical connection relationship between the port nodes and the internal nodes; performing matrix operations based on the node admittance matrix and the port admittance relationship representation to calculate the equivalent admittance that needs to be added between any two port nodes, and mathematically eliminating the internal nodes through the matrix operations; determining the parameter values ​​of the equivalent circuit elements that need to be added between corresponding port node pairs based on the calculated equivalent admittance, and adding the equivalent circuit elements configured with the parameter values ​​between the corresponding port nodes to generate a reduced circuit.

[0006] In the first aspect of the embodiment, the port admittance relationship representation is composed of admittance relationship vectors corresponding to each port node; the construction of the port admittance relationship representation includes: distinguishing the internal nodes into ordinary internal nodes and boundary nodes, wherein the ordinary internal nodes are internal nodes that have no direct admittance connection with any port node, and the boundary nodes are internal nodes that have a direct admittance connection with at least one of the port nodes; constructing a corresponding admittance relationship vector for each port node, wherein in the admittance relationship vector: when the internal node is a boundary node of the port node, the element at the corresponding position takes the actual admittance value between the port node and the internal node; when the internal node is an ordinary internal node of the port node, the element at the corresponding position takes a zero value.

[0007] In the first aspect of the embodiment, the equivalent admittance required to be added between any two port nodes is calculated using the following formula:

[0008]

[0009] in, This represents the equivalent admittance that needs to be added between port nodes p and q; K represents the total number of internal nodes; N i This represents the i-th internal node; This represents the relationship between port node p and internal node N. i The admittance relationship between the row vectors; Indicates internal node N i The row and column vectors representing the admittance relationship between the port node q and the port node q; Let i represent the i-th standard unit vector, which has a dimension of K×1, and the i-th element is 1 and the rest are 0; express The transpose of ; Y represents the node admittance matrix composed of all internal nodes after grounding all port nodes; Let Y be the inverse matrix.

[0010] In an embodiment of the first aspect, the equivalent circuit elements are equivalent capacitance elements and equivalent conductance elements.

[0011] In the first aspect embodiment, the formula for calculating the equivalent conductance value added between the port nodes is as follows:

[0012]

[0013] in, This represents the equivalent conductance added between port nodes p and q; K represents the total number of internal nodes; Ni and Nj represent the i-th and j-th internal nodes, respectively. This represents the electrical conductance between port node p and internal node Ni; This represents the relationship between port node q and internal node N. j The electrical conductance values ​​between nodes; G represents the electrical conductance matrix between internal nodes, with dimensions K×K; Let represent the element in the i-th row and j-th column of the inverse matrix of matrix G.

[0014] In the first aspect embodiment, the formula for calculating the equivalent capacitance added between the port nodes is:

[0015]

[0016]

[0017] in, This represents the equivalent capacitance value added between port nodes p and q; K represents the total number of internal nodes; Ni and Nj represent the i-th and j-th internal nodes, respectively. This represents the electrical conductance between port node p and internal node Ni; This represents the relationship between port node q and internal node N. j The electrical conductance values ​​between; This represents the relationship between port node p and internal node N. i The capacitance values ​​between; G represents the capacitance value between port node q and internal node Nj; G represents the conductance matrix between internal nodes; C represents the capacitance matrix between internal nodes, with dimensions K×K; Let represent the element in the i-th row and j-th column of the inverse matrix of matrix G.

[0018] In the first aspect of the embodiment, before identifying the port nodes and internal nodes in the target circuit, the method further includes: determining whether the total number of nodes in the target circuit exceeds a preset scale threshold; when the total number of nodes exceeds the scale threshold, using a graph partitioning algorithm to divide the target circuit into multiple interconnected sub-circuits; for each of the sub-circuits obtained by partitioning, executing the circuit reduction method described in the above embodiment in parallel; and integrating the reduced sub-circuits according to the connection relationship between the sub-circuit blocks of the target circuit before partitioning to generate a complete reduced circuit.

[0019] In the first aspect of the embodiment, when the graph partitioning algorithm is the METIS algorithm, the target circuit is partitioned into multiple interconnected sub-circuits, including: abstracting the topology of the target circuit into an undirected graph, where nodes correspond to circuit nodes and edges correspond to component connections; performing a multi-level graph partitioning process, including: forming supernodes by iteratively merging highly connected node pairs, generating a series of coarsened graphs composed of supernodes with progressively decreasing scale until a preset scale threshold is reached; partitioning the final coarsened graph to obtain multiple sub-graph partitions, and controlling the difference in the number of nodes between each sub-graph within a preset tolerance; expanding the partitioned coarsened graph layer by layer to the original graph scale in reverse order of generation, and applying the Kernighan-Lin algorithm or the Fiduccia-Mattheyses algorithm to locally optimize the partitioning boundary at each expansion level to minimize the number of connecting edges between sub-graphs; and partitioning the target circuit into multiple interconnected sub-circuits according to the optimized partitioning result.

[0020] In an embodiment of the first aspect, the method further includes triggering an internal node retention mechanism when the total number of nodes in the target circuit exceeds a preset complexity threshold, or when the user-specified reduction accuracy requirement is higher than a preset accuracy threshold; the internal node retention mechanism includes: selecting a set number of nodes from the internal nodes to retain, the number of retained nodes being determined according to a preset retention ratio or absolute number; the matrix operation is performed only on the unretained internal nodes.

[0021] In an embodiment of the first aspect, the selection of internal nodes to be retained is determined based on at least one of the following criteria: selecting nodes to be retained in descending order of time constant value according to the time constant attribute of the internal nodes; or selecting nodes to be retained in descending order of the shortest path distance between the nodes and other internal nodes according to the distribution attribute of the internal nodes in the circuit topology.

[0022] A second aspect of this disclosure provides a circuit reduction apparatus, comprising: an identification module for identifying port nodes and internal nodes in a target circuit; wherein the port nodes are circuit nodes directly connected to an external circuit, and the internal nodes are nodes in the target circuit other than the port nodes, connected between the port nodes via electrical components; a matrix construction module for constructing a node admittance matrix based on the electrical connection relationship between the internal nodes; an admittance relationship construction module for constructing a port admittance relationship representation based on the electrical connection relationship between the port nodes and the internal nodes; an equivalent admittance calculation module for performing matrix operations based on the node admittance matrix and the port admittance relationship representation to calculate the equivalent admittance that needs to be added between any two port nodes, and mathematically eliminating the internal nodes through the matrix operations; and a generation module for determining the parameter values ​​of the equivalent circuit elements that need to be added between corresponding port node pairs based on the calculated equivalent admittance, and adding the equivalent circuit elements configured with the parameter values ​​between the corresponding port nodes to generate a reduced circuit.

[0023] A third aspect of this disclosure discloses an electronic device comprising: a processor and a memory; wherein the memory is configured to store a computer program; and the processor is configured to execute the computer program stored in the memory to cause the electronic device to perform a circuit reduction method as described in any of the first aspects.

[0024] The fourth aspect of this disclosure discloses a computer-readable storage medium having a computer program stored thereon, which, when executed by an electronic device, implements the circuit reduction method described in any of the first aspects.

[0025] As described above, the circuit reduction method, apparatus, electronic device, and medium provided in this disclosure have at least the following technical effects:

[0026] (1) By performing matrix operations based on the nodal admittance matrix and the boundary admittance vector, a large number of internal nodes are eliminated at the mathematical level at once, and the accurate equivalent admittance to be added between the port nodes is calculated. Based on this, a reduced circuit composed of equivalent circuit elements is generated. This achieves a significant reduction in the order of the circuit model, greatly reducing the complexity and computational resource consumption of subsequent circuit simulations. At the same time, since the equivalent admittance is derived from rigorous mathematical derivation and mapped to physical elements, it ensures that the reduced model can accurately reproduce the electrical characteristics of the original circuit in the DC and low-frequency domains, ensuring the reliability and stability of the simulation results.

[0027] (2) A divide-and-conquer strategy based on graph partitioning algorithm is introduced, which divides the circuit into multiple sub-circuits and processes them in parallel, and finally merges the results. This effectively breaks through the computational bottleneck of traditional serial reduction methods when processing circuits with hundreds of millions of nodes. Parallel processing greatly improves the reduction efficiency and shortens the design cycle. At the same time, this partitioning strategy strives to ensure that the scale of each sub-circuit is balanced and the interconnection is minimized, which minimizes the complexity of subsequent merging operations and makes it possible to quickly analyze and verify ultra-large-scale circuits.

[0028] (3) The METIS multi-level graph partitioning algorithm adopted achieves the optimization goals of load balancing and minimizing cut edges through three stages: shrinking, initial partitioning, and optimization restoration. It can generate high-quality sub-circuit partitioning schemes, ensuring that the computational load of each sub-task is similar, making full use of parallel computing resources, and avoiding the efficiency drop caused by uneven load. At the same time, the extremely small number of cut edges minimizes the mutual influence between sub-circuits, ensuring the accuracy of block reduction and providing a solid foundation for subsequent merging.

[0029] (4) A triggerable, criterion-configurable internal node retention mechanism is introduced, allowing dynamic selection of key internal nodes to be retained based on circuit size or accuracy requirements. It provides a flexible means of balancing accuracy and efficiency. Users can set retention ratios or select criteria to selectively retain nodes that have a significant impact on circuit characteristics while ensuring reduction efficiency. This enables proactive control of reduction errors and significantly improves the accuracy of the reduction model in specific frequency bands or characteristics of interest, meeting the needs of high-precision design verification. Attached Figure Description

[0030] Figure 1 A schematic flowchart of a circuit reduction method according to an embodiment of the present disclosure is shown.

[0031] Figure 2 A schematic diagram of the nodes of the target circuit in one embodiment of this disclosure is shown.

[0032] Figure 3 A schematic flowchart illustrating the partitioning of the target circuit is shown in one embodiment of this disclosure.

[0033] Figure 4 A flowchart illustrating the multi-level graph partitioning steps is shown in another embodiment of this disclosure.

[0034] Figure 5 A flowchart illustrating the METIS algorithm in another embodiment of this disclosure is shown.

[0035] Figure 6 A flowchart illustrating a specific application example of this disclosure is provided.

[0036] Figure 7 A schematic diagram of a circuit reduction device module is shown in one embodiment of this disclosure.

[0037] Figure 8 A schematic diagram of the circuit structure of an electronic device according to an embodiment of the present disclosure is shown. Detailed Implementation

[0038] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, unless otherwise specified, the following embodiments and features described therein can be combined with each other.

[0039] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0040] To address the performance bottlenecks in large-scale circuit simulation, researchers have proposed various model reduction methods. The basic idea is to eliminate internal redundant nodes while preserving key inputs and outputs, thereby reducing the dimensionality of the circuit system and improving simulation efficiency. Current mainstream methods fall into two main categories: subspace projection-based methods and node elimination-based methods.

[0041] Representative methods for subspace projection-based model order reduction include the Krylov subspace projection method and the PRIMA Passive Reduced-Order Interconnect Macromodeling Algorithm. The core idea of ​​these methods is to map the original large-scale circuit system model to a lower-dimensional space using projection principles, thereby accelerating simulation. However, since the projected model is a mathematical model, it is difficult to map to an actual RC network, making these methods physically unrealizable.

[0042] Another type of model reduction method is based on node elimination, which reduces the order of the circuit network according to its topology, node attributes, and edge attributes. A widely studied and applied method is the TICER method, which reduces the network size by eliminating internal nodes in the RC network that meet the elimination criteria. Simultaneously, it connects the neighboring nodes of the eliminated nodes according to the algorithm to maintain the circuit's characteristics. The TICER algorithm is very flexible, allowing free selection of the nodes to be eliminated and their order based on connectivity and time constants, and is not limited by the number of ports, making it suitable for large-scale circuits. However, the one-dimensional TICER algorithm is not very efficient because each time a node is eliminated, the connectivity and attributes of the remaining nodes change, requiring recalculation of node degree and time constant.

[0043] This disclosure proposes a physically realizable parallel reduction method for high-dimensional large-scale circuits, which consists of two core parts. First, it employs a graph-based adaptive circuit partitioning strategy. This strategy adaptively determines the number of circuit partitions by balancing the speed and compression rate of model reduction, decomposing the large-scale circuit into sub-circuits, and utilizes multi-threaded parallel reduction to accelerate the algorithm. Second, this technical solution proposes a high-dimensional extension of the TICER method, namely the HD-TICER method.

[0044] The HD-TICER method is based on the principle of driving node impedance. Its core technology lies in strictly maintaining the total current flowing from each port node before and after order reduction. Specifically, this principle uses mathematical transformation to precisely equate the current flowing from one port node into the internal node network to the sum of a set of currents flowing directly to all other port nodes. Based on this principle, HD-TICER can capture and eliminate the entire circuit block composed of all internal nodes in one go, and add precisely calculated resistors and capacitors between the original port nodes of the eliminated circuit to form an equivalent circuit. This ensures a high degree of consistency in the port electrical characteristics of the circuit before and after order reduction, achieving physically realizable rapid model order reduction.

[0045] The technical solutions of the present invention will now be described in detail with reference to the accompanying drawings.

[0046] like Figure 1 The diagram shows a flowchart of the circuit reduction method of the first aspect of this disclosure, including steps S110-S150, wherein...

[0047] Step S110: Identify port nodes and internal nodes in the target circuit; wherein, the port node is a circuit node directly connected to the external circuit, and the internal node is a node in the target circuit other than the port node, which is connected between the port nodes through electrical components.

[0048] Specifically, the identification process includes: traversing the netlist or equivalent circuit description file of the target circuit, marking circuit nodes directly connected to external power supplies, signal sources, or other functional modules as port nodes; and marking the remaining circuit nodes interconnected through basic circuit elements such as resistors, capacitors, inductors, or transistors, and located between port nodes, as internal nodes. For circuits containing ground nodes, the ground nodes are forcibly classified as port nodes to ensure the integrity of the DC solution of the circuit.

[0049] For example, such as Figure 2 As shown, a target circuit module is illustrated, where nodes N1, N2, N3...N k The nodes represent the internal nodes of the target circuit, and nodes 1, 2, 3...m represent the port nodes of the RC circuit.

[0050] Step S120: Construct the node admittance matrix based on the electrical connection relationship between the internal nodes.

[0051] Specifically, the construction process of the node admittance matrix includes: extracting the interconnection admittance information between all internal nodes to form a K×K dimensional matrix Y (where K is the total number of internal nodes). The diagonal elements of this matrix Y... ii Y represents the sum of all admittances connected to the i-th internal node; the off-diagonal element Y ij (i≠j) represents the negative of the admittance value of the direct connection between node i and node j. For an RC circuit, this admittance matrix can be expressed as Y = G + sC, where G is the conductance matrix, C is the capacitance matrix, and s is the complex frequency variable.

[0052] For example, consider an RC circuit segment containing three internal nodes (N1, N2, N3), where: a conductance g is connected between N1 and N2. 12 and capacitor c 12 A conductivity g is connected between N2 and N3. 23 and capacitor c 23 A capacitor c1g is connected between N1 and ground; a conductor g2g is connected between N2 and ground. The corresponding nodal admittance matrix Y can then be constructed as follows:

[0053] ,

[0054] This matrix accurately characterizes the electrical properties of the internal node network, providing a mathematical basis for subsequent node elimination operations.

[0055] Step S130: Construct a port admittance relationship representation based on the electrical connection relationship between the port node and the internal node.

[0056] In some implementations, the port admittance relationship representation is composed of admittance relationship vectors corresponding to each port node; constructing the port admittance relationship representation includes:

[0057] The internal nodes are divided into ordinary internal nodes and boundary nodes. The ordinary internal nodes are internal nodes that have no direct admittance connection with any port node, and the boundary nodes are internal nodes that have a direct admittance connection with at least one of the port nodes.

[0058] For each port node, a corresponding admittance relationship vector is constructed. In the admittance relationship vector: when the internal node is the boundary node of the port node, the element at the corresponding position takes the actual admittance value between the port node and the internal node; when the internal node is an ordinary internal node of the port node, the element at the corresponding position takes a zero value.

[0059] For example, for each port node p, construct a K-dimensional column vector v p (Where K is the total number of internal nodes), the i-th element of this vector represents the relationship between port node p and the i-th internal node N. i The admittance value between. When the internal node N i When it is a boundary node of port node p (i.e., there is a direct electrical connection), this element takes the actual admittance value; when it is an internal node N... i When the element is a regular internal node (i.e., not directly connected to port node p), it takes the value of zero. For a circuit containing m port nodes, the column vectors v1, v2, ..., v corresponding to all port nodes are represented as follows: m Combined, they form the port admittance relation matrix V, which has a dimension of K×m.

[0060] For example, consider a circuit containing three internal nodes (N1, N2, N3) and two port nodes (p, q). Port node p is directly connected only to internal node N1, and its admittance is g. p N1 + sc p N1; Port node q is directly connected to internal nodes N2 and N3, with admittance values ​​g respectively. q N2 + sc q N2 and g q N3 + sc q N3; Internal node N2 is a normal internal node and has no direct connection to port node p. Therefore, the corresponding port admittance relation matrix V can be constructed as follows:

[0061] ,

[0062] Wherein, the first column corresponds to the admittance vector v of port node p. pThe second column corresponds to the admittance vector v of port node q. q This representation accurately captures the connection relationships between port nodes and the internal node network, providing complete input data for subsequent matrix operations.

[0063] Step S140: Perform matrix operations based on the node admittance matrix and the port admittance relationship representation to calculate the equivalent admittance that needs to be added between any two port nodes, and mathematically eliminate the internal nodes through the matrix operations.

[0064] In some implementations, the equivalent admittance required between any two port nodes is calculated using the following formula:

[0065]

[0066] in, This represents the equivalent admittance that needs to be added between port nodes p and q; K represents the total number of internal nodes; N i This represents the i-th internal node; This represents the relationship between port node p and internal node N. i Admittance values ​​between; Indicates internal node N i The admittance value between the port node q; Let i represent the i-th standard unit vector, which has a dimension of K×1, and the i-th element is 1 and the rest are 0; express The transpose of ; Y represents the node admittance matrix composed of all internal nodes after grounding all port nodes; Let Y be the inverse matrix.

[0067] Specifically, the formula achieves mathematical elimination of internal nodes through three key steps:

[0068] First, extract the boundary coupling relationship. The operation integrates the dispersed admittance relationships between the port node p and each internal node into a K-dimensional column vector v. p When internal node N i When it is a boundary node of p, Take the actual value; take 0 when it is a normal internal node, and similarly obtain the coupling vector v of the port node q. q .

[0069] Then, solve for the internal network response. Invert the internal node admittance matrix Y to obtain Yi. -1 This inverse matrix characterizes the equivalent impedance properties of the internal node network. Operation v p T Y -1 This can be understood as the voltage distribution generated in the internal network when the excitation is injected from port p.

[0070] Finally, synthesize the equivalent admittance. Calculate v. p T Y -1 v q This is equivalent to mapping the coupling relationship at port q to the response generated at port p. The physical essence of this operation is calculating the voltage response ratio at port q resulting from injecting current into port p.

[0071] For example, consider a circuit containing 2 internal nodes (N1, N2) and 2 port nodes (p, q): p is connected only to N1; y p,N1 =g1+sc1, since y is not connected to N2, therefore y p,N2 =0. q is connected to both N1 and N2: y N1,q =g2+sc2,y N2,q =g3+sc3, the internal nodal admittance matrix Y is a 2×2 matrix, then the calculation process is as follows:

[0072]

[0073]

[0074] Through this operation, the two internal nodes N1 and N2, which originally needed to be retained, are mathematically eliminated, and only the admittance value is added between ports p and q. The equivalent components can maintain the consistency of the external characteristics of the circuit.

[0075] Step S150: Based on the calculated equivalent admittance, determine the parameter values ​​of the equivalent circuit elements that need to be added between the corresponding port node pairs, and add the equivalent circuit elements configured with the parameter values ​​between the corresponding port nodes to generate the reduced circuit.

[0076] In some implementations, the equivalent circuit elements are specifically equivalent capacitance elements and equivalent conductance elements. The core of this step lies in physically realizing the equivalent admittance (which is a function of complex frequency s) obtained from the aforementioned matrix operation. Specifically, this is achieved by performing a Taylor expansion on the equivalent admittance function and extracting the zero-order coefficient of s as the equivalent conductance value, and extracting the first-order coefficient of s as the equivalent capacitance value.

[0077] The specific formula for calculating the equivalent conductance is as follows:

[0078]

[0079] in, This represents the equivalent conductance added between port nodes p and q; K represents the total number of internal nodes; N i and N j Let i and j represent the i-th and j-th internal nodes, respectively. This represents the relationship between port node p and internal node N. i The electrical conductance values ​​between; This represents the relationship between port node q and internal node N. j The electrical conductance values ​​between nodes; G represents the electrical conductance matrix between internal nodes, with dimensions K×K; Let represent the element in the i-th row and j-th column of the inverse matrix of matrix G.

[0080] The physical significance of this formula lies in the fact that, through a double summation operation, it accurately captures the path from port p through the internal node network (whose characteristics are determined by G). -1 The total effect of all possible conductive paths to port q is characterized, thus mathematically equivalent to the DC (s=0) conductivity of the eliminated internal node network.

[0081] The formula for calculating the equivalent capacitance is relatively complex and aims to characterize the frequency-dependent characteristics of the circuit. The formula for calculating the equivalent capacitance added between the port nodes is as follows:

[0082]

[0083]

[0084] in, This represents the initial equivalent capacitance value added between port nodes p and q; This represents the final equivalent capacitance added between port nodes p and q; K represents the total number of internal nodes; N i and N j Let i and j represent the i-th and j-th internal nodes, respectively. This represents the electrical conductance between port node p and internal node Ni; This represents the relationship between port node q and internal node N. j The electrical conductance values ​​between; This represents the relationship between port node p and internal node N. i The capacitance values ​​between; This represents the relationship between port node q and internal node N. j The capacitance values ​​between nodes; G represents the conductance matrix between internal nodes; C represents the capacitance matrix between internal nodes, with dimensions K×K; Let represent the element in the i-th row and j-th column of the inverse matrix of matrix G.

[0085] The first summation in this formula reflects the coupling effect through the conductance-capacitance path and the capacitance-conductance path, while the second summation is a correction term for the secondary modulation of the internal capacitor network through the conductance network. It is particularly important to emphasize that, to ensure the physical realizability and stability of the generated circuit, when the calculated... When the value is negative, this method sets it to zero, meaning that the capacitor element is not added.

[0086] For example, for an RC circuit, after successfully calculating the equivalent conductance and equivalent capacitance between a pair of port nodes p and q... (And its value is positive) then, a resistor with a resistance of 1 / is connected in parallel between nodes p and q. A resistor and a capacitor with a capacitance value The capacitors. By traversing all the port node pairs that need to be connected and performing this operation, the original circuit with complex internal nodes can be simplified into a minimal circuit model consisting only of port nodes and the equivalent resistance and capacitance connected between them, thus greatly reducing the complexity of circuit simulation and analysis.

[0087] In some implementations, adaptive graph segmentation is further included before identifying port nodes and internal nodes in the target circuit, such as... Figure 3 As shown, it includes steps S210-S240.

[0088] Step S210: Determine whether the total number of nodes in the target circuit exceeds a preset scale threshold.

[0089] Specifically, the scale threshold is set based on at least one of the following factors: the memory capacity of available computing resources, the preset reduction computation time target, and the required reduction accuracy. This judgment step constitutes the decision basis for the adaptive graph partitioning, and its core purpose is to achieve an adaptive balance between computational efficiency and reduction accuracy.

[0090] When the total number of nodes in the target circuit does not exceed the scale threshold, it indicates that the circuit size can be directly reduced as a whole, and the process proceeds directly to the subsequent node identification and matrix operation steps. When the total number of nodes in the target circuit exceeds the scale threshold, a graph partitioning mechanism is triggered because directly performing matrix operations on the entire circuit (especially large-scale matrix inversion) will face problems of high computational complexity, large memory consumption, and poor numerical stability. By dividing the large-scale circuit into multiple sub-circuits for parallel processing, the dimensionality of a single computational task can be significantly reduced, and parallel computing resources can be fully utilized, thereby completing the reduction of ultra-large-scale circuits within an acceptable time. The scale threshold can be set to a fixed value (e.g., 10,000 nodes) or designed as a variable that is dynamically adjusted according to available computing resources, thereby achieving an adaptive match between processing capacity and problem size.

[0091] Step S220: When the total number of nodes exceeds the scale threshold, the target circuit is divided into multiple interconnected sub-circuits using a graph partitioning algorithm.

[0092] In some implementations, when the graph partitioning algorithm is the METIS algorithm, the target circuit is divided into multiple interconnected sub-circuits, including:

[0093] First, the topology of the target circuit is abstracted as an undirected graph, where the nodes of the graph correspond to the circuit nodes, and the edges correspond to the connection relationships of components (such as resistors and capacitors) in the circuit. The weights of the edges can be set according to the admittance value of the connected components or a preset importance index.

[0094] Then, the multi-level graph partitioning process is performed, such as... Figure 4 As shown, it includes steps S221-S224.

[0095] S221, by iteratively merging highly connected node pairs to form supernodes, a series of coarsened graphs consisting of supernodes with progressively decreasing size are generated until a preset size threshold is reached.

[0096] Specifically, in each coarsening layer, the algorithm selects matching node pairs based on edge weights to merge, forming new supernodes, and updates edge weights until the graph size reaches a preset coarsening threshold. This process significantly reduces the complexity of the original graph, preparing it for subsequent partitioning.

[0097] S222, the final coarsened map is divided into multiple sub-maps, and the difference in the number of nodes between each sub-map is controlled within a preset tolerance.

[0098] Specifically, the coarsened graph is partitioned using a recursive binary search or direct multi-way partitioning strategy to divide the coarsened graph into a predetermined number of subgraphs. During the partitioning process, the goal is to minimize the cut edge weights (i.e., the connection weights between subgraphs), while constraining each subgraph to contain as many nodes (or weights) as possible, with the difference controlled within a predetermined tolerance.

[0099] S223 expands the coarsened graph after partitioning to the size of the original graph layer by layer in reverse order of generation, and applies the Kernighan-Lin algorithm or the Fiduccia-Mattheyses algorithm to locally optimize the partitioning boundary at each expansion level in order to minimize the number of connecting edges between subgraphs.

[0100] Specifically, at each restoration level, local optimization methods such as the Kernighan-Lin (KL) algorithm or the Fiduccia-Mattheyses (FM) algorithm are applied to tentatively move nodes on the partition boundary, evaluate their impact on the cut edge weights, and accept moves that can optimize the partition quality (i.e., further reduce the number or weight of connecting edges between subgraphs), thereby continuously optimizing the partition results while restoring the details of the original graph.

[0101] S224, based on the optimized partitioning results, divide the target circuit into multiple interconnected sub-circuits.

[0102] Specifically, based on the optimized partitioning results, each circuit node in the original target circuit is assigned to a specific subgraph, thereby dividing the entire circuit into multiple interconnected sub-circuits. Each sub-circuit contains a portion of the nodes of the original circuit and its internal connections, and the sub-circuits are interconnected through boundary nodes (i.e., the circuit nodes corresponding to the dividing edges).

[0103] like Figure 5 The diagram shows the flowchart of the METIS algorithm in the above implementation, illustrating the process of gradually simplifying the structure of the input undirected graph through a shrinking phase, then gradually restoring and optimizing the partitioning through a multi-level unfolding phase, and finally obtaining an output undirected graph with clear subgraph partitioning.

[0104] Step S230: For each of the sub-circuits obtained by partitioning, perform the circuit reduction method as described above in parallel.

[0105] Specifically, each sub-circuit obtained after dividing a large-scale circuit is regarded as an independent circuit unit, and the aforementioned circuit reduction process is performed on each sub-circuit unit.

[0106] In this embodiment, the reduction process of each sub-circuit is independent of each other, so parallel processing can be achieved in a multi-core processor or distributed computing environment. This significantly reduces the reduction time of large-scale circuits from the O(n³) level of traditional serial processing to near-linear complexity, greatly improving the analysis efficiency of very large-scale circuits.

[0107] Step S240: Based on the connection relationship between the sub-circuit blocks of the target circuit before division, integrate the reduced sub-circuits to generate a complete reduced circuit.

[0108] Specifically, after completing the parallel reduction of all sub-circuits, these reduced sub-circuit modules need to be reassembled into a complete circuit. The integration process is based on the topological connection information recorded during the original circuit partitioning, and specifically includes: first, identifying the boundary nodes in each reduced sub-circuit that correspond to the original circuit connection relationships (i.e., the nodes corresponding to the cut edges generated during partitioning); then, restoring the necessary connecting elements between these boundary nodes according to the connection relationships of the original circuit.

[0109] In this implementation, since each sub-circuit, after reduction, retains only its port nodes and equivalent elements between nodes, the final integrated circuit will consist of these equivalent elements and connecting elements, forming a simplified model with a significantly reduced size but maintaining a high degree of approximation to the original circuit's DC and low-frequency characteristics. This step ensures the integrity of the "divide and conquer" strategy, and the final simulable network maintains both computational accuracy and extremely high simulation efficiency.

[0110] In some implementations, to improve circuit reduction accuracy, the circuit reduction method further includes an internal node preservation mechanism. This mechanism is triggered when the following conditions are met:

[0111] The simulation is initiated when the total number of nodes in the target circuit exceeds a preset complexity threshold, or when the user-specified reduction accuracy requirement is higher than a preset accuracy threshold. The complexity threshold is typically set based on available computing resources and circuit characteristics, while the accuracy threshold is determined according to simulation requirements.

[0112] The core operation of the internal node retention mechanism includes two key steps: First, a set number of nodes are selected from the set of internal nodes to be retained. The number of nodes to be retained can be determined by a preset retention ratio (such as retaining 5% of the total number of internal nodes) or an absolute number (such as retaining a fixed 100 nodes); Second, in subsequent matrix operations, only the internal nodes that are not retained are eliminated, while the retained nodes will continue to exist in the reduced circuit as newly added port nodes.

[0113] For example, the selection of retained internal nodes is determined based on the following criteria: First, nodes with larger time constants are prioritized for retention, in descending order. This is because nodes with larger time constants typically correspond to low-frequency dominant poles in the circuit, having a more significant impact on the circuit's low-frequency characteristics. Retaining these nodes helps maintain the circuit's dynamic response accuracy. Second, based on the distribution of internal nodes in the circuit topology, nodes are selected for retention in descending order of the shortest path distance to other internal nodes. This criterion aims to retain nodes located at the edges of the topology or with sparse connections. These nodes often contain unique circuit state information, and their retention helps maintain the integrity of the circuit structure, avoiding the loss of topological features due to excessive reduction.

[0114] In this embodiment, through this selective retention mechanism, the method can significantly improve the accuracy of the reduced circuit model while maintaining computational efficiency, especially in terms of high-frequency characteristics and transient response.

[0115] To better illustrate the technical solution of this application, the following will be combined with... Figure 6 Provide a complete application example.

[0116] Suppose there is a medium-sized RC circuit containing 100 nodes (2 external port nodes and 98 internal nodes). The preset size threshold is 50 nodes. The processing flow is as follows:

[0117] First, input this 100-node RC network. The system determines that its number of nodes (100) is greater than the threshold (50), so the process moves to the "yes" branch, triggering the adaptive graph partitioning process.

[0118] Then, the system invokes a graph partitioning algorithm (such as METIS) to divide the entire circuit into four interconnected sub-circuits. The goal of the partitioning is to ensure that each sub-circuit has approximately the same number of nodes (e.g., about 25 nodes each) and to minimize the number of connections between the sub-circuits.

[0119] Next, these four sub-circuits will be processed in parallel. For each sub-circuit:

[0120] First, identify the nodes that connect the sub-circuit to other sub-circuits and mark these nodes as "port nodes" of the sub-circuit. Nodes entirely located inside the sub-circuit are marked as "internal nodes." Then, apply the HD-TICER algorithm independently to each sub-circuit. This process eliminates all internal nodes of the sub-circuit through matrix operations, ultimately generating and adding equivalent resistive and capacitive elements only between the port nodes of the sub-circuit.

[0121] After all sub-circuits have been reduced in order, four simplified circuit modules are obtained. At this point, based on the connection relationships recorded during the initial partitioning, these modules are reconnected at their common port nodes and merged into a complete new RC network.

[0122] The final output circuit will have far fewer nodes than the original 100 nodes (it may only have a dozen or so nodes left, i.e., the port nodes of each sub-circuit), but it is highly similar to the original circuit in important electrical characteristics, thus achieving efficient model reduction.

[0123] In contrast, if the circuit above has only 30 nodes (less than the threshold of 50), the process will proceed to the "No" branch. The system will skip the partitioning step and directly apply the HD-TICER algorithm to the entire circuit, eliminating all internal nodes at once and quickly obtaining the reduction result.

[0124] It should be specifically noted that the flowchart representations of the embodiments described above in this disclosure can be understood as representing modules, segments, or portions of code comprising one or more sets of executable instructions configured to implement specific logical functions or processes. Furthermore, the scope of the preferred embodiments of this disclosure includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functions involved.

[0125] like Figure 7 As shown, a circuit reduction device 700 of this disclosure is illustrated. It should be noted that the principle and technical implementation of the circuit reduction device can refer to an embodiment of a circuit reduction method in the previous embodiments (e.g., Figure 1 Therefore, this embodiment will not repeat the details.

[0126] Specifically, the circuit reduction device 700 includes: an identification module 710, a matrix construction module 720, an admittance relationship construction module 730, an equivalent admittance calculation module 740, and a generation module 750, wherein,

[0127] The identification module 710 is used to identify port nodes and internal nodes in the target circuit; wherein, the port node is a circuit node directly connected to an external circuit, and the internal node is a node in the target circuit other than the port node, which is connected between the port nodes through electrical components.

[0128] The matrix construction module 720 is used to construct a node admittance matrix based on the electrical connection relationship between the internal nodes;

[0129] The admittance relationship construction module 730 is used to construct a port admittance relationship representation based on the electrical connection relationship between the port node and the internal node;

[0130] The equivalent admittance calculation module 740 is used to perform matrix operations based on the node admittance matrix and the port admittance relationship representation to calculate the equivalent admittance that needs to be added between any two port nodes, and to mathematically eliminate the internal nodes through the matrix operations.

[0131] The generation module 750 is used to determine the parameter values ​​of the equivalent circuit elements that need to be added between the corresponding port node pairs based on the calculated equivalent admittance, and to add the equivalent circuit elements configured with the parameter values ​​between the corresponding port nodes to generate the reduced circuit.

[0132] It should be noted that, Figure 7The various functional modules in the embodiments can be implemented, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, they can be implemented, in whole or in part, in the form of a program instruction product. A program instruction product includes one or a set of program instructions. When the program instructions are loaded and executed on a computer, all or part of the flow or function according to this disclosure is generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The program instructions can be stored in a computer-readable storage medium or transferred from one computer-readable storage medium to another.

[0133] and, Figure 7 The apparatus disclosed in the embodiments can be implemented through other modular division methods. The apparatus embodiments shown above are merely illustrative. For example, the module division is only a logical functional division, and in actual implementation, there may be other division methods. For example, a group of modules or modules may be combined or dynamically integrated into another system, or some features may be ignored or not executed. Furthermore, the shown or discussed mutual coupling, direct coupling, or communication connection may be through some interfaces, and the indirect coupling or communication connection between devices or modules may be electrical or other forms.

[0134] in addition, Figure 7 The functional modules and sub-modules in the embodiments can be dynamically integrated within a single processing unit, or each module can exist physically independently, or two or more modules can be dynamically integrated within a single unit. These dynamic units can be implemented in hardware or as software functional modules. If these dynamic units are implemented as software functional modules and sold or used as independent products, they can also be stored in a computer-readable storage medium. This storage medium can be a read-only memory, a hard disk, or an optical disk, etc.

[0135] like Figure 8 The diagram shown illustrates the structure of an electronic device according to an embodiment of this disclosure.

[0136] The electronic device can execute computer program instructions to perform tasks such as... Figure 1 The method in any of the above. For example, the electronic device may be a server group / server, a desktop computer, a laptop computer, etc., or a cloud-based server / server group, a distributed computing node system, etc., that communicates remotely with a local terminal.

[0137] The electronic device 800 includes a bus 810, a processor 820, and a memory 830. The processor 820 and the memory 830 can communicate via the bus 810. The memory 830 can store program instructions. The processor 820 implements the method steps in the previous embodiments by running the program instructions in the memory 830, for example... Figure 1 Any one of the methods.

[0138] Bus 810 can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of representation, although only one thick line is used in the diagram, this does not indicate that there is only one bus or one type of bus.

[0139] In some embodiments, processor 820 may be implemented as a central processing unit (CPU), microprocessor unit (MCU), system-on-chip (SoC), or field-programmable array (FPGA). Memory 830 may include volatile memory for temporary data storage during program execution, such as random access memory (RAM).

[0140] The memory 830 may also include non-volatile memory for data storage, such as read-only memory (ROM), flash memory, hard disk drive (HDD), or solid-state disk (SSD).

[0141] In some embodiments, the electronic device 800 may further include a communicator 840. The communicator 840 is used for communication with external devices. In specific examples, the communicator 840 may include one or more wired and / or wireless communication circuit modules. For example, the communicator 840 may include one or more of, such as a wired network card, a USB module, a serial interface module, etc. The wireless communication protocols followed by the wireless communication module include, for example, Nearfield Communication (NFC) technology, Infrared (IR) technology, Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Wideband Code Division Multiple Access (WCDMA), Time-Division Code Division Multiple Access (TD-SCDMA), Long Term Evolution (LTE), Bluetooth (BT), Global Navigation Satellite System (GNSS), etc.

[0142] This disclosure also provides a computer-readable storage medium, characterized in that it stores program instructions, which are executed, for example... Figure 1 The circuit reduction method in the embodiments.

[0143] That is, the method steps in the above embodiments are implemented as software or computer code that can be stored in a recording medium (such as CD ROM, RAM, floppy disk, hard disk or magneto-optical disk), or implemented as computer code that is originally stored in a remote recording medium or a non-transitory machine-readable medium and will be stored in a local recording medium after being downloaded via a network, so that the method represented herein can be stored in such software processing on a recording medium using a general-purpose computer, a special processor or programmable or special hardware (such as ASIC or FPGA).

[0144] In summary, the circuit reduction method, apparatus, electronic device, and medium disclosed herein achieve batch elimination of internal nodes and physical realization of equivalent circuits through systematic matrix operations. This method first identifies the port nodes and internal nodes of the target circuit and constructs a node admittance matrix and a representation of the port admittance relationship accordingly. Then, based on matrix operations, it calculates the equivalent admittance between all pairs of port nodes in one go, mathematically completing the overall elimination of internal nodes. Finally, it determines specific circuit parameters based on the equivalent admittance values ​​and adds equivalent RC components between the port nodes to generate a physically realizable reduced circuit. This scheme achieves three technical advantages: it uses high-dimensional matrix operations to process the entire circuit block at once, breaking through the efficiency bottleneck of traditional point-by-point elimination and significantly improving the reduction speed of ultra-large-scale circuits; rigorous mathematical derivation ensures a high degree of consistency in port electrical characteristics before and after reduction, effectively maintaining simulation accuracy; and the generated equivalent circuit is composed of actual RC components, combining mathematical rigor with physical realizability, providing a reliable foundation for subsequent circuit simulation.

[0145] The above embodiments are merely illustrative of the principles and effects of this disclosure and are not intended to limit this disclosure. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this disclosure. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this disclosure should still be covered by the claims of this disclosure.

Claims

1. A circuit reduction method, characterized by, The method comprises: determining whether the total number of nodes of a target circuit exceeds a preset scale threshold; when the total number of nodes exceeds the scale threshold, using a graph partitioning algorithm to divide the target circuit into a plurality of sub-circuits connected to each other; identifying port nodes and internal nodes in the sub-circuits; wherein the port nodes are circuit nodes directly connected to external circuits, and the internal nodes are nodes in the target circuit other than the port nodes and connected between the port nodes through electrical elements; constructing a node admittance matrix according to the electrical connection relationship between the internal nodes; constructing a port admittance relationship representation according to the electrical connection relationship between the port nodes and the internal nodes; performing matrix operations based on the node admittance matrix and the port admittance relationship representation to calculate the equivalent admittance to be added between any two port nodes, and mathematically eliminating the internal nodes through the matrix operations; determining the parameter value of the equivalent circuit element to be added between the corresponding port node pairs according to the calculated equivalent admittance, and adding the equivalent circuit element configured with the parameter value between the corresponding port nodes to generate a reduced sub-circuit; when the total number of nodes of the sub-circuit exceeds a preset complexity threshold, or the user-specified reduction accuracy requirement is higher than a preset accuracy threshold, triggering an internal node retention mechanism; the internal node retention mechanism comprises: selecting a set number of nodes from the internal nodes to be retained, and the number of retained nodes is determined according to a preset retention ratio or an absolute number; the matrix operations are only performed on the internal nodes that are not retained; the selected retained internal nodes are determined based on the following criteria: According to the distribution attribute of the internal nodes in the circuit topology, the nodes to be retained are selected in the order of the shortest path distance from large to small between the nodes and other internal nodes.

2. The circuit reduction method of claim 1, wherein, The port admittance relationship representation is composed of admittance relationship vectors corresponding to each port node; the construction of the port admittance relationship representation comprises: distinguishing the internal nodes into ordinary internal nodes and boundary nodes, wherein the ordinary internal nodes are internal nodes that have no direct admittance connection with any port node, and the boundary nodes are internal nodes that have direct admittance connection with at least one port node; constructing a corresponding admittance relationship vector for each port node, wherein: when the internal node is a boundary node of the port node, the actual admittance value between the port node and the internal node is taken as the element at the corresponding position; when the internal node is an ordinary internal node of the port node, the element at the corresponding position takes a zero value.

3. The circuit reduction method of claim 2, wherein, The matrix operations based on the node admittance matrix and the port admittance relationship representation to calculate the equivalent admittance to be added between any two port nodes are realized through the following formula: ， wherein, represents the equivalent admittance to be added between port nodes p and q; K represents the total number of internal nodes; N i represents the i-th internal node; represents the admittance relationship row vector between port node p and internal node N i ; represents the admittance relationship column vector between internal node N i and port node q; represents the i-th standard unit vector, which has a dimension of Kx1, and the i-th element is 1 and the rest of the elements are 0; represents the transpose of ; Y represents the node admittance matrix composed of all internal nodes after grounding all port nodes; represents the inverse matrix of matrix Y.

4. The circuit reduction method of claim 1, wherein, The equivalent circuit element is an equivalent capacitance element and an equivalent conductance element.

5. The circuit reduction method of claim 4, wherein, The calculation formula for adding an equivalent conductance value between the port nodes is: ， wherein, represents the equivalent conductance value added between port nodes p and q; K represents the total number of internal nodes; Ni and Nj represent the i-th and j-th internal nodes, respectively; represents the conductance value between port node p and internal node Ni; represents the conductance value between port node q and internal node N j ; G represents the conductance matrix between internal nodes, with dimensions K x K; represents the element in the i-th row and j-th column of the inverse matrix of matrix G.

6. The circuit reduction method of claim 4, wherein, The calculation formula for adding an equivalent capacitance between the port nodes is: ， ， wherein, Gpqi represents the equivalent capacitance value added between port nodes p and q; K represents the total number of internal nodes; N i and N j respectively represent the i-th and j-th internal nodes; Gpni represents the conductance value between port node p and internal node N Gqni represents the conductance value between port node q and internal node N j ; Cpni represents the capacitance value between port node p and internal node N i ; Cqni represents the capacitance value between port node q and internal node N j ; G represents the conductance matrix between internal nodes; C represents the capacitance matrix between internal nodes, with dimensions K x K; Gij represents the element in the i-th row and j-th column of the inverse matrix of matrix G.

7. The circuit reduction method of claim 1, wherein, Further comprising: According to a connection relationship between each sub-circuit block of the target circuit before partition, the integrated reduced sub-circuits are generated to form a complete reduced circuit.

8. The circuit reduction method of claim 1, wherein, When the graph partition algorithm is the METIS algorithm, the target circuit is partitioned into a plurality of sub-circuits connected with each other, including: The topological structure of the target circuit is abstracted into an undirected graph, wherein a node corresponds to a circuit node, and an edge corresponds to an element connection relationship; A multi-level graph partition process is performed, including: A series of coarsened graphs with a size decreasing layer by layer are generated by iteratively merging highly connected node pairs to form supernodes until a preset size threshold is reached; The final obtained coarsened graph is partitioned to obtain a plurality of subgraph partitions, and the node number difference between each subgraph is controlled within a preset tolerance; The partitioned coarsened graph is expanded to the original graph size in reverse order of generation order layer by layer, and the Kernighan-Lin algorithm or the Fiduccia-Mattheyses algorithm is applied to each expansion layer to locally optimize the partition boundary to minimize the number of connection edges between subgraphs; According to the optimized partition result, the target circuit is partitioned into a plurality of sub-circuits connected with each other.

9. A circuit reduction apparatus, characterized by comprising: Including: A partition module is configured to determine whether the total number of nodes of the target circuit exceeds a preset size threshold; When the total number of nodes exceeds the size threshold, the target circuit is partitioned into a plurality of sub-circuits connected with each other by using a graph partition algorithm; An identification module is configured to identify port nodes and internal nodes in the sub-circuits; wherein the port nodes are circuit nodes directly connected with external circuits, and the internal nodes are nodes in the target circuit except the port nodes and connected between the port nodes through electrical elements; A matrix construction module is configured to construct a node admittance matrix according to the electrical connection relationship between the internal nodes; An admittance relationship construction module is configured to construct a port admittance relationship representation according to the electrical connection relationship between the port nodes and the internal nodes; An equivalent admittance calculation module is configured to perform matrix operations based on the node admittance matrix and the port admittance relationship representation to calculate the equivalent admittance to be added between any two port nodes, and mathematically eliminate the internal nodes through the matrix operations; A generation module is configured to determine the parameter value of the equivalent circuit element to be added between the corresponding port node pairs according to the calculated equivalent admittance, and add the equivalent circuit element configured with the parameter value between the corresponding port nodes to generate a reduced sub-circuit. A node retention module is configured to trigger an internal node retention mechanism when the total number of nodes of the sub-circuit exceeds a preset complexity threshold, or when a user-specified reduction accuracy requirement is higher than a preset accuracy threshold; the internal node retention mechanism includes: selecting a set number of nodes from the internal nodes to be reserved, the number of reserved nodes being determined according to a preset reservation ratio or absolute number; the matrix operation being performed only on the internal nodes that are not reserved; the reserved internal nodes being selected based on the following criteria: according to the distribution attribute of the internal nodes in the circuit topology, the nodes to be reserved are selected in descending order of the shortest path distance between the nodes and other internal nodes.

10. An electronic device, comprising: The electronic device comprises: a processor and a memory; wherein the memory is configured to store a computer program; the processor is configured to execute the computer program stored in the memory, so that the electronic device executes the circuit reduction method of any one of claims 1 to 8.

11. A computer readable storage medium having stored thereon a computer program, characterized in that, The program is executed by the electronic device to implement the circuit reduction method of any one of claims 1 to 8.

Images