Method and apparatus for operating memory device

Abstract

The invention relates to a method and a device for operating a memory device. In one example, a memory device includes a memory array including memory cells, and a peripheral circuit coupled to the memory array. The peripheral circuit includes a microcontroller unit (MCU) and a plurality of circuits controlled by the MCU. The MCU is configured to switch between a first register and a second register coupled to a first circuit of the plurality of circuits.

Description

Technical Field

[0001] This disclosure relates generally to the field of semiconductor technology, and more specifically to systems and methods for operating memory devices. Background Technology

[0002] Flash memory is a low-cost, high-density, non-volatile solid-state storage medium that can be electrically erased and reprogrammed. Flash memory includes NOR flash memory and NAND flash memory. The ever-growing demands of consumer electronics, cloud computing, and big data have created a continuous need for flash memory with larger capacities and better performance. Today, flash memory devices are designed with stringent performance and reliability requirements. Summary of the Invention

[0003] This disclosure relates to methods and apparatus for operating a memory device. In an example, the memory device includes a memory array and peripheral circuitry coupled to the memory array, the memory array including memory cells. The peripheral circuitry includes a microcontroller unit (MCU) and a plurality of circuits controlled by the MCU. The MCU is configured to switch between a first register and a second register of a first circuit coupled to the plurality of circuits.

[0004] While generally described as computer-implemented software embodied in the processing and transformation of corresponding data on a tangible medium, some or all aspects may be computer-implemented methods or further included in a corresponding system or other apparatus for performing said function. These and other aspects of this disclosure, as well as details of embodiments, are set forth in the accompanying drawings and the following description. Other features, objects, and advantages of this disclosure will become apparent from the description, drawings, and claims. Attached Figure Description

[0005] Figure 1 An example of a schematic diagram of a memory device including peripheral circuitry according to some aspects of this disclosure is shown.

[0006] Figure 2 Some example circuits of peripheral circuits according to some aspects of this disclosure are shown.

[0007] Figure 3 An example of a schematic diagram of a peripheral circuit according to some aspects of this disclosure is shown.

[0008] Figure 4A An example of a schematic diagram showing the connection between two registers of a circuit according to some aspects of this disclosure is shown.

[0009] Figure 4B Another example of a schematic diagram showing the connection between two registers of a circuit according to some aspects of this disclosure is shown.

[0010] Figure 5Example methods of operating a memory device according to some aspects of this disclosure are shown.

[0011] Figure 6A Another example method of operating a memory device according to some aspects of this disclosure is shown.

[0012] Figure 6B Another example method of operating a memory device according to some aspects of this disclosure is shown.

[0013] Figure 7 A block diagram of an example system having a memory device according to some aspects of this disclosure is shown.

[0014] Figure 8A A diagram of a memory card having a memory device is shown according to some aspects of this disclosure.

[0015] Figure 8B A diagram of a solid-state drive (SSD) having a memory device is shown according to some aspects of this disclosure.

[0016] Similar reference numerals and names in the various figures indicate similar elements. Detailed Implementation

[0017] Flash memory devices, such as NAND flash memory devices, can include memory arrays and peripheral circuitry that performs operations on the memory arrays. The peripheral circuitry can include control logic units and multiple circuits controlled by the control logic units. Current designs of control logic units can include state machine (STM) architectures and microcontroller unit (MCU) architectures. In an STM architecture, each circuit is controlled by a corresponding microprocessor. The microprocessor can run one cycle of operations in parallel. Conversely, in an MCU architecture, a general-purpose MCU can control multiple circuits via a bus. Due to factors such as the data width of the bus, the MCU executes one cycle of operations serially. In some cases, the MCU architecture allows for the implementation of complex control algorithms and provides greater flexibility in modifying control algorithms without remanufacturing. For example, by introducing a PC Re-Map structure, problematic or improveable firmware blocks can be mapped to new firmware blocks, which makes post-silicon modifications easier and improves design and verification efficiency.

[0018] This disclosure provides techniques for operating a memory device with control logic units within an MCU architecture. In some embodiments, the peripheral circuitry may have a main register and a backup register that couple the circuitry to the MCU. The main register and the backup register may share the same address. The MCU can switch between the main register and the backup register. For example, when the circuitry is performing an operation indicated by configuration parameters stored in the main register, the MCU can send the configuration parameters to the backup register for subsequent operations.

[0019] The techniques described in this disclosure can be implemented to achieve one or more of the following advantages. For example, since the MCU does not need to delay sending configuration parameters for subsequent operations until the circuit completes the current operation, the operating efficiency of the MCU can be enhanced. Furthermore, the read and programmable times of the memory device can be reduced, thereby improving the performance of the memory device.

[0020] Figure 1 An example of a schematic circuit diagram of a memory device 100 including peripheral circuitry 102 according to some aspects of this disclosure is shown. The memory device 100 may include a memory cell array 101 and peripheral circuitry 102 coupled to the memory cell array 101. The memory cell array 101 may be a NAND flash memory cell array, wherein the memory cells 106 are provided in the form of an array of NAND memory strings 108, each NAND memory string 108 on a substrate ( Figure 1 (Not shown in the diagram) Extending vertically above. In some embodiments, each NAND memory string 108 includes a plurality of memory cells 106 that are series-coupled and vertically stacked. Each memory cell 106 may hold a continuous analog value, such as voltage or charge depending on the number of electrons trapped within the storage layer of the memory cell 106. The logic state (e.g., data) of each memory cell 106 in block 104 may be based on a threshold voltage V of the memory cell 106. th To determine. Each memory cell 106 may be a floating-gate memory cell including a floating-gate transistor, or a charge-trapping memory cell including a charge-trapping transistor.

[0021] In some implementations, each memory cell 106 is a single-level cell (SLC) with two possible memory states, capable of storing one bit of data. For example, a first memory state "0" may correspond to a first voltage range, while a second memory state "1" may correspond to a second voltage range. In some implementations, each memory cell 106 is a multi-level cell (MLC) capable of storing more than one bit of data in more than two memory states. For example, an MLC may store two bits per cell, three bits per cell (also known as a three-level cell (TLC)), or four bits per cell (also known as a four-level cell (QLC)). Each MLC can be programmed to support a range of possible nominal memory values. In one example, if each MLC stores two bits of data, the MLC can be programmed from an erase state to one of three possible programming levels by writing one of the three possible nominal memory values ​​to the cell. A fourth nominal memory value can be used for the erase state.

[0022] like Figure 1As shown, each NAND memory string 108 may include a source select gate (SSG) 110 at its source end and a drain select gate (DSG) 112 at its drain end. SSG 110 and DSG 112 can be configured to activate the selected NAND memory string 108 (column of the array) during read and program operations. In some embodiments, the sources of memory strings 108 in the same block 104 are coupled via the same source line (SL) (e.g., common SL) 114. In other words, according to some embodiments, the NAND memory strings 108 in the same block 104 have an array common source (ACS). According to some embodiments, the DSG 112 of each NAND memory string 108 is coupled to a corresponding bit line 116, from which data can be read or written via an output bus (not shown). In some implementations, each NAND memory string 108 is configured to be selected or deselected by applying a selection voltage (e.g., exceeding the threshold voltage of the transistor having DSG 112) or a deselection voltage (e.g., 0V) to the corresponding DSG 112 via one or more DSG lines 113, and / or by applying a selection voltage (e.g., exceeding the threshold voltage of the transistor having SSG 110) or a deselection voltage (e.g., 0V) to the corresponding SSG 110 via one or more SSG lines 115.

[0023] like Figure 1 As shown, the NAND memory string 108 can be organized into multiple blocks 104, each block potentially having a common source line 114 coupled to the ACS. In some embodiments, each block 104 can serve as a basic data unit for erase operations, such that memory cells 106 on the same block 104 are erased simultaneously. To erase memory cells 106 in a selected block 104, an erase voltage (V) can be used. ers The source lines 114 of selected blocks 104 and unselected blocks coupled to the same plane are biased. For example, the erase voltage can be a high positive voltage (e.g., 20V or higher). In some implementations, the erase operation can be performed at a half-block level, a quarter-block level, or a level having any suitable number of blocks or portions of blocks.

[0024] Memory cells 106 of adjacent memory strings 108 can be coupled via word lines 118. Word lines 118 can select which row of memory cells 106 is affected by read and program operations. In some embodiments, memory cells 106 are SLCs, and each word line 118 is coupled to a page 120 of memory cells 106, which is the basic data unit used for programming operations. If the memory cells 106 are MLCs storing two bits of data per cell, each word line 118 can correspond to two pages. If the memory cells 106 are TLCs, each word line 118 can correspond to three pages. If the memory cells 106 are QLCs, each word line 118 can correspond to four pages. The size of the page 120, in bits, is related to the number of NAND memory strings 108 coupled by word lines 118 in block 104. Each word line 118 may include a gate line coupled to multiple control gates (gate electrodes) of multiple memory cells 106 in the corresponding page 120. Figure 1 The example word lines shown include dummy WL, WL1, WL2, WL3, WL4 and WL5 located between one or more DSG lines 113 and one or more SSG lines 115.

[0025] Peripheral circuitry 102 can be coupled to memory cell array 101 via bit line 116, word line 118, source line 114, SSG line 115, and DSG line 113. Peripheral circuitry 102 may include any suitable analog, digital, and mixed-signal circuitry for facilitating operation of memory cell array 101 by applying voltage and / or current signals to each target memory cell 106 via bit line 116, word line 118, source line 114, SSG line 115, and DSG line 113, and by sensing voltage and / or current signals from each target memory cell 106.

[0026] Figure 2 Peripheral circuits according to some aspects of this disclosure are shown (e.g., Figure 1 Some example circuits of the peripheral circuitry 102. The peripheral circuitry may include a control logic unit 212, a register 214 coupled to the control logic unit 212, an interface 216, and other circuitry controlled by the control logic unit 212, including a page buffer / sensor amplifier 204, a column decoder / bit line driver 206, a row decoder / word line driver 208, and a voltage generator 210. A data bus for the control logic unit can connect the control logic unit 212 to other circuitry and transmit signals and data to and from the control logic unit 212. In some examples, it may also include... Figure 3 Additional circuitry not shown.

[0027] Page buffer / sensor amplifier 204 can be configured to read data from memory cell array 101 and program (write) data to memory cell array 101 according to control signals from control logic unit 212. In one example, page buffer / sensor amplifier 204 can store a page of programming data (write data) to be programmed into a page 120 of memory cell array 101. In another example, page buffer / sensor amplifier 204 can perform a programming verification operation to ensure that data has been correctly programmed into memory cell 106 coupled to selected word line 118. In yet another example, page buffer / sensor amplifier 204 can also sense a low-power signal from bit line 116 representing a data bit stored in memory cell 106 and amplify a small voltage swing to a logic level recognizable in a read operation. Column decoder / bit line driver 206 can be configured to be controlled by control logic unit 212 and select one or more NAND memory strings 108 by applying a bit line voltage generated by voltage generator 210.

[0028] The row decoder / word line driver 208 can be configured to be controlled by the control logic unit 212 to select / deselect block 104 of the memory cell array 101 and to select / deselect word lines 118 of block 104. The row decoder / word line driver 208 can be further configured to drive word lines 118 using word line voltages generated from the voltage generator 210. In some embodiments, the row decoder / word line driver 208 can also select / deselect and drive SSG lines 115 and DSG lines 113. As described in detail below, the row decoder / word line driver 208 is configured to apply a programming voltage to the selected word line 118 during programming operations on memory cells 106 coupled to the selected word line 118.

[0029] Voltage generator 210 can be configured to be controlled by control logic unit 212 to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to memory cell array 101.

[0030] Control logic unit 212 may be coupled to each of the circuits described above and configured to control the operation of each circuit. Control logic unit 212 may be implemented by a microprocessor, microcontroller (also known as a microcontroller unit, MCU), digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), programmable logic device (PLD), state machine, gated logic unit, discrete hardware circuit, and other suitable hardware, firmware, and / or software configured to perform the various functions described above. Register 214 may be coupled to control logic unit 212 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each circuit.

[0031] Interface 216 can be coupled to control logic unit 212 and act as a control buffer to buffer and relay control commands received from the host (not shown) to control logic unit 212 and status information received from control logic unit 212 to the host. Interface 216 can also be coupled to column decoder / bit line driver 206 via data bus and act as a data input / output (I / O) interface and data buffer to buffer and relay data to and from memory cell array 101.

[0032] Figure 3 An example of a schematic diagram of a peripheral circuit 102 according to some aspects of this disclosure is shown. The peripheral circuit 102 includes a control logic unit (e.g., Figure 2 The control logic unit 212) and the circuits 310, 320, 330 controlled by the control logic unit (e.g., Figure 2 (One or more of the page buffer / sensor amplifier 204, column decoder / bit line driver 206, row decoder / word line driver 208, and voltage generator 210). The control logic unit may be implemented by one or more MCUs 302. In some embodiments, the control logic unit may include multiple types of MCUs 302 to control circuits 310, 320, and 330 with different functions. For example, the control logic unit may include three types of MCUs: a main program microcontroller (MP_MCU), a core microcontroller (CORE_MCU), and a page buffer microcontroller (PB_MCU). The MP_MCU may be configured to run the main program and control the CORE_MCU and PB_MCU. The CORE_MCU may be configured to control, for example, a row decoder (e.g., ...). Figure 2 The row decoder / word line driver 208), column decoder (e.g., Figure 2 The operation of the column decoder / bit line driver 206 and other analog circuits, etc. PB_MCU can be configured to control the page buffer (e.g., ...). Figure 2The operation of the page buffer / sensor amplifier 204 in the middle.

[0033] MCU 302 can communicate with the registers of one of circuits 310, 320, and 330 via bus 304. In some embodiments, bus 304 may include a data bus, an address bus, and a clock control bus. The data width of the data bus can be 8 bits, 16 bits, 32 bits, etc. That is, the data bus can transmit 8 bits, 16 bits, 32 bits, or other numbers of bits of data at a time. The address bus can transmit an address signal that instructs a target register to receive data transmitted by the data bus. For example, the address bus can transmit an address signal during data transmission on the data bus. The clock control bus can transmit a clock signal that synchronizes the timing of different operations of different circuits 310, 320, and 330.

[0034] In some implementations, each circuit 310 may have a register 312 that receives data from the MCU 302. The data received by register 312 may include configuration parameters that can configure the circuit 310 for upcoming operations. For example, circuits 0, 1, and 2 are coupled to registers 0, 1, and 2, respectively.

[0035] Taking circuit 0 as an example, register 0 can first receive data from MCU 302, which configures circuit 0 to perform a first operation (e.g., configuring the word line driver to select a target word line). While circuit 0 performs the first operation, register 0 can hold the data. After circuit 0 completes the first operation, register 0 can receive data from MCU 302, which configures circuit 0 to perform subsequent operations. Circuits 1, 2, and other circuits controlled by MCU 302 can operate in a similar manner with their respective registers.

[0036] Specifically, refer to Figure 5 At position 502, MCU 302 transmits data A and address 0 (e.g., the address of register 0) via bus 304. Register 0 receives data A, which configures circuit 0 to perform operation A. At position 504, MCU 302 transmits data B and address 1 (e.g., the address of register 1) via bus 304. Register 1 receives data B, which configures circuit 1 to perform operation B.

[0037] At point 506, circuit 0 can execute operation A based on the configuration parameters in data A stored in register 0. Meanwhile, register 0 can hold data A until operation A completes. At point 508, circuit 1 can execute operation B based on the configuration parameters in data B stored in register 1. Meanwhile, register 1 can hold data B until operation B completes. In some implementations, points 506 and 508 can be synchronized to start according to a clock signal transmitted via a clock control bus.

[0038] At 510, after circuit 0 completes operation A, MCU 302 sends data C and address 0 via bus 304. Register 0 receives data C, which configures circuit 0 to perform operation C. At 512, after circuit 1 completes operation B, MCU sends data D and address 1 via bus 304. Register 1 receives data D, which configures circuit 1 to perform operation D. At 514, circuit 0 performs operation C. At 516, circuit 1 performs operation D. In some implementations, 506 and 508 can start synchronously.

[0039] At point 518, after circuit 0 completes operation C, MCU 302 sends data E and address 0 via bus 304. Register 0 receives data E, which configures circuit 0 to execute operation E. At point 520, after circuit 1 completes operation D, MCU 302 sends data F and address 1 via bus 304. Register 1 receives data F, which configures circuit 1 to execute operation F.

[0040] It is important to note that Figure 5 Two circuits are shown for illustrative purposes only. In some embodiments, peripheral circuitry 102 may include multiple circuits 310 operating in a similar manner. That is, between 502 and 506, the MCU may need to transfer data to the registers of circuits 2, 3, ..., n. Due to the data width limitations of bus 304, MCU 302 may need to transfer data sequentially to circuits 0-n, which may require multiple clock cycles to complete. Figure 5 As can be seen, in an architecture where a circuit is coupled to a register, bus 304 is idle between 504 and 510, and between 512 and 518. That is, no data or signals are transmitted while the circuit is operating.

[0041] Return to reference Figure 3In some implementations, each circuit 310 may have two registers 312 and 314 that can alternately receive data from the MCU 302. One register 312 may be referred to as the master register. The other register 314 may be referred to as the backup register. For example, circuit 0 may be coupled to register 0 (master register) and register 0' (backup register); circuit 1 may be coupled to register 1 (master register) and register 1' (backup register); and circuit 2 may be coupled to register 2 (master register) and register 2' (backup register). The master register and the backup register may have the same address and the same configuration. In some implementations, the master register and the backup register may be coupled to a multiplexer (MUX), allowing the MCU 302 to send an enable signal to the MUX to switch between the master register and the backup register.

[0042] Taking circuit 0 as an example, register 0 can first receive data from MCU 302 configuring circuit 0 to perform a first operation. During the execution of the first operation by circuit 0, MCU 302 can send data to register 0' configuring circuit 0 to perform a second operation following the first operation. That is, when circuit 0 performs the first operation, bus 304 is not idle. After circuit 0 completes the first operation, MCU can send an enable signal to switch between register 0 and register 0'. In this way, circuit 0 can execute the second operation indicated by the data in register 0'. In some embodiments, during the time when circuit 0 is performing the second operation, MCU 302 can send data to register 0 configuring circuit 0 to perform a third operation following the second operation.

[0043] An architecture with two registers 312 and 314 in a circuit 310 can improve the operational efficiency of the MCU 302. For example, the MCU 302 does not have to wait for the circuit 310 to complete its operation before transmitting data configuring the next operation. While the circuit 310 is performing its current operation (e.g., as indicated by the data in the main register 312), the MCU 302 can transmit data configuring subsequent operations (e.g., to the backup register 314).

[0044] Figure 4A Circuits according to some aspects of this disclosure are shown (e.g., Figure 3 The two registers of circuit 0) (e.g., Figure 3 This is an example of a schematic diagram illustrating the connection between register 0 and register 0'. Each of the main register 402 and backup register 404 may include an input port 412 for receiving data, an enable port 414 for receiving an enable signal to enable or disable the register input port 412, a clock port 416 for receiving a clock signal, and an output port 418 for outputting data.

[0045] In some implementations, the input ports of both the main register 402 and the backup register 404 can be connected to the MCU (e.g., Figure 3 The data bus of the MCU 302 is connected to the main register. The clock ports of both the main register and the backup register can be connected to the MCU's clock control bus (not shown). The enable ports of both the main register and the backup register can receive an enable signal (e.g., MUX_EN) from the MCU. In some embodiments, an inverter 408 can be added before the input port of the backup register 404 to invert the enable signal from high to low (e.g., from 1 to 0) or from low to high (e.g., from 0 to 1). The output port of the backup register can be connected to the first input of the MUX 406 (e.g., port 1). The output port of the main register can be connected to the second input of the MUX 406 (e.g., port 0). The output of the MUX 406 can be connected to a circuit (e.g., ...). Figure 3 The circuit 0) is used to send data from either the main register 402 or the backup register 404 to the circuit.

[0046] The MUX 406 can also be configured to receive an enable signal (e.g., MUX_EN) from the MCU to select one of its two inputs. For example, when the MCU sets the enable signal high (e.g., set to 1), the input of the main register 402 is enabled, the input of the backup register 404 is disabled, and the MUX 406 can enable data output from the backup register 404 to the circuitry. As another example, when the MCU sets the enable signal low (e.g., set to 0), the input of the main register 402 is disabled, the input of the backup register 404 is enabled, and the MUX can enable data output from the main register 402 to the circuitry.

[0047] exist Figure 4A Under the connection scheme of the main register 402 and backup register 404 shown, the MCU can follow Figure 6A The method shown controls the operation of other circuits in the peripheral circuit 102. It should be noted that... Figure 6A Two circuits are shown for illustrative purposes only, and peripheral circuit 102 may include multiple circuits operating in a similar manner.

[0048] Prior to 602, the MCU could set the enable signal high, causing main register 402 (e.g., Figure 3 The inputs of registers 0 and 1 in the register are enabled, and backup register 404 (e.g., Figure 3 Input to registers 0' and 1' in the register is disabled.

[0049] At 602, the MCU communicates via a bus (e.g., Figure 3The bus 304 in the circuit transmits data A and address 0 (e.g., an address shared by register 0 and register 0'). Register 0 receives data A, which can configure circuit 0 to perform operation A.

[0050] At 604, the MCU sends data B and address 1 (e.g., an address shared by register 1 and register 1') via the bus. Register 1 receives data B, which configures circuit 1 to perform operation B.

[0051] At 606, after data has been transferred from the MCU to the registers of all target circuits, the MCU can switch the enable signal from high to low. This disables the input to main register 402, enables the input to backup register 404, and allows each MUX 406 to enable the output from each main register to its corresponding circuit. In some implementations, 606 may occupy only one clock cycle.

[0052] At 608, circuit 0 executes operation A based on the configuration parameters in data A stored in register 0. Meanwhile, register 0 can hold data A until operation A is complete.

[0053] At 610, circuit 1 executes operation B based on the configuration parameters in data B stored in register 1. Meanwhile, register 1 can hold data B until operation B is complete. In some implementations, 506 and 508 can start synchronously based on a clock signal transmitted via the clock control bus.

[0054] At position 612, during the time when circuit 0 is performing operation A, the MCU sends data C and address 0 via the bus. Register 0' receives data C, which configures circuit 0 to perform operation C.

[0055] At point 614, during the time when circuit 1 is performing operation B, the MCU sends data D and address 1 via the bus. Register 1' receives data D, which configures circuit 1 to perform operation D.

[0056] At 616, after all target circuits (e.g., circuit 0 and peripheral device 1) have completed their operations (e.g., operations A and B), the MCU can switch the enable signal from low to high. This enables the inputs of main register 402, disables the inputs of backup register 404, and allows each MUX 406 to enable the outputs from each backup register to its corresponding circuit. In some implementations, 616 may occupy only one clock cycle.

[0057] At position 618, circuit 0 executes operation C based on the configuration parameters in the data C stored in register 0'. Meanwhile, register 0' can hold data C until operation C is complete.

[0058] At 620, circuit 1 executes operation D based on the configuration parameters in the data D stored in register 1'. Meanwhile, register 1' can hold data D until operation D is complete. In some implementations, 618 and 620 can start synchronously.

[0059] At position 622, during the time when circuit 0 is performing operation C, the MCU sends data E and address 0 via the bus. Register 0 receives data E, which configures circuit 0 to perform operation E.

[0060] At position 624, during the time when circuit 1 is performing operation D, the MCU sends data F and address 1 via the bus. Register 1 receives data F, which configures circuit 1 to perform operation F.

[0061] Subsequent operations can be performed in the order described above, and will not be repeated here.

[0062] Figure 4B Circuits according to some aspects of this disclosure are shown (e.g., Figure 3 The two registers of circuit 0) (e.g., Figure 3 Another example of a schematic diagram of the connection between register 0 and register 0'.

[0063] In some implementations, the input port of the backup register 454 and the first input (e.g., port 1) of the MUX 456 can both be connected to the MCU's data bus. The output port of the backup register can be connected to the second output (e.g., port 0) of the MUX 456. The output of the MUX 456 can be connected to the input port of the main register 452. The output port of the main register 452 can be connected to a circuit (e.g., Figure 3 The circuit 0) is used to send data to the circuit.

[0064] MUX 456 can also be configured to receive an enable signal (e.g., MUX_EN) from the MCU to select one of its two inputs. For example, when the MCU sets the enable signal high (e.g., set to 1), MUX 406 can enable data output from the data bus to main register 452. As another example, when the MCU sets the enable signal low (e.g., set to 0), MUX can enable data output from backup register 454 to main register 452.

[0065] exist Figure 4B Under the connection scheme of the main register 452 and backup register 454 shown, the MCU can follow Figure 6B The method shown controls the operation of other circuits in the peripheral circuit 102. It should be noted that... Figure 6BTwo circuits are shown for illustrative purposes only, and peripheral circuit 102 may include multiple circuits operating in a similar manner.

[0066] Prior to the 652, the MCU could set the enable signal high, enabling the MUX 456 to connect from the data bus to the main register 452 (e.g., Figure 3 The output of registers 0 and 1 in the register.

[0067] At position 652, the MCU communicates via a bus (e.g., Figure 3 The bus 304 in the circuit transmits data A and address 0 (e.g., an address shared by register 0 and register 0'). Register 0 receives data A, which can configure circuit 0 to perform operation A.

[0068] At position 654, the MCU sends data B and address 1 (e.g., an address shared by register 1 and register 1') via the bus. Register 1 receives data B, which configures circuit 1 to perform operation B.

[0069] At 656, after data has been transferred from the MCU to the registers of all target circuits, the MCU can switch the enable signal from high to low. This enables the MUX output from backup registers (e.g., registers 0' and 1') to main registers (e.g., registers 0 and 1). In some implementations, 656 may occupy only one clock cycle.

[0070] At 658, circuit 0 performs operation A based on the configuration parameters in data A stored in register 0. Meanwhile, register 0 can hold data A until operation A is complete.

[0071] At 660, circuit 1 executes operation B based on the configuration parameters in data B stored in register 1. Meanwhile, register 1 can hold data B until operation B is complete. In some implementations, 506 and 508 can start synchronously.

[0072] At position 662, during the time when circuit 0 is performing operation A, the MCU sends data C and address 0 via the bus. Register 0' receives data C, which configures circuit 0 to perform operation C.

[0073] At address 664, during the time when circuit 1 is performing operation B, the MCU sends data D and address 1 via the bus. Register 1' receives data D, which configures circuit 1 to perform operation D.

[0074] At 666, after all target circuits (e.g., circuit 0 and peripheral device 1) have completed their operations (e.g., operations A and B), register 0' sends data C to register 0, and in parallel, register 1' sends data D to register 1.

[0075] At 668, circuit 0 executes operation C based on the configuration parameters in the data C stored in register 0. Meanwhile, register 0 can hold data C until operation C is complete.

[0076] At 670, circuit 1 executes operation D based on the configuration parameters in the data D stored in register 1. Meanwhile, register 1 can hold data D until operation D is complete. In some implementations, 668 and 670 can start synchronously.

[0077] At position 672, during the time when circuit 0 is performing operation C, the MCU sends data E and address 0 via the bus. Register 0' receives data E, which configures circuit 0 to perform operation E.

[0078] At position 674, during the time when circuit 1 is performing operation D, the MCU sends data F and address 1 via the bus. Register 1' receives data F, which configures circuit 1 to perform operation F.

[0079] At 676, after all target circuits (e.g., circuit 0 and peripheral device 1) have completed their operations (e.g., operations C and D), register 0' sends data E to register 0, and in parallel, register 1' sends data F to register 1.

[0080] Subsequent operations can be performed in the order described above, and will not be repeated here.

[0081] Figure 7 A block diagram of an example system 700 having a memory device according to some aspects of this disclosure is shown. System 700 may be a mobile phone, desktop computer, laptop computer, tablet computer, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 7 As shown, system 700 may include a host 708 and a memory system 702 having one or more memory devices 704 and a memory controller 706. The host 708 may be a processor of an electronic device, such as a central processing unit (CPU), or a system-on-a-chip (SoC), such as an application processor (AP). The host 708 may be configured to send data to or receive data from the memory device 704.

[0082] Memory device 704 can be any memory device disclosed in this disclosure. According to some embodiments, memory controller 706 is coupled to memory device 704 and host 708 and is configured to control memory device 704. Memory controller 706 can manage data stored in memory device 704 and communicate with host 708. In some embodiments, memory controller 706 is designed to operate in low duty cycle environments, such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB), flash drives, or other media used in electronic devices such as personal computers, digital cameras, and mobile phones. In some embodiments, memory controller 706 is designed to operate in high duty cycle environments, such as SSDs or embedded multimedia cards (eMMCs), used for data storage in mobile devices (such as smartphones, tablets, laptops, etc.) and enterprise storage arrays. Memory controller 706 can be configured to control the operation of memory device 704, such as read, erase, and program operations. The memory controller 706 can also be configured to manage various functions relating to data stored or to be stored in the memory device 704, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 706 is also configured to process error correction codes (ECC) for data read from or written to the memory device 704. Any other suitable function, such as formatting the memory device 704, can also be performed by the memory controller 706.

[0083] The memory controller 706 can communicate with an external device (e.g., host 708) according to a specific communication protocol. For example, the memory controller 706 can communicate with the external device through at least one of a variety of interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI-Fast (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, FireWire protocol, etc.

[0084] The memory controller 706 and one or more memory devices 704 can be integrated into various types of memory devices, for example, included in the same package, such as a Universal Flash Memory (UFS) package or an eMMC package. That is, the memory system 702 can be implemented and packaged into different types of end electronic products. Figure 8AIn one example shown, the memory controller 706 and memory device 704 can be integrated into the memory card 802. The memory card 802 can include PC cards (PCMCIA, Personal Computer Memory Card International Association), CF cards, Smart Media (SM) cards, Memory Sticks, Multimedia Cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 802 may also include a memory card connector 804 that couples the memory card 802 to the host computer. Figure 8B In another example shown, the memory controller 706 and multiple memory devices 1004 may be integrated into the SSD 806. The SSD 806 may also include an SSD connector 808 that couples the SSD 806 to the host. In some embodiments, the storage capacity and / or operating speed of the SSD 806 is greater than the storage capacity and / or operating speed of the memory card 802.

[0085] According to one aspect of this disclosure, a method for operating a memory device is provided. The memory device includes a memory array and peripheral circuitry coupled to the memory array, the memory array including memory cells. The peripheral circuitry includes a microcontroller unit (MCU) and a plurality of circuits controlled by the MCU. The MCU is configured to switch between a first register and a second register of a first circuit coupled to the plurality of circuits.

[0086] This method may include one or more of the following features.

[0087] In some implementations, the address of the first register is the same as the address of the second register.

[0088] In some implementations, the peripheral circuitry is configured to perform the following operations: During a first time period, first data corresponding to a first operation is sent from the MCU to a first register. During a second time period, the first operation is performed by the first circuitry, and second data corresponding to a second operation is sent from the MCU to a second register. The second operation occurs after the first operation.

[0089] In some implementations, a multiplexer (MUX) is coupled between the first register and the second register. The MCU is configured to send an enable signal to the MUX to enable switching between the first register and the second register.

[0090] In some implementations, the MCU is configured to send an enable signal to the MUX after a first time period and before a second time period.

[0091] In some implementations, the MCU is configured to switch between a third register and a fourth register of a second circuit coupled to multiple circuits. Peripheral circuitry is configured to perform the following operations: During a first time period, third data corresponding to a third operation is sent from the MCU to the third register. During a second time period, the third operation is performed by the second circuitry, and fourth data corresponding to a fourth operation is sent from the MCU to the fourth register. The fourth operation follows the third operation.

[0092] In some implementations, the peripheral circuitry is configured to perform the following operations: During a third time period, the first circuitry performs a second operation and sends fifth data corresponding to the fifth operation from the MCU to the first register. The fifth operation follows the second operation.

[0093] In some implementations, the MUX is coupled to the output terminal of the first register and the output terminal of the second register.

[0094] In some implementations, an enable signal is sent to the MUX, the enable terminal of the first register, and the enable terminal of the second register. The enable signal indicates that the input terminals of the first register and the output terminals of the second register are turned off, and the output terminals of the first register and the input terminals of the second register are turned on.

[0095] In some implementations, the peripheral circuitry is configured to perform the following operations: During a third time period, second data is sent from a second register to a first register, a second operation is performed by the first circuitry, and sixth data corresponding to a sixth operation is sent from the MCU to the second register. The sixth operation follows the second operation.

[0096] In some implementations, the MUX is coupled to the output terminal of the second register and the data bus of the MCU.

[0097] In some implementations, an enable signal is sent to the MUX and instructs data to be sent from the second register to the first register.

[0098] According to another aspect of this disclosure, a method for operating a memory device is provided. The method includes: during a first time period, sending first data corresponding to a first operation from a microcontroller unit (MCU) to a first register. The memory device includes peripheral circuitry including the MCU and a plurality of circuits controlled by the MCU. The first register is coupled to a first circuit among the plurality of circuits. The method further includes, during a second time period, performing the first operation by the first circuitry and sending second data corresponding to a second operation from the MCU to a second register coupled to the first circuitry. The second operation follows the first operation.

[0099] This method may include one or more of the following features.

[0100] In some implementations, the address of the first register is the same as the address of the second register.

[0101] In some implementations, the method further includes, after the first time period and before the second time period, the MCU sending a first enable signal indicating a switch between the first register and the second register.

[0102] In some implementations, the method further includes, during a first time period, sending third data corresponding to a third operation from the MCU to a third register. The third register is coupled to a second circuit in a plurality of circuits. The method further includes, during a second time period, having the third operation performed by the second circuit and sending fourth data corresponding to a fourth operation from the MCU to the fourth register coupled to the second circuit. The fourth operation follows the third operation.

[0103] In some implementations, the method further includes, during a third time period, the first circuit performing a second operation and sending fifth data corresponding to the fifth operation from the MCU to the first register. The fifth operation follows the second operation.

[0104] In some implementations, the method further includes: after the second time period and before the third time period, the MCU sends a second enable signal indicating a switch between the first register and the second register.

[0105] In some implementations, the method further includes: during a third time period, sending second data from a second register to a first register, performing a second operation by a first circuit, and sending sixth data corresponding to a sixth operation from the MCU to the second register. The sixth operation follows the second operation.

[0106] According to another aspect of this disclosure, a memory system is provided. The memory system includes a memory device and a memory controller coupled to the memory device. The memory device includes a memory array and peripheral circuitry coupled to the memory array, the memory array including memory cells. The peripheral circuitry includes a microcontroller unit (MCU) and a plurality of circuits controlled by the MCU. The MCU is configured to switch between a first register and a second register of a first circuit coupled to the plurality of circuits. The peripheral circuitry is configured to perform the following operations: During a first time period, first data corresponding to a first operation is sent from the MCU to the first register. During a second time period, the first operation is performed by the first circuitry, and second data corresponding to a second operation is sent from the MCU to the second register. The second operation follows the first operation. The controller is configured to send a signal to the memory device to initiate the first and second operations.

[0107] While this specification contains numerous specific implementation details, these should not be construed as limiting the scope of possible claims, but rather as descriptions of features that may be specific to particular embodiments. Certain features described in the context of individual embodiments in this specification may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any sub-combination in multiple embodiments. Furthermore, while previously described features may be described as functioning in certain combinations and even initially claimed in this way, in some cases, one or more features from the claimed combination may be removed from that combination, and the claimed combination may be for sub-combinations or variations thereof.

[0108] Note that references to "one embodiment," "implementation," "example embodiment," "some embodiments," etc., in this disclosure indicate that the described embodiments may include specific features, structures, or characteristics, but not every embodiment necessarily includes that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Additionally, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly described or not, incorporating other embodiments to affect such feature, structure, or characteristic is within the knowledge of those skilled in the art.

[0109] Generally, terms can be understood at least partly from their use in context. For example, depending at least partly on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, depending at least partly on the context, terms such as "a," "an," or "described" can again be understood to convey either a singular or a plural usage. Furthermore, the term "based on" can be understood to not necessarily be intended to convey an exclusive set of factors, and can alternatively allow for the presence of additional factors that are not necessarily explicitly described, again depending at least partly on the context.

[0110] As used in this disclosure, the terms “approximately” or “roughly” may allow for a degree of variability in the value or range, such as within 10%, 5%, or 1% of a specified value or range.

[0111] As used in this disclosure, the term “substantially” means the majority or most, such as at least about 50%, 60%, 70%, 80%, 90%, 95%, 96%, 97%, 98%, 99%, 99.5%, 99.9%, 99.99%, or at least about 99.999% or more.

[0112] Values ​​expressed in range format should be interpreted flexibly to include not only the values ​​explicitly listed as the limits of the range, but also all individual values ​​or subranges contained within that range, as if each value and subrange were explicitly stated. For example, a range of “0.1% to approximately 5%” or “0.1% to 5%” should be interpreted to include approximately 0.1% to approximately 5%, as well as individual values ​​within the specified range (e.g., 1%, 2%, 3%, and 4%) and subranges (e.g., 0.1% to 0.5%, 1.1% to 2.2%, 3.3% to 4.4%). Unless otherwise stated, the expression “X to Y” has the same meaning as “approximately X to approximately Y”. Similarly, unless otherwise stated, the expression “X, Y, or Z” has the same meaning as “approximately X, approximately Y, or approximately Z”.

[0113] Specific embodiments of the subject matter have been described. Other embodiments, modifications, and substitutions of the described embodiments are within the scope of the appended claims and will be apparent to those skilled in the art. Although operations are described in a specific order in the drawings or claims, it is not necessary to perform such operations in the specific or sequential order shown, or to perform all the operations shown (some operations may be considered optional), to achieve the desired result. In some cases, multitasking or parallel processing (or a combination of multitasking and parallel processing) may be advantageous and performed as deemed appropriate.

[0114] Furthermore, the separation or integration of the various system modules and components in the foregoing embodiments is not required in all embodiments, and the described components and systems can typically be integrated together or packaged into multiple products.

[0115] Therefore, the exemplary embodiments described above do not define or limit this disclosure. Other changes, substitutions, and modifications are possible without departing from the spirit and scope of this disclosure.

Claims

1. A memory device, comprising: A memory array, the memory array comprising memory cells; as well as Peripheral circuitry coupled to the memory array, wherein the peripheral circuitry includes a microcontroller unit (MCU) and multiple circuits controlled by the MCU, wherein the MCU is configured to switch between a first register and a second register of a first circuit coupled to the multiple circuits.

2. The memory device according to claim 1, wherein, The address of the first register is the same as the address of the second register.

3. The memory device according to claim 1 or 2, wherein, The peripheral circuit is configured as follows: During the first time period, first data corresponding to the first operation is sent from the MCU to the first register; and During the second time period: The first operation is performed by the first circuit; and The second data corresponding to the second operation is sent from the MCU to the second register, wherein the second operation follows the first operation.

4. The memory device according to claim 3, wherein, A multiplexer (MUX) is coupled between the first register and the second register, and wherein the MCU is configured to send an enable signal to the MUX to enable the switching between the first register and the second register.

5. The memory device according to claim 4, wherein, The MCU is configured to send the enable signal to the MUX after the first time period and before the second time period.

6. The memory device according to any one of claims 3 to 5, wherein, The MCU is configured to switch between a third register and a fourth register of a second circuit coupled to the plurality of circuits, wherein the peripheral circuits are configured as follows: During the first time period, third data corresponding to the third operation is sent from the MCU to the third register; and During the second time period: The third operation is performed by the second circuit; and The fourth data corresponding to the fourth operation is sent from the MCU to the fourth register, wherein the fourth operation is after the third operation.

7. The memory device according to any one of claims 3 to 6, wherein, The peripheral circuit is configured as follows: During the third time period: The second operation is performed by the first circuit; and The fifth data corresponding to the fifth operation is sent from the MCU to the first register, wherein the fifth operation follows the second operation.

8. The memory device according to claim 4 or 5, wherein, The MUX is coupled to the output terminals of the first register and the second register.

9. The memory device according to claim 8, wherein, The enable signal is sent to the MUX, the enable terminal of the first register, and the enable terminal of the second register, wherein the enable signal indicates: Disconnect the input terminals of the first register and the output terminals of the second register; and Connect the output terminal of the first register and the input terminal of the second register.

10. The memory device according to any one of claims 3 to 9, wherein, The peripheral circuit is also configured to: During the third time period: Send the second data from the second register to the first register; The second operation is performed by the first circuit; and The sixth data corresponding to the sixth operation is sent from the MCU to the second register, wherein the sixth operation is after the second operation.

11. The memory device according to claim 4 or 5, wherein, The MUX is coupled to the output terminal of the second register and the data bus of the MCU.

12. The memory device according to claim 11, wherein, The enable signal is sent to the MUX and instructs data to be sent from the second register to the first register.

13. A method for operating a memory device, wherein, The method includes: During a first time period, first data corresponding to a first operation is sent from a microcontroller unit (MCU) to a first register, wherein the memory device includes peripheral circuitry, the peripheral circuitry including the MCU and a plurality of circuits controlled by the MCU, and wherein the first register is coupled to a first circuit among the plurality of circuits; and During the second time period: The first operation is performed by the first circuit; and Second data corresponding to the second operation is sent from the MCU to a second register coupled to the first circuit, wherein the second operation follows the first operation.

14. The method according to claim 13, wherein, The address of the first register is the same as the address of the second register.

15. The method according to claim 13 or 14, further comprising: After the first time period and before the second time period, the MCU sends a first enable signal indicating a switch between the first register and the second register.

16. The method according to any one of claims 13 to 15, further comprising: During the first time period, third data corresponding to the third operation is sent from the MCU to a third register, wherein the third register is coupled to a second circuit among the plurality of circuits; and During the second time period: The third operation is performed by the second circuit; and Fourth data corresponding to the fourth operation is sent from the MCU to a fourth register coupled to the second circuit, wherein the fourth operation follows the third operation.

17. The method according to any one of claims 13 to 16, further comprising: During the third time period: The second operation is performed by the first circuit; and The fifth data corresponding to the fifth operation is sent from the MCU to the first register, wherein the fifth operation follows the second operation.

18. The method of claim 17, further comprising: After the second time period and before the third time period, the MCU sends a second enable signal indicating a switch between the first register and the second register.

19. The method according to any one of claims 13 to 18, further comprising: During the third time period: Send the second data from the second register to the first register; The second operation is performed by the first circuit; and The sixth data corresponding to the sixth operation is sent from the MCU to the second register, wherein the sixth operation is after the second operation.

20. A memory system, comprising: The memory device includes: Memory arrays including memory cells; and Peripheral circuitry coupled to the memory array, wherein the peripheral circuitry includes a microcontroller unit (MCU) and multiple circuits controlled by the MCU, wherein the MCU is configured to switch between a first register and a second register of a first circuit coupled to the multiple circuits, and wherein the peripheral circuitry is configured to: During the first time period, first data corresponding to the first operation is sent from the MCU to the first register; and During the second time period: The first operation is performed by the first circuit; and The second data corresponding to the second operation is sent from the MCU to the second register, wherein the second operation follows the first operation; and A controller, coupled to the memory device and configured to send signals to the memory device to initiate the first operation and the second operation.

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