Connection device, interconnection system and server

Abstract

The invention discloses a connecting device, an interconnection system and a server, and relates to the technical field of servers, the device comprises a device body and at least one connector assembly, the connector assembly comprises a plug sub-assembly and a socket sub-assembly, the socket sub-assembly is arranged on the device body, and the plug sub-assembly is arranged on the device body. One end of the first connector and one end of the second connector are connected with a third connector and a fourth connector in the plug sub-assembly through cables respectively, the other end of the first connector and the other end of the second connector are connected with the switching board circuit, and when the plug sub-assembly and the socket sub-assembly are mutually inserted, the third connector and the fourth connector are connected with the equipment body, so that the equipment body circuit is connected with the switching board circuit. And meanwhile, the device arrangement of the equipment body is not blocked, and the compatibility is better. The technical problem that the connector limits the equipment body architecture in the related technology is solved, and the technical effects of fully utilizing the space and improving the flexibility of the equipment body hardware architecture are achieved.

Description

Technical Field

[0001] This application relates to the field of server technology, and in particular to a connection device, interconnection system and server. Background Technology

[0002] In traditional server designs, especially in connection devices such as the mid-backplane (MBP), the layout of conventional blind-mating connectors presents significant limitations. High-density connectors on the front occupy a large projected area on the back of the device, preventing the placement of other components or signal traces in that area. This creates a physical and electrical shielding effect, isolating the wiring areas on the top and bottom sides of the backplane and hindering efficient space utilization. Furthermore, the placement of high-density connectors restricts the layout of surrounding components, forcing them to be placed close together, negatively impacting the overall board size, PCB (Printed Circuit Board) stack-up design, and thermal design. Particularly for connectors that need to route a large number of signals to the middle position on the top and bottom sides of the backplane, their placement must be in the central area of ​​the device, further restricting the flexibility of the overall system hardware architecture. Moreover, high-density connectors are non-standard connectors, potentially causing incompatibility issues when connecting to older or different brands of equipment, requiring additional adapters or conversion devices, increasing system complexity and cost. Summary of the Invention

[0003] This application provides a connection device, interconnection system, and server to at least solve the technical problem of connectors limiting device hardware architecture in related technologies.

[0004] This application provides a connection device, including: a device body and at least one set of connector assemblies; the connector assemblies include a first connector, a second connector, a first cable, a second cable, a socket subassembly, and a plug subassembly, wherein the socket subassembly includes a socket body and a first insertion portion and a second insertion portion formed within the socket body, the socket body being disposed on the device body; the plug assembly includes a plug body, a third insertion portion and a fourth insertion portion formed within the plug body, a third connector disposed within the third insertion portion, and a fourth connector disposed within the fourth insertion portion; the first connector, the second connector, the third connector, and the fourth connector are multi-channel input / output connectors; the first connector is connected to the third connector via a first cable, the second connector is connected to the fourth connector via a second cable, and the first connector and the second connector are connected to a switching board circuit. The third and fourth connectors connect to the switching board circuit upstream and to the graphics processor circuit, power board circuit, and fan board circuit downstream. The first and third connectors mate, and the second and fourth connectors mate to allow the plug and socket to be inserted into each other. When the plug and socket are inserted into each other, the connecting device is interconnected with the switching board circuit. The graphics processor circuit receives at least one of a high-speed signal, a reference clock signal, and a reset signal sent by the connecting device. The graphics processor circuit transmits data signals of at least one of a non-volatile memory, a universal serial bus, and a baseboard management controller between itself and the connecting device. The connecting device transmits sideband signals between itself and the power board circuit. The connecting device transmits fan-related sideband signals between itself and the fan board circuit. The connecting device transmits sideband signals and power signals between itself and the switching board circuit.

[0005] This application also provides an interconnection system, including: a switching board circuit, a graphics processor circuit, a power supply board circuit, and a fan board circuit; wherein the above-mentioned connection device is respectively connected to the switching board circuit, the graphics processor circuit, the power supply board circuit, and the fan board circuit.

[0006] This application also provides a server, including the aforementioned interconnection system.

[0007] This application utilizes at least one set of connector assemblies to achieve blind-mating interconnection between a device and a switching board circuit. Each connector assembly includes a plug subassembly and a socket subassembly. The socket subassembly is mounted on the device body. One end of the first and second connectors is connected to the third and fourth connectors in the plug assembly via cables, respectively. The other end of the first and second connectors is connected to the switching board circuit. When the plug assembly and socket assembly are inserted into each other, the third and fourth connectors connect to the device body, thus achieving interconnection between the device and the switching board circuit and establishing downlink connectivity with the device body. Using the lower-cost first, second, third, and fourth connectors enables blind-mating interconnection between the device and the switching board circuit, resulting in better compatibility. Therefore, this addresses the technical problem of connectors limiting device hardware architecture in related technologies, achieving the technical effect of fully utilizing device space and improving the flexibility of the device hardware architecture. Attached Figure Description

[0008] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0009] Figure 1 This application provides a schematic diagram of a connection device structure. Figure 2 Example diagrams of various plug-in portions on the plug assembly and socket assembly provided in the embodiments of this application; Figure 3 This application provides an embodiment of an interconnected system topology diagram; Figure 4 This is a structural diagram of a connector assembly provided in one embodiment of this application. Detailed Implementation

[0010] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0011] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0012] In related technologies, interconnection of switching boards is generally achieved through high-density connectors. Compared to some miniaturized connectors, high-density connectors are larger in size, especially in applications with extremely demanding space requirements, such as miniaturized servers and portable devices, where connector size may be a limitation. For connecting devices, such as backplanes, high-density connectors can make it difficult for high-speed PCB lines to avoid power layers, and some power layers may require additional copper busbars for connection. Furthermore, the design of high-density connectors is more complex, employing many advanced technologies to achieve high performance, such as integrated embossed grounding structures and beam-to-beam interface designs. This makes their manufacturing process more demanding, increasing production costs and resulting in relatively higher product prices. Especially for AI (Artificial Intelligence) servers, high-speed signal quality requirements are high, and the high-density connectors used are more expensive. At the same time, in order to fully utilize the performance advantages of high-density connectors, precise PCB design and manufacturing are required, including strict impedance control and precise routing planning, which increases the difficulty and cost of PCB manufacturing. In addition, high-density connectors are non-standard connectors, and when connecting with old equipment or equipment from different brands, incompatibility issues may occur, requiring additional adapters or conversion devices to achieve the connection, which increases the complexity and cost of the system.

[0013] To address the aforementioned shortcomings, this application proposes a connection device, an interconnection system, and a server to solve the technical problems of high connector costs and limitations on device hardware architecture in related technologies, thereby achieving cost savings. The details will be described in detail below.

[0014] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0015] Figure 1 This is a schematic diagram of the connection device structure provided in the embodiments of this application, such as... Figure 1As shown, the connection device includes: a device body 100, at least one set of connector assemblies 110, a first connector 111, a second connector 112, a first cable 113, a second cable 114, a plug subassembly 115, a plug body 1151, a third plug portion 1152, a fourth plug portion 1153, a third connector 1154, a fourth connector 1155, a socket subassembly 116, a socket body 1161, a first plug portion 1162, and a second plug portion 1163.

[0016] The connector assembly 110 includes a first connector 111, a second connector 112, a first cable 113, a second cable 114, a socket sub-assembly 116, and a plug assembly 115. The socket sub-assembly 116 includes a socket body 1161 and a first insertion portion 1162 and a second insertion portion 1163 formed within the socket body 1161. The socket body 1161 is disposed on the device body 100. The plug assembly 115 includes a plug body 1151 and a third insertion portion 1163 formed within the plug body 1151. 52 and the fourth connector 1153, the third connector 1154 and the fourth connector 1155 disposed in the third connector 1152 and the fourth connector 1155 disposed in the fourth connector 1153, the first connector 111, the second connector 112, the third connector 1154 and the fourth connector 1155 are multi-channel input / output connectors; the first connector 111 is connected to the third connector 1154 through the first cable 113, the second connector 112 is connected to the fourth connector 1155 through the second cable 114, the first connector 111 and the third connector 1155 are multi-channel input / output connectors; the first connector 111 is connected to the third connector 1154 through the first cable 113, the second connector 112 is connected to the fourth connector 1155 through the second cable 114, the first connector 111 and the fourth connector 1155 are multi-channel input / output connectors. Connector 112 connects to the switching board circuit 50. The upstream connections of the third connector 1154 and the fourth connector 1155 are connected to the switching board circuit 50. The downstream connections of the third connector 1154 and the fourth connector 1155 are connected to the graphics processor circuit 20, the power board circuit 30, and the fan board circuit 40. The first plug-in part 1162 cooperates with the third plug-in part 1152, and the second plug-in part 1163 cooperates with the fourth plug-in part 1153 to realize the mutual insertion of the plug and socket. When the plug and socket are mutually inserted, the connecting device is interconnected with the switching board circuit 50. The graphics processor circuit 20 receives at least one of the high-speed signal, the reference clock signal, and the reset signal sent by the connecting device 10. The graphics processor circuit 20 and the connecting device 10 transmit data signals of at least one of the non-volatile memory, the universal serial bus, and the board management controller. The connecting device 10 and the power board circuit 30 transmit sideband signals. The connecting device 10 and the fan board circuit 40 transmit fan-related sideband signals. The connecting device 10 and the switching board circuit 50 transmit sideband signals and power signals.

[0017] Among them, the switching board circuit 50 is a PCB module integrating a high-speed switching chip, responsible for efficiently forwarding and scheduling data traffic between multiple processors; the fan board is a dedicated circuit board in the server used to control and manage the fan module; the reference clock signal is PEX_REFCLK<0-2>, which is the PCIe reference clock signal, and the reset signal is PEX_RST<0-2>_N, which is the PCIe reset signal. High-speed signals of the graphics processor circuit are transmitted through the PCIE 5.0X16_GPU1B~8B interface, which has a 16-channel width and is designed specifically for high-performance graphics processors. Simultaneously, the digital signals of the non-volatile memory and the graphics processor circuit 20 are transmitted through the PCIE 3.0 X2_NVS interface, which has a 2-channel width and is designed specifically for high-performance graphics processors, for devices such as NVS (Non-Volatile Storage). The universal serial bus and the digital signals of the graphics processor circuit 20 are transmitted through the USB (Universal Serial Bus) managed by the HMC (High-Speed ​​Memory Controller, Hybrid Memory Cube). The BMC (Baseboard Management Controller) 2.0 interface transmits digital signals between the Baseboard Management Controller (BMC) and the Graphics Processor (GPU) circuit 20 via the BMC_I2C interface, enabling downlink data transmission and interconnection.

[0018] It should be noted that the multi-channel input / output connector is an MCIO (Mini Cool Edge Input / Output) connector. In this embodiment, the first connector 111 and the second connector 112 form a set of MCIO connectors, that is, a set consists of two MCIO connectors. The MCIO connector is a high-performance, high-density internal interface solution. The MCIO has a pin pitch of 0.6mm and adopts a compact design. It supports high-efficiency data transmission while optimizing system space. It is suitable for designs that require high-speed signal cabling and management in limited space, such as servers, network equipment, and other demanding data center applications. Furthermore, since the MCIO connector allows for cabling on the back, the cabling on the back of the device does not need to avoid the blind mating structure, which greatly reduces the difficulty of cabling. It supports multiple data transmission protocols, such as PCIe and CXL (Compute Express Link), and can meet the single-channel 56Gbps transmission requirement. The maximum data transmission rate can reach 64Gbps, enabling high-speed data transmission from chip to chip, chip to I / O (Input / Output), chip to backplane, board to board, and PCB edge.

[0019] The MCIO connector offers multiple channel options, including 4X (38 pins), 8X (74 pins), 16X (124 pins), and 20X (148 pins), where X indicates the number of high-speed differential signal channels supported by the connector. For example, 4X represents 4 channels, and up to 20 channels can be customized, providing flexible options for different application scenarios. The plug sub-assembly 115 and the socket sub-assembly form the Surelink connector. The first mating part 1162 and the second mating part 1163 of the Surelink connector, along with the corresponding third mating part 1152 and the fourth mating part 1153, ensure reliable blind mating through dual guidance. The dual guidance design is a mechanism that ensures that the plug sub-assembly 115 and the socket sub-assembly can be accurately aligned and smoothly connected during insertion. By guiding the two components through physical structural features, reliable connection can be achieved even in limited space or blind mating conditions. This effectively prevents incorrect connection, reduces wear, improves connection stability and lifespan, and provides a reliable blind mating connection solution.

[0020] It is understood that the embodiments of this application include a device body 100 and at least one set of connector assemblies 110. The connector assembly 110 is composed of a first connector 111, a second connector 112, a first cable 113, a second cable 114, a socket subassembly 116, and a plug subassembly 115. The socket subassembly 116 includes a socket body 1161 with a first insertion portion 1162 and a second insertion portion 1163, and is mounted on the device body 100. The plug assembly 115 includes a plug body 1151 with a third insertion portion 1152 and a fourth insertion portion 1153. The third connector 1154 and the fourth connector 1155 are respectively disposed in the third plug-in portion 1152 and the fourth plug-in portion 1153. All of these connectors are multi-channel input / output connectors, i.e., MCIO connectors. The first connector 111 and the third connector 1154 are connected via a first cable 113, and the second connector 112 and the fourth connector 1155 are connected via a second cable 114. The first connector 111 and the second connector 112 are connected to the switching board circuit 50, and the third connector 1154 and the fourth connector 1155 are connected to the downstream circuit of the device body 100 (as shown in the figure). The graphics processor circuit (GPU) is connected to the power board circuit (Power Board Circuit) 30 and the fan board circuit (Fan Board Circuit) 40. The GPU receives high-speed signals from the connection device 10, including at least one reference clock signal and a reset signal, and transmits data signals from at least one non-volatile memory, universal serial bus, and board management controller to the connection device 10 via the GPU. Sideband signals are transmitted between the connection device 10 and the power board circuit 30, and fan-related sideband signals are transmitted between the connection device 10 and the fan board circuit 40. Data signals are transmitted between the connection device 10 and the switchboard circuit 50. The transmission of sideband signals and power signals enables data communication between uplink and downlink. The plug sub-assembly 115 and the socket sub-assembly 116 complete the docking through the precise cooperation of the first plug part 1162 and the third plug part 1152, and the second plug part 1163 and the fourth plug part 1153. The Surelink connector structure it adopts has a dual guiding mechanism to ensure reliable alignment and smooth connection even in blind mating environment, effectively preventing mis-insertion and wear. In addition, since the MCIO connector can be wired on the back, the wiring on the back of the device does not need to avoid the blind mating structure, which greatly reduces the difficulty of wiring.

[0021] In this embodiment of the application, at least one fifth plug portion is formed on the plug body 1151, and at least one sixth plug portion is formed on the socket body 1161. The fifth plug portion and the sixth plug portion cooperate to realize the mutual insertion of the plug sub-assembly 115 and the socket sub-assembly 116.

[0022] The fifth and sixth mating parts employ dual guidance to ensure reliable blind mating. This guarantees correct positioning during blind mating, prevents incorrect connections, reduces wear, and improves connection stability and lifespan, thus achieving a reliable blind mating connection solution. Figure 2 The diagram shown is an example of the various plug-in portions on the plug sub-assembly 115 and socket sub-assembly 116 according to an embodiment of this application. The specific design can be determined according to actual needs. Figure 2 This is only a structural example and is not intended to impose any specific limitations.

[0023] It is understood that at least one fifth plug portion is formed on the plug body 1151 of this application embodiment, and at least one sixth plug portion is formed on the socket body 1161. The fifth plug portion and the sixth plug portion cooperate with each other to realize the plug sub-assembly 115 and the socket sub-assembly 116 pluggable connection. The fifth plug portion and the sixth plug portion ensure reliable blind insertion operation through a double guide structure, which can ensure accurate positioning during blind insertion, prevent incorrect connection, reduce plug wear, improve connection stability and service life, thereby realizing a highly reliable blind insertion connection solution.

[0024] In this embodiment, the connector assembly 110 is provided with a power supply line. The power supply line runs along the signal lines of the sideband signals of the first connector 111, the second connector 112, the third connector 1154 and the fourth connector 1155, and draws power from the switching board circuit 50 through the power supply line.

[0025] Some voltages of the device body 100 need to be drawn from the switching board circuit 50. For example, the 12V of the device body 100 needs to be drawn from the switching board circuit 50. Sideband signals refer to low-speed signals used to transmit control, status, and management information, other than the main high-speed data channel, such as I2C (Inter-Integrated Circuit), GPIO (General-Purpose Input / Output), USB (Universal Serial Bus), PSU (Power Supply Unit) communication, etc.

[0026] It is understood that the connector assembly 110 in this application embodiment is provided with a power supply line, which is wired along the signal line of the sideband signal between the first connector 111, the second connector 112, the third connector 1154 and the fourth connector 1155; through the power supply line, power is drawn from the connected switching board circuit 50 and transmitted to the device body 100.

[0027] In this embodiment of the application, the first connector 111, the second connector 112, the third connector 1154 and the fourth connector 1155 are provided with power supply pins, and the pins on both sides of the power supply pins are unused.

[0028] The purpose of leaving the pins on both sides of the power supply pin empty is to prevent misalignment of the first connector 111, the second connector 112, the third connector 1154, or the fourth connector 1155 due to blind insertion, which could cause the power supply pin to short-circuit to the pins on both sides, resulting in voltage breakdown of other devices. The in-position pin is a dedicated electrical contact for detecting whether the module or connection component has been correctly inserted and is in place. When the connector is fully inserted, this pin will change its level state by grounding or energizing, sending a signal to the system to indicate that the connector is in position.

[0029] It should be noted that, since the first connector 111 and the second connector 112 are a group, and the third connector 1154 and the fourth connector 1155 are a group, the first connector 111 and the second connector 112 only need to retain the in-position pin on one of the connectors, and it is not necessary to retain the in-position pin on each connector. This minimizes the occupation of the connector sideband pins and increases the number of available pins for interconnection. The same applies to the third connector 1154 and the fourth connector 1155.

[0030] It is understood that the first connector 111, the second connector 112, the third connector 1154, and the fourth connector 1155 in this embodiment of the application are provided with power supply pins, and the pin positions on both sides of the power supply pins are designed to be empty. The purpose of this empty design is to prevent the first connector 111, the second connector 112, the third connector 1154, or the fourth connector 1155 from becoming misaligned due to improper insertion or misalignment during blind mating, thereby causing the power supply pin to short-circuit with the adjacent pins on both sides, resulting in abnormal voltage conduction to other circuit devices, causing device breakdown or damage. By leaving the pins on both sides of the power supply pin empty, the safety and reliability of the connection are improved.

[0031] In this embodiment of the application, the first connector 111, the second connector 112, the third connector 1154 and the fourth connector 1155 are provided with in-place pins, which are used to determine the in-place state of the connector assembly 110.

[0032] The "in-position" pin is an electrical contact specifically used to detect whether a module or connection component has been correctly inserted and is in place. When the connector is fully inserted, this pin changes its level state by grounding or energizing, sending a signal to the system to indicate that the connector is in position.

[0033] It should be noted that, since the first connector 111 and the second connector 112 are a group, and the third connector 1154 and the fourth connector 1155 are a group, the first connector 111 and the second connector 112 only need to retain the in-position pin on one of the connectors, and it is not necessary to retain the in-position pin on each connector. This minimizes the occupation of the connector sideband pins and increases the number of available pins for interconnection. The same applies to the third connector 1154 and the fourth connector 1155.

[0034] It is understood that the first connector 111, the second connector 112, the third connector 1154, and the fourth connector 1155 in this application embodiment are provided with an in-position pin. The in-position pin serves as an electrical contact for detecting whether the module or connection component has been correctly inserted and positioned, and is used to determine the in-position status of the connector. Since the first connector 111 and the second connector 112 are a group, and the third connector 1154 and the fourth connector 1155 are a group, in the first connector 111 and the second connector 112, it is only necessary to select one connector to retain the in-position pin to realize the status detection. It is not necessary to set it on every connector, so as to minimize the occupation of the connector side pins and increase the number of pins available for interconnection. The same applies to the third connector 1154 and the fourth connector 1155.

[0035] In this embodiment of the application, the first connector 111, the second connector 112, the third connector 1154 and the fourth connector 1155 are provided with at least one sideband signal pin and at least one high-speed signal pin. The sideband signal pin receives a sideband signal, the high-speed signal pin receives a high-speed signal, and ground pins are provided on both sides of the high-speed signal pin. The ground pins are used to shield the high-speed signal.

[0036] Since the original MCIO has a limited number of high-speed signal pins, some relatively high-speed signals need to go through the sideband signals of the MCIO connector. Therefore, some high-speed signal pins are replaced by improved sideband signal pins. The high-speed signal pins are connected to the sideband signal pins of the MCIO by adding ground pins on both sides. The high-speed signals are shielded by the ground pins on both sides to ensure their signal integrity.

[0037] It should be noted that in this embodiment, the relatively low-speed I2C signal pins also ensure signal quality by adding ground pins on both sides of the pins. In addition, this method also ensures the standardization of the cable, so there is no need to make a separate cable for the high-speed sideband signal; only a standard cable is required.

[0038] It is understood that the first connector 111, the second connector 112, the third connector 1154, and the fourth connector 1155 in this application embodiment are provided with at least one sideband signal pin and at least one high-speed signal pin. The sideband signal pin is used to receive sideband signals, and the high-speed signal pin is used to receive high-speed signals. Since the original number of high-speed signal pins of the MCIO connector is limited, some relatively high-speed signals need to be transmitted through the MCIO sideband signal channel. Therefore, some high-speed signal pins are also used by the improved sideband signal pins. Furthermore, this application embodiment provides ground pins on both sides of the high-speed signal pins. The high-speed signals are shielded by the ground pins on both sides, ensuring the integrity of the high-speed signals. This eliminates the need for separate cables for high-speed sideband signals, requiring only standard cables and reducing design complexity.

[0039] In this embodiment, the power board circuit 30 includes a power board body, a power connector piece disposed on the power board body, and a sideband connector. The power connector piece is connected to the graphics processor circuit 20 and the fan board circuit 40. The sideband connector is connected to the third connector 1154 and the fourth connector 1155 to transfer the sideband signal to the power board circuit 30.

[0040] Among them, the power connector is CILP (Current Integrated Link Power), which is a high-power connection component used for high current power transmission. It is commonly used in scenarios with extremely high power supply requirements. In this embodiment, it provides a connection between the device body 100 and the power board, and provides a P54V input to the device body 100.

[0041] It is understood that the power board circuit 30 in this embodiment mainly includes a power board body, and a power connection piece and a sideband connector disposed thereon. The power connection piece is used to connect the graphics processor circuit 20 and the fan board circuit 40 to provide power to these functional modules. The power connection piece adopts a CILP structure, which is a high-density power connection component designed for high power and high current transmission. It is suitable for application scenarios with stringent power supply requirements and can provide a stable P54V power input to the device body 100. At the same time, the sideband connector is connected to the third connector 1154 and the fourth connector 1155 in the plug sub-assembly 115 to transfer the sideband signal from the switching board circuit 50 to the power board circuit 30, realizing auxiliary functions such as power status monitoring and management communication, thereby ensuring the reliability and manageability of the system power supply.

[0042] In this embodiment of the application, the graphics processor circuit 20 includes a high-density connector and a first power connector, wherein the high-density connector is connected to the third connector 1154 and the fourth connector 1155, and the first power connector is connected to the power connector piece.

[0043] Among them, the high-density connector is a high-density connector (such as EXAMAX) that supports high-speed serial protocols (such as PCIe, CXL) and is used to realize data transmission between the device and the graphics processing unit (GPU) board; the first power connector is a board-to-board power connector that can supply power to the graphics processing circuit 20.

[0044] It is understood that the graphics processor circuit 20 in this embodiment mainly includes a high-density connector and a first power connector. The high-density connector is connected to the third connector 1154 and the fourth connector 1155 in the plug sub-assembly 115 to realize high-speed data communication between the graphics processor board and the device. The first power connector is connected to the power connector on the power board to provide the necessary power to the graphics processor circuit 20. The high-density connector is a high-performance connection solution that supports high-speed serial protocols such as PCIe and CXL. It has high density, small pitch and excellent signal integrity, and is suitable for efficient interconnection between GPU and switching board in servers and high-performance computing devices. The first power connector adopts a board-to-board power connection structure, which can carry large current and ensure stable operation of the graphics processor under high load, thereby ensuring the high performance and reliability of the GPU system in terms of both data transmission and power supply.

[0045] According to the connection device provided in the embodiments of this application, at least one set of connector assemblies is used to realize blind mating interconnection between the device and the switching board circuit. The connector assembly includes a plug subassembly and a socket subassembly. The socket subassembly is disposed on the device body. One end of the first and second connectors is connected to the third and fourth connectors in the plug assembly through cables, respectively. The other end of the first and second connectors is connected to the switching board circuit. When the plug assembly and the socket assembly are inserted into each other, the third and fourth connectors are connected to the device body, realizing the interconnection between the device and the switching board circuit and the downlink connection with the device body. At the same time, it does not obstruct the device arrangement on the back of the device, resulting in better compatibility. It achieves the technical effect of making full use of device space and improving the flexibility of device hardware architecture.

[0046] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0047] The connection device of this application will be further described below through a specific embodiment.

[0048] This embodiment uses an MCIO connector to connect the switching board. The system topology diagram is as follows: Figure 3As shown, specifically: In this embodiment, the connection device is a backplane, using 16 MCIO connectors, i.e., 8 sets of connector assemblies, to achieve connection with the switch board and realize signal input and interaction. The backplane connects downstream to the graphics processor circuit Hopper-Next via a high-speed backplane connector assembly. This high-speed backplane connector assembly includes 8 high-speed EXAMAX connectors (a proprietary connector name) and 6 power adapters PWR CONNs. The power adapters PWR CONNs transfer the power input from the power clips on the backplane to provide the necessary power to the graphics processor circuit Hopper-Next. Simultaneously, the high-speed EXAMAX connectors receive high-speed signals from the first connector, such as... Figure 3 As shown, it includes: PEX_REFCLK<0-2>, the PCIe reference clock signal; PEX_RST<0-2>_N, the PCIe reset signal; and the following interfaces: PCIE 5.0X16_GPU1B~8B, a 16-channel interface designed for high-performance graphics processors; PCIE 3.0 X2_NVS, a PCIe 3.0 version, a 2-channel interface for devices such as NVS (Non-Volatile Storage); HMC_USB2.0, a USB (Universal Serial Bus) 2.0 interface managed by HMC (High-Speed ​​Memory Controller, Hybrid Memory Cube); and BMC_I2C, a BMC (Baseboard Management Controller) I2C interface, to achieve downlink data transmission and interconnection. Since the MCIO can be routed behind it, the board routing does not need to avoid the blind-plug structure, greatly reducing the routing difficulty.

[0049] In this embodiment, the present application embodiment also includes a power supply component disposed on the backplane, wherein the power supply component includes a power clip and a sideband connector; the power clip is used to transfer the power input of the 54V power board to the backplane, providing power input (i.e., P54V) ​​to the backplane, and the sideband connector is connected to the first connector to receive sideband signals (such as I2C, PSU, etc.) and transfer these signals to the relevant control circuit of the power supply component, thereby realizing the monitoring, management and coordinated control of the power status, and ensuring the stability and reliability of the system power supply; this embodiment also includes a board-to-board blade connector disposed on the backplane, one end of which is electrically connected to the power clip and the first connector, and the other end is connected to the fan board; through the board-to-board blade connector, the P54V working power of the power clip, the fan-related sideband signals from the first connector and the standby voltage signal P3V3_STBY, etc. are transferred to the fan board, realizing the power supply and control signal transmission to the fan board.

[0050] This embodiment also includes an MBP FRU (Mother Board Field Replaceable Unit), a backplane required for the motherboard, Thermal Sensor, and VR (Voltage Regulator) that can be replaced and maintained in the field. The MBP FRU transmits signals to the BMC_I2C9 (Baseboard Management Controller I2C Interface 9), and the standby voltage signal P3V3_STBY required by the fan board is obtained through VR adjustment.

[0051] This embodiment utilizes an MCIO connector and a corresponding blind-mating structure. Through special pin configurations, the MCIO connector can be used for backplane connections, thus addressing the technical problem in related technologies where connectors limit the hardware architecture of backplanes. Specifically, the following improvements were made to enable the application of MCIO to backplanes: Blind-mating issue between the backplane and the switch board: Since the backplane is located inside the chassis in the architecture, it is difficult to directly plug cables in during installation, requiring a blind-mating design. However, ordinary MCIO connectors currently cannot support blind mating inside the chassis. Therefore, this application introduces a Surelink connector (i.e., the aforementioned plug and socket) into the backplane. Using the Surelink connector, reliable blind mating is ensured through dual guidance, enabling high-speed blind mating between the switch board and the backplane. The structure of the Surelink connector + MCIO connector blind mating is as follows... Figure 4 As shown.

[0052] MCIO connector power supply design: Because the 12V of the middle backplane needs to be drawn from the switching board (e.g., Figure 3 (As shown in P12V_STBY, +12V standby power supply). Compared to traditional high-density connectors, MCIO connectors pose a relatively higher risk when supplying 12V power. Therefore, this embodiment employs a special design for the 12V power supply. The 12V power supply is routed through the sideband signal position of the MCIO connector. Based on current requirements, two pins are selected to supply 12V power to the backplane. For the 12V power supply pin, the pins on both sides are left unconnected to prevent misalignment during blind mating, which could cause the MCIO connector to misalign and short-circuit the 12V pin to the pins on both sides. Since the same MCIO connector is used, to prevent errors during blind mating, the positions of other MCIO power supply pins and the pins on both sides are also left unconnected to minimize the risk of 12V damage to other devices due to incorrect mating.

[0053] The method for processing sideband signals in this embodiment is as follows: Connector in-situ configuration: Due to the use of a Surelink connector + MCIO connector configuration, the two MCIO connectors on the backplane are grouped together and mated using a single housing (i.e., the Surelink connector). Each group of connectors reserves in-situ pins on only one MCIO connector to minimize the occupation of MCIO connector sideband pins and increase the number of available interconnect pins.

[0054] Because the MCIO connector has a limited number of high-speed pins, some relatively high-speed signals need to be routed through the MCIO connector's sideband signals. For high-speed signals such as USB and CPU (Central Processing Unit) Gen3 PCIe, ground pins are added to both sides to connect them to the MCIO connector's sideband signal pins. The ground pins on both sides shield the high-speed signals, ensuring signal integrity. The relatively low-speed I2C signals also maintain signal quality in this way. At the same time, this method ensures cable standardization; no separate MCIO cable is needed for high-speed sideband signals, only a standard cable is required.

[0055] Embodiments of this application also provide an interconnection system, including: a switching board circuit, a graphics processor circuit, a power supply board circuit, and a fan board circuit; and the aforementioned connection device, wherein the connection device is respectively connected to the switching board circuit, the graphics processor circuit, the power supply board circuit, and the fan board circuit.

[0056] Embodiments of this application also provide a server, including the interconnection system described above.

[0057] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0058] The foregoing has provided a detailed description of a connection device, interconnection system, and server provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only intended to aid in understanding the methods and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A connection device, characterized in that, include: The device body and at least one set of connector assemblies; The connector assembly includes a first connector, a second connector, a first cable, a second cable, a socket subassembly, and a plug subassembly. The socket subassembly includes a socket body and a first and a second insertion portion formed within the socket body. The socket body is disposed on the device body. The plug subassembly includes a plug body, a third and a fourth insertion portion formed within the plug body, a third connector disposed within the third insertion portion, and a fourth connector disposed within the fourth insertion portion. The first connector, the second connector, the third connector, and the fourth connector are multi-channel input / output connectors. The first connector is connected to the third connector via the first cable, and the second connector is connected to the fourth connector via the second cable. The first connector and the second connector are connected to the switching board circuit. The upstream of the third connector and the fourth connector is connected to the switching board circuit, and the downstream of the third connector and the fourth connector is connected to the graphics processor circuit, the power board circuit, and the fan board circuit. The first plug part cooperates with the third plug part, and the second plug part cooperates with the fourth plug part to realize the mutual insertion of the plug and the socket. When the plug and the socket are mutually inserted, the connecting device is interconnected with the switching board circuit. The graphics processor circuit receives at least one of a high-speed signal, a reference clock signal, and a reset signal sent by the connection device. The graphics processor circuit transmits data signals of at least one of a non-volatile memory, a universal serial bus, and a baseboard management controller between itself and the connection device. The connection device transmits sideband signals between itself and the power board circuit. The connection device transmits fan-related sideband signals between itself and the fan board circuit. The connection device transmits sideband signals and power signals between itself and the switching board circuit.

2. The connection device according to claim 1, characterized in that, The plug body has at least one fifth plug portion, and the socket body has at least one sixth plug portion. The fifth plug portion and the sixth plug portion cooperate to realize the mutual insertion of the plug sub-assembly and the socket sub-assembly.

3. The connection device according to claim 1, characterized in that, The connector assembly is provided with a power supply line, which runs along the signal lines of the sideband signals of the first connector, the second connector, the third connector and the fourth connector, and draws power from the switching board circuit through the power supply line.

4. The connection device according to claim 1, characterized in that, The first connector, the second connector, the third connector and the fourth connector are provided with power supply pins, and the pins on both sides of the power supply pins are unused.

5. The connection device according to claim 1, characterized in that, The first connector, the second connector, the third connector, and the fourth connector are provided with at least one sideband signal pin and at least one high-speed signal pin. The sideband signal pin receives the sideband signal, and the high-speed signal pin receives the high-speed signal. Ground pins are provided on both sides of the high-speed signal pin, and the ground pins are used to shield the high-speed signal.

6. The connection device according to claim 1, characterized in that, The power board circuit includes a power board body, a power connector piece disposed on the power board body, and a sideband connector. The power connector piece connects the graphics processor circuit and the fan board circuit. The sideband connector connects to the third connector and the fourth connector to transfer the sideband signal to the power board circuit.

7. The connection device according to claim 6, characterized in that, The graphics processor circuit includes a high-density connector and a first power connector, wherein the high-density connector is connected to the third connector and the fourth connector, and the first power connector is connected to the power connector piece.

8. The connection device according to claim 6, characterized in that, The fan board circuit includes a fan board body and a second power connector and a signal connector disposed on the fan board body, wherein the second power connector is connected to the power connector piece, and the signal connector is connected to the third connector and the fourth connector.

9. An interconnection system, characterized in that, include: Switching board circuit, graphics processor circuit, power supply board circuit, and fan board circuit; The connection device according to any one of claims 1-8, wherein the connection device is respectively connected to the switching board circuit, the graphics processor circuit, the power supply board circuit and the fan board circuit.

10. A server, characterized in that, Including the interconnection system as described in claim 9.

Images