ACOT control circuit for BUCK power supply

Abstract

The invention discloses an ACOT control circuit for a BUCK power supply, which comprises an SW node and an LDRV node of a BUCK circuit, the SW node is a switch node for connecting an upper power tube and a lower power tube in the BUCK circuit, the LDRV node inputs a lower power tube driving signal of the BUCK circuit, and the ACOT control circuit further comprises a comparator, a second NMOS tube, a current generating resistor and a charging capacitor, the SW node is connected with the negative electrode input end of the comparator through a current generating resistor, the charging capacitor changes the voltage of the negative electrode input end of the comparator through a second NMOS tube, and the second NMOS tube controls the on-off of the second NMOS tube through a signal input by an LDRV node; the circuit further comprises a follower, a charging resistor, a divider resistor and a current mirror. The SW node is connected with the positive input end of the comparator through the divider resistor, the follower, the current mirror and the charging resistor in sequence.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to an ACOT control circuit for a BUCK power supply. Background Technology

[0002] like Figure 1 As shown, the COT constant on-time control mode in the BUCK circuit has been widely used in switching power supply management chips due to its simple control mode and fast load response speed. However, because its working principle is based on a fixed on-time of the upper transistor, the chip frequency will change with the input voltage, resulting in poor EMC performance. The ACOT control mode was thus developed, which adaptively adjusts the on-time of the upper transistor (Ton) to keep the chip operating frequency relatively constant, thereby improving EMC performance. Summary of the Invention

[0003] In view of the above-mentioned shortcomings in the current integrated circuit technology field, the present invention provides an ACOT control circuit for BUCK power supply, which can obtain a power supply system with constant switching frequency, effectively improve the EMC characteristics of the system, and at the same time, errors in the circuit can be optimized by means of structural modification and replacement, further enabling the system frequency to match the set value.

[0004] To achieve the above objectives, the embodiments of the present invention adopt the following technical solutions: An ACOT control circuit for a BUCK power supply includes an SW node and an LDRV node of the BUCK circuit. The SW node is a switching node connecting the upper and lower power transistors in the BUCK circuit. The LDRV node receives the drive signal of the lower power transistor of the BUCK circuit. The circuit also includes a comparator, a second NMOS transistor, a current generating resistor, and a charging capacitor. The SW node is connected to the negative input terminal of the comparator through the current generating resistor. The charging capacitor changes the voltage at the negative input terminal of the comparator through the second NMOS transistor. The second NMOS transistor controls its own switching through the signal input to the LDRV node. The circuit also includes a follower, a charging resistor, a voltage divider resistor, and a current mirror. The SW node is connected to the positive input terminal of the comparator in sequence through the voltage divider resistor, the follower, the current mirror, and the charging resistor.

[0005] According to one aspect of the present invention, the voltage divider resistor includes a first voltage divider resistor and a second voltage divider resistor, wherein the sum of the resistance of the first voltage divider resistor and the second voltage divider resistor is set as a fixed multiple of the resistance of the second voltage divider resistor.

[0006] According to one aspect of the invention, it further includes a first filter and a second filter connected together, the first filter and the second filter being connected between the voltage divider resistor and the follower.

[0007] According to one aspect of the present invention, the follower includes an amplifier, an external frequency-selective resistor, and a first NMOS transistor. The positive input terminal of the amplifier is connected to a voltage divider resistor, the negative input terminal is connected to one end of the external frequency-selective resistor, the other end of the external frequency-selective resistor is grounded, the output terminal of the amplifier is connected to the gate of the first NMOS transistor, the source of the first NMOS transistor is connected to the external frequency-selective resistor, and the drain of the first NMOS transistor is connected to a current mirror.

[0008] According to one aspect of the present invention, the current mirror includes a first PMOS transistor and a second PMOS transistor, wherein the drain and gate of the first PMOS transistor are interconnected, the drain is connected to a follower, and the gate is connected to the gate of the second PMOS transistor; the source of the first PMOS transistor and the source of the second PMOS transistor are connected to VDD, and the drain of the second PMOS transistor is connected to a charging resistor and the positive input terminal of a comparator.

[0009] According to one aspect of the present invention, the ratio of the number of the first PMOS transistor and the number of the second PMOS transistor connected in parallel is set to a fixed value.

[0010] According to one aspect of the invention, one end of the charging resistor is connected to the positive input terminal of the current mirror and the comparator, and the other end is grounded.

[0011] According to one aspect of the invention, a third PMOS transistor is further included, which is used as an upper clamp. The gate of the third PMOS transistor is connected to a charging resistor, the drain is grounded, and the source is connected to the negative input terminal of the comparator.

[0012] According to one aspect of the present invention, when the second NMOS transistor is turned off, the SW node charges the charging capacitor, and the lower power transistor in the BUCK circuit is turned off and the upper power transistor is turned on, and the input voltage of the SW node is the input voltage of the BUCK circuit.

[0013] According to one aspect of the present invention, when the second NMOS transistor is turned off, the voltage at the negative input terminal of the comparator slowly increases until it reaches the voltage at the positive input terminal of the comparator, the comparator output flips, and the output signal is ultimately controlled by the logic circuit to control the turn-on time of the power transistor.

[0014] The advantages of this invention are as follows: It includes a SW node and an LDRV node in a BUCK circuit. The SW node is a switching node connecting the upper and lower power transistors in the BUCK circuit. The LDRV node receives the drive signal of the lower power transistor in the BUCK circuit. It also includes a comparator, a second NMOS transistor, a current generating resistor, and a charging capacitor. The SW node is connected to the negative input terminal of the comparator through the current generating resistor. The charging capacitor changes the voltage at the negative input terminal of the comparator through the second NMOS transistor. The second NMOS transistor controls its own switching through the signal input from the LDRV node. It also includes a follower, a charging resistor, a voltage divider resistor, and a current mirror. The SW node is connected to the positive input terminal of the comparator in sequence through the voltage divider resistor, the follower, the current mirror, and the charging resistor. This can obtain a power supply system with a constant switching frequency, effectively improving the EMC characteristics of the system. At the same time, errors in the circuit can be optimized through structural modifications and replacements, further ensuring that the system frequency matches the set value. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is an overall block diagram of the BUCK circuit for an ACOT control circuit used in a BUCK power supply, as described in this invention. Figure 2 This is a schematic diagram of the ACOT control circuit for a BUCK power supply according to the present invention. Detailed Implementation

[0017] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0018] Example 1: like Figure 2As shown, an ACOT control circuit for a BUCK power supply includes an SW node, an input voltage VDD, an LDRV node, a comparator COMP, voltage divider resistors, a filter, a follower, a current mirror, a charging resistor R0, a current generating resistor RX, a charging capacitor C0, a second NMOS transistor MN2, and a third PMOS transistor MP3. The SW node is the switching node connecting the upper and lower power transistors in the BUCK circuit. The LDRV node receives the in-phase control signal driven by the lower power transistor of the BUCK circuit. The SW node is connected to the positive input terminal of the comparator COMP in sequence through the voltage divider resistors, the filter, the follower, and the current mirror.

[0019] The voltage divider resistors include a first voltage divider resistor R1 and a second voltage divider resistor R2; the filter includes a first filter and a second filter, the first filter includes a resistor R3 and a capacitor C1, and the second filter includes a resistor R4 and a capacitor C2; the follower includes an amplifier OP, a first NMOS transistor MN1 and an external frequency selection resistor RT; the current mirror includes a first PMOS transistor MP1 and a second PMOS transistor MP2.

[0020] Node SW is connected to one end of the first voltage divider resistor R1. The other end of the first voltage divider resistor R1 is connected to the second voltage divider resistor R2 and resistor R3. The other end of the second voltage divider resistor R2 is grounded. The ratio of the combined resistance of the first voltage divider resistor R1 and the second voltage divider resistor R2 to the resistance of the second voltage divider resistor R2 is set to n:1. The other end of resistor R3 is connected to capacitor C1 and resistor R4. The other end of resistor R4 is connected to capacitor C2 and the positive input terminal of amplifier OP. The other ends of capacitors C1 and C2 are grounded. The negative input terminal of amplifier OP is connected to the external frequency selection resistor RT. The other end of the external frequency selection resistor RT is grounded. The output terminal of amplifier OP is connected to the gate of the first NMOS transistor MN1. The source of the first NMOS transistor MN1 is connected to the external frequency selection resistor RT, and the drain is connected to the drain of the first PMOS transistor MP1. The positive input terminal of amplifier OP is set to A, and the source terminal of the first NMOS transistor MN1 is set to B. The gate and drain of the first PMOS transistor MP1 are interconnected, and its gate is connected to the gate of the second PMOS transistor MP2. The sources of the first PMOS transistor MP1 and the second PMOS transistor MP2 are connected to the power supply VDD. The drain of the second PMOS transistor MP2 is connected to the positive input terminal of the comparator COMP and the charging resistor R0. The ratio of the number of first PMOS transistors MP1 and the number of second PMOS transistors MP2 connected in parallel is set to m:1, that is, the drain current flowing through the first PMOS transistor MP1 is m times the current flowing through the second PMOS transistor MP2. The other end of the charging resistor R0 is grounded, and the positive input terminal of the comparator COMP is set to C.

[0021] The SW node is connected to the current-generating resistor RX. The other end of the current-generating resistor RX is connected to the negative input terminal of comparator COMP and the charging capacitor C0, respectively. The other end of the charging capacitor C0 is grounded. The negative input terminal of comparator COMP is set to D. The drain of the second NMOS transistor MN2 is connected to the negative input terminal of comparator COMP, the source is grounded, and the gate is connected to the LDRV node. The source of the third PMOS transistor MP3 is connected to the negative input terminal of comparator COMP, the drain is grounded, and the gate is connected to the drain of the second PMOS transistor MP2. Comparator COMP outputs the TON signal.

[0022] The voltage at node SW is divided by a first voltage divider resistor R1 and a second voltage divider resistor R2, with the combined resistance of the first voltage divider resistor R1 and the second voltage divider resistor R2 being n times the resistance of the second voltage divider resistor R2. After voltage division, the voltage at point A is obtained after passing through a first filter composed of a third resistor R3, a first capacitor C1, a fourth resistor R4, and a second capacitor C2. Since SW is the switching node connecting the upper and lower power transistors in the BUCK circuit, the voltage value after passing through two cascaded filters is the output voltage value VOUT set by the BUCK circuit, and after a voltage division by a multiple of n resistors, the voltage at point A is VOUT / n. The relationship between the output voltage and input voltage of the BUCK circuit is as follows: Where D is the duty cycle. Therefore, the voltage at point A can be expressed as... .

[0023] Amplifier OP, the first NMOS transistor MN1, and the external frequency-selective resistor RT form a follower, transmitting the voltage at point A to point B. Therefore, the current flowing through the external frequency-selective resistor RT can be calculated as follows: .

[0024] The current flowing through the charging resistor is a multiple of m times the current mirror formed by the first PMOS transistor MP1 and the second PMOS transistor MP2, resulting in the voltage at point C being... .

[0025] For comparator COMP, the voltage at its positive input terminal, i.e., point C, is already determined. The negative input terminal voltage is a triangular wave voltage signal generated by the charging and discharging of capacitor C0, controlled by the in-phase control signal LDRV driven by the lower power transistor. The charging current is obtained by dividing the voltage at node SW by the current-generating resistor RX. Node SW charges capacitor C0 when the second NMOS transistor MN2 is turned off. At this time, the lower power transistor is off and the upper power transistor is on, so the voltage at SW is the same as the voltage at VIN. Therefore, the charging current for capacitor C0 is... The voltage at point C is the input voltage to the positive terminal of comparator COMP. The voltage at point D slowly increases until it reaches the voltage at point C. At this point, the output of comparator COMP flips, and the output TON signal, after passing through subsequent logic circuits, ultimately controls the turn-on time of the upper power transistor. When the lower power transistor turns on, the corresponding second NMOS transistor MN2 turns on, pulling the voltage at point D down to 0. This cycle continues until the lower power transistor turns off, at which point D rises again, entering the next cycle and continuously controlling the upper power transistor. Therefore, the actual turn-on time of the output signal TON, i.e., the time it takes for the voltage at point D on the capacitor to charge to the voltage at point C, can be expressed by the formula... Calculated. And Where T is the chip's operating frequency, which can be calculated from the above formula. The corresponding overall chip frequency is Where n is the voltage divider resistor multiplier, m is the current mirror multiplier, R0 is the charging resistor value, RX is the current generating resistor value, and C is the charging capacitor value, all of which are fixed values. RT is the external frequency selection resistor value, which can be adjusted according to actual needs. The third PMOS transistor MP3 is used for upper clamping to prevent the voltage at point D from being too high compared to the voltage at point C. Based on the above working principle, it can be concluded that the chip frequency is linearly controlled only by the external frequency selection resistor and is independent of the BUCK circuit input voltage VIN.

[0026] The advantages of this invention are as follows: It includes a SW node and an LDRV node in a BUCK circuit. The SW node is a switching node connecting the upper and lower power transistors in the BUCK circuit. The LDRV node receives the drive signal of the lower power transistor in the BUCK circuit. It also includes a comparator, a second NMOS transistor, a current generating resistor, and a charging capacitor. The SW node is connected to the negative input terminal of the comparator through the current generating resistor. The charging capacitor changes the voltage at the negative input terminal of the comparator through the second NMOS transistor. The second NMOS transistor controls its own switching through the signal input from the LDRV node. It also includes a follower, a charging resistor, a voltage divider resistor, and a current mirror. The SW node is connected to the positive input terminal of the comparator in sequence through the voltage divider resistor, the follower, the current mirror, and the charging resistor. This can obtain a power supply system with a constant switching frequency, effectively improving the EMC characteristics of the system. At the same time, errors in the circuit can be optimized through structural modifications and replacements, further ensuring that the system frequency matches the set value.

[0027] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. An ACOT control circuit for a BUCK power supply, comprising an SW node and an LDRV node of the BUCK circuit, wherein the SW node is a switching node connecting the upper power transistor and the lower power transistor in the BUCK circuit, and the LDRV node receives the drive signal of the lower power transistor of the BUCK circuit, characterized in that, It also includes a comparator, a second NMOS transistor, a current generating resistor, and a charging capacitor. The SW node is connected to the negative input terminal of the comparator through the current generating resistor. The charging capacitor changes the voltage at the negative input terminal of the comparator through the second NMOS transistor. The second NMOS transistor controls its own switching through the signal input to the LDRV node. It also includes a follower, a charging resistor, a voltage divider resistor, and a current mirror. The SW node is connected to the positive input terminal of the comparator in sequence through the voltage divider resistor, the follower, the current mirror, and the charging resistor.

2. The ACOT control circuit for a BUCK power supply according to claim 1, characterized in that, The voltage divider resistor includes a first voltage divider resistor and a second voltage divider resistor, and the sum of the resistance of the first voltage divider resistor and the second voltage divider resistor is set as a fixed multiple of the resistance of the second voltage divider resistor.

3. The ACOT control circuit for a BUCK power supply according to claim 1, characterized in that, It also includes a first filter and a second filter connected together, which are connected between the voltage divider resistor and the follower.

4. The ACOT control circuit for a BUCK power supply according to claim 1, characterized in that, The follower includes an amplifier, an external frequency-selective resistor, and a first NMOS transistor. The positive input terminal of the amplifier is connected to a voltage divider resistor, the negative input terminal is connected to one end of the external frequency-selective resistor, the other end of the external frequency-selective resistor is grounded, the output terminal of the amplifier is connected to the gate of the first NMOS transistor, the source of the first NMOS transistor is connected to the external frequency-selective resistor, and the drain of the first NMOS transistor is connected to a current mirror.

5. The ACOT control circuit for a BUCK power supply according to claim 1, characterized in that, The current mirror includes a first PMOS transistor and a second PMOS transistor. The drain and gate of the first PMOS transistor are interconnected, the drain is connected to a follower, and the gate is connected to the gate of the second PMOS transistor. The source of the first PMOS transistor and the source of the second PMOS transistor are connected to VDD, and the drain of the second PMOS transistor is connected to a charging resistor and the positive input terminal of a comparator.

6. The ACOT control circuit for a BUCK power supply according to claim 5, characterized in that, The ratio of the number of the first PMOS transistor and the number of the second PMOS transistor connected in parallel is set to a fixed value.

7. The ACOT control circuit for a BUCK power supply according to claim 1, characterized in that, One end of the charging resistor is connected to the current mirror and the positive input terminal of the comparator, and the other end is grounded.

8. The ACOT control circuit for a BUCK power supply according to claim 7, characterized in that, It also includes a third PMOS transistor, which is used as an upper clamp. The gate of the third PMOS transistor is connected to a charging resistor, the drain is grounded, and the source is connected to the negative input terminal of the comparator.

9. The ACOT control circuit for a BUCK power supply according to any one of claims 1 to 8, characterized in that, When the second NMOS transistor is turned off, the SW node charges the charging capacitor. In this case, the lower power transistor in the BUCK circuit is turned off and the upper power transistor is turned on. The input voltage of the SW node is the input voltage of the BUCK circuit.

10. The ACOT control circuit for a BUCK power supply according to claim 9, characterized in that, When the second NMOS transistor is turned off, the voltage at the negative input terminal of the comparator slowly increases until it reaches the voltage at the positive input terminal of the comparator. The comparator output flips, and the output signal is ultimately controlled by the logic circuit to control the turn-on time of the power transistor.

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