Jitter frequency control circuit and switching power supply

Abstract

The invention provides a jitter frequency control circuit and a switching power supply. The jitter frequency control circuit comprises a logic module and a delay output module, the logic module is electrically connected with the delay output module, and the delay output module is used for being electrically connected with a control module in the switching power supply. The logic module is used for outputting a control signal to the delay output module according to a preset signal; the delay output module is used for delaying a received first clock signal according to the control signal, outputting a second clock signal to the control module and providing jitter frequency for the control module, and the first clock signal is a clock signal in the switching power supply. According to the invention, multiplexing and delay processing are carried out on the internal existing clock signal, so that the hardware cost required by newly adding an independent oscillator module is saved, the additional synchronous logic design cost and the switching power supply chip space occupation cost under a double-clock architecture are reduced, and the design cost of the switching power supply is greatly saved.

Description

Technical Field

[0001] This application belongs to the field of switching power supply technology, and in particular relates to a frequency dithering control circuit and a switching power supply. Background Technology

[0002] In the field of switching power supplies, especially in applications such as automotive electronics and LED (Light-Emitting Diode) backlight drivers where stringent requirements exist for EMI (Electromagnetic Interference) and control precision, the stable operation and functionality of DC-DC switching power supplies heavily rely on clock signal support. On one hand, to accurately detect core parameters (such as PWM (Pulse-Width Modulation) duty cycle detection at chip pin inputs in LED backlight drivers), a high-frequency clock must be integrated within the power supply. This clock must maintain jitter-free characteristics; introducing jitter will directly lead to a decrease in duty cycle detection accuracy, subsequently causing functional abnormalities such as backlight brightness fluctuations. On the other hand, to suppress electromagnetic interference generated during DC-DC switching power supply operation, spectral dispersion must be achieved by introducing disturbances at high-frequency switching points. This process relies on a clock signal with jitter characteristics. In the existing technology, since the high-frequency clock used for detection cannot provide jitter function, it is usually necessary to add an additional independent oscillator module with clock jitter to form a dual clock architecture of "jitter-free detection" and "frequency jitter suppression EMI". However, this design will directly increase the design cost of the switching power supply. Summary of the Invention

[0003] This application provides a frequency dithering control circuit and a switching power supply, which can solve the problem of increased design costs caused by the dual-clock architecture of existing switching power supplies.

[0004] In a first aspect, embodiments of this application provide a frequency dithering control circuit, including a logic module and a delay output module, wherein the logic module is electrically connected to the delay output module, and the delay output module is used to be electrically connected to a control module in a switching power supply; The logic module is used to output a control signal to the delay output module according to a preset signal; the delay output module is used to delay the received first clock signal according to the control signal and output a second clock signal to the control module, wherein the first clock signal is the clock signal in the switching power supply.

[0005] In one possible implementation of the first aspect, the delay output module includes a switching unit and a plurality of first delay units, the switching unit being electrically connected to all the first delay units and the control module respectively, and each first delay unit being electrically connected to the logic module and the control module; The switching unit is used to output a first voltage signal according to the first clock signal; the first delay unit is used to adjust the frequency of the first voltage signal according to the control signal to obtain the second clock signal. In one possible implementation of the first aspect, the switching unit includes a first switching transistor and a second switching transistor, the gate of the first switching transistor and the gate of the second switching transistor are both used to receive the first clock signal, the source of the first switching transistor is used to be electrically connected to the power supply, the drain of the first switching transistor is electrically connected to the drain of the second switching transistor, all the first delay units and the control module, and the source of the second switching transistor is grounded. In one possible implementation of the first aspect, the first delay unit includes a third switch, a fourth switch, a transmission gate, and a first capacitor. The gate of the third switch is used to receive the first clock signal, the source of the third switch is used to be electrically connected to a power supply, the drain of the third switch is electrically connected to the source of the fourth switch, the gate of the fourth switch and the control terminal of the transmission gate are both electrically connected to the logic module, the drain of the fourth switch is electrically connected to the switching unit, the first terminal of the transmission gate and the control module, respectively, the first terminal of the first capacitor is electrically connected to the second terminal of the transmission gate, and the second terminal of the first capacitor is grounded. In one possible implementation of the first aspect, the delay output module further includes a first inverter and a second inverter, wherein the input terminal of the first inverter is used to receive the first clock signal, the output terminal of the first inverter is electrically connected to the input terminal of the second inverter, and the output terminal of the second inverter is electrically connected to the switching unit and all the first delay units respectively. In one possible implementation of the first aspect, the delay output module further includes a third inverter, the input of which is electrically connected to all the first delay units and the switching unit, and the output of which is electrically connected to the control module. In one possible implementation of the first aspect, the delay output module includes a multiplexing unit and a plurality of second delay units, all of which are electrically connected in sequence, the multiplexing unit is electrically connected to all of the second delay units and the logic module respectively, and the multiplexing unit is used to be electrically connected to the control module; Each of the second delay units is used to output a corresponding delay clock signal; the multiplexing unit is used to output the second clock signal according to the control signal, wherein the second clock signal is one of the multiple delay clock signals. In one possible implementation of the first aspect, the multiplexing unit includes a multiplexer, wherein a plurality of first input terminals of the multiplexer are electrically connected to a plurality of second delay units respectively, a second input terminal of the multiplexer is electrically connected to the logic module, and an output terminal of the multiplexer is used to be electrically connected to the control module. In one possible implementation of the first aspect, the second delay unit includes a fourth inverter, the input and output of which are both electrically connected to the multiplexing unit. Secondly, embodiments of this application provide a switching power supply, including a control module and a frequency dithering control circuit as described in the first aspect, wherein the control module is electrically connected to the delay output module in the frequency dithering control circuit.

[0006] The beneficial effects of the embodiments in this application compared with the prior art are: The frequency dithering control circuit provided in this application includes a logic module and a delay output module. The logic module can output a control signal to the delay output module based on a preset signal. The delay output module delays the received first clock signal according to the control signal and outputs a second clock signal to the control module, providing frequency dithering for the control module. Since the first clock signal used in this application embodiment is an integrated clock signal within the switching power supply, rather than an additional independent clock, the frequency dithering control circuit provided in this application embodiment does not require a dual-clock architecture to meet the dual requirements of "no jitter detection" and "frequency dithering EMI suppression." This design, by multiplexing and delaying the existing internal clock signal, not only eliminates the hardware cost required for adding an independent oscillator module but also reduces the additional synchronous logic design cost and switching power supply chip space occupation cost under a dual-clock architecture, thereby significantly saving the design cost of the switching power supply. Attached Figure Description

[0007] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0008] Figure 1 This is a schematic diagram of a frequency dithering control circuit provided in an embodiment of this application; Figure 2 This is a schematic diagram of a frequency dithering control circuit provided in another embodiment of this application; Figure 3 This is a circuit connection diagram of a frequency dithering control circuit provided in an embodiment of this application; Figure 4 This is a schematic diagram of a frequency dithering control circuit provided in another embodiment of this application; Figure 5 This is a schematic diagram of the triangular wave output of digital logic provided in an embodiment of this application; Figure 6 This is a schematic diagram showing the result of the oscillator output frequency change according to an embodiment of this application; Figure 7 This is a circuit connection diagram of a frequency dithering control circuit provided in another embodiment of this application.

[0009] In the diagram, 10 is the frequency dithering control circuit; 101 is the logic module; 102 is the delay output module; 1021 is the switching unit; 1022 is the first delay unit; 1023 is the multiplexing unit; 1024 is the second delay unit; and 20 is the control module. Detailed Implementation

[0010] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0011] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0012] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0013] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if [the described condition or event] is detected" may be interpreted, depending on the context, as "once determined," "in response to determination," "once [the described condition or event] is detected," or "in response to detection of [the described condition or event]."

[0014] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0015] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0016] In the field of switching power supplies, especially in applications like automotive electronics and LED backlight drivers where stringent requirements exist for EMI and control precision, the stable operation and functionality of DC-DC switching power supplies heavily rely on clock signals. On one hand, to accurately detect core parameters (such as the PWM duty cycle detection of chip pins in LED backlight drivers), a high-frequency clock (e.g., 20MHz) needs to be integrated within the power supply. This clock must be jitter-free; introducing jitter directly reduces duty cycle detection accuracy, leading to backlight brightness fluctuations and other functional abnormalities. On the other hand, to suppress electromagnetic interference generated during DC-DC switching power supply operation, spectral dispersion requires introducing disturbances at high-frequency switching points. This process relies on clock signals with jitter characteristics. In existing technologies, since the high-frequency clock used for detection cannot provide jitter functionality, an additional independent oscillator module with clock jitter is typically added, forming a dual-clock architecture for "jitter-free detection" and "frequency jitter suppression of EMI." However, this design directly increases the design cost of the switching power supply.

[0017] To address the aforementioned issues, the frequency dithering control circuit provided in this application includes a logic module and a delay output module. The logic module can output a control signal to the delay output module based on a preset signal. The delay output module delays the received first clock signal according to the control signal and outputs a second clock signal to the control module, providing frequency dithering for the control module. Since the first clock signal used in this application embodiment is an integrated clock signal within the switching power supply, rather than an additional independent clock, the frequency dithering control circuit provided in this application embodiment does not require a dual-clock architecture to meet the dual requirements of "jitter-free detection" and "frequency dithering EMI suppression." This design, by multiplexing and delaying the existing internal clock signal, not only eliminates the hardware cost required for adding an independent oscillator module but also reduces the additional synchronous logic design cost and switching power supply chip space occupation cost under a dual-clock architecture, thereby significantly saving the design cost of the switching power supply.

[0018] To illustrate the technical solution described in this application, specific embodiments are provided below.

[0019] Figure 1 A schematic diagram of a frequency dithering control circuit 10 according to an embodiment of this application is shown. See also Figure 1 As shown, the frequency dithering control circuit 10 includes a logic module 101 and a delay output module 102. The logic module 101 is electrically connected to the delay output module 102, and the delay output module 102 is used to be electrically connected to the control module 20 in the switching power supply.

[0020] Specifically, logic module 101 can output a control signal to delay output module 102 according to a preset signal. Delay output module 102 delays the received first clock signal according to the control signal and outputs a second clock signal CLK_OUT to control module 20, providing frequency dithering for control module 20. Since the first clock signal used in this embodiment is an integrated clock signal inside the switching power supply, rather than an additional independent clock, the frequency dithering control circuit 10 provided in this embodiment does not need to set up a dual-clock architecture to meet the dual requirements of "no jitter detection" and "frequency dithering to suppress EMI". This design, by multiplexing and delaying the existing internal clock signal, not only saves the hardware cost required to add an independent oscillator module, but also reduces the additional synchronous logic design cost and switching power supply chip space occupation cost under the dual-clock architecture, thereby greatly saving the design cost of the switching power supply.

[0021] It should be noted that the first clock signal, CLK0, is a high-frequency, jitter-free clock (e.g., a 20MHz clock) integrated within the switching power supply for accurate parameter detection (such as PWM duty cycle detection at the chip pin input in LED backlight driver). This clock signal is generated after frequency division and serves as the input clock signal CLK_IN for the delay output module 102. This clock itself needs to remain stable and jitter-free to ensure detection accuracy and cannot be directly used for frequency dithering. However, this solution only alters its output timing (generating jitter characteristics) through delay processing, without changing its jitter-free properties. Therefore, it can be reused as the basic clock source for frequency dithering without affecting the original detection function, fundamentally avoiding the need for a dual-clock architecture.

[0022] For example, the preset signal can be a control reference signal with specific rules that is pre-set to achieve different frequency dithering requirements. Its specific form needs to be determined in combination with the application scenario of the switching power supply (such as LED backlight driver, automotive electronic power supply, etc.) and EMI suppression target. It mainly covers the following categories: It can be a regular signal set based on the frequency dithering mode, such as a triangular wave mode signal to achieve smooth frequency fluctuations to adapt to the conventional EMI suppression requirements. This signal will drive the logic module 101 to output a control signal that changes according to a fixed period (such as gradually increasing from 4-bit code 0000 to 1111, and then decreasing back to 0000), so that the delay duration of the delay output module 102 increases or decreases linearly, and finally makes the frequency of the second clock signal CLK_OUT exhibit triangular wave dithering; It can also be a pseudo-random mode signal set to improve the EMI suppression effect and avoid the continuous occurrence of a single frequency point. This signal will trigger the logic module 101 to generate a code that conforms to the pseudo-random algorithm (such as a 4-bit pseudo-random code). By randomly selecting different delay durations, the frequency of the second clock signal CLK_OUT fluctuates irregularly, further dispersing the spectral energy. In addition, it can also be a parameter adaptation signal set in combination with the actual working parameters of the switching power supply. For example, a delay step control signal can be preset according to the PWM duty cycle detection accuracy requirements in LED backlight driver and the output power range of the switching power supply. This ensures that the control signal output by the logic module 101 can match the frequency characteristics of the first clock signal. While realizing the frequency dithering function, it does not affect the original detection function of the first clock signal. Ultimately, the entire frequency dithering control circuit 10 can accurately adapt to the actual working requirements of the switching power supply without relying on the dual clock architecture.

[0023] It should be noted that the logic module 101 can integrate a variety of digital devices to generate and output coded signals.

[0024] For example, logic module 101 may include a counter (such as a binary counter or a ring counter) to generate a periodically changing encoded sequence through a preset counting period or cyclic logic. Logic module 101 may also include a pseudo-random sequence generator to generate irregularly repeating pseudo-random codes through a specific algorithm, providing control signals for the pseudo-random frequency dithering mode. Logic module 101 may also include a mode selector to switch the operating states of the counter and the pseudo-random generator according to external instructions (such as mode control signals input from chip pins), enabling flexible switching between multiple frequency dithering modes. Logic module 101 may also include registers (such as a register group composed of D flip-flops) to temporarily store preset encoding parameters (such as the encoding value corresponding to the maximum delay duration), ensuring that the encoded signal output by logic module 101 is stable and reliable. In addition, logic module 101 may also include logic gate circuits (such as AND gates, OR gates, and XOR gates) to shape, verify, or adjust the bit width of the output signal of the counter or pseudo-random generator through combinational logic (such as converting an 8-bit counting signal into a 4-bit valid code), ultimately outputting a control signal that meets the requirements of delay output module 102.

[0025] The following is combined with Figure 2 and Figure 3 The circuit diagram shown provides a detailed description of the working principle of the delay output module 102 provided in an embodiment of this application.

[0026] In one embodiment of this application, such as Figure 2 As shown, the delay output module 102 includes a switching unit 1021 and a plurality of first delay units 1022. The switching unit 1021 is electrically connected to all the first delay units 1022 and the control module 20 respectively. Each first delay unit 1022 is electrically connected to the logic module 101 and the control module 20. All the first delay units 1022 are connected in parallel.

[0027] Specifically, the switching unit 1021 receives a first clock signal and outputs a first voltage signal according to the first clock signal. When the first clock signal is high, the switching unit 1021 is in a first switching state; when the first clock signal is low, the switching unit 1021 is in a second switching state. Thus, the switching unit 1021 can switch the switching state according to the first clock signal and obtain the first voltage signal. Each first delay unit 1022 receives a control signal output by the logic module 101 and selects whether to connect to the circuit to delay the first voltage signal according to the control signal, thereby adjusting the frequency of the first voltage signal. After the delay processing of multiple first delay units 1022, the second clock signal CLK_OUT can be obtained.

[0028] Taking the delay output module 102, which includes four first delay units 1022, as an example, the number of first delay units 1022 can be increased or decreased according to actual needs, and is not limited here. In one embodiment of this application, such as Figure 3 As shown, the switching unit 1021 includes a first switching transistor PM10 and a second switching transistor NM10. The gate of the first switching transistor PM10 and the gate of the second switching transistor NM10 are both used to receive the first clock signal. The source of the first switching transistor PM10 is used to be electrically connected to the power supply VDD. The drain of the first switching transistor PM10 is electrically connected to the drain of the second switching transistor NM10, all the first delay units 1022 and the control module 20, respectively. The source of the second switching transistor NM10 is grounded.

[0029] Specifically, both the first switch PM10 and the second switch NM10 function as switching devices, turning on or off according to the first clock signal received at their gates. When the first clock signal is high, the first switch PM10 is off, the second switch NM10 is on, and the switching unit 1021 is in the first switching state. At this time, the first delay unit 1022 can discharge through the on-state second switch NM10. When the first clock signal is low, the first switch PM10 is on, the second switch NM10 is off, and the switching unit 1021 is in the second switching state. At this time, the first delay unit 1022 can charge through the on-state first switch PM10. The first delay unit 1022 charges and discharges according to the change in the state of the switching unit 1021, thereby changing the frequency of the first voltage signal to obtain the second clock signal CLK_OUT.

[0030] For example, designers can select the type of the first switch PM10 and the second switch NM10 according to the actual situation; that is, both can be fully controlled power devices such as metal-oxide-semiconductor field-effect transistors or insulated-gate bipolar transistors. For example, the first switch PM10 can be selected as a PMOS transistor, and the second switch NM10 can be selected as an NMOS transistor.

[0031] In one embodiment of this application, such as Figure 3As shown, the first delay unit 1022 includes a third switch, a fourth switch, a transmission gate, and a first capacitor. The gate of the third switch receives the first clock signal, the source of the third switch is electrically connected to the power supply VDD, and the drain of the third switch is electrically connected to the source of the fourth switch. The gate of the fourth switch and the control terminal of the transmission gate are both electrically connected to the logic module 101. The drain of the fourth switch is electrically connected to the switching unit 1021, the first terminal of the transmission gate, and the control module 20, respectively. The first terminal of the first capacitor is electrically connected to the second terminal of the transmission gate, and the second terminal of the first capacitor is grounded. PM11, PM13, PM15, and PM17 serve as the third switches in their respective first delay units 1022, and their gates all receive the first clock signal. PM12, PM14, PM16, and PM18 serve as the fourth switches in their respective first delay units 1022, and their gates are all connected to the logic module 101. CTRL0~CTRL3 receive control signals from the logic module 101. TG0~TG3 serve as transmission gates in their respective first delay units 1022, and C0, C1, C2 and C3 serve as first capacitors in their respective first delay units 1022.

[0032] Specifically, the third switch, the fourth switch, the transmission gate, and the first capacitor are connected in series to form an RC delay circuit. The third switch adjusts the current flowing into the first delay unit 1022 according to the first clock signal. The fourth switch and the transmission gate both receive control signals output by the logic module 101 and turn on or off according to the control signals. When both the fourth switch and the transmission gate are on, the first capacitor is connected to the RC circuit; when both the fourth switch and the transmission gate are off, the first capacitor is disconnected from the RC circuit. As the core delay element, the first capacitor, after being connected, changes the time constant of the RC circuit through its charging and discharging process. The larger the capacitance value (or the larger the total capacitance when multiple capacitors are connected in parallel), the longer the charging and discharging time, and the longer the delay time of the corresponding output signal. Ultimately, through cooperation with the switch unit 1021 and other first delay units 1022, a step-wise adjustment of the frequency of the first voltage signal is achieved, providing hardware support for generating the second clock signal CLK_OUT with jitter characteristics.

[0033] For example, designers can select the types of the third and fourth switching transistors according to the actual situation; both can be fully controlled power devices such as metal-oxide-semiconductor field-effect transistors (MOSFETs) or insulated-gate bipolar transistors (IGBTs). For instance, both the third and fourth switching transistors can be PMOS transistors.

[0034] For example, if the control signal output by logic module 101 is set to 4-bit binary encoding (CTRL3~CTRL0), corresponding to four first delay units 1022 (each containing one transmission gate and one first capacitor; the capacitance values ​​of the four first capacitors can be set using binary weighting forms of C, 2C, 4C, and 8C, achieving more flexible delay duration adjustment through differentiated capacitance value allocation), taking "1 indicates that the transmission gate is on and the capacitor is connected, 0 indicates that the transmission gate is off and the capacitor is not connected" as an example, the specific correspondence is as follows: The core logic of this binary weighted design is to increase the capacitance value of each capacitor in powers of 2, corresponding to each bit of the 4-bit control signal (from the least significant bit to the most significant bit) controlling capacitor branches with capacitance values ​​of C, 2C, 4C, and 8C respectively. When a bit of the control signal is "1", the capacitor corresponding to the weight is connected to the RC circuit, and the total capacitance value is the sum of the capacitance values ​​of all capacitors corresponding to the "1" bits. For example, when the control signal is "0001", only capacitors with a capacitance value of C are connected, the total capacitance is C, and the delay time is the reference value t (determined by the RC time constant); when the control signal is "0010", capacitors with a capacitance value of 2C are connected, the total capacitance is 2C, and the delay time is 2t; when the control signal is "0101", capacitors with capacitance values ​​of C and 4C are connected, the total capacitance is 5C, and the delay time is 5t; when the control signal is "1111", all four capacitors are connected, the total capacitance is C + 2C + 4C + 8C = 15C, and the delay time reaches 15t. Compared to designs with the same capacitance value, this binary weighted capacitance setting can achieve a wider delay adjustment range with fewer capacitor branches (4 channels can achieve 16 total capacitance combinations from 0 to 15C). At the same time, by adjusting the connection status of capacitors with different weights, it can flexibly match the requirements of frequency dithering step size in different scenarios (for example, when small step size adjustment is required, control the switching of low weight capacitor branches; when large step size adjustment is required, control the switching of high weight capacitor branches). This further improves the adaptability of the delay output module 102 to EMI suppression scenarios, and no additional hardware cost is required. The functional dimensions can be expanded simply by differentiating the capacitance values.

[0035] For example, in addition to 4-bit binary encoding, thermometer codes can also be used to achieve stepped adjustment of the delay time. The core logic is to ensure that the total capacitance of the RC circuit is always continuously accumulating by adding a capacitor to the branch for each bit increment of the encoding, thus avoiding the problem of discontinuous capacitance changes that may occur with binary encoding. Taking the thermometer code control of four first delay units 1022 (corresponding to four capacitor branches, each with the same capacitance value, such as 10pF) as an example. When logic module 101 outputs the thermometer code "0001", only the transmission gate of the first delay unit 1022 is turned on, corresponding to a 10pF capacitor connected, the total capacitance of the RC circuit is 10pF, and the delay time is the reference value t (e.g., 10ns). When the output is "0011", a second transmission gate is added to the first channel, connecting a total capacitance of 10pF + 10pF = 20pF, and the delay time increases to 2t (20ns). When the output is "0111", a third transmission gate is further added, the total capacitance accumulates to 30pF, and the delay time increases to 3t (30ns). If the maximum delay is required, when the output is "1111", all four transmission gates are turned on, the total capacitance reaches 40pF, and the delay time is 4t (40ns). In this encoding method, each change in the control signal only adds or removes one capacitor branch, unlike binary encoding (such as from "0011" to "0100") which involves abrupt changes such as disconnecting two connected capacitors and then connecting one. This allows for a smoother charging and discharging speed of the RC circuit, resulting in a more linear and seamless frequency jitter of the second clock signal CLK_OUT. It is particularly suitable for EMI suppression scenarios with higher timing stability requirements (such as in automotive electronics where frequency jumps need to be avoided to prevent interference with radio signals). At the same time, it maintains the core logic consistent with binary encoding, balancing adjustment accuracy and timing smoothness.

[0036] In one embodiment of this application, such as Figure 3 As shown, the delay output module 102 also includes a first inverter INV1 and a second inverter INV2. The input terminal of the first inverter INV1 is used to receive the first clock signal. The output terminal of the first inverter INV1 is electrically connected to the input terminal of the second inverter INV2. The output terminal of the second inverter INV2 is electrically connected to the switching unit 1021 and all the first delay units 1022 respectively.

[0037] Specifically, the first inverter INV1 and the second inverter INV2 form a two-stage inverting buffer structure. Their core function is to condition and enhance the driving capability of the input first clock signal, providing a reliable timing reference for the stable operation of the subsequent switching unit 1021 and the first delay unit 1022. Specifically, the first inverter INV1 first receives the first clock signal from inside the switching power supply, inverts the signal for the first time, and shapes the signal edges. This filters out minor noise or edge glitches that may be carried by the first clock signal during transmission, ensuring steeper high / low level transitions and more accurate timing, avoiding the impact of original signal quality issues on the stability of subsequent circuits. Subsequently, the signal shaped by the first inverter INV1 is input to the second inverter INV2. The second inverter INV2 inverts the signal a second time, ensuring that the phase of the final output signal is consistent with the original first clock signal (counteracting the phase flip of the first inverter INV1 and ensuring that the timing logic is not disordered). Furthermore, the cascaded amplification of the two inverters significantly improves the driving capability of the clock signal. Since the switching unit 1021 requires sufficient signal drive strength to turn on / off, and multiple first delay units 1022 need to receive synchronized clock signals simultaneously, the signals output by the two-stage inverters can provide stable current drive for these loads, avoiding problems such as switching delay of the switching unit 1021 and poor clock synchronization of each first delay unit 1022 due to insufficient drive. Ultimately, this ensures accurate charging and discharging timing of the entire RC delay architecture and stable collaborative operation of each module, providing a reliable basic clock guarantee for the jitter characteristics of the second clock signal CLK_OUT.

[0038] In one embodiment of this application, such as Figure 3 As shown, the delay output module 102 also includes a third inverter INV3. The input terminal of the third inverter INV3 is electrically connected to all the first delay units 1022 and the switching unit 1021 respectively, and the output terminal of the third inverter INV3 is used to be electrically connected to the control module 20.

[0039] Specifically, the third inverter INV3 is used to perform final conditioning on the signal processed by the switching unit 1021 and the first delay unit 1022, ensuring that the second clock signal CLK_OUT output to the control module 20 meets the timing and level requirements. Specifically, the first voltage signal (charging / discharging waveform) after RC delay conditioning may exhibit slowly changing analog characteristics or noisy edges. The third inverter INV3, through its steep voltage switching characteristics, shapes this slowly changing signal into a steeply changing digital pulse signal, clearly distinguishing high / low level states and eliminating ambiguity in signal transmission. Simultaneously, the output level of the third inverter INV3 can precisely match the input level standard of the control module 20, avoiding signal recognition errors caused by level incompatibility. In addition, as the last buffer before signal output, the third inverter INV3 can also enhance the driving capability of the second clock signal CLK_OUT, ensuring that it remains stable during transmission to the control module 20 and is not affected by load changes. Ultimately, it provides the control module 20 with a jitter clock signal that is clear in timing, level-adapted, and reliable in driving, ensuring the accurate execution of the entire jitter control logic.

[0040] The following is combined with Figures 4 to 7 The circuit diagram shown provides a detailed description of the working principle of the delay output module 102 provided in another embodiment of this application.

[0041] In one embodiment of this application, such as Figure 4 As shown, the delay output module 102 includes a multiplexer unit 1023 and a plurality of second delay units 1024. All the second delay units 1024 are electrically connected in sequence. The multiplexer unit 1023 is electrically connected to all the second delay units 1024 and the logic module 101 respectively. The multiplexer unit 1023 is used to be electrically connected to the control module 20.

[0042] Specifically, multiple second delay units 1024 and multiplexing unit 1023 work together to achieve multi-level delay and precise selection of the clock signal, providing flexible timing adjustment capabilities for the frequency dithering function. The multiple second delay units 1024 adopt a cascaded structure with sequential electrical connections (i.e., the output of the previous second delay unit 1024 is connected to the input of the next second delay unit 1024). After the first clock signal is input from the first second delay unit 1024, a fixed delay duration is superimposed on it after each second delay unit 1024. Ultimately, each second delay unit 1024 can output a delayed clock signal with a corresponding delay duration (for example, the first unit outputs a signal delayed by t1, the second unit outputs a signal delayed by t1+t2, and so on, forming a multi-level delayed clock sequence). The cascaded design easily expands the number of delay duration levels to meet different frequency dithering range requirements.

[0043] The multiplexing unit 1023 serves as the signal output selection hub. Its input terminals are connected to the output terminals of all second delay units 1024 and the input terminal of the first second delay unit 1024 to obtain signals for the entire delay duration. The control terminal is used to receive control signals. During operation, the multiplexing unit 1023 selects a signal that meets the current dithering requirements from all delay clock signals as the second clock signal CLK_OUT, based on the control signal output by the logic module 101 (such as a binary encoded signal or thermometer code, where 4 bits correspond to 16 second delay units 1024 to achieve 16 different frequency delays, and the number of second delay units 1024 can be increased / decreased according to actual needs). The output of the second clock signal CLK_OUT is then sent to the control module 20. This design can achieve stepped coverage of delay duration through the cascading of the second delay unit 1024, and can also make the delay duration of the second clock signal CLK_OUT flexibly change with the control signal through the fast switching of the multiplexing unit 1023, thereby generating a clock signal with preset jitter characteristics, effectively supporting the frequency jitter control function. At the same time, the circuit structure is simple, the adjustment accuracy is controllable, and it is suitable for the EMI suppression requirements of different scenarios of switching power supplies.

[0044] For example, through the design of the above-described delay output module 102, the logic module 101 can have different output modes, such as triangular wave mode or pseudo-random mode.

[0045] If the triangular wave output mode is selected, taking a 4-bit output as an example, each cycle of the output will range from 0000 to 1111 and then back to 0000 as a complete cycle. Other encoding methods can also be used, such as thermometer codes. Figure 5 The encoding method causes the number of delay modules to gradually increase from 0 to the maximum value, and then decrease back to zero to complete one cycle.

[0046] The final frequency change is as follows: Figure 6 As shown, the oscillator output frequency follows a triangular wave pattern, increasing from fmin to fmax and then decreasing back to fmin. The key design parameters are fmin, fmax, and the period Tmod of the triangular wave.

[0047] However, the triangular wave mode has the problem that each frequency point can only maintain one cycle. If the next cycle delay is the same, then the frequency value is equal to the input frequency. Therefore, to obtain a better frequency dithering effect, a pseudo-random mode can be used, in which a four-bit pseudo-random code is generated internally by the digital logic. This allows for better control of the oscillator's modulation frequency.

[0048] In one embodiment of this application, such as Figure 7As shown, the multiplexing unit 1023 includes a multiplexer MUX. The multiple first input terminals of the multiplexer MUX are electrically connected to the multiple second delay units 1024 respectively. The second input terminal of the multiplexer MUX is electrically connected to the logic module 101. The output terminal of the multiplexer MUX is used to be electrically connected to the control module 20.

[0049] Specifically, the multiplexer MUX, as the core device of the multiplexing unit 1023, can accurately select the target signal from multiple delayed clock signals, making it an important component for achieving flexible frequency dithering control. Its multiple first input terminals are connected one-to-one with multiple second delay units 1024, allowing it to synchronously receive clock signals with different delay durations (e.g., signals delayed by t, 2t, 3t, and 4t respectively) output by each second delay unit 1024. These signals cover all preset frequency dithering levels. Its second input terminal is connected to the logic module 101, receiving control signals for selection. During operation, the multiplexer MUX can quickly switch internal paths according to the control signals output by the logic module 101 (e.g., encoding "00" corresponds to selecting the first path, and "01" corresponds to selecting the second path), uniquely selecting one signal from the multiple delayed clock signals that meets the current frequency dithering requirements, and transmitting it to the control module 20 as the second clock signal CLK_OUT through its output terminal. This design allows the output clock jitter level to be adjusted using only the control signal of the logic module 101. It also ensures the speed and stability of the signal switching process, avoids conflicts that may be caused by multiple parallel outputs, simplifies the circuit structure (single output replaces multiple parallel outputs), reduces the complexity of connecting to the control module 20, and ultimately provides a precise and controllable jitter clock for the switching power supply, effectively supporting EMI suppression.

[0050] In one embodiment of this application, such as Figure 7 As shown, the second delay unit 1024 includes a fourth inverter. The input and output terminals of the fourth inverter are both electrically connected to the multiplexing unit 1023. INV4-1, INV4-2, ..., INV4-n serve as the fourth inverters in their respective second delay units 1024.

[0051] Specifically, the fourth inverter, as the core delay and signal transmission device, achieves precise clock signal delay through its inherent transmission delay characteristics and provides a stable delayed clock signal for the multiplexer (MUX). Specifically, when the first clock signal is input to the fourth inverter, while performing signal logic inversion (high level to low level, low level to high level), the inverter generates a fixed transmission delay due to physical processes such as the charging and discharging of parasitic capacitances within the device (e.g., a delay duration of t0 introduced by each inverter stage). This delay characteristic causes the clock signal after the inverter to have a fixed time difference compared to the input signal, forming the delay duration corresponding to the second delay unit 1024. For multiple cascaded second delay units 1024, the output of each fourth inverter also serves as the input to the next stage of the second delay unit 1024. Through the cascading and superposition of multiple inverter stages, an increasing sequence of delay durations is formed (e.g., 2 stages of inverters correspond to a 2t0 delay, 3 stages correspond to a 3t0 delay). In addition, the digital logic characteristics of the fourth inverter can also shape the signal, ensuring that the delayed clock signal output to the multiplexer (MUX) has a steep edge and a clear level, providing a reliable signal foundation for subsequent gating logic. Finally, through the design of the number of cascaded inverters and the utilization of the inherent delay of the fourth inverter, precise control and flexible expansion of the delay duration can be achieved.

[0052] It should be noted that traditional solutions adjust the output frequency of an oscillator by periodically changing its resistance value, and achieve periodic modulation of the oscillator frequency by controlling the frequency change period. However, this method has significant limitations when a small jitter range (such as 1% frequency jitter) is required, namely, the jitter deviation of the resistor must be controlled within 1%, which is difficult to achieve precisely in actual manufacturing processes. This application, on the other hand, uses a delay control method to meet the low jitter range requirement. Not only is the circuit size much smaller than that of a conventional oscillator, but it also achieves frequency jitter by controlling the delay of the rising edge of the clock (which can be achieved using digital gate circuit delay or RC charging and discharging delay). The low jitter frequency target can be achieved by flexibly adjusting the delay duration, and the circuit implementation is simple and easy to adjust the modulation frequency.

[0053] Compared to Figure 4 The delay output module 102 shown is composed of a multiplexing unit 1023 and multiple (e.g., 16) second delay units 1024. Figure 2 and Figure 3 The delay output module 102 shown is composed of a switching unit 1021 and multiple (e.g., four) first delay units 1022. It can directly output the second clock signal CLK_OUT. Its 16 delay durations can be achieved by controlling the RC delay, and the overall circuit structure is more concise.

[0054] It should be noted that the embodiments provided in this application only show two circuit structures as the delay output module 102, and do not mean that only these two circuit structures can realize the function of the delay output module 102. Other circuit structures that can realize this function can also be substituted, and are not limited to these.

[0055] This application also discloses a switching power supply, including a control module 20 and the aforementioned frequency dithering control circuit 10. The control module 20 is electrically connected to the delay output module 102 in the frequency dithering control circuit 10. By integrating the aforementioned frequency dithering control circuit 10, the switching power supply can achieve high-frequency switching frequency dithering control using an internal clock signal without increasing the hardware cost of an independent oscillator. This not only simplifies the circuit structure and reduces chip area and manufacturing process costs, but also avoids timing disorder problems that may be caused by dual-clock coordination. It ensures that the switching power supply maintains stable output accuracy while achieving EMI suppression, taking into account electromagnetic compatibility, cost advantages, and operational reliability. It is especially suitable for scenarios that are sensitive to EMI and have strict cost control (such as power systems for automotive electronics and consumer smart devices).

[0056] Since the processing and functions implemented by the switching power supply in this embodiment are basically the same as the embodiments, principles and examples of the aforementioned frequency dithering control circuit, any details not covered in this embodiment can be found in the relevant descriptions in the aforementioned embodiments, and will not be repeated here.

[0057] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A frequency dithering control circuit, characterized in that, It includes a logic module and a delay output module, wherein the logic module is electrically connected to the delay output module, and the delay output module is used to be electrically connected to the control module in the switching power supply; The logic module is used to output a control signal to the delay output module according to a preset signal; the delay output module is used to delay the received first clock signal according to the control signal and output a second clock signal to the control module, wherein the first clock signal is the clock signal in the switching power supply.

2. The frequency dithering control circuit according to claim 1, characterized in that, The delay output module includes a switching unit and multiple first delay units. The switching unit is electrically connected to all the first delay units and the control module, and each first delay unit is electrically connected to the logic module and the control module. The switching unit is used to output a first voltage signal according to the first clock signal; the first delay unit is used to adjust the frequency of the first voltage signal according to the control signal to obtain the second clock signal.

3. The frequency dithering control circuit according to claim 2, characterized in that, The switching unit includes a first switching transistor and a second switching transistor. The gates of the first switching transistor and the second switching transistor are both used to receive the first clock signal. The source of the first switching transistor is used to be electrically connected to the power supply. The drain of the first switching transistor is electrically connected to the drain of the second switching transistor, all the first delay units, and the control module. The source of the second switching transistor is grounded.

4. The frequency dithering control circuit according to claim 2, characterized in that, The first delay unit includes a third switch, a fourth switch, a transmission gate, and a first capacitor. The gate of the third switch is used to receive the first clock signal, the source of the third switch is used to be electrically connected to the power supply, the drain of the third switch is electrically connected to the source of the fourth switch, the gate of the fourth switch and the control terminal of the transmission gate are both electrically connected to the logic module, the drain of the fourth switch is electrically connected to the switching unit, the first terminal of the transmission gate and the control module, respectively, the first terminal of the first capacitor is electrically connected to the second terminal of the transmission gate, and the second terminal of the first capacitor is grounded.

5. The frequency dithering control circuit according to any one of claims 2-4, characterized in that, The delay output module further includes a first inverter and a second inverter. The input terminal of the first inverter is used to receive the first clock signal. The output terminal of the first inverter is electrically connected to the input terminal of the second inverter. The output terminal of the second inverter is electrically connected to the switching unit and all the first delay units respectively.

6. The frequency dithering control circuit according to any one of claims 2-4, characterized in that, The delay output module further includes a third inverter, the input of which is electrically connected to all the first delay units and the switching unit, and the output of which is electrically connected to the control module.

7. The frequency dithering control circuit according to claim 1, characterized in that, The delay output module includes a multiplexer unit and multiple second delay units. All the second delay units are electrically connected in sequence. The multiplexer unit is electrically connected to all the second delay units and the logic module respectively. The multiplexer unit is used to be electrically connected to the control module. Each of the second delay units is used to output a corresponding delay clock signal; the multiplexing unit is used to output the second clock signal according to the control signal, wherein the second clock signal is one of the multiple delay clock signals.

8. The frequency dithering control circuit according to claim 7, characterized in that, The multiplexing unit includes a multiplexer, with multiple first input terminals of the multiplexer electrically connected to multiple second delay units respectively, a second input terminal of the multiplexer electrically connected to the logic module, and an output terminal of the multiplexer electrically connected to the control module.

9. The frequency dithering control circuit according to claim 7, characterized in that, The second delay unit includes a fourth inverter, the input terminal and the output terminal of which are both electrically connected to the multiplexing unit.

10. A switching power supply, characterized in that, It includes a control module and a frequency dithering control circuit as described in any one of claims 1-9, wherein the control module is electrically connected to the delay output module in the frequency dithering control circuit.

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