Implementation method, system and equipment for lightweight sequence cipher

Abstract

The invention relates to the technical field of information security, in particular to a lightweight sequence cipher implementation method, system and equipment, and the method comprises the steps: obtaining a secret key and an initial vector, and carrying out the segmentation and isolation mapping of the secret key and the initial vector to independent storage units of a feedback shift register and a linear feedback shift register through a physical isolation mechanism; the driving layer executes multiple rounds of nonlinear iteration to strengthen state confusion in the initialization stage, and switches cyclic shift operation to reduce power consumption in the working stage; extracting a high bit of the feedback shift register and a fixed bit of the linear feedback shift register through a curing path to generate recombined data; executing permutation table query, linear diffusion and exclusive-or operation by a finite-state machine three-stage pipeline to generate a key stream, wherein permutation table pre-burning, register multiplexing and parallel query optimize resource occupation; and the bitwise XOR unit outputs the encrypted data stream. The problems of sharp power consumption increase, volume burden, encryption delay and hardware fault caused by resource occupation of an industrial control embedded system, satellite-borne equipment and a satellite terminal are solved.

Description

Technical Field

[0001] This invention relates to the field of information security technology, and in particular to a method, system and device for implementing lightweight stream cipher. Background Technology

[0002] Lightweight stream ciphers, a branch of cryptography, are specifically designed for resource-constrained environments, such as IoT devices or embedded systems. Their core principle involves generating a keystream using an efficient pseudo-random number generator, which is then combined bit-by-bit with the input data to complete encryption and decryption. While current implementations of stream ciphers require complex logic and significant storage resources, lightweight versions, through optimized algorithm structures such as integrating linear feedback shift registers and combining them with nonlinear functions, significantly reduce hardware overhead and energy consumption while maintaining necessary security levels and processing speed. This makes them suitable for scenarios with limited computing power without sacrificing basic encryption strength.

[0003] Stream ciphers operate on a layered architecture, including a driver layer responsible for key stream generation, a bit recombination layer for data extraction, and a finite state machine for handling nonlinear transformations. The driver layer typically includes a linear feedback shift register and a feedback shift register, used to generate the initial key sequence. The bit recombination layer extracts specific bit positions from the shift registers and recombines them. The finite state machine employs an iterative structure to implement nonlinear obfuscation operations, such as using permutation tables and linear transformations. While these technologies are designed for conventional IoT devices, they fail to adequately consider the unique operating conditions of industrial control embedded systems, resource-constrained spaceborne platforms, or portable satellite communication terminals.

[0004] In application environments such as industrial control embedded devices, spaceborne resource-constrained devices, and portable or micro-terminal devices for satellite communication, the problem of excessive resource consumption caused by stream cipher implementation becomes particularly prominent. Algorithm components, such as nonlinear permutation tables and complex feedback mechanisms, occupy too much logic gate and register space, significantly increasing system power consumption and size. Spaceborne devices face the risk of radiation interference, and the intensive computation with high resource consumption may accelerate component aging and reduce error tolerance; industrial control embedded systems, due to strict power consumption limitations, are prone to heat accumulation and operational instability due to high-power designs, affecting the feasibility of low-power encryption operations; satellite communication terminals have high miniaturization requirements, and resource waste makes it impossible for small devices to balance performance and space constraints. Frequency limitations cause encryption delays, weakening real-time communication capabilities, while resource-intensive structures increase the probability of hardware failure, posing a potential threat to the security of critical applications. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention provides a lightweight stream cipher implementation method, system, and device. This invention solves the technical pain points caused by the excessive resource consumption of nonlinear permutation tables and complex feedback mechanisms in stream cipher algorithms, resulting in soaring power consumption, increased size burden, significant encryption delay, and increased probability of hardware failure in industrial control embedded systems, spaceborne resource-constrained equipment, and portable satellite communication terminals.

[0006] To solve the above-mentioned technical problems, the specific contents of the present invention are as follows: The present invention provides a method for implementing a lightweight stream cipher, comprising: Step 1: Obtain the key and initialization vector. Divide the key into a first key block and a second key block using a physical isolation mechanism. Divide the initialization vector into a first vector block and a second vector block. Step 2: Map the segmented first key block, second key block, first vector block, and second vector block to the feedback shift register and linear feedback shift register defined in the hardware layer, respectively. The first key block is mapped to the first storage unit of the feedback shift register, the second key block is mapped to the second storage unit of the feedback shift register, the first vector block is mapped to the third storage unit of the linear feedback shift register, and the second vector block is mapped to the fourth storage unit of the linear feedback shift register; [pk1] Step 3: In the initialization phase, the driver layer of the hardware layer performs multiple rounds of nonlinear iterative operations on the mapped register to generate confused state data. In the working phase, the driver layer performs cyclic shift operations on the register to generate shift state data. From the shift state data, the bit recombination operation is performed on the shift state data through the solidified path to generate the first recombined data of the feedback shift register and the second recombined data of the linear feedback shift register. Step 4: The extracted first and second recombined data are processed in three levels using a finite state machine at the hardware layer. The first level uses a permutation table to generate nonlinear transformation data. The second level uses a linear diffusion operation to process the nonlinear transformation data and generate diffusion data. The third level reuses the diffusion data to perform an XOR operation and generate a key stream. Step 5: Receive the input data to be encrypted, and perform a bitwise XOR operation between the key stream and the input data using a bitwise XOR unit to output the generated encrypted data stream.

[0007] Furthermore, in the implementation method of the lightweight stream cipher of the present invention, step 1 includes: Receive a 128-bit key and a 96-bit initialization vector; Divide the 128-bit key into four 32-bit key blocks; Divide the 96-bit initial vector into three 32-bit vector blocks; The four key blocks are mapped to the first, second, third, and fourth storage units of the feedback shift register, respectively. The three vector blocks are mapped to the fifth, sixth, and seventh memory units of the linear feedback shift register, respectively.

[0008] Furthermore, in the implementation method of the lightweight stream cipher of the present invention, step 3 includes: during the initialization phase, the driver layer performs 32 rounds of combined operations on the feedback shift register and the linear feedback shift register. The 32 rounds of combined operations include modular addition and cyclic shift. The data in the storage unit of the register is read, the modular addition operation is performed to generate intermediate data, and the intermediate data is cyclically shifted. During the working phase, the driver layer performs a single-step cyclic shift operation, reads the shift status data, and performs a single-bit cyclic right shift.

[0009] Furthermore, in the implementation method of the lightweight stream cipher of the present invention, step 3 includes: locating the position of the high 4 bits from the storage unit of the feedback shift register; Extract the data from the high 4 bits to generate the first recombined data; Locate the fixed bit position determined according to a preset rule from the storage cell of the linear feedback shift register; Data is extracted from preset fixed bit positions to generate the second recombined data.

[0010] Furthermore, in the implementation method of the lightweight stream cipher of the present invention, step 4 includes: The constant data required for generating the substitution table is generated offline, and the constant data is pre-programmed into the read-only memory; During the permutation table lookup phase, constant data is read from read-only memory to generate nonlinear transformation data; During the linear diffusion operation phase, the same set of registers from the finite state machine is reused to execute the operation, receive nonlinear transformation data, perform linear diffusion, and store the diffusion data.

[0011] Furthermore, in the implementation method of the lightweight stream cipher of the present invention, step 4 further includes: Receive the first recombinant data; The first reassembled data is split into eight 32-bit sub-data segments; The replacement table of read-only memory is accessed synchronously through eight independent query channels; The eight query results are concatenated into 256 bits of nonlinear transformation data.

[0012] Furthermore, in the implementation method of the lightweight stream cipher of the present invention, step 3 further includes: generating 256 bits of constant data required for the substitution table offline; The constant data is pre-stored in the eighth memory unit preset by the linear feedback shift register; During the initialization phase, the driver layer reads constant data from the eighth storage unit; The constant data read is used in the substitution table lookup phase.

[0013] Furthermore, in the implementation method of the lightweight stream cipher described in this invention, step 3 further includes: monitoring the radiation interference signal of the spaceborne equipment; When radiated interference is detected, 4 bits of redundant parity are injected into the shift state data during the driving layer operation phase. Parity check calculations are performed on the shift state data containing check bits using a cyclic shift check chain; Correct the erroneous bits in the shift state data based on the verification results.

[0014] Secondly, the present invention provides a lightweight stream cipher implementation system, applied to the aforementioned lightweight stream cipher implementation method, comprising: Acquisition device, used to acquire the key and initialization vector; A segmentation device is used to segment the key into a first key block and a second key block through a physical isolation mechanism, and to segment the initial vector into a first vector block and a second vector block; A mapping device is used to map the segmented key blocks and vector blocks to designated storage units of the feedback shift register and linear feedback shift register defined in the hardware layer, respectively. The driving device is used to perform multiple rounds of nonlinear iterative operations to generate confused state data during the initialization phase and to perform cyclic shift operations to generate shift state data during the working phase. A recombination device is used to extract first recombination data from a feedback shift register and second recombination data from a linear feedback shift register from shift state data via a solidification path. A state machine device is used to perform a three-stage pipeline operation on the first and second recombined data to generate a key stream; An encryption device is used to receive input data, perform a bitwise XOR operation between the key stream and the input data using a bitwise XOR unit, and output an encrypted data stream.

[0015] Thirdly, the present invention provides an electronic device, comprising: Memory, which stores computer programs; The steps of implementing the lightweight stream cipher method when the processor executes the computer program.

[0016] Beneficial effects of this invention; The beneficial effects of this invention are manifested in the following aspects: First, by physically isolating the key and initialization vector and mapping them to different storage units in the registers, storage resource conflicts in industrial control embedded systems are eliminated, reducing the size burden. Second, the dual-mode architecture of the driver layer separates the multi-round nonlinear iteration in the initialization phase from the pure cyclic shift operation in the working phase, significantly reducing the dynamic power consumption of the onboard equipment while maintaining cryptographic security strength. Third, the fixed path extracts high-bit data from the feedback shift register and fixed-bit data from the linear feedback shift register, eliminating dynamic addressing overhead and optimizing the space and energy balance of the satellite communication terminal. Fourth, the finite state machine three-level pipeline reuses the permutation table pre-programming and register sharing mechanism, reducing the number of logic unit instantiations and improving the resource utilization of the embedded system. Fifth, offline generation of constant data pre-stored combined with a fault-tolerant verification injection mechanism suppresses the probability of soft errors and hardware failure risks on the onboard platform. Sixth, the overall solution collaboratively addresses the problems of encryption latency, power consumption surge, and reliability degradation in resource-constrained scenarios. Attached Figure Description

[0017] To more clearly illustrate the technical solution of the present invention, the drawings used in the embodiments will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on the drawings without creative effort.

[0018] Figure 1 The system architecture diagram is shown for the implementation system of lightweight stream cipher provided in the embodiments of the present invention. Detailed Implementation

[0019] To make the technical solution of the present invention clearer, the present invention will be clearly and completely described below with reference to specific embodiments and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. The present invention provided by various embodiments will be described in detail below with reference to the accompanying drawings. To better understand the purpose of the present invention, the present invention will be described in further detail below.

[0020] Please see Figure 1 The present invention provides a method for implementing a lightweight stream cipher, comprising: Step 1: Obtain the key and initialization vector. Divide the key into a first key block and a second key block using a physical isolation mechanism. Divide the initialization vector into a first vector block and a second vector block. Step 2: Map the segmented first key block, second key block, first vector block, and second vector block to the feedback shift register and linear feedback shift register defined in the hardware layer, respectively. The first key block is mapped to the first storage unit of the feedback shift register, the second key block is mapped to the second storage unit of the feedback shift register, the first vector block is mapped to the third storage unit of the linear feedback shift register, and the second vector block is mapped to the fourth storage unit of the linear feedback shift register. Step 3: In the initialization phase, the driver layer of the hardware layer performs multiple rounds of nonlinear iterative operations on the mapped register to generate confused state data. In the working phase, the driver layer performs cyclic shift operations on the register to generate shift state data. From the shift state data, the bit recombination operation is performed on the shift state data through the solidified path to generate the first recombined data of the feedback shift register and the second recombined data of the linear feedback shift register. Step 4: The extracted first and second recombined data are processed in three levels using a finite state machine at the hardware layer. The first level uses a permutation table to generate nonlinear transformation data. The second level uses a linear diffusion operation to process the nonlinear transformation data and generate diffusion data. The third level reuses the diffusion data to perform an XOR operation and generate a key stream. Step 5: Receive the input data to be encrypted, and perform a bitwise XOR operation between the key stream and the input data using a bitwise XOR unit to output the generated encrypted data stream.

[0021] After obtaining the key and initialization vector, a segmentation operation is performed using a physical isolation mechanism. This mechanism divides the complete key into independent first key blocks and second key blocks, and similarly, the initialization vector into independent first vector blocks and second vector blocks. This segmentation ensures that different data blocks do not overlap during subsequent mapping, eliminating the risk of storage resource contention. The segmented data blocks then enter the register mapping stage as independent inputs, providing an isolated data source for hardware-level processing.

[0022] The segmented data blocks are mapped to specified storage units in registers defined by the hardware layer. The first key block is mapped to the first storage unit of the feedback shift register, and the second key block is mapped to the second storage unit of the feedback shift register; the first vector block is mapped to the third storage unit of the linear feedback shift register, and the second vector block is mapped to the fourth storage unit of the linear feedback shift register. This mapping operation establishes a fixed correspondence between data blocks and physical storage locations, avoiding the overhead of dynamic addressing. Registers, as fundamental components of the hardware layer, provide static data storage for driver layer operations.

[0023] The driver layer performs multiple rounds of nonlinear iterative operations during the initialization phase. It reads data from the mapped register's storage cells, performs compound operations to generate intermediate data, and strengthens state confusion through cyclic shifting, ultimately outputting confused state data. These nonlinear iterative operations enhance the initial entropy value, improving cryptographic security. The confused state data serves as input for the working phase, supporting subsequent operations in the encryption process.

[0024] The driver layer performs cyclic shift operations during the working phase. During this phase, the driver layer reads the shift state data and performs a single-bit cyclic shift to generate updated shift state data. The cyclic shift uses a lightweight hardware-level operation, significantly reducing dynamic power consumption and computational latency. The shift state data serves as input for the bit recombination operation and is passed to the fixed path processing stage.

[0025] The fixed path performs bit recombination operations on the shifted state data. It locates the high-order bit position from the storage cell of the feedback shift register, extracts a specified bit to generate the first recombined data, and locates the fixed bit position determined according to preset rules from the storage cell of the linear feedback shift register, extracts a specified bit to generate the second recombined data. The fixed path eliminates dynamic shift overhead through preset hardware rules, ensuring data extraction efficiency. The recombined first and second recombined data are then input into a finite state machine for processing.

[0026] The finite state machine executes a three-stage pipelined process. The first stage converts the recombined data into nonlinear transformed data through a permutation table, which is pre-programmed into read-only memory. The second stage processes the nonlinear transformed data using linear diffusion operations, generating diffused data and reusing the same set of registers to perform multiple stages of operations. The third stage reuses the diffused data for XOR operations to directly generate the key stream. This three-stage pipeline achieves hierarchical computation and hardware reuse, optimizing resource utilization.

[0027] The encrypted data stream is generated by a bitwise XOR unit. It receives the input data to be encrypted and the key stream, and performs an XOR operation bit by bit using a hardware-level bitwise XOR unit. The XOR operation outputs an encrypted data stream, completing the end-to-end encryption process. This encrypted data stream serves as the final output, addressing the encryption latency and power consumption issues of resource-constrained devices.

[0028] Specifically, in the lightweight stream cipher implementation method of the present invention, step 1 includes: Receive a 128-bit key and a 96-bit initialization vector; Divide the 128-bit key into four 32-bit key blocks; Divide the 96-bit initial vector into three 32-bit vector blocks; The four key blocks are mapped to the first to fourth memory units of the feedback shift register, respectively. The three vector blocks are mapped to the fifth to seventh memory units of the linear feedback shift register, respectively.

[0029] The physical isolation mechanism receives a 128-bit key and a 96-bit initialization vector as input. The key is divided into four 32-bit key blocks, and the initialization vector is divided into three 32-bit vector blocks. The key blocks are mapped to the first to fourth memory cells of the feedback shift register, and the vector blocks are mapped to the fifth to seventh memory cells of the linear feedback shift register. This cell mapping establishes physical storage isolation between the key blocks and vector blocks, eliminating the risk of register space overlap. Independent cell allocation enables parallel storage of multiple data blocks, adapting to the space constraints of resource-constrained devices.

[0030] Specifically, in the implementation method of the lightweight stream cipher of the present invention, step 3 includes: in the initialization phase, the driver layer performs 32 rounds of combined operations on the feedback shift register and the linear feedback shift register. The 32 rounds of combined operations include modular addition and cyclic shift. The data in the storage unit of the register is read, the modular addition operation is performed to generate intermediate data, and the intermediate data is cyclically shifted. During the working phase, the driver layer performs a single-step cyclic shift operation, reads the shift status data, and performs a single-bit cyclic right shift.

[0031] During the initialization phase, the driver layer reads data from the storage units of the feedback shift register and the linear feedback shift register, and performs modular addition to generate intermediate data. Modular addition combines arithmetic and logical operation characteristics to enhance non-linear obfuscation strength. The intermediate data undergoes a cyclic shift operation to change the bit position distribution. This composite operation iterates 32 times to generate high-entropy obfuscated state data. During the working phase, the driver layer reads the shift state data and performs a single-bit cyclic right shift. This single-step shift simplifies the calculation process, reduces dynamic power consumption and clock cycle usage, and supports real-time encryption requirements.

[0032] Specifically, in the lightweight stream cipher implementation method of the present invention, step 3 includes: locating the high 4 bits from the storage unit of the feedback shift register; Extract the data from the high 4 bits to generate the first recombined data; Locate the fixed bit position determined according to a preset rule from the storage cell of the linear feedback shift register; Data is extracted from preset fixed bit positions to generate the second recombined data.

[0033] The fixed path locates the high 4 bits of the feedback shift register storage unit and extracts the high-order bits to generate the first reconstructed data. The high-order bits retain valid data information, avoiding redundant calculations in the lower bits. Simultaneously, the fixed bit position of the linear feedback shift register storage unit is located, and the fixed bit data is extracted to generate the second reconstructed data. The fixed bit position is preset according to the hardware architecture to ensure data extraction stability. The fixed path eliminates dynamic displacement addressing operations, reducing data transfer resource consumption.

[0034] Specifically, in the lightweight stream cipher implementation method of the present invention, step 4 includes: The constant data required for generating the substitution table is generated offline, and the constant data is pre-programmed into the read-only memory; During the permutation table lookup phase, constant data is read from read-only memory to generate nonlinear transformation data; During the linear diffusion operation phase, the same set of registers from the finite state machine is reused to execute the operation, receive nonlinear transformation data, perform linear diffusion, and store the diffusion data.

[0035] The constant data required for generating the permutation table is pre-programmed into read-only memory (ROM) offline. This pre-programming operation permanently stores the permutation table content, saving on real-time computation circuitry. During the permutation table lookup phase, constant data is read from ROM and combined with the recombined data to generate nonlinear transformation data. In the linear diffusion operation phase, the same set of registers from the finite state machine is reused to receive the nonlinear transformation data and perform linear transformations. This register-sharing mechanism reduces the number of logic unit instantiations, optimizing hardware resource utilization. The transformation result is stored as diffusion data and passed to the next stage of processing.

[0036] Specifically, in the lightweight stream cipher implementation method of the present invention, step 4 further includes: Receive the first recombinant data; The first reassembled data is split into eight 32-bit sub-data segments; The replacement table of read-only memory is accessed synchronously through eight independent query channels; The eight query results are concatenated into 256 bits of nonlinear transformation data.

[0037] The first reassembled data is received and split into eight 32-bit sub-segments. This data segmentation adapts to a parallel processing architecture, improving query throughput. Eight independent query channels synchronously access the permutation table in read-only memory, outputting eight query results. Parallel operation eliminates serial query latency, reducing encryption response time. The query results are concatenated into 256 bits of nonlinear transformation data and transmitted completely to the linear diffusion stage.

[0038] Specifically, in the implementation method of the lightweight stream cipher of the present invention, step 3 further includes: generating 256 bits of constant data required for the substitution table offline; The constant data is pre-stored in the eighth memory unit preset by the linear feedback shift register; During the initialization phase, the driver layer reads constant data from the eighth storage unit; The constant data read is used in the substitution table lookup phase.

[0039] A 256-bit permutation table constant is generated offline and pre-stored in the eighth memory cell of the linear feedback shift register. This dedicated memory cell isolates the constant storage area, avoiding data conflicts during initialization. During initialization, the driver layer reads the constant data from the eighth memory cell and directly calls the pre-stored data. This constant data is then used in the permutation table lookup phase, eliminating the computational burden of real-time generation. This pre-stored mechanism reduces dynamic power consumption and improves the long-term operational stability of onboard equipment.

[0040] Specifically, in the lightweight stream cipher implementation method of the present invention, step 3 further includes: monitoring the radiation interference signal of the spaceborne equipment; When radiated interference is detected, 4 bits of redundant parity are injected into the shift state data during the driving layer operation phase. Parity check calculations are performed on the shift state data containing check bits using a cyclic shift check chain; Correct the erroneous bits of the shift state data based on the verification results.

[0041] The system monitors radiation interference signals from onboard equipment and detects high-energy particle impact events in real time. When radiation interference is detected, a 4-bit redundant parity bit is injected into the shift state data during the drive layer's operational phase. This parity bit enhances data integrity verification capabilities and identifies potential bit errors. Parity checks are performed on the data containing the parity bit using a cyclic shift check chain to locate the position of the erroneous bit. Based on the check results, the erroneous bits in the shift state data are corrected, restoring data consistency in the encryption process. This fault-tolerance processing improves radiation resistance in the onboard environment.

[0042] Secondly, the present invention provides a lightweight stream cipher implementation system, applied to the aforementioned lightweight stream cipher implementation method, comprising: Acquisition device, used to acquire the key and initialization vector; A segmentation device is used to segment the key into a first key block and a second key block through a physical isolation mechanism, and to segment the initial vector into a first vector block and a second vector block; A mapping device is used to map the segmented key blocks and vector blocks to designated storage units of the feedback shift register and linear feedback shift register defined in the hardware layer, respectively. The driving device is used to perform multiple rounds of nonlinear iterative operations to generate confused state data during the initialization phase and to perform cyclic shift operations to generate shift state data during the working phase. A recombination device is used to extract first recombination data from a feedback shift register and second recombination data from a linear feedback shift register from shift state data via a solidified path. A state machine device is used to perform a three-stage pipeline operation on the first and second recombined data to generate a key stream; An encryption device is used to receive input data, perform a bitwise XOR operation between the key stream and the input data using a bitwise XOR unit, and output an encrypted data stream.

[0043] Thirdly, the present invention provides an electronic device, comprising: Memory, which stores computer programs; The steps of implementing the lightweight stream cipher method when the processor executes the computer program.

[0044] This invention addresses resource consumption issues through multi-level collaborative optimization. A physical isolation mechanism divides the key and initialization vector into independent data blocks, mapping them to different storage units of the feedback shift register and the linear feedback shift register. This mechanism eliminates the risk of register space overlap, reduces storage conflicts during multi-task encryption in industrial control embedded systems, and lowers the overall size burden.

[0045] The driver layer employs a dual-mode architecture to separate security strength from operational efficiency. During initialization, multiple rounds of nonlinear iterations are performed to strengthen state obfuscation, ensuring a cryptographic security baseline. During operation, a pure cyclic shift operation is used, significantly reducing the frequency of logic gate triggering. This dual-mode design adapts to the low-power requirements of radiation-resistant spaceborne equipment while simultaneously meeting the real-time response requirements of industrial control systems.

[0046] Fixed path extraction eliminates dynamic displacement overhead. Pre-defined hardware rules locate the high bits of the feedback shift register and the fixed bits of the linear feedback shift register, directly extracting and reconstructing data. The fixed operation eliminates the computational load of dynamic addressing, reducing the space occupation and transmission power consumption of satellite communication terminals.

[0047] A three-stage pipelined finite state machine achieves hardware reuse. The permutation table is pre-programmed into read-only memory, eliminating the need for real-time computation circuitry; the linear diffusion stage reuses the same set of registers to perform multi-stage operations; and eight-way parallel lookups of the permutation table improve throughput. This reuse mechanism reduces the number of logic unit instantiations, optimizing the resource utilization of the embedded system.

[0048] In the keystream synthesis stage, diffused data is multiplexed for XOR operations to avoid redundant state machine calculations. A single-step update mechanism in the driver layer adapts to low-frequency clock synchronization, maintaining timing stability in harsh satellite terminal environments. Offline generation of constant data is pre-stored in dedicated register units to suppress the probability of soft errors on the onboard platform.

[0049] Fault-tolerant mechanisms enhance reliability in extreme environments. Redundant parity bits are injected when radiated interference is triggered, and parity checks are performed through a cyclic shift check chain. The check results correct erroneous bits in the shift state data in real time, improving the onboard equipment's resistance to single-event upsets. A pre-programmed permutation table, combined with a register-sharing design, simultaneously reduces the heat dissipation pressure and hardware failure risk of industrial control equipment.

Claims

1. A method for implementing a lightweight stream cipher, characterized in that, include: Step 1: Obtain the key and initialization vector. Divide the key into a first key block and a second key block using a physical isolation mechanism. Divide the initialization vector into a first vector block and a second vector block. Step 2: Map the segmented first key block, second key block, first vector block, and second vector block to the feedback shift register and linear feedback shift register defined in the hardware layer, respectively. The first key block is mapped to the first storage unit of the feedback shift register, the second key block is mapped to the second storage unit of the feedback shift register, the first vector block is mapped to the third storage unit of the linear feedback shift register, and the second vector block is mapped to the fourth storage unit of the linear feedback shift register. Step 3: In the initialization phase, the driver layer of the hardware layer performs multiple rounds of nonlinear iterative operations on the mapped register to generate confused state data. In the working phase, the driver layer performs cyclic shift operations on the register to generate shift state data. From the shift state data, the bit recombination operation is performed on the shift state data through the solidified path to generate the first recombined data of the feedback shift register and the second recombined data of the linear feedback shift register. Step 4: The extracted first and second recombined data are processed in three levels using a finite state machine at the hardware layer. The first level uses a permutation table to generate nonlinear transformation data. The second level uses a linear diffusion operation to process the nonlinear transformation data and generate diffusion data. The third level reuses the diffusion data to perform an XOR operation and generate a key stream. Step 5: Receive the input data to be encrypted, and perform a bitwise XOR operation between the key stream and the input data using a bitwise XOR unit to output the generated encrypted data stream.

2. The method for implementing lightweight stream ciphers according to claim 1, characterized in that, Step 1 includes: Receive a 128-bit key and a 96-bit initialization vector; Divide the 128-bit key into four 32-bit key blocks; Divide the 96-bit initial vector into three 32-bit vector blocks; The four key blocks are mapped to the first, second, third, and fourth storage units of the feedback shift register, respectively. The three vector blocks are mapped to the fifth, sixth, and seventh memory units of the linear feedback shift register, respectively.

3. The method for implementing lightweight stream cipher according to claim 1, characterized in that, Step 3 includes: During the initialization phase, the driver layer performs 32 rounds of compound operations on the feedback shift register and the linear feedback shift register. The 32 rounds of compound operations include modular addition and cyclic shifting, reading data from the register's storage unit, performing modular addition to generate intermediate data, and performing cyclic shifting on the intermediate data. During the working phase, the driver layer performs a single-step cyclic shift operation, reads the shift status data, and performs a single-bit cyclic right shift.

4. The method for implementing lightweight stream cipher according to claim 1, characterized in that, Step 3 includes: Locate the high 4 bits from the memory location of the feedback shift register; Extract the data from the high 4 bits to generate the first recombined data; Locate the fixed bit position determined according to a preset rule from the storage cell of the linear feedback shift register; Data is extracted from preset fixed bit positions to generate the second recombined data.

5. The method for implementing lightweight stream cipher according to claim 1, characterized in that, Step 4 includes: The constant data required for generating the substitution table is generated offline, and the constant data is pre-programmed into the read-only memory; During the permutation table lookup phase, constant data is read from read-only memory to generate nonlinear transformation data; During the linear diffusion operation phase, the same set of registers from the finite state machine is reused to execute the operation, receive nonlinear transformation data, perform linear diffusion, and store the diffusion data.

6. The method for implementing lightweight stream cipher according to claim 5, characterized in that, Step 4 also includes: Receive the first recombinant data; The first reassembled data is split into eight 32-bit sub-data segments; The replacement table of read-only memory is accessed synchronously through eight independent query channels; The eight query results are concatenated into 256 bits of nonlinear transformation data.

7. The method for implementing lightweight stream cipher according to claim 1, characterized in that, Step 3 also includes: The 256-bit constant data required for offline generation of the substitution table; The constant data is pre-stored in the eighth memory unit preset by the linear feedback shift register; During the initialization phase, the driver layer reads constant data from the eighth storage unit; The constant data read is used in the substitution table lookup phase.

8. The method for implementing lightweight stream cipher according to claim 1, characterized in that, Step 3 also includes: Monitor radiated interference signals from spaceborne equipment; When radiated interference is detected, 4 bits of redundant check bits are injected into the shift state data during the driving layer operation phase. Parity check calculations are performed on the shift state data containing check bits using a cyclic shift check chain; Correct the erroneous bits in the shift state data based on the verification results.

9. A system for implementing a lightweight stream cipher, applied to the implementation method of the lightweight stream cipher as described in any one of claims 1 to 8, characterized in that, include: Acquisition device, used to acquire the key and initialization vector; A segmentation device is used to segment the key into a first key block and a second key block through a physical isolation mechanism, and to segment the initial vector into a first vector block and a second vector block; A mapping device is used to map the segmented key blocks and vector blocks to designated storage units of the feedback shift register and linear feedback shift register defined in the hardware layer, respectively. The driving device is used to perform multiple rounds of nonlinear iterative operations to generate confused state data during the initialization phase, and to perform cyclic shift operations to generate shift state data during the working phase. The cyclic shift operations include modulo addition and cyclic shift. A recombination device is used to extract first recombination data from a feedback shift register and second recombination data from a linear feedback shift register from shift state data via a solidification path. A state machine device is used to perform a three-stage pipeline operation on the first and second recombined data to generate a key stream; An encryption device is used to receive input data, perform a bitwise XOR operation between the key stream and the input data using a bitwise XOR unit, and output an encrypted data stream.

10. An electronic device, characterized in that, include: Memory, which stores computer programs; The processor, when executing the computer program, implements the steps of the lightweight stream cipher implementation method according to any one of claims 1 to 8.

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