Semiconductor device, manufacturing method thereof and electronic equipment

Abstract

The invention relates to a semiconductor device, a manufacturing method thereof and electronic equipment, and the manufacturing method comprises the steps: providing a substrate, and alternately forming insulating layers and sacrificial layers on the substrate; forming a capacitance hole, and transversely etching the sacrificial layer based on the capacitance hole to form a first transverse hole; forming a first electrode in the first transverse hole; forming a dielectric layer covering the first electrode and a second electrode in the capacitor hole to form a capacitor; forming a corresponding channel hole in one side of the capacitor hole, and transversely etching the sacrificial layer based on the channel hole to form a second transverse hole; forming a semiconductor channel in the second transverse hole to cover the exposed first electrode; a bit line is formed, the bit line is arranged perpendicular to the substrate, and the bit line is far away from the capacitor; the sacrificial layer is removed, and the gate dielectric layer and the word line are sequentially formed in the region where the sacrificial layer is removed, so that the integration density of the storage unit is improved, the storage density of the semiconductor device is expanded, and the Moore's law can be continued.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a semiconductor device and its fabrication method, and an electronic device. Background Technology

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and number of devices contained in a single chip are increasing, which means that any slight difference in the manufacturing process can affect the performance of the devices.

[0003] To minimize product costs, the goal is to fabricate as many device cells as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor device design and process optimizations to meet current product demands. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0005] In a first aspect, this disclosure provides a method for fabricating a semiconductor device, comprising:

[0006] A substrate is provided on which insulating layers and sacrificial layers are alternately formed;

[0007] A capacitor hole is formed that penetrates the entire sacrificial layer vertically, and the sacrificial layer is etched laterally based on the capacitor hole to form a first lateral hole;

[0008] A first electrode is formed in the first transverse hole;

[0009] A dielectric layer and a second electrode are formed in the capacitor hole, sequentially covering the first electrode, so as to form a capacitor together with the first electrode;

[0010] A corresponding channel hole is formed on one side of the capacitor hole, and the sacrificial layer is laterally etched based on the channel hole to expose part of the first electrode, forming a second lateral hole;

[0011] A semiconductor channel is formed in the second lateral hole, covering the exposed first electrode;

[0012] Bit lines are formed in the channel holes, the bit lines are disposed perpendicular to the substrate, and the bit lines are away from the capacitor;

[0013] The sacrificial layer is removed, and a gate dielectric layer and a word line are sequentially formed around the first electrode and the semiconductor channel in the area where the sacrificial layer is removed.

[0014] Optionally, forming a first electrode in the first transverse hole includes:

[0015] A first electrode material layer is formed to cover the walls of the capacitor hole and the first lateral hole;

[0016] A first dielectric layer is formed to cover the first electrode material layer and fill the area where the first lateral hole is not filled.

[0017] The first dielectric layer and the first electrode material layer in the capacitor hole are removed by etching layer by layer, and the first electrode is formed in the first electrode material layer in the first lateral hole;

[0018] The first dielectric layer in the first lateral hole is etched away to expose the first electrode.

[0019] Optionally, after forming the dielectric layer that sequentially covers the first electrode and the second electrode, the method further includes:

[0020] A common electrode post is formed in the capacitor hole, the common electrode post is connected to the second electrode, and the common electrode post extends into the substrate and is connected to the substrate.

[0021] Optionally, a common electrode post is formed in the capacitor hole, including:

[0022] A contact layer is formed, which covers the second electrode and forms an initial contact hole in the capacitor hole;

[0023] The initial contact hole is etched to deepen its depth, forming a contact hole that extends into the substrate and exposes a portion of the substrate.

[0024] The common electrode post is formed in the contact hole, the common electrode post covers the contact layer and is in contact with the second electrode through the contact layer, and the common electrode post also covers the exposed substrate to be connected to the substrate.

[0025] Optionally, the manufacturing method includes:

[0026] A semiconductor layer is formed to cover the walls of the channel hole and the second lateral hole;

[0027] A second dielectric layer is formed to cover the semiconductor layer and fill the area where the second lateral hole is not filled.

[0028] The second dielectric layer and the semiconductor layer in the channel hole are removed by etching layer by layer;

[0029] The second dielectric layer in the second lateral hole is removed by etching.

[0030] Optionally, after etching away the second dielectric layer in the second lateral hole, the process further includes:

[0031] A third dielectric layer is formed to fill the unfilled areas of the channel holes and the second transverse holes;

[0032] Etching removes a portion of the third dielectric layer and a portion of the semiconductor layer to form a bit line hole, the projection of the bit line hole on the substrate being inscribed within the second lateral hole;

[0033] The bit line is formed in the bit line hole, and the bit line is connected to the semiconductor channel.

[0034] Optionally, a plurality of capacitor holes are formed at intervals along a first direction parallel to the substrate;

[0035] Along the first direction, a plurality of channel holes are formed corresponding one-to-one with the plurality of capacitor holes. Each channel hole is formed between two adjacent capacitor holes, and the channel hole is close to the capacitor hole corresponding to it and away from the capacitor hole on the other side.

[0036] After the second lateral hole is formed by etching based on the channel hole, the second lateral hole exposes the corresponding first lateral hole, and the second lateral hole is separated from the first lateral hole on the other side by the sacrificial layer;

[0037] The word line extends along the first direction and intersects with multiple sets of capacitors and semiconductor channels.

[0038] In a second aspect, this disclosure provides a semiconductor device, comprising:

[0039] Substrate;

[0040] At least one column of memory cells includes a plurality of memory cells spaced apart along a direction perpendicular to the substrate, each memory cell including a connected transistor and a capacitor, the transistor including a semiconductor channel projected as an annular shape on the substrate, the capacitor including a first electrode projected as an annular shape on the substrate, the semiconductor channel and the first electrode being in contact connection;

[0041] At least one bit line, along a plane perpendicular to the substrate, the bit line being away from the capacitor and in contact with a row of semiconductor channels;

[0042] At least one word line is spaced apart in a direction perpendicular to the substrate, the word line extends in a direction parallel to the substrate, the word line surrounds the memory cell in its extension direction, and the word line surrounds the area outside the region where the first electrode and the semiconductor channel are connected.

[0043] Optionally, each transistor further includes a gate, a first source / drain, and a second source / drain, wherein the gate is connected to the word line, the first source / drain is connected to the first electrode, and the second source / drain is connected to the bit line.

[0044] Optionally, along a plane perpendicular to the substrate, the capacitor further includes a dielectric layer and a second electrode that sequentially surround the inner wall of the first electrode.

[0045] Optionally, the capacitor further includes:

[0046] A common electrode post is vertically disposed on the substrate. The common electrode post is disposed on the inner side of the second electrode away from the first electrode and is connected to the second electrode. The common electrode post extends into the substrate and is connected to the substrate.

[0047] Optionally, the semiconductor device further includes:

[0048] A contact portion is disposed between the second electrode and the common electrode post, the contact portion surrounds the second electrode, and the common electrode post is connected to the second electrode through the contact portion.

[0049] Optionally, at least one column of the memory cells is spaced apart and arranged in multiple rows along a first direction parallel to the substrate, and the multiple rows of the memory cells are spaced apart along a second direction parallel to the substrate, the first direction being perpendicular to the second direction, the word lines extending along the first direction and spaced apart along the second direction, and each word line intersecting with one or more rows of the memory cells.

[0050] Optionally, the bit lines of at least one column of the memory cells are arranged in multiple rows along a third direction parallel to the substrate, the third direction intersecting obliquely with the first direction and the second direction.

[0051] Optionally, it also includes:

[0052] At least one bit line lead wire extends along the second direction on the column of memory cells, and each column of memory cells is connected by the bit line and the bit line lead wire.

[0053] Optionally, the transistors and capacitors of at least one column of the memory cells are arranged in a hexagonal pattern on the substrate.

[0054] Thirdly, this disclosure provides an electronic device, characterized in that it includes the semiconductor device as described in the second aspect.

[0055] The semiconductor device and its fabrication method disclosed herein utilize a three-dimensional stacked architecture of memory cells formed in a third dimension perpendicular to the substrate, which improves the integration density of memory cells, expands the storage density of semiconductor devices, improves the space utilization of semiconductor devices, and is conducive to the continuation of Moore's Law. Attached Figure Description

[0056] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0057] Figure 1 This is a process flow diagram of a method for fabricating a semiconductor device provided in one embodiment.

[0058] Figure 2 This is a schematic diagram of alternating insulating and sacrificial layers formed on a substrate, as provided in one embodiment.

[0059] Figure 3 This is a schematic diagram of the capacitor hole after it has been formed, as provided in one embodiment.

[0060] Figure 4 This is a schematic diagram of the first transverse hole after it has been formed, as provided in one embodiment.

[0061] Figure 5 This is a schematic diagram of the formation of the first electrode material layer in one embodiment.

[0062] Figure 6 This is a schematic diagram of the formation of the first dielectric layer in one embodiment.

[0063] Figure 7 This is a schematic diagram of the process after removing the first dielectric layer from the capacitor hole, as provided in one embodiment.

[0064] Figure 8 This is a schematic diagram of a first electrode formed in a first transverse hole, as provided in one embodiment.

[0065] Figure 9 This is a schematic diagram of the first electrode after the first dielectric layer has been removed, as provided in one embodiment.

[0066] Figure 10 This is a schematic diagram showing the dielectric layer and the second electrode formed sequentially in one embodiment.

[0067] Figure 11 This is a schematic diagram after the contact layer has been formed in one embodiment.

[0068] Figure 12 This is a schematic diagram after the contact hole has been formed in one embodiment.

[0069] Figure 13 This is a schematic diagram of the common electrode post after it has been formed in one embodiment.

[0070] Figure 14 This is a schematic diagram of the channel holes formed in one embodiment.

[0071] Figure 15 This is a schematic diagram of a second transverse hole formed after the first transverse hole is externally tangent to it, in one embodiment.

[0072] Figure 16 This is a schematic diagram after the semiconductor layer has been formed in one embodiment.

[0073] Figure 17 This is a schematic diagram after the second dielectric layer has been formed in one embodiment.

[0074] Figure 18 This is a schematic diagram of a semiconductor channel formed after removing the second dielectric layer and semiconductor layer from the capacitor hole in one embodiment.

[0075] Figure 19 This is a schematic diagram of a semiconductor channel after the second dielectric layer has been removed in one embodiment.

[0076] Figure 20 This is a schematic diagram after the third dielectric layer has been formed in one embodiment.

[0077] Figure 21 This is a schematic diagram after the bit line hole is formed in one embodiment.

[0078] Figure 22 This is a schematic diagram after the bit lines are formed in one embodiment.

[0079] Figure 23 This is a schematic diagram of the process after removing the sacrificial layer to form word line slots in one embodiment.

[0080] Figure 24 This is a schematic diagram showing the sequence of forming the gate dielectric layer and word lines in one embodiment.

[0081] Figure 25 A top view of a storage unit provided in one embodiment.

[0082] Figure 26 This is a schematic diagram of the structure of semiconductor channel and bit line connection provided in one embodiment.

[0083] Figure 27 A top view of a semiconductor device provided in one embodiment.

[0084] Figure 28A top view of a semiconductor device provided for another embodiment. Explanation of reference numerals in the attached figures

[0085] 10. Substrate; 21. Insulating layer; 22. Sacrificial layer; 130. Capacitor via; 131. First lateral via; 171. Dielectric layer; 271. Second dielectric layer; 371. Third dielectric layer; 190. Contact via; 190a. Initial contact via; 230. Channel via; 231. Second lateral via; 330. Bit line via; 430. Word line slot; 40. Capacitor; 41. First electrode; 41a. First electrode material layer; 42. Dielectric layer 43. Electrode layer; 44a. Contact layer; 44. Contact portion; 45. First diffusion barrier layer; 46. Common electrode post; 50. Semiconductor channel; 50-1. Vertical portion; 50-2. First horizontal portion; 50-3. Second horizontal portion; 51. Semiconductor layer; 60. Bit line; 61. Second diffusion barrier layer; 70. Word line; 170. First word line; 270. Second word line; 71. Gate dielectric layer; 80. Bit line lead-out conductor;

[0086] 1. Memory cell column; 100. Memory cell; MCT. Transistor; S / D1. First source / drain; S / D2. Second source / drain; D1. First direction; D2. Second direction; D3. Third direction. Detailed Implementation

[0087] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0088] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0089] This disclosure provides a method for fabricating a semiconductor device in exemplary embodiments, referring to... Figure 1 As shown, Figure 1 A flowchart illustrating a method for fabricating a semiconductor device according to an exemplary embodiment of the present disclosure is shown. This embodiment does not limit the semiconductor device; the following description will use Dynamic Random Access Memory (DRAM) as an example.

[0090] Reference Figure 1As shown in some embodiments of this disclosure, a method for fabricating a semiconductor device includes the following steps:

[0091] Step S110: Provide a substrate and alternately form an insulating layer and a sacrificial layer on the substrate.

[0092] Step S120: Form a capacitor hole that vertically penetrates the entire sacrificial layer, and etch the sacrificial layer laterally based on the capacitor hole to form a first lateral hole.

[0093] Step S130: Form a first electrode in the first transverse hole.

[0094] Step S140: A dielectric layer and a second electrode are formed in the capacitor hole, which sequentially cover the first electrode, so as to form a capacitor together with the first electrode.

[0095] Step S150: Form a corresponding channel hole on one side of the capacitor hole, and etch the sacrificial layer laterally based on the channel hole to expose part of the first electrode and form a second lateral hole.

[0096] Step S160: Form a semiconductor channel in the second lateral hole to cover the exposed first electrode.

[0097] Step S170: Form a bit line in the channel hole, the bit line is disposed perpendicular to the substrate and away from the capacitor.

[0098] Step S180: Remove the sacrificial layer, and sequentially form a gate dielectric layer and word lines surrounding the first electrode and semiconductor channel in the area where the sacrificial layer is removed.

[0099] Figures 2-27 This example illustrates schematic diagrams of various stages of a method for fabricating a semiconductor device according to some embodiments of this example. The following is in conjunction with... Figures 2-27 A method for fabricating a semiconductor device according to this exemplary embodiment will be described.

[0100] In step S110, refer to Figure 2 As shown, substrate 10 can be a semiconductor substrate, and the material of the semiconductor substrate can include silicon (Si), silicon germanium (SiGe), silicon germanium carbon (SiGeC), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), indium phosphide (InP), or other III / V or II / VI semiconductor materials. Alternatively, for example, the semiconductor substrate can be a layered substrate including materials such as Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon germanium-on-insulator.

[0101] The substrate 10 is doped with conductive ions, and the substrate 10 can be of P-type or N-type conductivity.

[0102] Continue to refer to Figure 2The insulating layer 21 and the sacrificial layer 22 can be deposited alternately using any of the following deposition processes: chemical vapor deposition (CVD), atomic layer deposition (ALD), or sputtering. The number of stacked layers of the insulating layer 21 and the sacrificial layer 22 can be set according to the number of layers of the semiconductor device. The bottom layer and the top layer of the stack formed on the substrate 10 are both insulating layers 21.

[0103] The insulating layer 21 has a high etch ratio relative to the sacrificial layer 22; for example, the material of the insulating layer 21 includes silicon oxide, and the material of the sacrificial layer 22 includes silicon nitride.

[0104] In step S120, firstly, refer to Figure 3 As shown, the insulating layer 21 and the sacrificial layer 22 are etched layer by layer in a direction perpendicular to the substrate 10. The etching ends in the bottom insulating layer 21, forming a capacitor hole 130 extending in a direction perpendicular to the substrate 10. The capacitor hole 130 penetrates the entire sacrificial layer 22 and the insulating layer 21 located between adjacent sacrificial layers 22. The hole wall of the capacitor hole 130 exposes part of the sacrificial layer 22 and part of the insulating layer 21.

[0105] For example, the capacitor hole 130 can be formed by etching using a dry process.

[0106] Then, refer to Figure 4 As shown, the sacrificial layer 22 exposed by the capacitor hole 130 is etched laterally using a wet process. For example, an etching solution can be injected into the capacitor hole 130, and part of the sacrificial layer 22 can be removed by etching laterally with the etching solution, forming a first lateral hole 131 extending in the lateral direction on the sidewall of the capacitor hole 130.

[0107] For example, the etching solution can be a phosphoric acid solution.

[0108] In step S130, refer to Figure 4 , Figure 9 , Figure 25 As shown, a first electrode 41 is formed in each first transverse hole 131. The first electrode 41 covers the hole wall of the first transverse hole 131, that is, it covers the sacrificial layer 22 exposed by the first transverse hole 131 and the insulating layer 21 exposed by the first transverse hole 131. The first electrode 41 is formed in a ring shape on the substrate 10. Along the direction perpendicular to the substrate 10, the first electrodes 41 are spaced apart, and adjacent first electrodes 41 are isolated by the insulating layer 21.

[0109] For example, the material of the first electrode 41 can be selected from metals such as cobalt (Co), titanium (Ti), tantalum (Ta), titanium nitride (TiN), and tantalum titanide (TaTi). In this embodiment, the material of the first electrode 41 includes titanium nitride.

[0110] In this embodiment, the first electrode is formed in the first transverse hole, which can be achieved through the following implementation:

[0111] Step S131: Form a first electrode material layer to cover the walls of the capacitor hole and the first lateral hole.

[0112] Reference Figure 5 As shown, a first electrode material layer 41a can be deposited in the capacitor hole 130 using chemical vapor deposition or atomic layer deposition. The first electrode material layer 41a covers the sacrificial layer 22 and insulating layer 21 exposed by the capacitor hole 130 and the first lateral hole 131.

[0113] Step S132: Form a first dielectric layer to cover the first electrode material layer and fill the area where the first lateral hole was not filled.

[0114] Reference Figure 6 As shown, a first dielectric layer 171 can be deposited in the capacitor hole 130 using chemical vapor deposition or atomic layer deposition. The first dielectric layer 171 covers the first electrode material layer 41a and fills the unfilled area of ​​the first transverse hole 131 to protect the first electrode material layer 41a in the first transverse hole 131.

[0115] The first dielectric layer 171 has a high etching ratio relative to the first electrode material layer 41a and the insulating layer 21; for example, the material of the first dielectric layer 171 may include at least one of silicon oxide, silicon nitride or silicon carbide.

[0116] It is understandable that the materials of the first dielectric layer 171 and the insulating layer 21 can both be silicon oxide, and a high etching ratio of the first dielectric layer 171 and the insulating layer 21 can be achieved by controlling the process conditions of the deposition process.

[0117] Step S133: Etch away the first dielectric layer and the first electrode material layer in the capacitor hole layer by layer, and form the first electrode in the first lateral hole layer.

[0118] First, refer to Figure 6 , Figure 7 As shown, the first dielectric layer 171 of the insulating layer 21 covering the capacitor hole 130 can be removed by dry or wet etching, exposing the first dielectric layer 171 in the capacitor hole 130, while retaining the first dielectric layer 171 in the first lateral hole 131.

[0119] Then, refer to Figure 7, Figure 8 As shown, a wet etching process is used to remove the first electrode material layer 41a exposed by the first dielectric layer 171, exposing the insulating layer 21 of the hole wall of the capacitor hole 130. The first electrode material layer 41a in each of the first lateral holes 131 is etched and retained to form a first electrode 41 that is disconnected along the direction perpendicular to the substrate 10.

[0120] The etching solution for etching the first electrode material layer 41a of the hole wall of the capacitor hole 130 has a high etching selectivity for the first dielectric layer 171 and the insulating layer 21, which avoids etching damage to the first dielectric layer 171 in the first lateral hole 131 and affecting the structure of the first electrode 41. At the same time, it avoids etching damage to the insulating layer 21 and destroying the structure and morphology of the capacitor hole 130, thus avoiding affecting the structure and electrical performance of the final semiconductor device.

[0121] Step S134: Etch away the first dielectric layer in the first lateral hole to expose the first electrode.

[0122] Reference Figure 8 , Figure 9 As shown, the first dielectric layer 171 in the first transverse hole 131 can be removed by wet etching process, and the etching solution has a high etching selectivity for the first electrode 41 and the insulating layer 21.

[0123] In step S140, refer to Figure 10 As shown, a dielectric layer 42 can be deposited using an atomic layer deposition process. The dielectric layer 42 covers the insulating layer 21 of the first electrode 41 and the hole wall of the capacitor hole 130.

[0124] For example, the material of dielectric layer 42 may include at least one of strontium titanate (SrTiO3), aluminum oxide (Al2O3), zirconium oxide (ZrO) or hafnium oxide (HfO2).

[0125] Then, continue to refer to Figure 10 The second electrode 43 can be deposited using chemical vapor deposition or atomic layer deposition. The second electrode 43 covers the dielectric layer 42. The first electrode 41, the dielectric layer 42, and the second electrode 43 together form a capacitor 40. The capacitors 40 are spaced apart along a direction perpendicular to the substrate 10.

[0126] For example, the material of the second electrode 43 can be selected from metal materials such as cobalt, titanium, tantalum, titanium nitride, and tantalum titanide.

[0127] In some embodiments, after the second electrode is formed, the following steps are also performed:

[0128] Step S100: A common electrode post is formed in the capacitor hole, the common electrode post is connected to the second electrode, and the common electrode post extends into the substrate and is connected to the substrate.

[0129] Reference Figure 13 As shown, a common electrode post 46 is vertically disposed on and connected to the substrate 10. The second electrode 43 of the capacitor 40, which is arranged in a direction perpendicular to the substrate 10, is connected to the common electrode post 46 and connected to the substrate 10 through the common electrode post 46.

[0130] For example, forming a common electrode post 46 in the capacitor hole 130 can be achieved using the following implementation:

[0131] Step S101: Form a contact layer that covers the second electrode and forms an initial contact hole in the capacitor hole.

[0132] like Figure 10 , Figure 11 As shown, the contact layer 44a can be deposited using atomic layer deposition or chemical vapor deposition. The contact layer 44a covers the inner wall of the second electrode 43 and fills part of the capacitor hole 130. Part of the contact layer 44a also covers the top surface of the structure. The contact layer 44a forms an initial contact hole 190a in the capacitor hole 130.

[0133] For example, the material of contact layer 44a includes germanium silicon.

[0134] Step S102: Etch to deepen the initial contact hole to form a contact hole that extends into the substrate, exposing part of the substrate.

[0135] First, such as Figure 11 , Figure 12 As shown, a dry process is used to etch back the contact layer 44a, removing the contact layer 44a on the top surface of the structure and the contact layer 44a at the bottom of the initial contact hole 190a, exposing the second electrode 43 located on the bottom wall of the capacitor hole 130.

[0136] Then, a dry etching process can be used to remove the second electrode 43 and dielectric layer 42 exposed by the initial contact hole 190a layer by layer, and after exposing part of the substrate 10, the exposed substrate 10 can be further etched to deepen the trench depth and form the contact hole 190 extending into the substrate 10.

[0137] Among them, such as Figure 12 , Figure 13 As shown, the etched contact layer 44a is formed as a contact portion 44. The contact portion 44 is disposed between the second electrode 43 and the subsequently formed common electrode post 46, which helps to reduce the contact resistance between the second electrode 43 and the common electrode post 46, helps to increase the discharge speed of the capacitor 40, improves the refresh efficiency of the semiconductor device, shortens the refresh consumption time of the semiconductor device, and improves the storage performance of the semiconductor device.

[0138] Step S103: A common electrode post is formed in the contact hole. The common electrode post covers the contact layer and is connected to the second electrode through the contact layer. The common electrode post also covers the exposed substrate and is connected to the substrate.

[0139] like Figure 13 As shown, conductive material can be deposited to fill the contact hole 190 using atomic layer deposition or chemical vapor deposition processes, forming a common electrode post 46 in the contact hole 190.

[0140] In some implementations, such as Figure 13 As shown, a common electrode post 46 is formed in the contact hole 190. First, a first diffusion barrier layer 45 is deposited to cover the substrate 10 exposed by the contact hole 190 and the contact portion 44. Then, a conductive material is deposited to cover the first diffusion barrier layer 45 and fill the contact hole 190 to form the common electrode post 46. The first diffusion barrier layer 45 prevents the material of the common electrode post 46 from diffusing to other devices or film layers, avoiding contamination of other devices or film layers. This helps reduce the risk of short circuits between devices and improves the safety and stability of semiconductor devices.

[0141] For example, the material of the first diffusion barrier layer 45 includes titanium nitride; the material of the common electrode post 46 includes tungsten.

[0142] It should be noted that, in some embodiments, silicon nitride can be used to form the common electrode post 46, which is directly connected to the contact portion 44 and the substrate 10, thus saving the step of forming the first diffusion barrier layer 45. Subsequent steps will be described based on this example.

[0143] In step S150, as Figure 14 As shown, taking a first direction D1 parallel to the substrate 10 as an example, a channel hole 230 is formed on one side of the capacitor hole 130 along the first direction D1. The insulating layer 21 and the sacrificial layer 22 are etched layer by layer along the direction perpendicular to the substrate 10, and the etching ends in the bottom insulating layer 21, forming a channel hole 230 extending along the direction perpendicular to the substrate 10.

[0144] Reference Figure 15 As shown and combined Figure 25 The sacrificial layer 22 exposed by the channel hole 230 is etched laterally using a wet process until part of the first electrode 41 is exposed, and the sidewall of the channel hole 230 forms a second lateral hole 231 extending in the lateral direction.

[0145] In this embodiment, the second transverse hole 231 is externally tangent to the first transverse hole 131.

[0146] In other embodiments, after the second lateral aperture 231 exposes a portion of the first electrode 41 in the first lateral aperture 131, the sacrificial layer 22 can be etched to increase the size of the second lateral aperture 231 so that the second lateral aperture 231 exposes more of the first electrode 41, thereby increasing the contact area between the semiconductor channel 50 subsequently formed in the second lateral aperture 231 and the first electrode 41.

[0147] For example, the sacrificial layer 22 can be etched laterally using a phosphoric acid solution.

[0148] In step S160, firstly, refer to Figure 16 As shown, a semiconductor layer 51 is formed, covering the walls of the channel via 230 and the second lateral via 231. For example, the semiconductor layer 51 can be formed using an atomic layer deposition process.

[0149] Then, refer to Figure 17 As shown, a second dielectric layer 271 is formed, covering the semiconductor layer 51 and filling the unfilled area of ​​the second lateral via 231. The second dielectric layer 271 has a high etch selectivity relative to the semiconductor layer 51 and the insulating layer 21. For example, the material of the second dielectric layer 271 may include at least one of silicon oxide, silicon nitride, or silicon carbide.

[0150] Next, refer to Figure 18 As shown, the second dielectric layer 271 and the semiconductor layer 51 in the channel via 230 are removed by etching layer by layer. The second dielectric layer 271 in the second lateral via 231 protects the semiconductor layer 51 in the second lateral via 231 from being etched and damaged. The semiconductor layer 51 in the second lateral via 231 forms a semiconductor channel 50. The semiconductor channels 50 are arranged at intervals along a direction perpendicular to the substrate 10. Each semiconductor channel 50 is connected to the first electrode 41 of each capacitor 40 in a one-to-one correspondence.

[0151] Next, refer to Figure 19 As shown, etching removes the second dielectric layer 271 in the second lateral hole 231 to expose the semiconductor channel 50.

[0152] For example, the material of the semiconductor channel 50 may include indium gallium zinc oxide (IGZO). For instance, at least one of the following: zinc tin oxide (ZTO), indium zinc oxide (IZO), indium tin oxide (ITO), indium tungsten oxide (IWO), zinc oxide (ZnOx), indium oxide (InOx, In2O3), tin oxide (SnO2), titanium oxide (TiOx), indium zinc oxide (InSnOx), zinc oxynitride (ZnxOyNz), zinc magnesium oxide (MgxZnyOz), indium zinc oxide (InxZnyOz), indium gallium zinc oxide (InxGayZnzOa), zirconium indium zinc oxide, hafnium indium zinc oxide, tin indium zinc oxide, aluminum tin indium zinc oxide, silicon indium zinc oxide, zinc tin oxide, aluminum zinc tin oxide, gallium zinc tin oxide, zirconium zinc tin oxide, and indium gallium silicon oxide.

[0153] In step S170, in some embodiments, after etching away the second dielectric layer in the second lateral aperture, the following steps are performed:

[0154] Step S171: Form a third dielectric layer to fill the unfilled areas of the channel holes and the second transverse holes.

[0155] Reference Figure 20 As shown, the third dielectric layer 371 can be deposited using atomic layer deposition or chemical vapor deposition processes. The third dielectric layer 371 covers the semiconductor layer 51 in the second lateral hole 231 and fills the unfilled areas in the second lateral hole 231 and the channel hole 230.

[0156] For example, the material of the third dielectric layer 371 includes silicon oxide.

[0157] Step S172: Etch away part of the third dielectric layer and part of the semiconductor layer to form a bit line hole. The projection of the bit line hole on the substrate is tangent to the second lateral hole.

[0158] Reference Figure 21 As shown, in conjunction with reference Figure 25 A mask layer with a bit line hole 330 pattern is formed on the top surface of the structure. The insulating layer 21, the third dielectric layer 371 and the semiconductor layer 51 exposed by the mask layer are etched layer by layer. The etching ends in the bottom insulating layer 21, forming a bit line hole 330 extending in a direction perpendicular to the substrate 10. The bit line hole 330 is formed inside the second lateral hole 231 away from the capacitor 40. The bit line hole 330 is an internal hole of the second lateral hole 231.

[0159] In this embodiment, the semiconductor layer 51 that is etched and retained after the bit line via 330 is formed forms a semiconductor channel 50. The bit line via 330 exposes a portion of the inner wall surface of a row of semiconductor channels 50 arranged perpendicular to the substrate 10.

[0160] Step S173: Form a bit line in the bit line hole, and connect the bit line to the semiconductor channel.

[0161] Reference Figure 22 As shown, a second diffusion barrier layer 61 can be deposited first to cover the hole wall of the bit line hole 330, and then a bit line 60 can be deposited to cover the second diffusion barrier layer 61 and fill the unfilled area of ​​the bit line hole 330.

[0162] In this embodiment, the bit line 60 is tangent to the semiconductor channel 50, covers a portion of the inner wall of the semiconductor channel 50, and is connected to the semiconductor channel 50 through the second diffusion barrier layer 61. Thus, the second diffusion barrier layer 61 is disposed between the bit line 60 and other film layers and devices, preventing material in the bit line 60 from diffusing into other film layers and devices, avoiding contamination of other devices or film layers, reducing the risk of short circuits between devices, and improving the safety and stability of the semiconductor device.

[0163] For example, the second diffusion barrier layer 61 can be formed by atomic layer deposition or chemical vapor deposition; the material of the second diffusion barrier layer 61 may include silicon nitride.

[0164] A conductive metal material can be used to fill the bit line hole 330 to form a bit line 60, which may be formed by atomic layer deposition, chemical vapor deposition or physical vapor deposition (PVD) process. The material of the bit line 60 may include tungsten.

[0165] In step S180, refer to Figure 23 As shown, a wet etching process is used to remove all of the sacrificial layer 22. In the area where the sacrificial layer 22 is removed, a word line groove 430 extending parallel to the substrate 10 is formed. All outer walls of the first electrode 41 and the semiconductor channel 50, except for the area where the first electrode 41 and the semiconductor channel 50 are connected, are exposed in the word line groove 430.

[0166] For example, sacrificial layer 22 can be removed by dissolving it with a phosphoric acid solution.

[0167] Then, refer to Figure 24 As shown, a gate dielectric layer 71 and a word line 70 are sequentially formed in the word line groove 430. The gate dielectric layer 71 covers the exposed first electrode 41 and the semiconductor channel 50, and the word line 70 covers the gate dielectric layer 71 and extends parallel to the substrate 10.

[0168] The gate dielectric layer 71 can be deposited using an atomic layer deposition process. The material of the gate dielectric layer 71 may include at least one of alumina (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2), strontium titanium oxide (SrTiO3), hafnium silicate (HfSiO), zirconium silicate (ZrSiO), and strontium silicate (SrSiO).

[0169] The word line 70 can be formed by atomic layer deposition or chemical vapor deposition, and the material of the word line 70 may include tungsten.

[0170] The semiconductor device fabrication method of this exemplary embodiment utilizes a three-dimensional stacked architecture of memory cells formed in a third dimension perpendicular to the substrate, which improves the integration density of memory cells, expands the storage density of semiconductor devices, improves the space utilization of semiconductor devices, and is conducive to the continuation of Moore's Law.

[0171] The semiconductor device fabrication method of this embodiment applies the mature non-volatile memory process to the fabrication of volatile memory, ensuring the fabrication feasibility of the semiconductor device; and by optimizing the process flow, forming capacitors first and then transistors, the thermal budget required for capacitor fabrication is saved, which can greatly improve the performance of transistors and further enhance the performance of the semiconductor device.

[0172] In some embodiments, this embodiment does not constitute a limitation on the above embodiments, but is merely a further description of the above embodiments. In this embodiment, reference is made to... Figure 3 Combination Figure 25 As shown, a plurality of capacitor holes 130 are formed at intervals along a first direction D1 parallel to the substrate 10.

[0173] Reference Figure 14 Combination Figure 25 As shown, along the first direction D1, multiple channel holes 230 are formed, each corresponding to one of the multiple capacitor holes 130. Each channel hole 230 is formed between two adjacent capacitor holes 130, with the channel hole 230 closer to its corresponding capacitor hole 130 and farther away from the capacitor hole 130 on the other side. In other words, multiple sets of capacitor hole 130-channel hole 230 groups are arranged in a one-to-one correspondence with the capacitor holes 130 and the channel holes 230. These multiple sets of capacitor hole 130-channel hole 230 groups are spaced apart along the first direction D1. The distance between capacitor holes 130 and channel holes 230 in different groups is greater than the distance between capacitor holes 130 and channel holes 230 in the same group, so as to ensure that the memory cells 100 formed by the capacitor hole 130-channel hole 230 groups in different groups are electrically isolated, and to avoid short circuits in the memory cells 100 formed by the capacitor hole 130-channel hole 230 groups in different groups.

[0174] Reference Figure 15 Combination Figure 25 As shown, after the second lateral hole 231 is formed by etching based on the channel hole 230, the second lateral hole 231 exposes the corresponding first lateral hole 131. The second lateral hole 231 is separated from the first lateral hole 131 on the other side by the sacrificial layer 22.

[0175] Reference Figure 24 Combination Figure 25 As shown, the word line 70 extends along the first direction D1 and intersects with multiple sets of capacitors 40 and semiconductor channels 50. That is, multiple memory cells 100 arranged along the first direction D1 are connected to each word line 70.

[0176] The semiconductor device fabrication method of this embodiment makes full use of the space utilization of the semiconductor device. The memory cells are stacked in three dimensions along the direction parallel to the substrate and the direction perpendicular to the substrate, which further increases the stacking density of the memory cells and improves the storage capacity of the semiconductor device.

[0177] It is understood that the above embodiments of this disclosure are illustrated using DRAM as an example, but the embodiments of this disclosure are not limited thereto. The semiconductor device in the embodiments of this disclosure can also be other types of volatile memory, such as static random-access memory (SRAM), ferroelectric random-access memory (FRAM), magnetic random-access memory (MRAM), etc.

[0178] According to an exemplary embodiment, this embodiment provides a semiconductor device, referring to... Figure 24 , Figure 25 , Figure 26 , Figure 27As shown, the semiconductor device includes a substrate 10, at least one column of memory cells 1, at least one bit line 60, and at least one word line 70. The at least one column of memory cells 1 includes a plurality of memory cells 100 spaced apart along a direction perpendicular to the substrate 10. Each memory cell 100 includes a connected transistor MCT and a capacitor 40. The transistor MCT includes a semiconductor channel 50 projected as a ring on the substrate 10, and the capacitor 40 includes a first electrode 41 projected as a ring on the substrate 10. The semiconductor channel 50 and the first electrode 41 are in contact connection. At least one bit line 60 is along a plane perpendicular to the substrate 10. The bit line 60 is away from the capacitor 40 and in contact connection with the column of semiconductor channels 50. At least one word line 70 is spaced apart along a direction perpendicular to the substrate 10. The word line 70 extends along a direction parallel to the substrate 10. The word line 70 covers the memory cells 100 in its extension direction and covers the area outside the area where the first electrode 41 and the semiconductor channel 50 are connected.

[0179] In this embodiment, the memory cells 100 are arranged along a third dimension perpendicular to the substrate 10, which increases the integration density of the memory cells 100, expands the storage density of the semiconductor device, improves the space utilization of the semiconductor device, and is conducive to the continuation of Moore's Law.

[0180] In this embodiment, the semiconductor device, through the design of the structure of the memory cell 100, has the semiconductor channel 50 of the transistor MCT externally tangent to the first electrode 41 of the capacitor 40, and the bit line 60 internally tangent to the semiconductor channel 50 away from the capacitor 40. This saves the area occupied by the bit line 60 alone, further reduces the area occupied by the memory cell 100, and improves the integration density of the memory cell 100.

[0181] In some embodiments, the semiconductor channel 50 is tangent to the first electrode 41; each bit line 60 is tangent to the semiconductor channel 50 of a column of memory cells 1.

[0182] In some embodiments, refer to Figure 24 , Figure 25 , Figure 26 , Figure 27 As shown, each transistor MCT also includes a gate G, a first source / drain S / D1 and a second source / drain S / D2. The gate G is connected to the word line 70, the first source / drain S / D1 is connected to the first electrode 41, and the second source / drain S / D2 is connected to the bit line 60.

[0183] In this configuration, one of the first source / drain S / D1 and the second source / drain S / D2 is the source, and the other is the drain. That is, one of the source and drain of the transistor MCT is connected to the bit line 60 and connected to the voltage of the bit line 60, while the other of the source and drain of the transistor MCT is connected to the first electrode 41 of the capacitor 40.

[0184] In some embodiments, refer to Figure 24 , Figure 25 , Figure 26 , Figure 27 As shown, along a plane perpendicular to the substrate 10, the capacitor 40 also includes a dielectric layer 42 and a second electrode 43 that sequentially cover the inner wall of the first electrode 41.

[0185] In some embodiments, refer to Figure 24 , Figure 25 , Figure 26 , Figure 27 As shown, the capacitor 40 also includes a common electrode post 46, which is vertically disposed on the substrate 10. The common electrode post 46 is disposed on the inner side of the second electrode 43 away from the first electrode 41 and is connected to the second electrode 43. The common electrode post 46 extends into the substrate 10 and is connected to the substrate 10. In this way, when the capacitor 40 discharges, the substrate 10 is grounded. The capacitor 40 is grounded through the common electrode post 46, which helps to improve the discharge speed of the capacitor 10, save the refresh time of the memory cell 100, improve the refresh efficiency of the memory cell body 100, and improve the storage performance of the semiconductor device.

[0186] In some embodiments, refer to Figure 24 , Figure 25 , Figure 26 , Figure 27 As shown, the semiconductor device also includes a contact portion 44, which is disposed between the second electrode 43 and the common electrode post 46. The contact portion 44 surrounds the inner wall of the second electrode 43, and the common electrode post 46 is connected to the second electrode 43 through the contact portion 44. The contact portion 44 helps to reduce the contact resistance between the second electrode 43 and the common electrode post 46, thereby improving the electrical performance of the semiconductor device.

[0187] In some embodiments, refer to Figure 24 , Figure 25 , Figure 26 , Figure 27 As shown, the semiconductor device also includes an insulating layer 21, which is spaced apart along a direction perpendicular to the substrate 10. The insulating layer 21 and word lines 70 are arranged alternately, and the memory cells 100 in the same column of memory cells 1 are separated by the insulating layer 21.

[0188] In some embodiments, an insulating layer 21 is provided between the memory cell column 1 and the substrate 10, the memory cell column 1 is separated from the substrate 10 by the insulating layer 21, the bit line 60 is disposed on the insulating layer 21 and is isolated from the substrate 10 by the insulating layer 21, and the common electrode post 46 passes through the insulating layer 21 and is connected to the substrate 10.

[0189] In this embodiment, "phase isolation" refers to both physical separation and electrical insulation.

[0190] In some embodiments, refer to Figure 24 , Figure 25 , Figure 26 , Figure 27 As shown, the semiconductor device also includes a third dielectric layer 371, which fills the space between the semiconductor channel 50 and the bit line 60.

[0191] In some embodiments, such as Figure 26 As shown, the semiconductor channel 50 includes a vertical portion 50-1, a first horizontal portion 50-2, and a second horizontal portion 50-3. The vertical portion 50-1 extends continuously in a plane parallel to the substrate 10, and is in contact with the bit line 60 and the first electrode 41. The first horizontal portion 50-2 is disposed outside the contact area between the vertical portion 50-1 and the bit line 60, and is connected to the top of the vertical portion 50-1. The first horizontal portion 50-2 extends away from the word line 70 along a plane perpendicular to the substrate 10. The second horizontal portion 50-3 is disposed outside the contact area between the vertical portion 50-1 and the bit line 60, and is connected to the bottom of the vertical portion 50-1. The second horizontal portion 50-3 extends away from the word line 70 along a plane perpendicular to the substrate 10.

[0192] The structure of the vertical part 50-1, the first horizontal part 50-2, and the second horizontal part 50-3 increases the structural robustness and stability of the semiconductor channel 50, avoids damage to the semiconductor channel 50 during the process of forming the bit line 60 tangent to it, and ensures the structural integrity and high yield of the semiconductor device.

[0193] The projection of the semiconductor channel 50 onto the substrate 10 is annular, and the word line 70 surrounds the outer peripheral surface of the vertical portion 50-1, which increases the contact area between the word line 70 and the semiconductor channel 50, improves the gate control capability of the transistor MCT, and helps to reduce the power consumption of the semiconductor device 1 and improve the signal strength of the semiconductor device 1.

[0194] In some embodiments, such as Figure 24 , Figure 25 , Figure 26 , Figure 27 As shown, at least one column of memory cells 1 is arranged at intervals along a first direction D1 parallel to the substrate 10, word lines 70 extend along the first direction D1, each word line 70 intersects with a plurality of memory cells 100 arranged along the first direction D1, and each word line is connected to the gate G of a plurality of transistors MCT arranged along the first direction D1.

[0195] In some embodiments, such as Figure 27As shown, at least one column of memory cells 1 is spaced apart and arranged in multiple rows along a first direction D1 parallel to the substrate 10. Multiple rows of memory cells 1 are spaced apart along a second direction D2 parallel to the substrate 10. The first direction D1 is perpendicular to the second direction D2. Word lines 70 extend along the first direction D1 and are spaced apart along the second direction D2. Each word line 70 intersects with one or more rows of memory cells 100. Each word line 70 covers and controls one or more rows of memory cells 100 arranged along its extension direction.

[0196] Each word line 70 may intersect with three rows of storage cells 1 arranged along the first direction D1, and each word line 70 controls the storage cells 100 of the three rows of storage cells 1; or, each word line 70 may intersect with four, five or more rows of storage cells 1.

[0197] In this embodiment, each word line 70 intersects with one or more rows of memory cell columns 100, which increases the number of memory cells 100 controlled by the word line 70. This can increase the integration density of the memory cell column 1 intersecting with the same word line 70, which is beneficial for further miniaturization of the semiconductor device.

[0198] For example, such as Figure 28 As shown, the semiconductor device includes a multi-column memory cell column 1, which is arranged in six rows along a first direction D1. The semiconductor device includes a first word line 170 and a second word line 270 extending along the first direction D1 and spaced apart along a second direction D2. The first word line 170 and the second word line 270 each intersect with three rows of memory cells 100. That is, the first word line 170 and the second word line 270 control the three rows of memory cells 100 respectively.

[0199] In some embodiments, such as Figure 27 , Figure 28 As shown, the bit lines 60 of at least one column of memory cells 1 are arranged in multiple rows along a third direction D3 parallel to the substrate 10, and the third direction D3 intersects the first direction D1 and the second direction D2 at an angle.

[0200] like Figure 28 As shown, the semiconductor device also includes at least one bit line lead wire 80, which extends along the second direction D2 on the memory cell column 1, and each memory cell column 1 is connected by a bit line 60 and a bit line lead wire 80.

[0201] This configuration makes the structure layout of the semiconductor device more reasonable, facilitates the wiring of bit line lead-out wires 80 on the semiconductor device, reduces the difficulty and complexity of wiring, and enables the memory cell column 1 that intersects with the same word line 70 to be connected one-to-one with at least one bit line lead-out wire 80, so that a bit line lead-out wire 80 and a word line 70 can accurately select the unique corresponding memory cell 100.

[0202] In some embodiments, refer to Figure 27 As shown, the projections of at least one column of memory cell 1's transistors (MCTs) and capacitors (40s) onto the substrate 10 are arranged in a hexagonal pattern. In this way, the memory cells 100 of the semiconductor device achieve the densest possible stacking, maximizing the integration density of the semiconductor device and maximizing its space utilization.

[0203] Furthermore, such as Figure 28 As shown, the transistors (MCTs) and capacitors (40) of the memory cell column 1 intersecting the same word line 70 in the semiconductor device are arranged in a hexagonal pattern on the substrate 10, with the distance between word lines 70 increasing along the second direction D2. This improves the storage density of the semiconductor device while ensuring isolation between word lines 70, preventing short circuits between adjacent word lines 70.

[0204] According to an exemplary embodiment, this embodiment provides an electronic device, including the semiconductor device described in the above embodiments. The electronic device may be a mobile phone, computer, tablet computer, television, artificial intelligence device, etc.

[0205] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0206] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: A substrate is provided on which insulating layers and sacrificial layers are alternately formed; A capacitor hole is formed that penetrates the entire sacrificial layer vertically, and the sacrificial layer is etched laterally based on the capacitor hole to form a first lateral hole; A first electrode is formed in the first transverse hole; A dielectric layer and a second electrode are formed in the capacitor hole, sequentially covering the first electrode, so as to form a capacitor together with the first electrode; A corresponding channel hole is formed on one side of the capacitor hole, and the sacrificial layer is laterally etched based on the channel hole to expose part of the first electrode, forming a second lateral hole; A semiconductor channel is formed in the second lateral hole, covering the exposed first electrode; Bit lines are formed in the channel holes, the bit lines are disposed perpendicular to the substrate, and the bit lines are away from the capacitor; The sacrificial layer is removed, and a gate dielectric layer and a word line are sequentially formed around the first electrode and the semiconductor channel in the area where the sacrificial layer is removed.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that, Forming a first electrode in the first transverse hole includes: A first electrode material layer is formed to cover the walls of the capacitor hole and the first lateral hole; A first dielectric layer is formed to cover the first electrode material layer and fill the area where the first lateral hole is not filled. The first dielectric layer and the first electrode material layer in the capacitor hole are removed by etching layer by layer, and the first electrode is formed in the first electrode material layer in the first lateral hole; The first dielectric layer in the first lateral hole is etched away to expose the first electrode.

3. The method for fabricating a semiconductor device according to claim 1, characterized in that, After forming the dielectric layer that sequentially covers the first electrode and the second electrode, the process further includes: A common electrode post is formed in the capacitor hole, the common electrode post is connected to the second electrode, and the common electrode post extends into the substrate and is connected to the substrate.

4. The method for fabricating a semiconductor device according to claim 3, characterized in that, Forming a common electrode post in the capacitor hole includes: A contact layer is formed, which covers the second electrode and forms an initial contact hole in the capacitor hole; The initial contact hole is etched to deepen its depth, forming a contact hole that extends into the substrate and exposes a portion of the substrate. The common electrode post is formed in the contact hole, the common electrode post covers the contact layer and is in contact with the second electrode through the contact layer, and the common electrode post also covers the exposed substrate to be connected to the substrate.

5. The method for fabricating a semiconductor device according to claim 1, characterized in that, The manufacturing method includes: A semiconductor layer is formed to cover the walls of the channel hole and the second lateral hole; A second dielectric layer is formed to cover the semiconductor layer and fill the area where the second lateral hole is not filled. The second dielectric layer and the semiconductor layer in the channel hole are removed by etching layer by layer; The second dielectric layer in the second lateral hole is removed by etching.

6. The method for fabricating a semiconductor device according to claim 5, characterized in that, After etching away the second dielectric layer in the second lateral hole, the process further includes: A third dielectric layer is formed to fill the unfilled areas of the channel holes and the second transverse holes; Etching removes a portion of the third dielectric layer and a portion of the semiconductor layer to form a bit line hole, the projection of the bit line hole on the substrate being inscribed within the second lateral hole; The bit line is formed in the bit line hole, and the bit line is connected to the semiconductor channel.

7. The method for manufacturing a semiconductor device according to any one of claims 1-6, characterized in that, A plurality of capacitor holes are formed at intervals along a first direction parallel to the substrate; Along the first direction, a plurality of channel holes are formed corresponding one-to-one with the plurality of capacitor holes. Each channel hole is formed between two adjacent capacitor holes, and the channel hole is close to the capacitor hole corresponding to it and away from the capacitor hole on the other side. After the second lateral hole is formed by etching based on the channel hole, the second lateral hole exposes the corresponding first lateral hole, and the second lateral hole is separated from the first lateral hole on the other side by the sacrificial layer; The word line extends along the first direction and intersects with multiple sets of capacitors and semiconductor channels.

8. A semiconductor device, characterized in that, include: Substrate; At least one column of memory cells includes a plurality of memory cells spaced apart along a direction perpendicular to the substrate, each memory cell including a connected transistor and a capacitor, the transistor including a semiconductor channel projected as an annular shape on the substrate, the capacitor including a first electrode projected as an annular shape on the substrate, the semiconductor channel and the first electrode being in contact connection; At least one bit line, along a plane perpendicular to the substrate, the bit line being away from the capacitor and in contact with a row of semiconductor channels; At least one word line is spaced apart in a direction perpendicular to the substrate, the word line extends in a direction parallel to the substrate, the word line surrounds the memory cell in its extension direction, and the word line surrounds the area outside the region where the first electrode and the semiconductor channel are connected.

9. The semiconductor device according to claim 8, characterized in that, Each of the transistors further includes a gate, a first source / drain, and a second source / drain, the gate being connected to the word line, the first source / drain being connected to the first electrode, and the second source / drain being connected to the bit line.

10. The semiconductor device according to claim 8, characterized in that, Along a plane perpendicular to the substrate, the capacitor further includes a dielectric layer and a second electrode that sequentially surround the inner wall of the first electrode.

11. The semiconductor device according to claim 10, characterized in that, The capacitor also includes: A common electrode post is vertically disposed on the substrate. The common electrode post is disposed on the inner side of the second electrode away from the first electrode and is connected to the second electrode. The common electrode post extends into the substrate and is connected to the substrate.

12. The semiconductor device according to claim 11, characterized in that, The semiconductor device further includes: A contact portion is disposed between the second electrode and the common electrode post, the contact portion surrounds the second electrode, and the common electrode post is connected to the second electrode through the contact portion.

13. The semiconductor device according to claim 8, characterized in that, At least one column of the memory cells is spaced apart and arranged in multiple rows along a first direction parallel to the substrate. The multiple rows of the memory cells are spaced apart along a second direction parallel to the substrate. The first direction is perpendicular to the second direction. The word lines extend along the first direction and are spaced apart along the second direction. Each word line intersects with one or more rows of the memory cells.

14. The semiconductor device according to claim 13, characterized in that, The bit lines of at least one column of the memory cells are arranged in multiple rows along a third direction parallel to the substrate, and the third direction intersects the first direction and the second direction at an angle.

15. The semiconductor device according to claim 14, characterized in that, Also includes: At least one bit line lead wire extends along the second direction on the column of memory cells, and each column of memory cells is connected by the bit line and the bit line lead wire.

16. The semiconductor device according to claim 13, characterized in that, The transistors and capacitors of at least one column of the memory cells are arranged in a hexagonal pattern on the substrate.

17. An electronic device, characterized in that, Includes the semiconductor device as described in any one of claims 8-16.

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