Three-dimensional memory array and preparation method thereof, memory and electronic equipment

Abstract

The embodiment of the invention provides a three-dimensional memory array and a preparation method thereof, a memory and electronic equipment, the three-dimensional memory comprises a substrate, a plurality of memory layers, isolation layers and a plurality of bit lines, the memory layers and the isolation layers are alternately stacked in the direction perpendicular to the substrate, each memory layer comprises a plurality of memory units and a plurality of word lines, and the bit lines are arranged in the memory units. The plurality of memory cells are arranged in an array, the plurality of word lines extend along the row direction and are arranged at intervals, and each word line is electrically connected with one row of memory cells; the plurality of bit lines extend in the thickness direction of the substrate and are arranged at intervals, the bit lines are perpendicular to the substrate and penetrate through the storage layers and the isolation layers, and one bit line is electrically connected with a plurality of storage units arranged in the direction perpendicular to the substrate on the plurality of storage layers. According to the three-dimensional storage array, the vertical bit lines and the horizontal word lines are adopted, so that the capacitance of the bit lines is reduced, and the sensing amplifier SA can read data more easily.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a three-dimensional memory array and its fabrication method, as well as a memory and electronic device. Background Technology

[0002] Memory, such as dynamic random access memory (DRAM), is widely used in electronic devices requiring low-cost, high-capacity memory, such as computers, graphics cards, portable devices, and game consoles. With the increasing integration density and miniaturization of DRAM manufacturing processes, the negative impacts of shrinking DRAM gate transistors and capacitors are becoming increasingly significant. For example, transistor leakage is severe, and manufacturing high aspect ratio capacitors is becoming increasingly difficult and costly. Therefore, the miniaturization of planar DRAM has reached its limit, and three-dimensional (3D) DRAM has become the focus of various manufacturers.

[0003] However, existing 3D DRAMs typically use vertical word lines and horizontal bit lines, resulting in larger capacitance of the bit lines. Summary of the Invention

[0004] This application provides a three-dimensional memory array and its fabrication method, a memory, and an electronic device. The three-dimensional memory uses vertical bit lines and horizontal word lines to reduce the capacitance of the bit lines.

[0005] In a first aspect, embodiments of this application provide a three-dimensional storage array, including:

[0006] Substrate;

[0007] Multiple memory layers are disposed on the substrate and stacked along a direction perpendicular to the substrate. Each memory layer includes multiple memory cells and multiple word lines. The multiple memory cells are arranged in an array, and the multiple word lines extend along the row direction and are spaced apart. Each word line is electrically connected to a row of memory cells.

[0008] An isolation layer is disposed between two adjacent storage layers;

[0009] In addition, there are multiple bit lines that extend along the thickness direction of the substrate and are spaced apart. The bit lines are perpendicular to the substrate and penetrate the memory layer and the isolation layer. One bit line is electrically connected to multiple memory cells arranged on the multiple memory layers along a direction perpendicular to the substrate.

[0010] The aforementioned three-dimensional memory array uses vertical bit lines and horizontal word lines to reduce the capacitance of the bit lines, making it easier for the sense amplifier (SA) to read data.

[0011] In one possible implementation, the orthographic projections of the multiple bit lines and the multiple word lines in the thickness direction of the substrate do not overlap, thus reducing the risk of short circuits between bit lines and word lines compared to overlapping word lines and bit lines.

[0012] In one possible implementation, each memory cell includes a transistor; the transistor includes a patterned semiconductor layer, a gate dielectric layer, and a gate contact layer stacked sequentially along a column direction, the semiconductor layer including a source region and a drain region disposed on a surface opposite to the gate dielectric layer. Transistors with this structure exhibit more stable performance and higher yield because the channel material is not affected by subsequent processes during fabrication.

[0013] In one possible implementation, the three-dimensional memory array further includes a plurality of first insulators extending along the row direction and spaced apart, the first insulators penetrating the plurality of memory layers and the isolation layer between the plurality of memory layers, and a plurality of stacked structures are respectively disposed on both sides of each first insulator, the stacked structure including the word line, the gate contact layer, the gate dielectric layer and the semiconductor layer sequentially formed on the side of the first insulator.

[0014] This three-dimensional memory array isolates two rows of transistors, or two rows of memory cells, through a first insulator, resulting in higher integration. Furthermore, transistors and word lines in multiple memory layers can be fabricated together, leading to higher fabrication efficiency.

[0015] In one possible implementation, the first insulator includes a plurality of first portions extending toward the memory layer along the column direction, the plurality of first portions being spaced apart, and the word line, the gate contact layer, the gate dielectric layer and the semiconductor layer in the stacked structure sequentially wrapping the first portions.

[0016] In one possible implementation, in each of the memory layers, the gate dielectric layer along the row direction is connected and / or the gate contact layer along the row direction is connected, which reduces the number of process steps. The semiconductor layers along the row direction are not connected, so that the individual memory cells along the row direction are independent.

[0017] In one possible implementation, within the same storage layer, the two rows of storage cells disposed on both sides of the first insulator are arranged in a mirror-symmetrical manner.

[0018] In one possible implementation, within the same storage layer, the two word lines located on either side of the first insulator are arranged in a mirror-symmetrical configuration.

[0019] In one possible implementation, the semiconductor layer, the gate dielectric layer, and the gate contact layer all have semi-annular cross-sections along the thickness direction perpendicular to the storage layer.

[0020] In one possible implementation, each of the memory cells further includes a capacitor, the capacitor comprising: a first conductive layer, a second conductive layer, and a dielectric layer disposed between the first conductive layer and the second conductive layer;

[0021] Wherein, the first conductive layer is electrically connected to the source region of the transistor, and the drain region of the transistor is electrically connected to the corresponding bit line; or, the first conductive layer is electrically connected to the drain region of the body transistor, and the source region of the transistor is electrically connected to the corresponding bit line.

[0022] In one possible implementation, the three-dimensional memory array further includes a plurality of metal bodies extending along the thickness direction of the substrate and spaced apart, the metal bodies penetrating the plurality of memory layers and the isolation layer between the plurality of memory layers, wherein the second conductive layer, the dielectric layer and the first conductive layer of each capacitor sequentially surround the metal body.

[0023] In one possible implementation, the metal body includes a plurality of second portions extending toward the storage layer, the plurality of second portions being spaced apart, and the second conductive layer, the dielectric layer, and the first conductive layer sequentially surrounding the second portions. The capacitor, by extending, increases its surface area and thus its capacitance.

[0024] In one possible implementation, the dielectric layers of two adjacent storage layers are connected along the thickness direction of the substrate and / or the second conductive layers are connected along the thickness direction of the substrate.

[0025] In one possible implementation, the first conductive layer, the second conductive layer, and the dielectric layer of each capacitor are annular in cross-section along a direction perpendicular to the thickness of the storage layer.

[0026] In one possible implementation, the three-dimensional storage array further includes at least one second insulator that penetrates the plurality of storage layers and the isolation layer between the plurality of storage layers, wherein the second conductive layer, the dielectric layer, and the first conductive layer of each capacitor sequentially surround at least one second insulator. The capacitor, by also having the first conductive layer, the dielectric layer, and the second conductive layer disposed on the second insulator, increases the surface area of ​​the capacitor and improves its capacitance.

[0027] In one possible implementation, the first conductive layer, the second conductive layer, and the dielectric layer of each capacitor are arranged in a plurality of rings along a cross section perpendicular to the thickness direction of the storage layer, the plurality of rings including a first ring surrounding the metal body and a second ring disposed within the first ring and surrounding the second insulator.

[0028] Secondly, embodiments of this application also provide a memory, including a three-dimensional storage array and a controller as described in the first aspect or any possible implementation of the first aspect, wherein the controller is electrically connected to the three-dimensional storage array and is used to control the reading and writing of the three-dimensional storage array.

[0029] Thirdly, embodiments of this application also provide an electronic device, including a memory and a circuit board as described in the second aspect or any possible implementation of the second aspect, wherein the memory is disposed on the circuit board.

[0030] Fourthly, embodiments of this application also provide an electronic device, including a processor and a memory as described in the second aspect or any possible implementation of the second aspect, wherein the processor is electrically connected to the memory, the memory is used to store data, and the processor is used to process the data stored in the memory.

[0031] Fifthly, embodiments of this application also provide a method for fabricating a three-dimensional storage array, comprising:

[0032] Provide a substrate;

[0033] Multiple memory layers and multiple isolation layers are formed on the substrate, and the multiple memory layers and multiple isolation layers are stacked alternately along a direction perpendicular to the substrate; each memory layer includes multiple memory cells and multiple word lines, the multiple memory cells are arranged in an array, the multiple word lines extend along the row direction and are spaced apart, and each word line is electrically connected to a row of memory cells;

[0034] Multiple bit lines are formed on the substrate, the multiple bit lines extend along the thickness direction of the substrate and are spaced apart, the bit lines are perpendicular to the substrate and penetrate the memory layer and the isolation layer, and one bit line is electrically connected to multiple memory cells arranged on the multiple memory layers along the direction perpendicular to the substrate.

[0035] The three-dimensional memory array prepared by the above method uses vertical bit lines and horizontal word lines to reduce the capacitance of the bit lines, making it easier for the sensing amplifier SA to read data.

[0036] In one possible implementation, a plurality of storage layers and a plurality of isolation layers are formed on the substrate, including:

[0037] A plurality of first insulating layers and a plurality of second insulating layers are formed on the substrate, and the first insulating layers and the second insulating layers are stacked alternately along a direction perpendicular to the substrate;

[0038] A plurality of first holes are formed that penetrate the multilayer first insulating layer and the second insulating layer between the multilayer first insulating layers;

[0039] The first insulating layer is laterally etched along the column direction within the first hole to form a plurality of first grooves, the plurality of first grooves being spaced apart and communicating with the first hole;

[0040] A semiconductor layer, a gate dielectric layer, and a gate contact layer are sequentially formed on the inner wall of the first groove;

[0041] A first metal layer is formed on the surface of the gate contact layer and on the inner wall of the first hole;

[0042] The first metal layer is etched to form the word lines;

[0043] A first insulator is formed to fill the first hole and the first groove.

[0044] In one possible implementation, a plurality of storage layers and a plurality of isolation layers are formed on the substrate, and the method further includes:

[0045] A plurality of second holes are formed that penetrate the multilayer first insulating layer and the second insulating layer between the multilayer first insulating layers;

[0046] The first insulating layer is etched laterally into each second hole to form a plurality of second grooves, the plurality of second grooves being spaced apart along the thickness direction of the substrate, and the second grooves communicating with the second holes;

[0047] A first conductive layer, a dielectric layer, and a second conductive layer are sequentially formed on the inner wall of the second groove;

[0048] A metal body is formed to fill the second hole and the second groove.

[0049] In one possible implementation, a plurality of storage layers and a plurality of isolation layers are formed on the substrate, and the method further includes:

[0050] Multiple third holes are formed that penetrate the multilayer first insulating layer and the second insulating layer between the multilayer first insulating layers;

[0051] The first insulating layer is etched laterally into the third hole to form a plurality of third grooves. The plurality of third grooves are spaced apart along the thickness direction of the substrate, and the third grooves are connected to the third hole.

[0052] A first sacrificial layer is formed to fill the second hole and the second groove;

[0053] A plurality of fourth holes are formed that penetrate the multilayer first insulating layer and the second insulating layer between the multilayer first insulating layers;

[0054] The first insulating layer is etched laterally into the fourth hole to form a plurality of fourth grooves. The plurality of fourth grooves are spaced apart and communicate with the third hole to expose the first sacrificial layer.

[0055] A second insulator is formed to fill the third hole, so that the fourth groove forms a closed container;

[0056] Remove the first sacrificial layer to make the third groove communicate with the container;

[0057] Through the third hole, a third conductive layer, a second dielectric layer, and a fourth conductive layer are sequentially formed on the inner wall of the third groove and the inner wall of the container.

[0058] A metal body is formed to fill the third hole, the container, and the third groove.

[0059] In one possible implementation, forming multiple bit lines on the substrate includes:

[0060] A plurality of fifth holes are formed that penetrate the multilayer first insulating layer and the second insulating layer between the multilayer first insulating layers;

[0061] The first insulating layer is etched laterally into the fifth hole to form a plurality of fifth grooves. The plurality of fifth grooves are spaced apart along the thickness direction of the substrate. The fifth grooves are connected to the fourth hole. The fifth grooves are connected to the semiconductor layer.

[0062] The first electrode is formed by doping the semiconductor layer;

[0063] The bit line is formed by filling the fifth hole and the fifth groove with a conductive material. Attached Figure Description

[0064] Figure 1 This is an equivalent circuit diagram of a three-dimensional storage array provided in an embodiment of this application.

[0065] Figure 2A This is a schematic diagram of the three-dimensional structure of a storage array provided in an embodiment of this application.

[0066] Figure 2B This is provided by the embodiments of this application. Figure 2A The top view of the three-dimensional storage array shown.

[0067] Figure 2C This is provided by the embodiments of this application. Figure 2A The diagram shows a cross-section of the three-dimensional storage array at line A1-A2.

[0068] Figure 2D This is provided by the embodiments of this application. Figure 2A The diagram shows a cross-section of the three-dimensional storage array at line B1-B2.

[0069] Figure 3A This is a schematic diagram of another three-dimensional storage array structure provided in the embodiments of this application.

[0070] Figure 3B This is provided by the embodiments of this application. Figure 3A The top view of the three-dimensional storage array shown.

[0071] Figure 3C This is provided by the embodiments of this application. Figure 3A The diagram shows a cross-section of the three-dimensional storage array at line C1-C2.

[0072] Figure 3D This is provided by the embodiments of this application. Figure 3A The diagram shows a cross-section of the three-dimensional storage array at line D1-D2.

[0073] Figure 4 This is a schematic diagram of the structure of a memory provided in an embodiment of this application.

[0074] Figure 5 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application.

[0075] Figure 6 This is a schematic diagram of the structure of another electronic device provided in an embodiment of this application.

[0076] Figure 7A This is a top view of a structure involved in the fabrication method of the three-dimensional storage array provided in this application embodiment.

[0077] Figure 7B This is provided by the embodiments of this application. Figure 7A The diagram shows a cross-section of the structure at line A1-A2.

[0078] Figure 8A This is a top view of a structure involved in the fabrication method of the three-dimensional storage array provided in this application embodiment.

[0079] Figure 8B This is provided by the embodiments of this application. Figure 8A The diagram shows a cross-section of the structure at line A1-A2.

[0080] Figure 9A This is a top view of a structure involved in the fabrication method of the three-dimensional storage array provided in this application embodiment.

[0081] Figure 9B This is provided by the embodiments of this application. Figure 9AThe diagram shows a cross-section of the structure at line A1-A2.

[0082] Figure 10A This is a top view of a structure involved in the fabrication method of the three-dimensional storage array provided in this application embodiment.

[0083] Figure 10B This is provided by the embodiments of this application. Figure 10A The diagram shows a cross-section of the structure at line B1-B2.

[0084] Figure 11A This is a top view of a structure involved in the fabrication method of the three-dimensional storage array provided in this application embodiment.

[0085] Figure 11B This is provided by the embodiments of this application. Figure 11A The diagram shows a cross-section of the structure at line B1-B2.

[0086] Figure 12A This is a top view of a structure involved in the fabrication method of the three-dimensional storage array provided in this application embodiment.

[0087] Figure 12B This is provided by the embodiments of this application. Figure 12A The diagram shows a cross-section of the structure at line A1-A2.

[0088] Figure 13A The embodiments provided in this application are as follows Figure 3A The diagram shows a top view of a structure involved in the fabrication method of the capacitors in the three-dimensional storage array.

[0089] Figure 13B This is provided by the embodiments of this application. Figure 13A The diagram shows a cross-section of the structure at line D1-D2.

[0090] Figure 14A The embodiments provided in this application are as follows Figure 3A The diagram shows a top view of a structure involved in the fabrication method of the capacitors in the three-dimensional storage array.

[0091] Figure 14B This is provided by the embodiments of this application. Figure 13A The diagram shows a cross-section of the structure at line D1-D2.

[0092] Figure 15A The embodiments provided in this application are as follows Figure 3A The diagram shows a top view of a structure involved in the fabrication method of the capacitors in the three-dimensional storage array.

[0093] Figure 15B This is provided by the embodiments of this application. Figure 13AThe diagram shows a cross-section of the structure at line D1-D2.

[0094] Figure 16A The embodiments provided in this application are as follows Figure 3A The diagram shows a top view of a structure involved in the fabrication method of the capacitors in the three-dimensional storage array.

[0095] Figure 16B This is provided by the embodiments of this application. Figure 13A The diagram shows a cross-section of the structure at line D1-D2.

[0096] Figure 17A The embodiments provided in this application are as follows Figure 3A The diagram shows a top view of a structure involved in the fabrication method of the capacitors in the three-dimensional storage array.

[0097] Figure 17B This is provided by the embodiments of this application. Figure 13A The diagram shows a cross-section of the structure at line D1-D2. Detailed Implementation

[0098] It should be noted that in the following description of this application, "multiple" can be understood as "at least two". "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. "One or more of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, one or more of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0099] Furthermore, unless otherwise specified, the ordinal numbers such as "first" and "second" mentioned in the embodiments of this application are used only for the purpose of distinguishing descriptions and should not be construed as indicating or implying relative importance or order. For example, the "first conductive layer" and "second conductive layer" mentioned below are only used to indicate storage film layers at different locations and do not have any difference in order, priority or importance.

[0100] The following describes the three-dimensional storage array provided in the embodiments of this application.

[0101] This application provides a three-dimensional storage array for use in a memory, which may be DRAM. The three-dimensional storage array adopts a vertical word line and horizontal bit line architecture to reduce the capacitance of the bit lines, thereby reducing the interference of bit line capacitance on the reading of data in the memory cell and improving the accuracy of data reading.

[0102] like Figure 1 The diagram shown is an equivalent circuit diagram of a three-dimensional storage array provided in an embodiment of this application.

[0103] See Figure 1 A three-dimensional memory array may include Q memory layers arranged along the thickness direction of the substrate (i.e., the z-direction, which is also the thickness direction of the memory layers). Each memory layer may include multiple memory cells MU arranged in an array and multiple word lines WL extending along the row direction (i.e., the y-direction) and spaced apart. For example, each memory layer includes M rows and N columns of memory cells MU. Q, M, and N are all positive integers greater than 1. It should be understood that the column direction of the memory array is the x-direction.

[0104] Each memory cell MU may include a transistor 10 and a capacitor 20. The control terminal (e.g., gate) of transistor 10 is electrically connected to a word line WL, the first terminal (e.g., source) of transistor 10 is electrically connected to a word line BL, and the second terminal (e.g., drain) of transistor 10 is electrically connected to the first terminal of capacitor 20. The second terminal of capacitor 20 may be grounded. Transistor 10 may be a thin-film transistor (TFT) or a metal-oxide-semiconductor field-effect transistor (MOS), etc., used to select its corresponding memory cell MU. Capacitor 20 is used to store charge to store data. This embodiment uses a memory cell MU consisting of one transistor and one capacitor (also called a single-transistor single-capacitor 1T1C) as an example. It should be understood that in other embodiments, the memory cell MU may include more transistors 10 and / or more capacitors, such as a dual-transistor single-capacitor (2T1C) structure. It should also be understood that the first and second terminals of transistor 10 may be the drain and source of the transistor, respectively, without limitation.

[0105] Specifically, the i-th word line WL on the k-th storage layer k,i The control terminal of the transistor in the i-th row of the k-th memory layer is electrically connected. k is the index of the memory layer, used to distinguish different memory layers, and k is a positive integer not greater than Q; i is the row index, and i is a positive integer not greater than M.

[0106] The three-dimensional memory array also includes M*N bit lines BL extending along the z-direction and spaced apart. Each bit line BL is electrically connected to a transistor 10 in a memory cell MU arranged along the z-direction. Exemplarily, the bit lines BL...i,j The memory cell MU in the i-th row and j-th column of each memory layer is electrically connected. Specifically, the first terminal of transistor 10 in memory cell MU is connected.

[0107] It should be noted that the M*N bit lines BL can be parallel to each other. The word lines WL in the Q memory layers can also be parallel to each other.

[0108] as follows Figure 2A An exemplary schematic diagram of a three-dimensional storage array structure is shown. Figure 2B yes Figure 2A The top view of the three-dimensional storage array shown. Figure 2C yes Figure 2A The diagram shown is a structural schematic of the cross-section of the storage array at line A1-A2. Figure 2D yes Figure 2A The diagram shows a cross-sectional view of the storage array at point B1-B2. Figures 2A-2D The equivalent circuit diagram of the three-dimensional memory array shown can be as described above. Figure 1 As shown.

[0109] like Figures 2A-2D As shown. This three-dimensional memory array may include: a substrate 1, multiple memory layers 2 disposed on the substrate 1, isolation layers 3 disposed between each pair of adjacent memory layers 2, and multiple bit lines 5. K is a positive integer greater than 1.

[0110] The multiple memory layers 2 are stacked along a direction perpendicular to the substrate 1 (i.e., the thickness direction of the substrate 1), and each memory layer 2 includes multiple memory cells and multiple word lines 4. The memory cells in each memory layer 2 are arranged in an array, and the multiple word lines 4 extend along the row direction (i.e., the y-direction) and are spaced apart. Each word line 4 is electrically connected to a row of memory cells.

[0111] For example, as described above Figure 1 The three-dimensional storage array includes Q storage layers 2. The storage cells within each storage layer 2 are arranged in an array, exemplarily comprising M rows and N columns of storage cells. Each storage layer 2 also includes M word lines 4. The M word lines 4 extend along the row direction, are parallel to each other, and are spaced apart along the column direction (i.e., the y-direction). Each of the M word lines 4 corresponds one-to-one with one of the M rows of storage cells, and each word line 4 is electrically connected to its corresponding row of storage cells.

[0112] Isolation layer 3 is used to isolate storage cells in two adjacent storage layers.

[0113] Multiple bit lines 5, such as M*N bit lines 5, extend along the thickness direction of the substrate 1 and are spaced apart. Each bit line 5 is perpendicular to the substrate and passes through the memory layer 2 and the isolation layer 3 disposed on the substrate 1. One bit line 5 is electrically connected to multiple memory cells arranged on each memory layer 2 along the direction perpendicular to the substrate 1.

[0114] In some embodiments, each memory cell may include a transistor 10 and a capacitor 20, forming a single-transistor-single-capacitor (1T1C) structure. The transistor 10 and capacitor 20 can be electrically connected via a conductive electrode layer 6 or directly.

[0115] The transistor 10 may include a patterned semiconductor layer 11, a gate dielectric layer 12, and a gate contact layer 13, sequentially stacked along the thickness direction of the storage layer 2. The semiconductor layer 11 may include a channel and source and drain regions disposed on opposite sides of the channel. The source and drain regions are disposed on the surface of the semiconductor layer 11 away from the gate dielectric layer 12 and can be formed by heavy doping in a semiconductor material. The gate dielectric layer 12 may be an oxide, such as silicon dioxide, silicon nitride, hafnium dioxide, hafnium oxynitride, or other materials with high dielectric constants. The gate contact layer 13 may be a conductive material such as titanium nitride, tungsten nitride, tantalum nitride, niobium oxide, titanium, or tantalum.

[0116] For example, such as Figure 2C and Figure 2D As shown, the three-dimensional memory array also includes a plurality of first insulators 7 extending along the row direction and spaced apart, such as M / 2 first insulators 7 (where M is an even number). Each first insulator 7 penetrates the Q memory layers 2 and the isolation layer 3 between the Q memory layers 2. A plurality of stacked structures are respectively arranged on both sides of each first insulator 7. The stacked structure includes word lines 4, gate contact layers 13, gate dielectric layers 12 and semiconductor layers 11 formed sequentially on the side of the first insulator 7.

[0117] like Figure 2C and Figure 2D As shown, each first insulator 7 includes a plurality of first portions extending toward the storage layer 2 along the column direction. The plurality of first portions are spaced apart and the stacked structure wraps around the first portion. That is, the word line 4, the gate contact layer 13 of the transistor 10, the gate dielectric layer 12 and the semiconductor layer 11 in the stacked structure sequentially wrap the first portion.

[0118] In each memory layer, the gate dielectric layer 12 along the row direction is connected and / or the gate contact layer 13 along the row direction is connected. That is, the gate dielectric layer 12 along the row direction is connected and / or the gate contact layer 13 along the row direction is connected. The semiconductor layer 11 along the row direction is not connected.

[0119] It is understood that the first insulator 7 and the word lines 4 and transistors 10 arranged around the first insulator 7 can be formed by depositing material in the holes, and the word lines 4 and transistors 10 in multiple storage layers can be fabricated together to improve fabrication efficiency.

[0120] In some embodiments, within the same storage layer 2, two rows of storage cells disposed on both sides of the first insulator 7 are arranged in a mirror-symmetrical manner. For example, for each storage layer 2, two storage cells (including transistors 10 and capacitors 20) disposed on both sides of each first insulator 7 are arranged in a mirror-symmetrical manner with the first insulator 7 as the center.

[0121] In some embodiments, within the same storage layer 2, the two word lines 4 disposed on both sides of the first insulator 7 are arranged in a mirror-symmetrical manner. For example, for each storage layer 2, the two word lines 4 disposed on both sides of each first insulator 7 are mirror-symmetrical about the first insulator 7.

[0122] In some embodiments, for each transistor 10, the cross-section of the semiconductor layer 11, the gate dielectric layer 12, and the gate contact layer 13 along the direction perpendicular to the thickness of the storage layer 2 is semi-annular. The semi-annular shape can be half a circular ring, half a rectangular ring, or half a rounded rectangular ring, such as... Figure 2B As shown, it can also be an irregular shape; no limitation is made here.

[0123] The aforementioned three-dimensional memory array can fully utilize the two-dimensional planar space near the bit lines, increasing the number of bit lines (BL) within that planar space. Furthermore, it can increase the stair spacing of word lines (WL), reduce the number of stair spacings in the word lines (WL), free up three-dimensional space on the WL side, and reduce the difficulty of process development.

[0124] Bit line 5 is disposed on the side of the semiconductor layer 11 of transistor 10 away from the gate dielectric layer 12, and is electrically connected to the first terminal (source or drain) of transistor 10. The source is also known as the source region, and the drain is also known as the drain region.

[0125] In some embodiments, the orthogonal projections of the M*N bit lines and the word lines 4 in each memory layer 2 onto the thickness direction of the substrate do not overlap.

[0126] Each capacitor 20 includes: a first conductive layer 21, a second conductive layer 23, and a dielectric layer 22 disposed between the first conductive layer 21 and the second conductive layer 23. The first conductive layer 21 is electrically connected to the first terminal (source) of the transistor 10 in the memory cell containing the capacitor 20, and the second terminal (drain) of the transistor 10 is electrically connected to the corresponding bit line 5; or, the first conductive layer 21 is electrically connected to the second terminal (drain) of the transistor 10 in the memory cell containing the capacitor 20, and the first terminal (source) of the transistor 10 is electrically connected to the corresponding bit line 5.

[0127] Optionally, the three-dimensional memory array may further include a plurality of metal bodies 8 extending along the thickness direction of the substrate and spaced apart, such as M*N metal bodies 8. Each metal body 8 penetrates Q memory layers and the isolation layer 3 between the Q memory layers. The second conductive layer 23, dielectric layer 22, and first conductive layer 21 of each capacitor 20 sequentially surround the metal body 8. The metal body 8 is used for grounding.

[0128] In some embodiments, each metal body 8 may include a plurality of second portions extending toward the storage layer, such as Q portions, the Q portions being spaced apart, each capacitor 20 being disposed around the second portion, that is, the second conductive layer 23, the dielectric layer 22 and the first conductive layer 21 sequentially surround / wrap the second portion to obtain a capacitor 20 with a high aspect ratio, increasing the surface area of ​​the capacitor 20 to improve its charge storage capacity.

[0129] In two adjacent storage layers 2, the dielectric layer 22 along the thickness direction of the substrate 1 is connected and / or the second conductive layer 23 along the thickness direction of the substrate 1 is connected, while the first conductive layer 21 along the thickness direction of the substrate 1 is not connected.

[0130] like Figure 2B As shown, the first conductive layer 21, the second conductive layer 23, and the dielectric layer 22 of each capacitor 20 are annular in cross-section along the thickness direction perpendicular to the storage layer 2 (i.e., the thickness direction of the substrate 1). The annular shape can be circular, rectangular, or rounded rectangular, such as... Figure 2B As shown, it can also be an irregular shape; no limitation is made here.

[0131] Unlike Figure 2B The embodiment of this application also provides another type of capacitor, such as the capacitor 20 of the annular interface shown. Figures 3A-3D The diagram shown is a structural schematic of another three-dimensional storage array provided in this application embodiment. This three-dimensional storage array adopts a different approach than that described above. Figures 2A-2D The capacitors of the three-dimensional storage array shown can be the same as those described above. Figures 2A-2D The three-dimensional storage array shown is the same, so it will not be described again here.

[0132] as follows Figure 3A An exemplary schematic diagram of a three-dimensional storage array structure is shown. Figure 3B yes Figure 3A The top view of the three-dimensional storage array shown. Figure 3C yes Figure 3A The diagram shows a cross-sectional view of the storage array at point C1-C2. Figure 3D yes Figure 3A The diagram shows a cross-sectional view of the storage array at point D1-D2. Figures 3A-3D The equivalent circuit diagram of the three-dimensional memory array shown can be as described above. Figure 1 As shown.

[0133] like Figures 3A-3D As shown, in addition to the aforementioned substrate 1, storage layer 2, isolation layer 3, bit line 5, first insulator 7, and metal body 8, the three-dimensional storage array may also include at least one second insulator 9, such as 2*M*N. Each second insulator 9 is disposed at the location of the capacitor 20. For example, the capacitor 20 in the i-th row and j-th column storage cell of the Q storage layers corresponds to the same two second insulators 9. Each second insulator 9 penetrates the Q storage layers 2 and the isolation layer 3 between the Q storage layers 2. The second conductive layer 23, dielectric layer 22, and first conductive layer 21 of each capacitor 20 also sequentially surround at least one second insulator 9 to further increase the surface area of ​​the capacitor 20 and increase the capacity of the capacitor 20 to store charge.

[0134] Figure 3B As shown, the first conductive layer 21, the second conductive layer 23, and the dielectric layer 22 of each capacitor 20 are arranged in multiple rings along a cross-section perpendicular to the thickness direction of the storage layer 2. These multiple rings include a first ring surrounding a metal body and a second ring disposed within the first ring and surrounding a second insulator.

[0135] The bit lines, word lines, electrode layer 6, first conductive layer 21 or second conductive layer 23 mentioned above can be metals, alloys or conductive metal compounds, such as gold, silver, palladium, titanium, ruthenium, titanium nitride, tungsten nitride, etc.

[0136] It should be understood that the structure of the above-mentioned three-dimensional storage array can also refer to the following three-dimensional storage array fabrication method.

[0137] This application also provides a method including the above-described embodiments. Figures 3A-3D The three-dimensional storage array of capacitor 20 shown is different from the above. Figures 3A-3D The three-dimensional memory array shown has word lines 4WL that can extend along the thickness direction of substrate 1 and are spaced apart, and bit lines BL that can extend along the row direction and are spaced apart.

[0138] like Figure 4 The diagram shown is a structural schematic of a memory according to an embodiment of this application. The memory 40 may include a three-dimensional storage array 41 and a controller 42. The controller 42 is electrically connected to the three-dimensional storage array 41 and is used to control the reading and writing of the three-dimensional storage array 41. The three-dimensional storage array 41 may be any of the three-dimensional storage arrays described in the above possible embodiments.

[0139] like Figure 5 The diagram shown is a structural schematic of an electronic device 50 provided in an embodiment of this application. The electronic device 50 may include, for example: Figure 4The memory 40 and circuit board 51 are shown, with the memory 40 disposed on the circuit board 51.

[0140] like Figure 6 As shown, an electronic device 60 is provided in an embodiment of this application. The electronic device may include a processor 61 and the aforementioned... Figure 4 The memory 40 shown is electrically connected to the processor 61. The memory 40 is used to store data, and the processor 61 is used to process the data stored in the memory 40.

[0141] Specifically, the electronic device includes, but is not limited to: smartphones, smartwatches, tablets, virtual reality (VR) devices, augmented reality (AR) devices, in-vehicle devices, desktop computers, personal computers, handheld computers, or personal digital assistants.

[0142] The following combination Figures 7A-12B This application describes a method for fabricating a three-dimensional storage array. The method may include, but is not limited to, some or all of the following steps:

[0143] S101: A substrate is provided, on which Q first insulating layers 102 and multiple layers of second insulating layers 101 are formed, and the first insulating layers 102 and the second insulating layers 101 are alternately stacked along a direction perpendicular to the substrate 1. Figure 7A The top view of the structure shown and Figure 7B The diagram shows a cross-sectional view of the structure along line A1-A2. The first insulating layer 102 is used to form the storage layer, and the second insulating layer 101 is the isolation layer 3.

[0144] It should be understood that the first insulating layer 102 and the second insulating layer 101 can also be the same insulating layer, formed together.

[0145] S102: A first hole 801 is formed on the substrate 1, penetrating Q first insulating layers 101 and Q second insulating layers 101 between the first insulating layers 102, and the first insulating layers 102 are laterally etched along the column direction to form a plurality of first grooves 802. The plurality of first grooves 802 are spaced apart and communicate with the first hole 801. Figure 8A The top view shown and Figure 8B The diagram shows a cross-sectional view of the structure along line A1-A2.

[0146] S103: A semiconductor layer 11, a gate dielectric layer 12, and a gate contact layer 13 are sequentially formed on the inner wall of the first groove 802.

[0147] S104: A first metal layer is formed on the surface of the gate contact layer 13 and the inner wall of the first hole 801;

[0148] S105: Etch the first metal layer to form the word line 4;

[0149] S106: Form a first insulator 7 that fills the first hole 801 and the first groove 802. After S103-S106, the following is obtained: Figure 9A The top view of the structure shown and Figure 9B The diagram shows a cross-sectional view of the structure along line A1-A2.

[0150] S107: Forming a plurality of fourth holes 1001 that penetrate the multilayer first insulating layer 102 and the second insulating layer 101 between the multilayer first insulating layer 102.

[0151] S108: The first insulating layer 102 is etched laterally into the fourth hole 1001 towards the first insulating layer to form a plurality of fifth grooves 1002. These fifth grooves 1002 are spaced apart along the thickness direction of the substrate 1, and each fifth groove 1002 communicates with the fourth hole 1001; the fifth grooves 1002 expose the semiconductor layer 11. After S108, the following is obtained: Figure 10A The top view of the structure shown and Figure 10B The diagram shows a cross-sectional view of the structure along line B1-B2.

[0152] S109: The semiconductor layer 11 is doped to form a first electrode, which may be a source or a drain.

[0153] S110: The bit line 5 is formed by filling the fourth hole 1001 and the fifth groove 1002 with conductive material. After S110, the following is obtained: Figure 11A The top view of the structure shown and Figure 11B The diagram shows a cross-sectional view of the structure along line B1-B2.

[0154] S111: Forming a plurality of second holes 1201 that penetrate the multilayer first insulating layer 102 and the second insulating layer 101 between the multilayer first insulating layer 102.

[0155] S112: The first insulating layer 102 is etched laterally into each of the second holes 1201 to form a plurality of second grooves 1202. The plurality of second grooves 1202 are spaced apart along the thickness direction of the substrate 1, and the second grooves 1202 communicate with the second holes 1201. At this time, the following is obtained: Figure 12A The top view of the structure shown and Figure 12B The diagram shows a cross-sectional view of the structure along line A1-A2.

[0156] S113: A first conductive layer 21, a dielectric layer 22, and a second conductive layer 23 are sequentially formed on the inner wall of the second groove 1202.

[0157] Optionally, an electrode layer 6, a first conductive layer 21, a dielectric layer 22, and a second conductive layer 23 may be sequentially formed on the inner wall of the second groove 1202.

[0158] S114: Form a metal body 8 that fills the second hole 1201 and the second groove 1202.

[0159] After S114, the following was obtained: Figures 2A-2D The three-dimensional storage array shown above can be found in the details above. Figures 2A-2D In addition, the various structural components in the above preparation method can also be found in the above description. Figures 2A-2D The relevant descriptions of the three-dimensional storage array shown are not repeated here.

[0160] It should be understood that the above S111-S114 describes Figures 2A-2D The method for fabricating capacitors in the three-dimensional storage array shown should be understood to also employ the methods described above. Figures 3A-3D In the structure shown, capacitor 20 is combined with the following... Figures 13A-17B This explains the above. Figures 3A-3D The method for fabricating capacitor 20 in the structure shown may include, but is not limited to, some or all of the following steps:

[0161] S201: Forming a plurality of third holes 1301 that penetrate the multilayer first insulating layer 102 and the second insulating layer 101 between the multilayer first insulating layer 102.

[0162] S202: The first insulating layer 102 is etched laterally into the third hole to form a plurality of third grooves 1302. The plurality of third grooves 1302 are spaced apart along the thickness direction of the substrate 1, and the third grooves 1302 communicate with the third hole 1301. At this time, the following is obtained: Figure 13A The structure shown and Figure 13B The diagram shows a cross-sectional view of the structure at line D1-D2.

[0163] S203: A first sacrificial layer 1401 is formed to fill the third hole 1301 and the third groove 1302. At this point, the desired result is... Figure 14A The structure shown and Figure 14B The diagram shows a cross-sectional view of the structure at line D1-D2.

[0164] S204: Forming a plurality of fourth holes 1501 that penetrate the multilayer first insulating layer 102 and the second insulating layer 101 between the multilayer first insulating layer 102.

[0165] S205: The first insulating layer 102 is etched laterally into the fourth hole 1501 to form a plurality of fourth grooves 1502. The plurality of fourth grooves 1502 are spaced apart and communicate with the fourth hole 1501, exposing the first sacrificial layer 1401. At this time, the following is obtained: Figure 15A The structure shown and Figure 15B The diagram shows a cross-sectional view of the structure at line D1-D2.

[0166] S206: Form a filling of the second insulator 9 to make the fourth groove 1502 form a closed container. At this point, the desired result is... Figure 16A The structure shown and Figure 16B The diagram shows a cross-sectional view of the structure at line D1-D2.

[0167] S207: Remove the first sacrificial layer 1401 to make the third groove 1302 communicate with the container, at which point the following is obtained: Figure 17A The structure shown and Figure 17B The diagram shows a cross-sectional view of the structure at line D1-D2.

[0168] S208: Through the third hole 1301, a first conductive layer 21, a dielectric layer 22, and a second conductive layer 23 are sequentially formed on the inner wall of the third groove 1302 and the inner wall of the container.

[0169] S209: Form a metal body 8 that fills the third hole 1301, the container, and the third groove 1302.

[0170] At this time, we get the following: Figures 3A-3D The structure shown can be found in the above description. Figures 3A-3D This will not be elaborated upon here.

[0171] In addition, the various structural components in the above preparation method can also be found in the above... Figures 3A-3D The relevant descriptions of the three-dimensional storage array shown are not repeated here.

[0172] The storage solution disclosed in this application can be applied to devices with storage functions, such as storage devices with only storage functions, like memory, or electronic devices with storage functions and other functions (such as read / write functions). The electronic device can be a portable electronic device including functions such as a personal digital assistant and / or a music player, such as a mobile phone, tablet computer, wearable device with wireless communication functions (such as a smartwatch), or in-vehicle device. Exemplary embodiments of the portable electronic device include, but are not limited to, portable electronic devices running or other operating systems. The aforementioned portable electronic device can also be a laptop computer with a touch-sensitive surface (e.g., a touch panel). It should also be understood that in some other embodiments of this application, the aforementioned electronic device can also be a desktop computer with a touch-sensitive surface (e.g., a touch panel).

[0173] For example, the memory may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. The volatile memory may be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), flash EPROM (FE), synchronous DRAM (SDRAM), double data rate synchronous DRAM (DDR SDRAM), enhanced synchronous DRAM (ESDRAM), synchronous linked DRAM (SLDRAM), and direct rambus RAM (DR RAM), as well as novel memories such as ferroelectric random access memory (FeRAM), phase change random access memory (PCRAM), magnetic random access memory (MRAM), or resistive random access memory (ReRAM). Non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. It should be noted that the memory described in this application is intended to include, but is not limited to, these and any other suitable types of memory.

[0174] Although some possible embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make further changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the embodiments of this application as well as all changes and modifications falling within the scope of this application.

[0175] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the scope of protection of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A three-dimensional storage array, characterized in that, include: Substrate; Multiple memory layers are disposed on the substrate and stacked along a direction perpendicular to the substrate. Each memory layer includes multiple memory cells and multiple word lines. The multiple memory cells are arranged in an array, and the multiple word lines extend along the row direction and are spaced apart. Each word line is electrically connected to a row of memory cells. An isolation layer is disposed between two adjacent storage layers; In addition, there are multiple bit lines that extend along the thickness direction of the substrate and are spaced apart. The bit lines are perpendicular to the substrate and penetrate the memory layer and the isolation layer. One bit line is electrically connected to multiple memory cells arranged on the multiple memory layers along a direction perpendicular to the substrate.

2. The three-dimensional storage array according to claim 1, characterized in that, The orthographic projections of the multiple bit lines and the multiple word lines in the thickness direction of the substrate do not overlap.

3. The three-dimensional storage array according to claim 1 or 2, characterized in that, Each of the memory cells includes a transistor; the transistor includes a patterned semiconductor layer, a gate dielectric layer and a gate contact layer stacked sequentially along the column direction, the semiconductor layer including a source region and a drain region disposed on a surface opposite to the gate dielectric layer.

4. The three-dimensional storage array according to claim 3, characterized in that, The three-dimensional memory array further includes a plurality of first insulators that extend along the row direction and are spaced apart. The first insulators penetrate the plurality of memory layers and the isolation layer between the plurality of memory layers. A plurality of stacked structures are respectively disposed on both sides of each first insulator. The stacked structure includes the word line, the gate contact layer, the gate dielectric layer and the semiconductor layer formed sequentially on the side of the first insulator.

5. The three-dimensional storage array according to claim 4, characterized in that, The first insulator includes a plurality of first portions extending toward the memory layer along the column direction, the plurality of first portions being spaced apart, and the word line, the gate contact layer, the gate dielectric layer and the semiconductor layer in the stacked structure sequentially wrapping the first portions.

6. The three-dimensional storage array according to claim 4 or 5, characterized in that, In each of the memory layers, the gate dielectric layer is connected along the row direction and / or the gate contact layer is connected along the row direction.

7. The three-dimensional storage array according to any one of claims 4-6, characterized in that, Within the same storage layer, the two rows of storage cells located on both sides of the first insulator are arranged in a mirror-symmetrical manner.

8. The three-dimensional storage array according to claim 1 or 2, characterized in that, Within the same storage layer, the two word lines located on both sides of the first insulator are arranged in a mirror-symmetrical manner.

9. The three-dimensional storage array according to any one of claims 3-8, characterized in that, The semiconductor layer, the gate dielectric layer, and the gate contact layer all have semi-circular cross-sections along the thickness direction perpendicular to the storage layer.

10. The three-dimensional storage array according to any one of claims 3-9, characterized in that, Each of the memory cells further includes a capacitor, the capacitor comprising: a first conductive layer, a second conductive layer, and a dielectric layer disposed between the first conductive layer and the second conductive layer; Wherein, the first conductive layer is electrically connected to the source region of the transistor, and the drain region of the transistor is electrically connected to the corresponding bit line; or, the first conductive layer is electrically connected to the drain region of the body transistor, and the source region of the transistor is electrically connected to the corresponding bit line.

11. The three-dimensional storage array according to claim 10, characterized in that, The three-dimensional storage array further includes a plurality of metal bodies extending along the thickness direction of the substrate and spaced apart. The metal bodies penetrate the plurality of storage layers and the isolation layer between the plurality of storage layers. The second conductive layer, the dielectric layer and the first conductive layer of each capacitor sequentially surround the metal body.

12. The three-dimensional storage array according to claim 11, characterized in that, The metal body includes a plurality of second portions extending toward the storage layer, the plurality of second portions being spaced apart, and the second conductive layer, the dielectric layer and the first conductive layer sequentially surrounding the second portions.

13. The three-dimensional storage array according to any one of claims 10-12, characterized in that, The dielectric layers of two adjacent storage layers are connected along the thickness direction of the substrate and / or the second conductive layers are connected along the thickness direction of the substrate.

14. The three-dimensional storage array according to any one of claims 10-13, characterized in that, The first conductive layer, the second conductive layer, and the dielectric layer of each capacitor are annular in cross-section along the thickness direction perpendicular to the storage layer.

15. The three-dimensional storage array according to any one of claims 10-13, characterized in that, The three-dimensional storage array further includes at least one second insulator that penetrates the plurality of storage layers and the isolation layer between the plurality of storage layers, and the second conductive layer, the dielectric layer and the first conductive layer of each capacitor also sequentially surround at least one second insulator.

16. The three-dimensional storage array according to claim 15, characterized in that, The first conductive layer, the second conductive layer, and the dielectric layer of each capacitor are arranged in a plurality of rings along a cross section perpendicular to the thickness direction of the storage layer. The plurality of rings include a first ring surrounding the metal body and a second ring disposed within the first ring and surrounding the second insulator.

17. A memory, characterized in that, Includes a three-dimensional storage array and a controller as described in any one of claims 1-16, wherein the controller is electrically connected to the three-dimensional storage array and is used to control the reading and writing of the three-dimensional storage array.

18. An electronic device, characterized in that, It includes the memory and circuit board as described in claim 17, wherein the memory is disposed on the circuit board.

19. An electronic device, characterized in that, It includes a processor and a memory as described in claim 17, the processor being electrically connected to the memory, the memory being used to store data, and the processor being used to process the data stored in the memory.

20. A method for fabricating a three-dimensional storage array, characterized in that, include: Provide a substrate; Multiple memory layers and multiple isolation layers are formed on the substrate, and the multiple memory layers and multiple isolation layers are stacked alternately along a direction perpendicular to the substrate; each memory layer includes multiple memory cells and multiple word lines, the multiple memory cells are arranged in an array, the multiple word lines extend along the row direction and are spaced apart, and each word line is electrically connected to a row of memory cells; Multiple bit lines are formed on the substrate, the multiple bit lines extend along the thickness direction of the substrate and are spaced apart, the bit lines are perpendicular to the substrate and penetrate the memory layer and the isolation layer, and one bit line is electrically connected to multiple memory cells arranged on the multiple memory layers along the direction perpendicular to the substrate.

21. The method according to claim 20, characterized in that, Multiple storage layers and multiple isolation layers are formed on the substrate, including: A plurality of first insulating layers and a plurality of second insulating layers are formed on the substrate, and the first insulating layers and the second insulating layers are stacked alternately along a direction perpendicular to the substrate; A plurality of first holes are formed that penetrate the multilayer first insulating layer and the second insulating layer between the multilayer first insulating layers; The first insulating layer is laterally etched along the column direction within the first hole to form a plurality of first grooves, the plurality of first grooves being spaced apart and communicating with the first hole; A semiconductor layer, a gate dielectric layer, and a gate contact layer are sequentially formed on the inner wall of the first groove; A first metal layer is formed on the surface of the gate contact layer and on the inner wall of the first hole; The first metal layer is etched to form the word lines; A first insulator is formed to fill the first hole and the first groove.

22. The method according to claim 21, characterized in that, The substrate is formed with a plurality of storage layers and a plurality of isolation layers, and further includes: A plurality of second holes are formed that penetrate the multilayer first insulating layer and the second insulating layer between the multilayer first insulating layers; The first insulating layer is etched laterally into each second hole to form a plurality of second grooves, the plurality of second grooves being spaced apart along the thickness direction of the substrate, and the second grooves communicating with the second holes; A first conductive layer, a dielectric layer, and a second conductive layer are sequentially formed on the inner wall of the second groove; A metal body is formed to fill the second hole and the second groove.

23. The method according to claim 21, characterized in that, The substrate is formed with a plurality of storage layers and a plurality of isolation layers, and further includes: A plurality of third holes are formed that penetrate the multilayer first insulating layer and the second insulating layer between the multilayer first insulating layers; The first insulating layer is etched laterally into the third hole to form a plurality of third grooves. The plurality of third grooves are spaced apart along the thickness direction of the substrate, and the third grooves are connected to the third hole. A first sacrificial layer is formed to fill the second hole and the second groove; A plurality of fourth holes are formed that penetrate the multilayer first insulating layer and the second insulating layer between the multilayer first insulating layers; The first insulating layer is etched laterally into the fourth hole to form a plurality of fourth grooves. The plurality of fourth grooves are spaced apart and communicate with the third hole to expose the first sacrificial layer. A second insulator is formed to fill the third hole, so that the fourth groove forms a closed container; Remove the first sacrificial layer to make the third groove communicate with the container; Through the third hole, a third conductive layer, a second dielectric layer, and a fourth conductive layer are sequentially formed on the inner wall of the third groove and the inner wall of the container. A metal body is formed to fill the third hole, the container, and the third groove.

24. The method according to any one of claims 21-23, characterized in that, The formation of multiple bit lines on the substrate includes: A plurality of fifth holes are formed that penetrate the multilayer first insulating layer and the second insulating layer between the multilayer first insulating layers; The first insulating layer is etched laterally into the fifth hole to form a plurality of fifth grooves. The plurality of fifth grooves are spaced apart along the thickness direction of the substrate. The fifth grooves are connected to the fifth hole. The fifth grooves expose the semiconductor layer. The semiconductor layer is doped to form a first electrode; The bit line is formed by filling the fifth hole and the fifth groove with a conductive material.

Images