MIM capacitor manufacturing method

Abstract

The invention discloses an MIM capacitor manufacturing method comprising the following steps: providing a substrate, and forming a lower pole plate layer in the substrate; depositing a dielectric layer to cover the exposed areas of the substrate and the lower polar plate layer; depositing a first upper polar plate layer to cover the dielectric layer; the first upper electrode plate layer is covered with photoresist, and the photoresist in the first target area is removed through exposure and development in sequence; etching is carried out, and a groove is formed through etching; depositing a second upper polar plate layer to cover the first upper polar plate layer and the surface of the groove; depositing an insulating dielectric layer to cover the second upper polar plate layer; and by taking the groove as an alignment mark, etching to a predetermined region in the dielectric layer through a photoetching process. According to the method, the AMARK process in the related technology is subjected to hysteresis processing, etching is carried out after deposition of the upper polar plate layer is completed, damage to the dielectric layer in the original AMARK process is avoided, the defects of the dielectric layer caused by the damage are reduced, the overall yield is improved, and meanwhile, the alignment accuracy can be guaranteed and the electrical requirement of the capacitor can be met by depositing the upper polar plate layer step by step.

Description

Technical Field

[0001] This application relates to the field of semiconductor device technology, and in particular to a method for manufacturing a MIM capacitor. Background Technology

[0002] The traditional copper (Cu) process for semiconductor products integrates metal-insulator-metal (MIM) capacitors by adding three photolithographic layers between the metal layers. These layers are used for the alignment mark (AMARK), the lower electrode (Metal Cu Bottom, MCB), and the upper electrode (Metal Cap Top, MCT). This process is relatively expensive.

[0003] In related technologies, Cu metal is used as the MCB, saving one mask, but restricting its alignment with the AMARK layer to be done only after the dielectric layer. AMARK processes (such as photolithography, plasma treatment, resist removal, and etching) can damage the critical film (MIM dielectric layer) and produce residues. The presence of these residues may lead to problems such as short circuits and degraded capacitor performance. Summary of the Invention

[0004] This application provides a method for manufacturing MIM capacitors, which can solve the problems in related technologies where the AMARK process can damage the key film and produce residues, the presence of which may lead to short circuits and degraded capacitor performance.

[0005] On one hand, embodiments of this application provide a method for manufacturing a MIM capacitor, including: A substrate is provided in which a lower electrode layer is formed, the upper surface of the lower electrode layer being exposed; The deposition medium layer covers the exposed areas of the substrate and the lower electrode layer; A first upper electrode layer is deposited to cover the dielectric layer; Photoresist is applied to the first upper electrode layer, and the photoresist in the first target area is removed by exposure and development in sequence. The first target area is located on one side of the lower electrode layer in the lateral direction. Etching is performed to a predetermined depth in the substrate of the first target region to form a groove; A second upper electrode layer is deposited to cover the first upper electrode layer and the surface of the groove; A deposited insulating dielectric layer covers the second upper electrode layer; Using the groove as an alignment mark, etching is performed through photolithography to etch into a predetermined area in the dielectric layer, removing the insulating dielectric layer, the second upper electrode layer, and the first upper electrode layer from areas other than the second target area. From a top view, the second target area is located within the lower electrode layer.

[0006] In some embodiments, the deposition medium layer covers the exposed areas of the substrate and the lower electrode layer, including: The dielectric layer was deposited using a CVD method.

[0007] In some embodiments, the thickness of the dielectric layer is 300 to 700 angstroms.

[0008] In some embodiments, the deposition of the first upper electrode layer covering the dielectric layer includes: The first upper electrode layer was deposited using the PVD method.

[0009] In some embodiments, the thickness of the first upper electrode layer is 300 to 500 angstroms.

[0010] In some embodiments, the dielectric of the first upper electrode layer comprises TiN.

[0011] In some embodiments, the thickness of the second upper electrode layer is 500 to 700 angstroms.

[0012] In some embodiments, the deposition of the insulating dielectric layer covering the second upper electrode layer includes: The insulating dielectric layer was deposited using a CVD method.

[0013] In some embodiments, the thickness of the insulating dielectric layer is 100 to 500 angstroms.

[0014] The technical solution of this application has at least the following advantages: The AMARK process in related technologies is delayed, and etching is performed after the upper electrode layer is deposited. This avoids damage to the dielectric layer caused by the original AMARK process, reduces dielectric layer defects, and improves the overall yield. At the same time, the stepwise deposition of the upper electrode layer can ensure the alignment accuracy while meeting the electrical requirements of the capacitor. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0016] Figure 1 This is a flowchart of a manufacturing method provided in an exemplary embodiment of this application; Figure 2 This is a cross-sectional view of the structure after the lower electrode layer is formed, provided in an exemplary embodiment of this application; Figure 3 This is a cross-sectional view of the structure after the formation of the dielectric layer and the first upper-level plate layer provided in an exemplary embodiment of this application; Figure 4 This is a cross-sectional view of the structure after removing the first target region, provided in an exemplary embodiment of this application; Figure 5 This is a cross-sectional view of the structure after the formation of the second upper electrode layer, provided in an exemplary embodiment of this application; Figure 6 This is a cross-sectional view of the structure after the deposition of the insulating dielectric layer provided in an exemplary embodiment of this application; Figure 7 This is a cross-sectional view of the structure after removing the second target region, provided in an exemplary embodiment of this application; Figure 8 This is a defect distribution diagram of the upper plate of a MIM capacitor manufactured using related techniques described in the background art, after etching and testing. Figure 9 The image is an electronic scan of a defect in a MIM capacitor produced using related techniques described in the background section. Figure 10 These are electron scanning images of MIM capacitors manufactured using related techniques described in the background section, representing defect energy spectrum analysis and failure analysis. Figure 11 This is a schematic diagram of the structure of a MIM capacitor provided in an exemplary embodiment of this application; Figure 12 This is a defect distribution diagram of the upper electrode plate after etching test provided in an exemplary embodiment of this application; Figure 13 This is a statistical table comparing the number of defects in different samples provided in an exemplary embodiment of this application. Figure 14 This is a statistical table of etching alignment errors in the horizontal direction when the thickness of the first upper electrode layer is 500 angstroms, provided in an exemplary embodiment of this application. Figure 15 This is a statistical table of etching alignment errors in the vertical direction when the thickness of the first upper electrode layer is 500 angstroms, provided in an exemplary embodiment of this application. Detailed Implementation

[0017] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0018] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0019] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0020] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0021] refer to Figure 1 It presents a flowchart of a manufacturing method provided in an exemplary embodiment of this application, such as... Figure 1 As shown, it includes: Step S101: A substrate is provided, in which a lower electrode layer is formed, and the upper surface of the lower electrode layer is exposed.

[0022] refer to Figure 2 It presents a cross-sectional view of the structure after the lower electrode layer is formed, as provided in an exemplary embodiment of this application, such as... Figure 2 As shown, it includes: For example, a substrate 201 is selected, in which a lower electrode layer 202 is formed, the lower electrode layer 202 may include a copper (Cu) metal layer, and the upper surface of the lower electrode layer 202 is exposed.

[0023] Step S102: The deposited medium layer covers the exposed areas of the substrate and the lower electrode layer.

[0024] Optionally, the deposited medium layer may cover the exposed areas of the substrate and lower electrode layer, including depositing the medium layer using a chemical vapor deposition (CVD) method.

[0025] The thickness of the dielectric layer can be from 300 angstroms to 700 angstroms.

[0026] refer to Figure 3 It presents a cross-sectional view of the structure after the formation of the dielectric layer and the first upper-level plate layer provided in an exemplary embodiment of this application, such as... Figure 3 As shown, it includes: For example, a dielectric layer 203 is deposited on the surface of the substrate 201 and in the exposed area of ​​the lower electrode layer 202 by a CVD method. The thickness of the deposited dielectric layer 203 is 300 angstroms, and the filling medium of the dielectric layer 203 may include silicon nitride (Si3N4).

[0027] Step S103: Deposit the first upper electrode layer to cover the dielectric layer.

[0028] Optionally, depositing the first upper electrode layer over the dielectric layer includes depositing the first upper electrode layer using a physical vapor deposition (PVD) method.

[0029] The thickness of the first upper electrode layer can be 300 to 500 angstroms, and the dielectric of the first upper electrode layer may include titanium nitride (TiN).

[0030] like Figure 3 As shown, for example, a first upper electrode layer 204 is deposited on the dielectric layer 203 using a PVD method. The thickness of the first upper electrode layer 204 is 500 angstroms, and the filling medium is TiN.

[0031] Step S104: Photoresist is applied to the first upper electrode layer, and the photoresist in the first target area is removed by exposure and development in sequence. The first target area is located on one side of the lower electrode layer in the lateral direction.

[0032] refer to Figure 4 It presents a structural cross-sectional view of the structure after removing the first target region, as provided in an exemplary embodiment of this application, such as... Figure 4 As shown, it includes: For example, photoresist is uniformly coated on the first upper electrode layer 204. After completion, the photoresist in the first target area is removed by exposure and development in sequence. The first target area is the etching removal area. In the lateral direction, the first target area is located on one side of the lower electrode layer 202.

[0033] Step S105: Etching is performed to a predetermined depth in the substrate of the first target area to form a groove.

[0034] like Figure 4 As shown, for example, etching to a predetermined depth in the first target area base removes a portion of the first upper plate layer 204, dielectric layer 203 and substrate 201, forming a groove 205 after completion.

[0035] Step S106: Deposit a second upper electrode layer to cover the first upper electrode layer and the groove surface.

[0036] Optionally, the thickness of the second upper electrode layer can be from 500 angstroms to 700 angstroms.

[0037] refer to Figure 5 It presents a cross-sectional view of the structure after the formation of the second upper electrode layer according to an exemplary embodiment of this application, such as... Figure 5 As shown, it includes: For example, a second upper electrode layer 206 is deposited again using the PVD method. The thickness of the second upper electrode layer 206 can be 700 angstroms. The second upper electrode layer 206 covers the first upper electrode layer 204 and the surface of the groove 205. The filling medium of the second upper electrode layer 206 is the same as that of the first upper electrode layer 204.

[0038] Step S107: Deposit an insulating dielectric layer to cover the second upper electrode layer.

[0039] Optionally, an insulating dielectric layer can be deposited using a CVD method.

[0040] The thickness of the insulating dielectric layer can range from 100 angstroms to 500 angstroms.

[0041] refer to Figure 6 It presents a cross-sectional view of the structure after the deposition of the insulating dielectric layer according to an exemplary embodiment of this application, such as... Figure 6 As shown, it includes: For example, an insulating dielectric layer 207 is deposited using a CVD method, which covers the second upper electrode layer 206. The filling medium of the insulating dielectric layer 207 can be silicon oxynitride (SiON), and the thickness of the insulating dielectric layer 207 is 500 angstroms.

[0042] In step S108, using the groove as an alignment mark, etching is performed through photolithography to the predetermined area in the dielectric layer, removing the insulating dielectric layer, the second upper electrode layer, and the first upper electrode layer from areas other than the second target area. From a top view, the second target area is located within the lower electrode layer.

[0043] refer to Figure 7 It presents a structural cross-sectional view of the structure after removing the second target region, as provided in an exemplary embodiment of this application, such as... Figure 7 As shown, it includes: For example, the groove 205 is used as the alignment mark for etching. The etching is performed by photolithography to remove the insulating dielectric layer 207, the second upper electrode layer 206, the first upper electrode layer 204 and the dielectric layer 203 in areas other than the second target area. From a top view, the second target area is located in the lower electrode layer. After the etching is completed, the dielectric layer 203, the first upper electrode layer 204, the second upper electrode layer 206 and the insulating dielectric layer 207 are stacked on top of the lower electrode layer 202 in sequence.

[0044] refer to Figure 8 It presents a defect distribution diagram of the upper electrode plate of a MIM capacitor manufactured using related techniques in the background art after etching testing, such as... Figure 8 As shown, it is clear that the AMARK process in the relevant technology causes damage to the dielectric layer and generates defects, which can be magnified and monitored after etching the upper electrode plate.

[0045] refer to Figure 9 It presents electronic scan images of defects in MIM capacitors manufactured using related techniques in the background art, such as... Figure 9 As shown, it can be seen that residues were generated in the MIM capacitors manufactured in the related technology.

[0046] refer to Figure 10 It presents electron scanning images of defect energy dispersive spectroscopy and failure analysis of MIM capacitors manufactured using related techniques in the background art, such as... Figure 10 As shown, it can be concluded that the relevant technology has obvious defects. The AMARK process damages the key film and produces residues. The presence of these residues leads to problems such as short circuits and degraded capacitor performance.

[0047] refer to Figure 11 It presents a schematic diagram of the structure of a MIM capacitor provided in an exemplary embodiment of this application, such as... Figure 11 As shown, it includes: For example, after the deposition and etching process is completed, the lower electrode layer 202 and the second upper electrode layer 206 are connected to the conductive metal through the Cu contact hole 208, and the insulating layer filling the Cu contact hole 208 is not shown.

[0048] refer to Figure 12 It presents a defect distribution diagram of the upper electrode plate after etching test according to an exemplary embodiment of this application, such as... Figure 12 As shown, the number of defects is 0, indicating that the defect problem in the related technology has been significantly resolved and improved.

[0049] refer to Figure 13 It presents a statistical table comparing the number of defects in different samples provided in an exemplary embodiment of this application, such as... Figure 13As shown, it includes: Samples numbered CT0343601, CT352901, and CT0343602 were manufactured using the manufacturing method provided in this application, and all of them had zero defects. The remaining samples were manufactured using related technologies and contained varying numbers of defects.

[0050] refer to Figure 14 It presents a statistical table of etching alignment errors in the horizontal direction when the thickness of the first upper electrode layer 204 provided in an exemplary embodiment of this application is 500 angstroms, where the horizontal axis is the sample number and the vertical axis is the alignment error value (in nanometers). Figure 14 A statistical table of alignment error values ​​in the horizontal (X) direction is shown below. Figure 14 As shown in the figure, the closer the error value is to 0, the better the alignment effect. The sample with the sample number CT0109501 is the sample manufactured by the method of this application. The other samples, such as the samples numbered CT0109508 to CT0109525, are manufactured by related technologies. It can be seen that the alignment error values ​​of these samples fluctuate in the range of (-10, 10), while the sample CT0109501 is closer to the standard value of 0. It can be seen that the alignment effect of the sample manufactured by this method is good in the X direction.

[0051] refer to Figure 15 It presents a statistical table of vertical etching alignment error when the thickness of the first upper electrode layer 204 provided in an exemplary embodiment of this application is 500 angstroms, where the horizontal axis is the sample number and the vertical axis is the alignment error value (unit: nanometer). Figure 15 The table shows the alignment error values ​​in the vertical Y direction. Figure 15 As shown in the figure, the closer the error value is to 0, the better the alignment effect. Sample number CT0109501 is the sample manufactured using the method of this application, while the other samples are manufactured using related technologies. It can be seen that the alignment error values ​​of these samples fluctuate within the range of [-10, 10], and the alignment error values ​​are relatively large. In contrast, the error value of sample CT0109501 is smaller and closer to the standard value of 0. It can be seen that the sample manufactured by this method in the Y direction significantly solves the error problem in related technologies. It should be noted that the appendix... Figures 13 to 15 Data for other sample numbers are not detailed here.

[0052] In the embodiments provided in this application, the AMARK process in the related technology is delayed, and etching is performed after the deposition of the first upper electrode layer 204 is completed. This avoids damage to the dielectric layer 203 caused by the original AMARK process, reduces the resulting defects in the dielectric layer 203, and improves the overall yield. At the same time, the stepwise deposition of the first upper electrode layer 204 and the second upper electrode layer 206 can meet the electrical requirements of the capacitor while ensuring the alignment accuracy.

[0053] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.

Claims

1. A method for manufacturing a MIM capacitor, characterized in that, include: A substrate is provided in which a lower electrode layer is formed, the upper surface of the lower electrode layer being exposed; The deposition medium layer covers the exposed areas of the substrate and the lower electrode layer; A first upper electrode layer is deposited to cover the dielectric layer; Photoresist is applied to the first upper electrode layer, and the photoresist in the first target area is removed by exposure and development in sequence. The first target area is located on one side of the lower electrode layer in the lateral direction. Etching is performed to a predetermined depth in the substrate of the first target region to form a groove; A second upper electrode layer is deposited to cover the first upper electrode layer and the surface of the groove; A deposited insulating dielectric layer covers the second upper electrode layer; Using the groove as an alignment mark, etching is performed through photolithography to etch into a predetermined area in the dielectric layer, removing the insulating dielectric layer, the second upper electrode layer, and the first upper electrode layer from areas other than the second target area. From a top view, the second target area is located within the lower electrode layer.

2. The manufacturing method as described in claim 1, characterized in that, The area covered by the deposition medium layer and the exposed areas of the substrate and the lower electrode layer includes: The dielectric layer was deposited using a CVD method.

3. The manufacturing method as described in claim 2, characterized in that, The thickness of the dielectric layer is 300 to 700 angstroms.

4. The manufacturing method as described in claim 1, characterized in that, The deposition of the first upper electrode layer covering the dielectric layer includes: The first upper electrode layer was deposited using the PVD method.

5. The manufacturing method as described in claim 4, characterized in that, The thickness of the first upper electrode layer is 300 to 500 angstroms.

6. The manufacturing method as described in claim 4, characterized in that, The dielectric of the first upper electrode layer includes TiN.

7. The manufacturing method as described in claim 1, characterized in that, The thickness of the second upper electrode layer is 500 to 700 angstroms.

8. The manufacturing method as described in claim 1, characterized in that, The deposition of the insulating dielectric layer covering the second upper electrode layer includes: The insulating dielectric layer was deposited using a CVD method.

9. The manufacturing method as described in claim 8, characterized in that, The thickness of the insulating dielectric layer is 100 to 500 angstroms.

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