Semiconductor device and method for manufacturing semiconductor device

Abstract

The invention provides a semiconductor device and a method for manufacturing the same, wherein a base electrode and surrounding wiring can be connected without crossing an emitter mesa while suppressing increase in base resistance. A base layer containing a compound semiconductor of a second conductivity type opposite to the first conductivity type is disposed on a surface facing the first direction of a collector layer containing a compound semiconductor of the first conductivity type. At least one emitter mesa containing a first conductivity type compound semiconductor and having a heterojunction with the base layer is disposed in a local region of the surface of the base layer facing the first direction. A collector electrode is disposed on a surface of the collector layer facing a second direction opposite to the first direction. An emitter electrode is disposed on a surface of the emitter mesa facing the first direction. The base electrode is disposed in a region where the emitter mesa is not disposed in a surface of the base layer facing the first direction. The base electrode includes a first layer and a second layer, which partially overlap each other, do not include a closed pattern in plan view, and continuously surround the emitter mesa as a whole.

Description

Technical Field

[0001] This invention relates to a semiconductor device and a method for manufacturing a semiconductor device. Background Technology

[0002] An improved HBT (Patent Document 1) was proposed, which is an improvement on the conventional heterojunction bipolar transistor (HBT) with striped emitter electrodes. In this improved HBT, a base layer is disposed on the collector layer, and an emitter mesa is disposed on the base layer. The emitter mesa has multiple openings, and a base electrode is disposed in each of the multiple openings.

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Publication No. 2021-506114 Summary of the Invention

[0006] The problem the invention aims to solve

[0007] In the HBT disclosed in Patent Document 1, the base electrode is disposed within the opening of the emitter mesa. Therefore, in order to connect the multiple isolated base electrodes to the surrounding circuitry, wiring intersecting the emitter mesa is required. Furthermore, in a conventional configuration where the emitter mesa is striped and striped base electrodes are disposed on both sides of the emitter mesa, two striped base electrodes can be connected to each other within the same metal layer. However, the base electrodes become elongated, resulting in higher base resistance.

[0008] The object of the present invention is to provide a semiconductor device and a method thereof that suppresses the rise of base resistance and enables the base electrode to be connected to the surrounding wiring without intersecting with the emitter mesa.

[0009] Solution for solving the problem

[0010] According to one aspect of the present invention, a semiconductor device is provided, comprising: a collector layer containing a compound semiconductor of a first conductivity type; a base layer disposed on a surface of the collector layer facing a first direction, containing a compound semiconductor of a second conductivity type opposite to the first conductivity type; at least one emitter mesa disposed in a local region of the surface of the base layer facing the first direction, containing the compound semiconductor of the first conductivity type, wherein a heterojunction is formed between the emitter mesa and the base layer; and a collector electrode disposed on the collector layer facing the first direction. The surface is a second direction opposite to the first direction; an emitter electrode disposed on the surface of the emitter mesa facing the first direction; and a base electrode disposed in the area of ​​the base layer on the surface facing the first direction where the emitter mesa is not disposed, the base electrode comprising a first layer and a second layer, a portion of the first layer overlapping a portion of the second layer, neither the first layer nor the second layer being included in a closed pattern when viewed from above, the first layer and the second layer generally continuously surrounding the emitter mesa when viewed from above.

[0011] According to another aspect of the present invention, a method for manufacturing a semiconductor device is provided, wherein a release layer is formed on a surface of a temporary substrate facing a first direction; a collector layer containing a compound semiconductor of a first conductivity type is formed on the surface of the release layer facing the first direction; a base layer containing a compound semiconductor of a second conductivity type opposite to the first conductivity type is formed on the surface of the collector layer facing the first direction; at least one emitter mesa containing the compound semiconductor of the first conductivity type is formed on the surface of the base layer facing the first direction; a base electrode continuously surrounding the emitter mesa when viewed from above is formed on the surface of the base layer facing the first direction; an emitter electrode is formed on the surface of the emitter mesa facing the first direction; the release layer is removed by etching to separate the collector layer from the temporary substrate; a collector electrode is formed on the surface of the collector layer facing a second direction opposite to the first direction; and the collector electrode is bonded to a support substrate.

[0012] The effects of the invention

[0013] The base electrode continuously surrounds the emitter mesa when viewed from above, thus suppressing the rise in base resistance. Furthermore, the base electrode can be connected to surrounding wiring without intersecting the emitter mesa. Attached Figure Description

[0014] Figure 1 This is a top view of the semiconductor device of the first embodiment.

[0015] Figure 2 yes Figure 1The sectional view at point 2-2, marked by a single-dotted line.

[0016] Figure 3A , Figure 3B ,as well as Figure 3C This is a cross-sectional view of the semiconductor device of the first embodiment during a manufacturing process.

[0017] Figure 4A This is a top view of a stage in the manufacturing process of a semiconductor device. Figure 4B yes Figure 4A A cross-sectional view at point 4B-4B, marked by a single-dotted line.

[0018] Figure 5A This is a top view of a stage in the manufacturing process of a semiconductor device. Figure 5B yes Figure 5A A cross-sectional view at point 5B-5B, marked by a single-dotted line.

[0019] Figure 6 This is a top view of a semiconductor device according to a variation of the first embodiment.

[0020] Figure 7 This is a top view of a semiconductor device, which is another variation of the first embodiment.

[0021] Figure 8 This is a top view of the semiconductor device of the second embodiment.

[0022] Figure 9A and Figure 9B These are top views of the first layer 30B1 and the second layer 30B2 of the base electrode 30B.

[0023] Figure 10 yes Figure 8 A cross-sectional view at point 10-10, indicated by a single-dotted line.

[0024] Figure 11 This is a top view of a semiconductor device of a modified embodiment of the second embodiment.

[0025] Figure 12A and Figure 12B They are Figure 11 A top view of the first layer 30B1 and the second layer 30B2 of the base electrode 30B of the semiconductor device shown.

[0026] Figure 13 This is a top view of the semiconductor device of the third embodiment.

[0027] Figure 14 This is a cross-sectional view of the semiconductor device of the fourth embodiment.

[0028] Figure 15 This is a cross-sectional view of the semiconductor device of the fifth embodiment.

[0029] Figure 16A and Figure 16B This is a cross-sectional view of the semiconductor device of the fifth embodiment during the manufacturing process.

[0030] Figure 17 This is a cross-sectional view of the semiconductor device of the sixth embodiment.

[0031] Explanation of reference numerals in the attached figures

[0032] 20. Heterojunction Bipolar Transistor (HBT); 20B. Base layer; 20C. Collector layer; 20E. Emitter mesa; 20EB. Ballast resistor layer; 30B. Base electrode; 30B1. First layer of base electrode; 30B2. Second layer of base electrode; 30C. Collector electrode; 30E. Emitter electrode; 41B, 41B1, 41B2. Base wiring; 41Bias. Bias wiring; 41BR. Base ballast resistor element; 41E. Emitter wiring; 42C. Electrode wiring; 42E, Emitter wiring; 42RF, Signal input wiring; 43, Input capacitor; 45C, Collector pad; 45E, Emitter pad; 50, Cell; 60, Support substrate; 61C, Collector wiring; 65, Multilayer wiring layer; 65V, Via; 65W, Wiring; 70, Electronic circuit; 80, 81, Resist film; 90, Temporary substrate; 91, Release layer; D1, First direction; D2, Second direction; H1, H2, Openings; OVP, Overlapping area. Detailed Implementation

[0033] [First Embodiment]

[0034] Reference from Figures 1 to 5B The semiconductor device of the first embodiment will be described with reference to the accompanying drawings. Figure 1 This is a top view of the semiconductor device of the first embodiment. Figure 2 yes Figure 1 A cross-sectional view at point 2-2, marked by a single-dotted line. Furthermore, in... Figure 2 The description of the interlayer insulating film is omitted.

[0035] On the surface of the collector layer 20C facing the first direction D1 (in Figure 1 The center is the surface facing forward. Figure 2 A base layer 20B is disposed in a localized area of ​​the surface (facing upwards). An emitter mesa 20E is disposed on the surface of the base layer 20B facing the first direction D1. The base layer 20B and the emitter mesa 20E are circular when viewed from above. In this specification, the surface of various parts facing the first direction D1 may be referred to as the upper surface.

[0036] The collector layer 20C contains a compound semiconductor of a first conductivity type, and the base layer 20B contains a compound semiconductor of a second conductivity type, opposite to the first conductivity type. Here, "first conductivity type" and "second conductivity type" mean that one is an n-type conductivity type and the other is a p-type conductivity type. The emitter mesa 20E contains a compound semiconductor of the first conductivity type. The heterojunction is formed by the base layer 20B and the emitter mesa 20E. For example, the collector layer 20C is formed of n-type GaAs, the base layer 20B is formed of p-type GaAs, and the emitter mesa 20E is formed of n-type InGaP. The collector layer 20C, the base layer 20B, and the emitter mesa 20E constitute a heterojunction bipolar transistor 20 (HBT).

[0037] Alternatively, a so-called ledge structure can be used, in which a first conductivity type compound semiconductor layer is disposed over the entire surface of the upper surface of the base layer 20B, and an emitter capping layer and a contact layer are disposed locally on its surface. In this structure, the region of the first conductivity type compound semiconductor layer covering the upper surface of the base layer 20B that overlaps with the emitter capping layer, the emitter capping layer, and the contact layer correspond to the emitter mesa 20E. The region of the first conductivity type compound semiconductor layer covering the entire surface of the upper surface of the base layer 20B that is not covered by the emitter capping layer functions as a protective film for the base layer 20B.

[0038] An emitter electrode 30E is disposed over the entire area of ​​the upper surface of the emitter mesa 20E. Figure 1 In the image, emitter electrode 30E is shaded in the upper right corner. Emitter electrode 30E makes ohmic contact with emitter mesa 20E. Emitter electrode 30E and emitter mesa 20E are patterned using, for example, a self-aligned process.

[0039] A base electrode 30B is disposed in a region of the base layer 20B facing the first direction D1, where the emitter mesa 20E is not disposed. The base electrode 30B makes ohmic contact with the base layer 20B. The base electrode 30B continuously surrounds the emitter mesa 20E when viewed from above. That is, the emitter mesa 20E is disposed inside a closed pattern formed by the base electrode 30B. Here, "closed pattern" refers to a pattern that returns to its original position when a point is moved in one direction along the pattern. The spacing between the outer perimeter of the emitter mesa 20E and the inner perimeter of the base electrode 30B is approximately constant in the circumferential direction. The emitter mesa 20E is processed using, for example, dry etching. Furthermore, the thickness of the emitter mesa 20E is, for example, 200 nm or less.

[0040] The base electrode 30B includes a first layer 30B1 and a second layer 30B2. Figure 1In the diagram, layer 1 (30B1) has a lower right shading line, and layer 2 (30B2) has an upper right shading line. A portion of layer 1 (30B1) overlaps with a portion of layer 2 (30B2). Neither layer 1 (30B1) nor layer 2 (30B2) is included in the closed pattern when viewed from above. Layer 1 (30B1) and layer 2 (30B2) together continuously surround the emitter platform 20E when viewed from above.

[0041] For example, layers 30B1 and 30B2, when viewed from above, are arcs along a common circumference, with their ends overlapping each other. That is, the sum of the central angles of the arcs along which layers 30B1 and 30B2 are located is greater than 360°. In the overlapping region OVP, layer 30B1 is positioned closer to the base layer 20B than layer 30B2.

[0042] The top of the base wiring 41B of the first layer overlaps with a portion of the upper surface of the base electrode 30B, and the base wiring 41B extends to the outside of the base layer 20B when viewed from above. The emitter wiring 41E of the first layer is disposed on the upper surface of the emitter electrode 30E. An emitter pad 45E for external circuit connection is disposed on the upper surface of the emitter wiring 41E. Figure 1 The description of emitter wiring 41E and emitter pad 45E is omitted.

[0043] A collector electrode 30C is disposed on the surface of the collector layer 20C facing a second direction D2, which is opposite to the first direction D1. The collector electrode 30C makes ohmic contact with the collector layer 20C. In this specification, the surface of various parts facing the second direction D2 is referred to as the "lower surface".

[0044] Next, refer to Figure 3A , Figure 3B ,as well as Figure 3C The manufacturing method of the semiconductor device of the first embodiment will be described. Figure 3A , Figure 3B ,as well as Figure 3C This is a cross-sectional view of the semiconductor device of the first embodiment during a manufacturing process.

[0045] like Figure 3A As shown, a release layer 91 is epitaxially grown on a temporary substrate 90 formed of a compound semiconductor. A collector layer 20C is further epitaxially grown on the release layer 91. A device structure including a base layer 20B, an emitter mesa 20E, a base electrode 30B, an emitter electrode 30E, a first-layer base wiring 41B, and an emitter wiring 41E is formed on the upper surface of the collector layer 20C. These formations can be achieved using conventional semiconductor processes. (The following refers to...) Figures 4A to 5B The accompanying drawings illustrate in detail the sequence used to form the base electrode 30B.

[0046] In this stage, the collector layer 20C is disposed over the entire area of ​​the upper surface of the temporary substrate 90, and multiple semiconductor device element structures (chips) are disposed on the upper surface of the collector layer 20C. Figure 3A Only one chip section is shown in the diagram. In addition, the chip also includes multiple heterojunction bipolar transistors 20 and other passive components (not shown).

[0047] like Figure 3B As shown, each chip is segmented by patterning the collector layer 20C and the release layer 91. During this stage, multiple chips are supported on a general-purpose temporary substrate 90. A protective tape (not shown) is attached to the upper surface of the multiple chips. The multiple chips are connected by the protective tape.

[0048] By selectively etching away the release layer 91, the chip, including the collector layer 20C, is peeled off from the temporary substrate 90. Multiple chips are then connected by a protective strip.

[0049] like Figure 3C As shown, a collector electrode 30C is formed on the lower surface of the collector layer 20C. As an example, after forming the collector electrode 30C, each chip is peeled off from the protective strip, and the collector electrode 30C is bonded to a support substrate, etc. After the chip is bonded to the support substrate, an emitter pad 45E is formed. Figure 2 )wait.

[0050] Next, refer to from Figures 4A to 5B The order of forming the base electrode 30B is explained in the attached figure. Figure 4A and Figure 5A This is a top view of a stage in the manufacturing process of a semiconductor device. Figure 4B and Figure 5B They are Figure 4A The single-dot dashed line 4B-4B and Figure 5A A cross-sectional view at the dashed line 5B-5B. A stripping process was used to form the base electrode 30B.

[0051] like Figure 4B As shown, after forming the emitter electrode 30E and the emitter mesa 20E, a resist film 80 is formed covering the collector layer 20C, the base layer 20B, the emitter mesa 20E, and the emitter electrode 30E. Then, an opening H1 aligned with the planar pattern of the first layer 30B1 of the base electrode 30B is formed in the resist film 80. A conductive film is formed on the upper surface of the base layer 20B exposed at the bottom of the opening H1 and on the upper surface of the resist film 80. The resist film 80 is removed along with the conductive film covering the upper surface of the resist film 80. Thus, the first layer 30B1 of the base electrode 30B remains on the upper surface of the base layer 20B. Figure 4AAs shown, layer 1 30B1 does not include the closed pattern when viewed from above.

[0052] like Figure 5B As shown, after forming the first layer 30B1 of the base electrode 30B, a resist film 81 is formed covering the collector layer 20C, the base layer 20B, the emitter mesa 20E, the emitter electrode 30E, and the first layer 30B1. Then, an opening H2 is formed in the resist film 81, aligned with the planar pattern of the second layer 30B2 of the base electrode 30B. In the overlapping region OVP ( Figure 5A In the first layer 30B1, the first layer is exposed within the opening H2, while in other regions, the base layer 20B is exposed.

[0053] A conductive film is formed on the upper surface of the base layer 20B and the first layer 30B1 exposed at the bottom surface of the opening H2, and on the upper surface of the resist film 81. The resist film 81 is removed along with the conductive film covering the upper surface of the resist film 81. As a result, the second layer 30B2 of the base electrode 30B remains on the upper surface of the base layer 20B and in the overlapping region OVP. Figure 5A As shown, layer 2 30B2 is not included in the closed pattern when viewed from above. In addition, layer 1 30B1 and layer 2 30B2 form a closed pattern overall.

[0054] Next, the superior effects of the first embodiment will be explained.

[0055] In the semiconductor device of the first embodiment, when viewed from above, the emitter mesa 20E is circular, and the base electrode 30B ( Figure 1 The base electrode 30B is continuously arranged opposite to the entire area of ​​the outer periphery of the emitter mesa 20E, as the emitter mesa 20E and the base electrode 30B are arranged in a striped pattern. In contrast, in a structure where the emitter mesa 20E and the base electrode 30B are arranged in a striped pattern, the opposing base electrode is not arranged on a portion of the outer periphery of the emitter mesa. Therefore, in the semiconductor device of the first embodiment, the base resistance can be reduced compared to a structure where the emitter mesa 20E and the base electrode 30B are arranged in a striped pattern. Furthermore, it is not necessary for the base wiring 41B, which connects the base electrode 30B to the surrounding wiring, to intersect the emitter mesa 20E when viewed from above.

[0056] In addition, the collector electrode 30C, which is formed of a metallic material, is disposed over the entire area of ​​the lower surface of the collector layer 20C, thereby suppressing the increase in resistance of the current path from the external circuit to the collector layer 20C.

[0057] Furthermore, in the first embodiment, the first layer 30B1 and the second layer 30B2 of the base electrode 30B are formed using different stripping processes. Therefore, the conductor pattern formed in a single stripping process should not include closed patterns. Generally, when the conductor pattern formed using a stripping process includes closed patterns, there is a tendency for a decrease in yield. In the first embodiment, the base electrode 30B including closed patterns is formed using two stripping processes, thus suppressing the decrease in yield.

[0058] Next, refer to Figure 6 and Figure 7 The semiconductor device of the modified example of the first embodiment will be described. Figure 6 and Figure 7 This is a top view of a semiconductor device according to a variation of the first embodiment. In the first embodiment ( Figure 1 In the diagram, when viewed from above, the pattern of the base electrode 30B is a closed pattern along the circumference, or it can be other closed patterns.

[0059] exist Figure 6 In the modified example shown, when viewed from above, the pattern of the base electrode 30B is a closed pattern along the outer perimeter of a square. Figure 6 In the example shown, the overlapping region OVP is positioned approximately at the midpoint of a pair of opposite sides of the square; it could also be positioned elsewhere. Furthermore, the pattern of the base electrode 30B could also be a closed pattern along the outer perimeter of a rectangle instead of a square. Figure 7 In the modified example shown, when viewed from above, the pattern of the base electrode 30B is a closed pattern along the outer periphery of a regular hexagon. Figure 7 In the example shown, an overlapping region OVP is positioned at the midpoint of a pair of opposite sides of the regular hexagon; it could also be positioned elsewhere. The shape of the emitter mesa 20E, viewed from above, reflects the pattern of the base electrode 30B. For example, in Figure 6 In the variant shown, the emitter platform 20E is square or rectangular in shape. Figure 7 In the variant shown, the emitter platform 20E is a regular hexagon.

[0060] Next, the superior effects of the first embodiment and its modifications will be explained. If, as in the first embodiment ( Figure 1 By designing the emitter mesa 20E as a circle, the length of the current path from the outer periphery of the emitter mesa 20E to the base electrode 30B remains approximately constant throughout the entire outer periphery of the emitter mesa 20E. Therefore, the base current flows approximately uniformly throughout almost the entire outer periphery of the emitter mesa 20E. In other words, this achieves the excellent effect of eliminating regions with relatively low base current or regions where there is almost no current flow.

[0061] On the other hand, Figure 6 and Figure 7 In the modified example shown, as will be explained later in the second embodiment, the structure consisting of the base electrode 30B and the emitter mesa 20E can be completely covered in the two-dimensional plane. Therefore, in a structure with multiple emitter mesa 20E, Figure 6 and Figure 7 The variant shown excels in space utilization efficiency.

[0062] exist Figure 7 The diagram shows an example where the base electrode 30B is along the outer periphery of a regular hexagon; it can also be provided along the outer periphery of a hexagon other than a regular hexagon. Furthermore, if at least one interior angle of the hexagon is acute, the base current hardly flows from the portion of the base electrode 30B corresponding to the vertex of the acute angle. To minimize the area where the base current hardly flows, it is preferable that the six interior angles of the hexagon are all obtuse angles. In this case, it is also preferable to have a shape that allows the structure formed by the base electrode 30B and the emitter mesa 20E to completely cover the two-dimensional plane.

[0063] To increase output, multiple... Figure 1 , Figure 6 , Figure 7 The heterojunction bipolar transistors 20 shown are connected in parallel. In this case, to suppress thermal runaway, it is preferable to connect a base ballast resistor for each heterojunction bipolar transistor 20.

[0064] [Second Embodiment]

[0065] Next, refer to from Figures 8 to 10 The semiconductor device of the second embodiment will be described with reference to the accompanying drawings. Hereinafter, the semiconductor device will be described with reference to the accompanying drawings. Figures 1 to 7 The semiconductor device of the first embodiment and its modifications, as illustrated in the accompanying drawings, has a general structure, and the description is omitted.

[0066] Figure 8 This is a top view of the semiconductor device of the second embodiment. In the first embodiment ( Figure 1 In the first embodiment, there is only one emitter mesa 20E. In the second embodiment, multiple emitter mesa 20Es are discretely arranged. The base electrode 30B continuously surrounds each of the multiple emitter mesa 20Es. The portion of the base electrode 30B disposed between two adjacent emitter mesa 20Es is shared as a portion surrounding the emitter mesa 20Es on both sides.

[0067] More specifically, the base electrode 30B is arranged in a lattice pattern with orthogonal vertical and horizontal lines. Emitter mesa 20E are respectively disposed within multiple lattice-shaped sections separated by vertical and horizontal lines. When viewed from above, the outer perimeter of each emitter mesa 20E is spaced apart from the edge of the base electrode 30B, having a shape along the edge of the base electrode 30B. Since the multiple sections separated by the orthogonal lattice pattern are square or rectangular, the shape of the emitter mesa 20E when viewed from above is also square or rectangular.

[0068] The base electrode 30B, like in the first embodiment, includes a first layer 30B1 and a second layer 30B2. Figure 8 In the diagram, the first layer 30B1 has a shaded line at the upper right, and the second layer 30B2 has a shaded line at the lower right. Furthermore, the emitter electrode 30E also has a shaded line at the upper right.

[0069] Figure 9A and Figure 9B These are top views of the first layer 30B1 and the second layer 30B2 of the base electrode 30B, respectively. The first layer 30B1... Figure 9A ) and 2nd floor 30B2 ( Figure 9B Each layer has a pattern with horizontal and vertical lines that resemble a grid. At the grid points where the horizontal and vertical lines intersect (overlapping area OVP), layer 1 30B1 overlaps with layer 2 30B2. Neither layer 1 30B1 nor layer 2 30B2 contains closed patterns.

[0070] The outermost portion of the lattice-shaped base electrode 30B, when viewed from above, is widened, and the base wiring 41B of the first layer is connected to the widened portion. The base wiring 41B does not intersect with any emitter mesa 20E or any emitter electrode 30E when viewed from above, and extends to the outside of the base layer 20B.

[0071] Figure 10 yes Figure 8 A cross-sectional view at point 10-10 (dotted line). Multiple emitter mesa surfaces 20E are arranged on the upper surface of the base layer 20B. Figure 10 The cross-section shown presents two emitter mesa 20E. An emitter electrode 30E is disposed on the upper surface of each emitter mesa 20E. Emitter wiring 41E of the first layer electrically connects the multiple emitter electrodes 30E to each other. A collector pad 45C is disposed on the upper surface of the emitter wiring 41E.

[0072] The base wiring 41B of the first layer is electrically connected to the outermost portion of the base electrode 30B. The base wiring 41B intersects the edge of the base layer 20B and extends to the outside of the base layer 20B when viewed from above.

[0073] Next, the superior effects of the second embodiment will be explained.

[0074] In the second embodiment, similarly to the first embodiment, the base electrode 30B is arranged opposite to the entire area of ​​the outer periphery of the emitter mesa 20E. Therefore, compared to a structure where the emitter mesa 20E and the base electrode 30B are striped, the increase in base resistance can be suppressed. Furthermore, neither the first layer 30B1 nor the second layer 30B2 of the base electrode 30B includes a closed pattern when viewed from above, thus suppressing the reduction in yield during the formation process of the base electrode 30B.

[0075] Furthermore, since the multiple emitter mesa 20Es are discretely distributed, the base electrode 30B can be electrically continuous within the same layer. Additionally, the base wiring 41B of the first layer does not intersect with any of the multiple emitter electrodes 30E when viewed from above; therefore, all emitter electrodes 30E can be electrically connected to each other using emitter wiring 41E disposed on the same conductor layer as the base wiring 41B of the first layer. Moreover, the emitter pad 45E disposed on the upper surface of the emitter wiring 41E can be electrically connected to the emitter mesa 20E via the shortest path. For example, when viewed from above, the emitter wiring 41E and the emitter pad 45E can be disposed in the region overlapping with the emitter mesa 20E and the emitter electrode 30E.

[0076] In addition, the base electrode 30B can be formed by vertical and horizontal lines. Figure 8 When designing patterns using CAD, slanted lines cannot fall on the grid that serves as the reference for pattern configuration, thus creating layout difficulties. In the second embodiment, the pattern of the base electrode 30B can be designed using only vertical and horizontal lines, thus achieving the excellent effect of easy layout of the base electrode 30B.

[0077] In the second embodiment, the partitions separated by the base electrode 30B are square or rectangular, and more preferably, the partitions separated by the base electrode 30B are square. If the partitions separated by the base electrode 30B are square, the uniformity of the current distribution is improved compared to the case where they are rectangular. Therefore, setting the partitions to squares is effective against current collapse.

[0078] In addition, in the second embodiment, the base electrode 30B is set as a grid with vertical and horizontal lines orthogonal, but the vertical and horizontal lines do not need to be strictly orthogonal in geometry, and can be slightly deviated from the orthogonal relationship.

[0079] Next, refer to Figure 11 , Figure 12A ,as well as Figure 12B The semiconductor device of the modified example of the second embodiment will be described.

[0080] Figure 11This is a top view of a semiconductor device according to a variation of the second embodiment. In the second embodiment ( Figure 8 In this embodiment, the base electrode 30B is in the form of a lattice with orthogonal vertical and horizontal lines; in this modified example, the base electrode 30B is honeycomb-shaped. Multiple hexagonal partitions are formed, separated by the base electrodes 30B. Emitter mesa 20E and emitter electrodes 30E are respectively disposed in each of the multiple partitions. The top view of each emitter mesa 20E and emitter electrode 30E is a regular hexagon reflecting the shape of the partition. The base electrode 30B, like in the second embodiment, includes a first layer 30B1 and a second layer 30B2.

[0081] Figure 12A and Figure 12B These are top views of floor 1, 30B1, and floor 2, 30B2, respectively. (Example) Figure 12A As shown, the first layer 30B1 is formed by the base electrode 30B along one direction (in Figure 11 , Figure 12A The middle part is composed of multiple parts of a horizontally parallel regular hexagon. For example... Figure 12B As shown, the second layer 30B2 is composed of multiple portions along the six sides of a regular hexagon, excluding the sides along which the first layer 30B1 is located. That is, the second layer 30B2 extends in a zigzag shape in a direction orthogonal to the respective length direction of the first layer 30B1. The ends of each of the first layers 30B1 overlap with the corner portions of the zigzag-shaped second layer 30B2.

[0082] As in this modified example, the base electrode 30B can also be honeycomb shaped. Also in this modified example, neither the first layer 30B1 nor the second layer 30B2 is included in the closed pattern when viewed from above.

[0083] Furthermore, the multiple partitions separated by the base electrode 30B do not necessarily have to be regular hexagons; they can also be convex hexagons formed by distorting regular hexagons. Moreover, if the vertices of the hexagons are acute angles, the useless region between the emitter mesa 20E and the base electrode 30B, where the base current substantially does not flow, becomes larger. To reduce this useless region and improve area efficiency, it is preferable to set the six vertices of the convex hexagon to obtuse angles.

[0084] [Third Embodiment]

[0085] Next, refer to Figure 13 The semiconductor device of the third embodiment will now be described. Hereinafter, the device will be described in relation to the referenced semiconductor device. Figure 11 , Figure 12A , Figure 12B The semiconductor device of the modified example of the second embodiment described herein has a general structure, and the description is omitted.

[0086] Figure 13This is a top view of the semiconductor device of the third embodiment. The semiconductor device of the third embodiment includes a plurality of units 50. Each of the plurality of units 50 has a semiconductor device (as described in the modified example of the second embodiment) Figure 11 The same structure. Furthermore, the configuration of the multiple emitter mesa 20E of each element 50 is the same as... Figure 11 The configuration of the emitter mesa 20E of the semiconductor device in the modified embodiment of the second embodiment shown is different. A base electrode 30B is provided for each cell 50, and the base electrodes 30B are not directly connected to each other between cells 50.

[0087] Each unit 50 is configured with first-layer base wiring 41B1, 41B2 connected to the base electrode 30B. Multiple base wirings 41B are connected to a general-purpose bias wiring 41Bias via base ballast resistor elements 41BR. Another base wiring 41B2 is connected to a general-purpose signal input wiring 42RF via an input capacitor 43.

[0088] Next, the superior effects of the third embodiment will be explained.

[0089] If the temperature of any one of the units 50 rises, the current concentrates in that unit 50, causing the temperature to rise further and potentially leading to thermal runaway. In the third embodiment, a base ballast resistor element 41BR is provided for each unit 50, thus suppressing the current concentration in the unit 50 where the collector current increases relatively. This results in the excellent effect of minimizing the occurrence of thermal runaway.

[0090] Next, a modified semiconductor device of the third embodiment will be described.

[0091] In the third embodiment, the base electrode 30B of each unit 50 is configured in a honeycomb shape, or as follows: Figure 8 The base electrode 30B of the semiconductor device in the second embodiment shown is configured as a grid with vertical and horizontal lines orthogonal.

[0092] [Example 4]

[0093] Next, refer to Figure 14 The semiconductor device of the fourth embodiment will now be described. Hereinafter, the device will be described in relation to the one referenced from... Figures 8 to 10 The structure of the semiconductor device of the second embodiment, which is described with reference to the accompanying drawings, is a general structure and the description is omitted.

[0094] Figure 14 This is a cross-sectional view of the semiconductor device of the fourth embodiment. In the fourth embodiment, it is also similar to the second embodiment (…). Figure 8 , Figure 10 Similarly, multiple emitter tectonics 20E are configured. In the first embodiment ( Figure 2In the first embodiment, the emitter mesa 20E includes an emitter layer, an emitter capping layer, and a contact layer that are heterojunctioned with the base layer 20B. In contrast, in the fourth embodiment, the emitter mesa 20E further includes a ballast resistor layer 20EB.

[0095] The ballast resistor layer 20EB is formed of a compound semiconductor with a positive temperature dependence of resistivity. For example, the emitter mesa 20E includes an n-type InGaP layer, an n-type AlGaAs ballast resistor layer 20EB, an n-type GaAs layer, and an n-type InGaAs layer, which are stacked sequentially from the base layer 20B.

[0096] Next, the superior effects of the fourth embodiment will be explained.

[0097] If the temperature of a portion of the multiple emitter mesa 20E rises relatively, current will concentrate towards the emitter mesa 20E with the increased temperature, resulting in thermal runaway. In the fourth embodiment, the resistance of the ballast resistor layer 20EB of the emitter mesa 20E with the increased temperature becomes higher. Therefore, it is possible to obtain an excellent effect such as suppressing the concentration of current towards the emitter mesa 20E and making it difficult to cause thermal runaway.

[0098] [Version 5]

[0099] Next, refer to Figure 15 , Figure 16A , Figure 16B The semiconductor device of the fifth embodiment will now be described. Hereinafter, the device will be described in relation to the one referenced from... Figures 1 to 14 The semiconductor device structures of the embodiments from the first to the fourth embodiment, as illustrated in the accompanying drawings, are general structures, and descriptions are omitted.

[0100] Figure 15 This is a cross-sectional view of the semiconductor device according to the fifth embodiment. The semiconductor device of the fifth embodiment includes a support substrate 60, which has sufficient support force at a mechanical level. As the support substrate 60, a substrate having a thermal conductivity higher than that of the collector layer 20C is used. For example, a silicon-containing substrate (e.g., a silicon substrate) is used as the support substrate 60.

[0101] The semiconductor device of the fifth embodiment includes the semiconductor device of the first embodiment ( Figure 2 The component structure is the same as that in the second embodiment, from the collector electrode 30C to the emitter wiring 41E and base wiring 41B of the first layer. Alternatively, it may include components similar to those in the second embodiment. Figure 8 , Figure 10 ), and variations of the second embodiment ( Figure 11 ), Semiconductor device of the third embodiment ( Figure 13 ), Semiconductor device of the fourth embodiment ( Figure 14The components have the same structure as those of other components.

[0102] A collector wiring 61C is disposed on one side of the surface of the support substrate 60. The surface of the collector electrode 30C of the semiconductor device of the first embodiment facing the second direction D2 is bonded to the collector wiring 61C, and the collector electrode 30C is electrically connected to the collector wiring 61C. In top view, the support substrate 60 is larger than the collector layer 20C, and the collector wiring 61C extends to the outside of the collector electrode 30C.

[0103] Viewed from collector wiring 61C, a collector pad 45C for external circuit connection is arranged on the first direction D1 side. When viewed from above, the collector pad 45C is positioned to overlap with collector wiring 61C but not with collector electrode 30C or collector layer 20C. A collector wiring 42C is arranged between the collector pad 45C and collector wiring 61C, and the collector pad 45C is electrically connected to the collector wiring 61C via the collector wiring 42C.

[0104] A second-layer emitter wiring 42E is disposed on the upper surface of the emitter wiring 41E of the first layer, and an emitter pad 45E is disposed on the upper surface of the second-layer emitter wiring 42E. The emitter pad 45E is electrically connected to the emitter electrode 30E via the emitter wirings 42E and 41E. The emitter wiring 42E and the collector wiring 42C are disposed in the same wiring layer.

[0105] The semiconductor device of the fifth embodiment has its emitter pad 45E and collector pad 45C mounted on a module substrate or the like, opposite to the module substrate.

[0106] Next, refer to Figure 16A and Figure 16B The manufacturing method of the semiconductor device in the fifth embodiment will be described. Figure 16A and Figure 16B This is a cross-sectional view of the semiconductor device of the fifth embodiment during the manufacturing process.

[0107] like Figure 16A As shown, a device structure is fabricated from the collector electrode 30C on the lower surface of the collector layer 20C to the emitter wiring 41E and base wiring 41B of the first layer. The fabrication method of this device structure is the same as that described in the reference. Figures 3A to 5B The manufacturing method of the semiconductor device of the first embodiment, which is described with reference to the accompanying drawings, is the same. A collector wiring 61C is formed on one side of the support substrate 60.

[0108] like Figure 16B As shown, the collector electrode 30C is positioned opposite the collector wiring 61C, and the two are joined together. This joining is achieved by van der Waals bonding, hydrogen bonding, etc. Alternatively, electrostatic forces, covalent bonds, eutectic alloy bonding, etc., can also be used for joining.

[0109] After connecting the collector electrode 30C to the collector wiring 61C, as Figure 15 As shown, a second layer of emitter wiring 42E and collector wiring 42C is formed on the surface of the component structure and collector wiring 61C facing the first direction, and emitter pad 45E and collector pad 45C are also formed. These formations are achieved using a typical multilayer wiring layer formation process.

[0110] Next, the superior effects of the fifth embodiment will be explained.

[0111] In the fifth embodiment, the support substrate 60, in addition to serving as a substrate for mechanically supporting the device structure including the HBT 20, also functions as a heat dissipation path for heat dissipation from the HBT 20. Generally, the thermal conductivity of the compound semiconductor constituting the collector layer 20C, base layer 20B, and emitter mesa 20E of the HBT 20 is lower than that of the silicon-containing support substrate 60. By bonding the device structure including the HBT 20 to the support substrate 60, which has relatively high thermal conductivity, good heat dissipation from the HBT 20 can be ensured.

[0112] Furthermore, the current path from the collector pad 45C to the collector layer 20C consists of collector wirings 42C and 61C and collector electrode 30C formed of metallic material, and does not contain semiconductor material. Therefore, the increase in resistance from the collector layer 20C to the external circuit connected to the collector layer 20C can be suppressed.

[0113] [Sixth Embodiment]

[0114] Next, refer to Figure 17 The semiconductor device of the sixth embodiment will now be described. Hereinafter, the device will be described in relation to the referenced semiconductor device. Figure 15 , Figure 16A , Figure 16B The semiconductor device in the fifth embodiment described herein has a general structure, and the description is omitted.

[0115] Figure 17 This is a cross-sectional view of the semiconductor device of the sixth embodiment. In the semiconductor device of the fifth embodiment ( Figure 15 In the first embodiment, when viewed from the collector wiring 61C, a collector pad 45C is provided on the first direction D1 side. In contrast, in the sixth embodiment, when viewed from the collector wiring 61C, no collector pad is provided on the first direction D1 side.

[0116] An electronic circuit 70, including a MOSFET, is formed on the surface of the support substrate 60 facing the first direction D1, and a multilayer wiring layer 65 is also formed thereon. A collector wiring 61C is disposed on the surface of the multilayer wiring layer 65 facing the first direction D1. The collector layer 20C of the HBT20 is electrically connected to the electronic circuit 70 via a collector electrode 30C, the collector wiring 61C, and wiring 65W and vias 65V within the multilayer wiring layer 65. The electronic circuit 70 is, for example, a switching element that distributes high-frequency signals amplified by the HBT20.

[0117] Next, the superior effects of the sixth embodiment will be explained.

[0118] In the sixth embodiment, similarly to the fifth embodiment, the support substrate 60 functions as a heat dissipation path for heat dissipation from the HBT20. Furthermore, the collector of the HBT20 can be connected to the electronic circuit 70 formed on the support substrate 60 without the need for external circuit connection pads.

[0119] A collector electrode 30C, formed of a metallic material, is disposed over the entire lower surface region of the collector layer 20C, and the entire lower surface region of the collector electrode 30C is connected to the collector wiring 61C. Furthermore, the collector wiring 61C is connected to the electronic circuit 70 via wiring 65W and vias 65V within the multilayer wiring layer 65. Since the current path from the collector layer 20C to the electronic circuit 70 is formed solely of metal and excludes portions formed of semiconductor material, the increase in resistance of the current path from the electronic circuit 70 to the collector layer 20C can be suppressed.

[0120] The above embodiments are illustrative, and it can be said that parts of the structure shown in different embodiments and modifications can be replaced or combined. The same effects resulting from the same structure in multiple embodiments and modifications are not mentioned sequentially in each embodiment and modification. Furthermore, the present invention is not limited to the above embodiments and modifications. For example, it will be apparent to those skilled in the art that various changes, improvements, combinations, etc., can be made.

[0121] Based on the embodiments described in this specification, the following technical solutions are disclosed.

[0122] <1> A semiconductor device, wherein the semiconductor device comprises:

[0123] Collector layer, which contains a compound semiconductor of conductivity type 1;

[0124] The base layer, disposed on the surface of the collector layer facing the first direction, contains a compound semiconductor of a second conductivity type opposite to the first conductivity type;

[0125] At least one emitter mesa, disposed in a local region of the surface of the base layer facing the first direction, contains a compound semiconductor of the first conductivity type, and a heterojunction is formed between the emitter mesa and the base layer;

[0126] A current collector electrode, which is disposed on the surface of the current collector layer facing a second direction that is opposite to the first direction;

[0127] An emitter electrode, disposed on the surface of the emitter mesa facing the first direction; and

[0128] The base electrode is disposed in the region of the base layer's surface facing the first direction, where the emitter mesa is not located.

[0129] The base electrode includes a first layer and a second layer, a portion of the first layer overlaps with a portion of the second layer, neither the first layer nor the second layer is included in the closed pattern when viewed from above, and the first layer and the second layer as a whole continuously surround the emitter platform when viewed from above.

[0130] <2> The semiconductor device according to <1>, wherein,

[0131] The emitter platform has a circular, square, rectangular, or regular hexagonal shape when viewed from above.

[0132] <3> The semiconductor device according to <1>, wherein,

[0133] The emitter platforms are discretely arranged in multiple ways.

[0134] The base electrode continuously surrounds each of the emitter tertices in the emitter tertices, and the portion of the base electrode disposed between two adjacent emitter tertices is shared as a portion surrounding the emitter tertices on both sides.

[0135] <4> The semiconductor device according to <3>, wherein,

[0136] At least a portion of the base electrode, when viewed from above, has a lattice-like shape with orthogonal vertical and horizontal lines.

[0137] The plurality of emitter platforms are respectively arranged in a grid-like pattern within multiple partitions enclosed by vertical and horizontal lines.

[0138] <5> The semiconductor device according to <3>, wherein,

[0139] At least a portion of the base electrode has a honeycomb shape when viewed from above.

[0140] The multiple emitter platforms are respectively arranged in multiple honeycomb-shaped partitions.

[0141] <6> The semiconductor device according to <4> or <5>, wherein,

[0142] When viewed from above, the outer periphery of each of the plurality of emitter mesa faces the edge of the base electrode with a gap between them, and has a shape along the edge of the base electrode.

[0143] <7> The semiconductor device according to any one of <3> to <6>, wherein,

[0144] The emitter mesa includes a ballast resistor layer.

[0145] <8> The semiconductor device according to any one of <1> to <7>, wherein,

[0146] The semiconductor device also includes emitter pads for external circuit connections.

[0147] The emitter pad is positioned on the first direction side when viewed from the emitter electrode, and is positioned at a location that partially overlaps with the emitter electrode when viewed from above.

[0148] <9> The semiconductor device according to any one of <1> to <8>, wherein,

[0149] The semiconductor device further includes a support substrate disposed on the surface of the collector electrode facing the second direction, the support substrate having a higher thermal conductivity than the collector electrode layer.

[0150] <10> The semiconductor device according to <9>, wherein,

[0151] The semiconductor device also includes:

[0152] Collector wiring, disposed on the surface of the support substrate facing the first direction, electrically connected to the collector electrode, and extending to the outside of the collector electrode when viewed from above; and

[0153] The collector pad for external circuit connection is disposed on the first direction side when viewed from the collector wiring, and disposed at a position on the collector wiring that does not overlap with the collector electrode when viewed from above, and is electrically connected to the collector wiring.

[0154] <11> The semiconductor device according to <9>, wherein,

[0155] The semiconductor device also includes:

[0156] A multilayer wiring layer disposed on the surface of the support substrate facing the first direction;

[0157] Collector wiring, disposed on the surface of the multilayer wiring layer facing the first direction, and electrically connected to the collector electrode; and

[0158] Electronic circuitry, which is disposed on the supporting substrate,

[0159] The multilayer wiring layer includes wiring that electrically connects the collector wiring to the electronic circuit.

[0160] <12> A method for manufacturing a semiconductor device, wherein,

[0161] A release layer is formed on the surface of the temporary substrate facing the first direction.

[0162] A collector layer containing a compound semiconductor of a first conductivity type is formed on the surface of the release layer facing the first direction.

[0163] A base layer containing a compound semiconductor with a second conductivity type opposite to the first conductivity type is formed on the surface of the collector layer facing the first direction.

[0164] At least one emitter mesa containing the first conductivity type of a compound semiconductor is formed on the surface of the base layer facing the first direction.

[0165] A base electrode is formed on the surface of the base layer facing the first direction, which continuously surrounds the emitter mesa when viewed from above.

[0166] An emitter electrode is formed on the surface of the emitter mesa facing the first direction.

[0167] The collector layer is separated from the temporary substrate by etching to remove the release layer.

[0168] A current collector electrode is formed on the surface of the current collector layer in a second direction, which is opposite to the first direction.

[0169] The collector electrode is bonded to the support substrate.

[0170] <13> The method for manufacturing a semiconductor device according to <12>, wherein,

[0171] The base electrode comprises two layers, a first layer and a second layer. Neither the first layer nor the second layer includes a closed pattern. The first layer and the second layer continuously surround the emitter mesa.

[0172] When forming the base electrode, the first layer is formed using a stripping process, and the second layer is formed using other stripping processes.

Claims

1. A semiconductor device, wherein, This semiconductor device has: Collector layer, which contains a compound semiconductor of conductivity type 1; The base layer, disposed on the surface of the collector layer facing the first direction, contains a compound semiconductor of a second conductivity type opposite to the first conductivity type; At least one emitter mesa, disposed in a local region of the surface of the base layer facing the first direction, contains a compound semiconductor of the first conductivity type, and a heterojunction is formed between the emitter mesa and the base layer; A current collector electrode, which is disposed on the surface of the current collector layer facing a second direction that is opposite to the first direction; An emitter electrode, disposed on the surface of the emitter mesa facing the first direction; as well as The base electrode is disposed in the region of the base layer's surface facing the first direction, where the emitter mesa is not located. The base electrode includes a first layer and a second layer, a portion of the first layer overlaps with a portion of the second layer, neither the first layer nor the second layer is included in the closed pattern when viewed from above, and the first layer and the second layer as a whole continuously surround the emitter platform when viewed from above.

2. The semiconductor device according to claim 1, wherein, The emitter platform has a circular, square, rectangular, or regular hexagonal shape when viewed from above.

3. The semiconductor device according to claim 1, wherein, The emitter platforms are discretely arranged in multiple ways. The base electrode continuously surrounds each of the emitter mesa. The portion of the base electrode disposed between two adjacent emitter mesa is shared as a portion surrounding the emitter mesa on both sides.

4. The semiconductor device according to claim 3, wherein, At least a portion of the base electrode, when viewed from above, has a lattice-like shape with orthogonal vertical and horizontal lines. The plurality of emitter platforms are respectively arranged in a grid-like pattern within multiple partitions enclosed by vertical and horizontal lines.

5. The semiconductor device according to claim 3, wherein, At least a portion of the base electrode has a honeycomb shape when viewed from above. The multiple emitter platforms are respectively arranged in multiple honeycomb-shaped partitions.

6. The semiconductor device according to claim 4 or 5, wherein, When viewed from above, the outer periphery of each of the plurality of emitter mesa faces the edge of the base electrode with a gap between them, and has a shape along the edge of the base electrode.

7. The semiconductor device according to any one of claims 3 to 6, wherein, The emitter mesa includes a ballast resistor layer.

8. The semiconductor device according to any one of claims 1 to 7, wherein, The semiconductor device also includes emitter pads for external circuit connections. The emitter pad is positioned on the first direction side when viewed from the emitter electrode, and is positioned at a location that partially overlaps with the emitter electrode when viewed from above.

9. The semiconductor device according to any one of claims 1 to 8, wherein, The semiconductor device further includes a support substrate disposed on the surface of the collector electrode facing the second direction. The thermal conductivity of the support substrate is higher than that of the collector layer.

10. The semiconductor device according to claim 9, wherein, The semiconductor device also includes: Collector wiring, disposed on the surface of the support substrate facing the first direction, electrically connected to the collector electrode, and extending to the outside of the collector electrode when viewed from above; and The collector pad for external circuit connection is disposed on the first direction side when viewed from the collector wiring, and disposed at a position on the collector wiring that does not overlap with the collector electrode when viewed from above, and is electrically connected to the collector wiring.

11. The semiconductor device according to claim 9, wherein, The semiconductor device also includes: A multilayer wiring layer disposed on the surface of the support substrate facing the first direction; Collector wiring, disposed on the surface of the multilayer wiring layer facing the first direction, and electrically connected to the collector electrode; and Electronic circuitry, which is disposed on the supporting substrate, The multilayer wiring layer includes wiring that electrically connects the collector wiring to the electronic circuit.

12. A method for manufacturing a semiconductor device, wherein, A release layer is formed on the surface of the temporary substrate facing the first direction. A collector layer containing a compound semiconductor of a first conductivity type is formed on the surface of the release layer facing the first direction. A base layer containing a compound semiconductor with a second conductivity type opposite to the first conductivity type is formed on the surface of the collector layer facing the first direction. At least one emitter mesa containing the first conductivity type of a compound semiconductor is formed on the surface of the base layer facing the first direction. A base electrode is formed on the surface of the base layer facing the first direction, which continuously surrounds the emitter mesa when viewed from above. An emitter electrode is formed on the surface of the emitter mesa facing the first direction. The collector layer is separated from the temporary substrate by etching to remove the release layer. A current collector electrode is formed on the surface of the current collector layer in a second direction, which is opposite to the first direction. The collector electrode is bonded to the support substrate.

13. The method for manufacturing a semiconductor device according to claim 12, wherein, The base electrode comprises two layers, a first layer and a second layer. Neither the first layer nor the second layer includes a closed pattern. The first layer and the second layer continuously surround the emitter mesa. When forming the base electrode, the first layer is formed using a stripping process, and the second layer is formed using other stripping processes.

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