Semiconductor device and method for manufacturing semiconductor device

Abstract

The invention provides a semiconductor device and a manufacturing method of the semiconductor device, which can improve current density of collector current and in-plane uniformity in a collector mesa. A base layer, which includes a compound semiconductor of a second conductivity type opposite to the first conductivity type and is heterojunction with an emitter layer, is disposed on a surface facing the first direction of the emitter layer including the compound semiconductor of the first conductivity type. At least one collector mesa containing a compound semiconductor of a first conductivity type is disposed on a surface of the base layer facing the first direction. An emitter electrode is disposed on a surface of the emitter layer in a second direction opposite to the first direction. A base electrode continuously surrounding the collector mesa in plan view is disposed on a surface of the base layer facing the first direction. A collector electrode is disposed on a surface of the collector mesa facing the first direction.

Description

Technical Field

[0001] This invention relates to a semiconductor device and a method for manufacturing a semiconductor device. Background Technology

[0002] Heterojunction bipolar transistors (HBTs) with a base layer disposed on a collector layer and an emitter mesa disposed on the base layer are known (Patent Document 1). In addition, Patent Document 1 mentions a collector-on-top structure with a base layer disposed on an emitter layer and a collector mesa disposed on a base layer.

[0003] In an HBT with the collector layer disposed on the substrate side, a base electrode is disposed such that it clamps the emitter mesa from both sides when viewed from above, and a collector electrode is disposed at a position outside the base electrode. In a collector-top configuration, the base electrode is disposed such that it clamps the collector mesa from both sides, and an emitter electrode is disposed at a position outside the base electrode.

[0004] Existing technical documents

[0005] Patent documents

[0006] Patent Document 1: Japanese Patent Application Publication No. 5-243257 Summary of the Invention

[0007] The problem the invention aims to solve

[0008] In the HBT disclosed in Patent Document 1, when viewed from the collector mesa in a top view, the base electrodes are arranged in two opposite directions, while no base electrodes are arranged in two directions orthogonal to these directions. Thus, there are directions with and without base electrodes, resulting in reduced in-plane uniformity of the collector current density within the collector mesa. In a structure with reduced in-plane uniformity of the collector current density, it is difficult to improve breakdown resistance.

[0009] The object of the present invention is to provide a semiconductor device and a method thereof that can improve the current density of the collector current and the in-plane uniformity of the collector mesa.

[0010] Solution for solving the problem

[0011] According to one aspect of the present invention, a semiconductor device is provided, comprising: an emitter layer containing a compound semiconductor of a first conductivity type; a base layer disposed on a surface of the emitter layer facing a first direction, containing a compound semiconductor of a second conductivity type opposite to the first conductivity type, wherein the base layer and the emitter layer are in a heterojunction; at least one collector mesa disposed on the surface of the base layer facing the first direction, containing the compound semiconductor of the first conductivity type; an emitter electrode disposed on a surface of the emitter layer facing a second direction opposite to the first direction; a base electrode disposed on the surface of the base layer facing the first direction, continuously surrounding the collector mesa when viewed from above; and a collector electrode disposed on the surface of the collector mesa facing the first direction.

[0012] According to another aspect of the present invention, a method for manufacturing a semiconductor device is provided, wherein a release layer is formed on a surface of a temporary substrate facing a first direction; an emitter layer containing a compound semiconductor of a first conductivity type is formed on the surface of the release layer facing the first direction; a base layer containing a compound semiconductor of a second conductivity type opposite to the first conductivity type is formed on the surface of the emitter layer facing the first direction; at least one collector mesa containing the compound semiconductor of the first conductivity type is formed on the surface of the base layer facing the first direction; a base electrode is formed on the surface of the base layer facing the first direction; a collector electrode is formed on the surface of the collector mesa facing the first direction; the release layer is removed by etching to separate the emitter layer from the temporary substrate; an emitter electrode is formed on the surface of the emitter layer facing a second direction opposite to the first direction; and the emitter electrode is bonded to a support substrate.

[0013] The effects of the invention

[0014] When viewed from above, the base electrode continuously surrounds the collector mesa, thus increasing the symmetry of the shape formed by the base electrode and the collector mesa. As a result, the in-plane uniformity of the collector current density and the collector mesa is improved. Attached Figure Description

[0015] Figure 1 This is a top view of the semiconductor device of the first embodiment.

[0016] Figure 2 yes Figure 1 The sectional view at point 2-2, marked by a single-dotted line.

[0017] Figure 3A , Figure 3B ,as well as Figure 3C This is a cross-sectional view of the semiconductor device of the first embodiment during a manufacturing process.

[0018] Figure 4A This is a top view of the semiconductor device of the first embodiment during a manufacturing stage. Figure 4B yes Figure 4A A cross-sectional view at point 4B-4B, marked by a single-dotted line.

[0019] Figure 5A This is a top view of the semiconductor device of the first embodiment during a manufacturing stage. Figure 5B yes Figure 5A A cross-sectional view at point 5B-5B, marked by a single-dotted line.

[0020] Figure 6 This is a top view of a semiconductor device according to a variation of the first embodiment.

[0021] Figure 7 This is a top view of a semiconductor device, which is another variation of the first embodiment.

[0022] Figure 8 This is a top view of the semiconductor device of the second embodiment.

[0023] Figure 9A and Figure 9B These are top views of the first layer 30B1 and the second layer 30B2 of the base electrode 30B of the semiconductor device of the second embodiment.

[0024] Figure 10 yes Figure 8 A cross-sectional view at point 10-10, indicated by a single-dotted line.

[0025] Figure 11 This is a top view of a semiconductor device of a modified embodiment of the second embodiment.

[0026] Figure 12A and Figure 12B These are top views of the first layer 30B1 and the second layer 30B2 of the semiconductor device in the modified example of the second embodiment.

[0027] Figure 13 This is a top view of the semiconductor device of the third embodiment.

[0028] Figure 14 This is a cross-sectional view of the semiconductor device of the fourth embodiment.

[0029] Figure 15A and Figure 15B This is a cross-sectional view of the semiconductor device of the fourth embodiment during the manufacturing process.

[0030] Figure 16 This is a cross-sectional view of the semiconductor device of the fifth embodiment.

[0031] Explanation of reference numerals in the attached figures

[0032] 20. Heterojunction Bipolar Transistor (HBT); 20B. Base layer; 20C. Collector mesa; 20E. Emitter layer; 30B. Base electrode; 30B1. First layer of base electrode; 30B2. Second layer of base electrode; 30C. Collector electrode; 30E. Emitter electrode; 41B, 41B1, 41B2. Base wiring; 41Bias. Bias wiring; 41BR. Base ballast resistor element; 41C. Collector wiring; 42C. Collector Wiring; 42E, Emitter wiring; 42RF, Signal input wiring; 43, Input capacitor; 45C, Collector pad; 45E, Emitter pad; 50, Cell; 60, Support substrate; 61E, Emitter wiring; 65, Multilayer wiring layer; 65G, Ground conductor; 65V, Via; 80, 81, Resist film; 90, Temporary substrate; 91, Release layer; D1, First direction; D2, Second direction; H1, H2, Openings; OVP, Overlapping area. Detailed Implementation

[0033] [First Embodiment]

[0034] Reference from Figures 1 to 5B The semiconductor device of the first embodiment will be described with reference to the accompanying drawings. Figure 1 This is a top view of the semiconductor device of the first embodiment. Figure 2 yes Figure 1 A cross-sectional view at point 2-2, marked by a single-dotted line. Furthermore, in... Figure 2 The description of the interlayer insulating film is omitted.

[0035] On the surface of the emitter layer 20E facing the first direction D1 (in Figure 1 The center is the surface facing forward. Figure 2 A base layer 20B is disposed in a localized area of ​​the surface (facing upwards). A collector mesa 20C is disposed on the surface of the base layer 20B facing the first direction D1. The base layer 20B and the collector mesa 20C are circular when viewed from above. In this specification, the surface facing the first direction D1 of various parts may be referred to as the upper surface.

[0036] The emitter layer 20E contains a compound semiconductor of a first conductivity type, and the base layer 20B contains a compound semiconductor of a second conductivity type, opposite to the first conductivity type. Here, "first conductivity type" and "second conductivity type" mean that one is an n-type conductivity type and the other is a p-type conductivity type. The collector mesa 20C contains a compound semiconductor of the first conductivity type. The heterojunction is formed by the emitter layer 20E and the base layer 20B. For example, the emitter layer 20E is formed of n-type InGaP, the base layer 20B is formed of p-type GaAs, and the collector mesa 20C is formed of n-type GaAs. The emitter layer 20E, the base layer 20B, and the collector mesa 20C constitute a heterojunction bipolar transistor 20 (HBT).

[0037] Alternatively, the etch stop layer can be disposed over the entire area of ​​the upper surface of the base layer 20B, and the collector mesa 20C can be disposed on top of the etch stop layer. The etch stop layer is formed of a semiconductor material with different etch resistance than the collector mesa 20C. For example, when n-type GaAs is used for the collector mesa 20C, n-type InGaP, n-type AlAs, etc., are used for the etch stop layer.

[0038] Collector electrodes 30C are disposed over the entire area of ​​the upper surface of the collector mesa 20C. Figure 1 In the image, collector electrode 30C is shaded in the upper right corner. Collector electrode 30C makes ohmic contact with collector mesa 20C. Collector electrode 30C and collector mesa 20C are patterned using, for example, a self-aligned process.

[0039] A base electrode 30B is disposed in a region of the base layer 20B facing the first direction D1, where no collector mesa 20C is disposed. The base electrode 30B makes ohmic contact with the base layer 20B. When an etch stop layer is disposed on the upper surface of the base layer 20B, the base electrode 30B penetrates the etch stop layer in the thickness direction to reach the base layer 20B.

[0040] The base electrode 30B continuously surrounds the collector mesa 20C when viewed from above. That is, the collector mesa 20C is disposed within a closed pattern formed by the base electrode 30B. Here, a "closed pattern" refers to a pattern that returns to its original position when a point is moved in one direction along the pattern. The spacing between the outer perimeter of the collector mesa 20C and the inner perimeter of the base electrode 30B is approximately constant in the circumferential direction. The collector mesa 20C is processed using, for example, dry etching.

[0041] The base electrode 30B includes a first layer 30B1 and a second layer 30B2. Figure 1In the diagram, layer 1 (30B1) has a lower right shaded line, and layer 2 (30B2) has an upper right shaded line. A portion of layer 1 (30B1) overlaps with a portion of layer 2 (30B2). Neither layer 1 (30B1) nor layer 2 (30B2) is included in the closed pattern when viewed from above. Layer 1 (30B1) and layer 2 (30B2) together continuously surround the collector mesa 20C when viewed from above.

[0042] For example, layers 30B1 and 30B2, when viewed from above, are arcs along a common circumference, with their ends overlapping each other. That is, the sum of the central angles of the arcs along which layers 30B1 and 30B2 are located is greater than 360°. In the overlapping region OVP, layer 30B1 is positioned closer to the base layer 20B than layer 30B2.

[0043] The top of the base wiring 41B of the first layer overlaps with a portion of the upper surface of the base electrode 30B, and the base wiring 41B extends to the outside of the base layer 20B when viewed from above. The collector wiring 41C of the first layer is disposed on the upper surface of the collector electrode 30C. A collector pad 45C for external circuit connection is disposed on the upper surface of the collector wiring 41C. Figure 1 The description of collector wiring 41C and collector pad 45C is omitted.

[0044] An emitter electrode 30E is disposed on the surface of the emitter layer 20E facing the second direction D2, which is opposite to the first direction D1. The emitter electrode 30E makes ohmic contact with the emitter layer 20E. In this specification, the surface of various parts facing the second direction D2 may be referred to as the "lower surface".

[0045] Next, refer to Figure 3A , Figure 3B ,as well as Figure 3C The manufacturing method of the semiconductor device of the first embodiment will be described. Figure 3A , Figure 3B ,as well as Figure 3C This is a cross-sectional view of the semiconductor device of the first embodiment during a manufacturing process.

[0046] like Figure 3A As shown, a release layer 91 is epitaxially grown on a temporary substrate 90 formed of a compound semiconductor. An emitter layer 20E is further epitaxially grown on the release layer 91. A device structure including a base layer 20B, a collector mesa 20C, a base electrode 30B, a collector electrode 30C, a first-layer base wiring 41B, and a collector wiring 41C is formed on the upper surface of the emitter layer 20E. These formations can be achieved using conventional semiconductor processes. (The following refers to...) Figures 4A to 5B The accompanying drawings illustrate in detail the sequence used to form the base electrode 30B.

[0047] In this stage, the emitter layer 20E is disposed over the entire area of ​​the upper surface of the temporary substrate 90, and multiple semiconductor device element structures (chips) are disposed on the upper surface of the emitter layer 20E. Figure 3A Only one chip section is shown in the diagram. In addition, the chip also includes multiple heterojunction bipolar transistors 20 and other passive components (not shown).

[0048] like Figure 3B As shown, each chip is segmented by patterning the emitter layer 20E and the release layer 91. In this stage, multiple chips are supported on a general-purpose temporary substrate 90. A protective tape (not shown) is attached to the upper surface of the multiple chips. The multiple chips are connected by the protective tape.

[0049] By selectively etching away the release layer 91, the chip, including the emitter layer 20E, is peeled off from the temporary substrate 90. Multiple chips are then connected by a protective strip.

[0050] like Figure 3C As shown, an emitter electrode 30E is formed on the lower surface of the emitter layer 20E. As an example, after forming the emitter electrode 30E, each chip is peeled off from the protective strip, and the emitter electrode 30E is bonded to a support substrate, etc. After the chips are bonded to the support substrate, a collector pad 45C is formed. Figure 2 )wait.

[0051] Next, refer to from Figures 4A to 5B The order of forming the base electrode 30B is explained in the attached figure. Figure 4A and Figure 5A This is a top view of a stage in the manufacturing process of a semiconductor device. Figure 4B and Figure 5B They are Figure 4A The single-dot dashed line 4B-4B and Figure 5A A cross-sectional view at the dashed line 5B-5B. A stripping process was used to form the base electrode 30B.

[0052] like Figure 4B As shown, after forming the collector electrode 30C and the collector mesa 20C, a resist film 80 is formed covering the emitter layer 20E, the base layer 20B, the collector mesa 20C, and the collector electrode 30C. Then, an opening H1 aligned with the planar pattern of the first layer 30B1 of the base electrode 30B is formed in the resist film 80. A conductive film is formed on the upper surface of the base layer 20B exposed at the bottom of the opening H1 and on the upper surface of the resist film 80. The resist film 80 is removed along with the conductive film covering the upper surface of the resist film 80. Thus, the first layer 30B1 of the base electrode 30B remains on the upper surface of the base layer 20B. Figure 4AAs shown, layer 1 30B1 does not include the closed pattern when viewed from above.

[0053] like Figure 5B As shown, after forming the first layer 30B1 of the base electrode 30B, a resist film 81 is formed covering the emitter layer 20E, the base layer 20B, the collector mesa 20C, the collector electrode 30C, and the first layer 30B1. Then, an opening H2 is formed in the resist film 81, aligned with the planar pattern of the second layer 30B2 of the base electrode 30B. In the overlapping region OVP ( Figure 5A In the first layer 30B1, the first layer is exposed within the opening H2, while in other regions, the base layer 20B is exposed.

[0054] A conductive film is formed on the upper surface of the base layer 20B and the first layer 30B1 exposed at the bottom surface of the opening H2, and on the upper surface of the resist film 81. The resist film 81 is removed along with the conductive film covering the upper surface of the resist film 81. As a result, the second layer 30B2 of the base electrode 30B remains on the upper surface of the base layer 20B and in the overlapping region OVP. Figure 5A As shown, layer 2 30B2 is not included in the closed pattern when viewed from above. In addition, layer 1 30B1 and layer 2 30B2 form a closed pattern overall.

[0055] Next, the superior effects of the first embodiment will be explained.

[0056] In the semiconductor device of the first embodiment, when viewed from above, the collector mesa 20C is circular, and the base electrode 30B ( Figure 1 The base electrode 30B is continuously surrounded by the collector mesa 20C, thus the entire area of ​​the outer periphery of the collector mesa 20C is arranged opposite to it. That is, the base electrode 30B is arranged in all directions when viewed from the collector mesa 20C, thereby improving the symmetry of the shapes of the collector mesa 20C and the base electrode 30B when viewed from above. Therefore, the in-plane uniformity of the collector current density within the collector mesa 20C is improved. The collector current is less likely to concentrate in specific locations, thus achieving excellent results such as improved breakdown resistance of the heterojunction bipolar transistor 20.

[0057] In addition, the emitter electrode 30E, which is formed of a metallic material, is disposed over the entire area of ​​the lower surface of the emitter layer 20E, thereby suppressing the increase in resistance of the current path from the external circuit to the emitter layer 20E.

[0058] Furthermore, in the first embodiment, the base electrode 30B is arranged opposite to the entire area of ​​the outer periphery of the collector mesa 20C. In contrast, in a structure where the base electrode is arranged on both sides of the collector mesa, an opposing base electrode is not arranged for a portion of the outer periphery of the collector mesa. Therefore, in the semiconductor device of the first embodiment, the base electrode resistance can be reduced compared to a structure where the base electrode is arranged on both sides of the collector mesa.

[0059] Furthermore, in the first embodiment, the first layer 30B1 and the second layer 30B2 of the base electrode 30B are formed using different stripping processes. Therefore, the conductor pattern formed in a single stripping process should not include closed patterns. Generally, when the conductor pattern formed using a stripping process includes closed patterns, there is a tendency for a decrease in yield. In the first embodiment, the base electrode 30B including closed patterns is formed using two stripping processes, thus suppressing the decrease in yield.

[0060] Furthermore, in the heterojunction bipolar transistor 20 of the first embodiment, a collector mesa 20C is disposed thereon. Figure 1 A parasitic capacitance Cbc is generated between the base and collector in the region where the base electrode 30B is located. Since there is no base-collector junction interface in the region where the base electrode 30B is disposed, the area occupied by the base electrode 30B is not the main cause of the increase in the parasitic capacitance Cbc between the base and collector. Therefore, by making the base electrode 30B a closed ring shape, even if the area occupied by the base electrode 30B is increased, the increase in the parasitic capacitance Cbc between the base and collector can be avoided.

[0061] Next, refer to Figure 6 and Figure 7 The semiconductor device of the modified example of the first embodiment will be described. Figure 6 and Figure 7 This is a top view of a semiconductor device according to a variation of the first embodiment. In the first embodiment ( Figure 1 In the diagram, when viewed from above, the pattern of the base electrode 30B is a closed pattern along the circumference, or it can be other closed patterns.

[0062] exist Figure 6 In the modified example shown, when viewed from above, the pattern of the base electrode 30B is a closed pattern along the outer perimeter of a square. Figure 6 In the example shown, the overlapping area OVP is positioned approximately at the midpoint of a pair of opposite sides of the square; it could also be positioned elsewhere. Figure 7 In the modified example shown, when viewed from above, the pattern of the base electrode 30B is a closed pattern along the outer periphery of a regular hexagon. Figure 7In the example shown, the overlapping region OVP is positioned at the midpoint of a pair of opposite sides of the regular hexagon; it could also be positioned elsewhere. The pattern of the base electrode 30B is reflected in the shape of the collector mesa 20C when viewed from above. For example, in Figure 6 In the variant shown, the collector mesa 20C is square in shape. Figure 7 In the variant shown, the collector mesa 20C is a regular hexagon.

[0063] Next, the superior effects of the first embodiment and its modifications will be explained. If, as in the first embodiment ( Figure 1 By designing the collector mesa 20C as a circle, the symmetry of the shapes of the collector mesa 20C and the base electrode 30B when viewed from above is maximized. Furthermore, the length of the current path from the outer periphery of the collector mesa 20C to the base electrode 30B remains approximately constant throughout the entire outer periphery of the collector mesa 20C. Therefore, this is advantageous from the perspective of improving the uniformity of the collector current density within the surface of the collector mesa 20C.

[0064] On the other hand, Figure 6 and Figure 7 In the modified example shown, as will be explained later in the second embodiment, the structure consisting of the base electrode 30B and the collector mesa 20C can be completely covered in the two-dimensional plane. Therefore, in a structure with multiple collector mesa 20Cs, Figure 6 and Figure 7 The variant shown excels in space utilization efficiency.

[0065] exist Figure 6 The image shows an example where the base electrode 30B is along the outer perimeter of a square. Figure 7 The diagram shows an example where the base electrode 30B is along the outer periphery of a regular hexagon, but the "square" or "regular hexagon" need not be geometrically strictly square or regular hexagonal. It can also be a shape slightly skewed relative to a square or regular hexagon. For example, skewness relative to a square or regular hexagon is permissible within a range that maintains sufficient in-plane uniformity within the collector mesa 20C to sustain the current density of the collector current.

[0066] To increase output, multiple... Figure 1 , Figure 6 , Figure 7 The heterojunction bipolar transistors 20 shown are connected in parallel. In this case, to suppress thermal runaway, it is preferable to connect a base ballast resistor to each heterojunction bipolar transistor 20.

[0067] [Second Embodiment]

[0068] Next, refer to from Figures 8 to 10The semiconductor device of the second embodiment will be described with reference to the accompanying drawings. Hereinafter, the semiconductor device will be described with reference to the accompanying drawings. Figures 1 to 7 The semiconductor device of the first embodiment and its modifications, as illustrated in the accompanying drawings, has a general structure, and the description is omitted.

[0069] Figure 8 This is a top view of the semiconductor device of the second embodiment. In the first embodiment ( Figure 1 In the first embodiment, there is only one collector mesa 20C. In the second embodiment, multiple collector mesa 20Cs are discretely arranged. The base electrode 30B continuously surrounds each of the multiple collector mesa 20Cs. The portion of the base electrode 30B disposed between two adjacent collector mesa 20Cs is shared as a portion surrounding the collector mesa 20Cs on both sides.

[0070] More specifically, the base electrode 30B is arranged in a square grid pattern with orthogonal vertical and horizontal lines. Collector mesa 20Cs are respectively disposed within multiple partitions (cells) of the grid pattern separated by vertical and horizontal lines. When viewed from above, the outer perimeters of each collector mesa 20C are spaced apart and aligned with the edge of the base electrode 30B, exhibiting a shape along the edge of the base electrode 30B. Since the multiple partitions separated by the orthogonal grid pattern are each square, the collector mesa 20C also has a square shape when viewed from above.

[0071] The base electrode 30B, like in the first embodiment, includes a first layer 30B1 and a second layer 30B2. Figure 8 In the diagram, the first layer 30B1 has a shaded line at the upper right, and the second layer 30B2 has a shaded line at the lower right. Furthermore, the collector electrode 30C also has a shaded line at the upper right.

[0072] Figure 9A and Figure 9B These are top views of the first layer 30B1 and the second layer 30B2 of the base electrode 30B, respectively. The first layer 30B1... Figure 9A ) and 2nd floor 30B2 ( Figure 9B Each layer has a pattern with horizontal and vertical lines that resemble a square grid. At the grid point where the horizontal and vertical lines intersect (overlapping area OVP), layer 1 30B1 overlaps with layer 2 30B2. Neither layer 1 30B1 nor layer 2 30B2 contains closed patterns.

[0073] The outermost portion of the base electrode 30B, which appears as a grid when viewed from above, is widened, and the base wiring 41B of the first layer is connected to the widened portion. Figure 8 The base wiring 41B, when viewed from above, does not intersect with either the collector mesa 20C or either the collector electrode 30C, and extends to the outside of the base layer 20B.

[0074] Figure 10 yes Figure 8 A cross-sectional view at the dashed line 10-10. Multiple collector mesa surfaces 20C are disposed on the upper surface of the base layer 20B. Figure 10 The cross-section shown presents two collector mesa 20Cs. A collector electrode 30C is disposed on the upper surface of each collector mesa 20C. A first-layer collector wiring 41C electrically connects the multiple collector electrodes 30Cs to each other. A collector pad 45C is disposed on the upper surface of the collector wiring 41C.

[0075] The base wiring 41B of the first layer is electrically connected to the outermost portion of the base electrode 30B. The base wiring 41B intersects the edge of the base layer 20B and extends to the outside of the base layer 20B when viewed from above.

[0076] Next, the superior effects of the second embodiment will be explained.

[0077] In the second embodiment, similarly to the first embodiment, the base electrode 30B is arranged opposite to the entire area of ​​the outer periphery of the collector mesa 20C. Therefore, in each collector mesa 20C, the in-plane uniformity of the collector current density within the collector mesa 20C can be improved. Furthermore, neither the first layer 30B1 nor the second layer 30B2 of the base electrode 30B includes a closed pattern when viewed from above, thus suppressing the reduction in yield during the formation process of the base electrode 30B.

[0078] Furthermore, the multiple collector mesa 20Cs are discretely distributed, thus allowing the base electrodes 30B to be electrically continuous within the same layer. The base wiring 41B of the first layer does not intersect with any of the multiple collector electrodes 30C when viewed from above; therefore, all the collector electrodes 30Cs can be electrically connected to each other using collector wiring 41C disposed on the same conductor layer as the base wiring 41B of the first layer. Moreover, the collector pads 45C disposed on the upper surface of the collector wiring 41C can be electrically connected to the collector mesa 20C via the shortest path. For example, when viewed from above, the collector wiring 41C and the collector pads 45C can be disposed in the region overlapping with the collector mesa 20C and the collector electrodes 30C.

[0079] In addition, the base electrode 30B can be formed by vertical and horizontal lines. Figure 8 When designing patterns using CAD, slanted lines cannot fall on the grid that serves as the reference for pattern configuration, thus creating layout difficulties. In the second embodiment, the pattern of the base electrode 30B can be designed using only vertical and horizontal lines, thus achieving the excellent effect of easy layout of the base electrode 30B.

[0080] In the second embodiment, the base electrode 30B is configured as a lattice with orthogonal vertical and horizontal lines. The vertical and horizontal lines do not need to be geometrically strictly orthogonal; they can be slightly deviated from the orthogonal relationship, provided that sufficient in-plane uniformity in the collector mesa 20C is maintained to ensure the current density of the collector current is within acceptable limits. Similarly, the partitions separated by the base electrode 30B can be slightly skewed relative to a square.

[0081] Next, refer to Figure 11 , Figure 12A ,as well as Figure 12B The semiconductor device of the modified example of the second embodiment will be described.

[0082] Figure 11 This is a top view of a semiconductor device according to a variation of the second embodiment. In the second embodiment ( Figure 8 In this embodiment, the base electrode 30B is a square grid with orthogonal vertical and horizontal lines. In this modified example, the base electrode 30B is honeycomb-shaped. Multiple hexagonal partitions (cells) are formed, separated by the base electrodes 30B. Collector mesa 20C and collector electrodes 30C are respectively disposed in each of the multiple partitions. The top view of each collector mesa 20C and collector electrode 30C is a regular hexagon reflecting the shape of the partition. The base electrode 30B, like in the second embodiment, includes a first layer 30B1 and a second layer 30B2.

[0083] Figure 12A and Figure 12B These are top views of floor 1, 30B1, and floor 2, 30B2, respectively. (Example) Figure 12A As shown, the first layer 30B1 is formed by the base electrode 30B along one direction (in Figure 11 , Figure 12A The middle part is composed of multiple parts of a horizontally parallel regular hexagon. For example... Figure 12B As shown, the second layer 30B2 is composed of multiple portions along the six sides of a regular hexagon, excluding the sides along which the first layer 30B1 is located. That is, the second layer 30B2 extends in a zigzag shape in a direction orthogonal to the respective length direction of the first layer 30B1. The ends of each of the first layers 30B1 overlap with the corner portions of the zigzag-shaped second layer 30B2.

[0084] As in this modified example, the base electrode 30B can also be honeycomb shaped. Also in this modified example, neither the first layer 30B1 nor the second layer 30B2 is included in the closed pattern when viewed from above.

[0085] Furthermore, the multiple partitions separated by the base electrode 30B do not necessarily have to be regular hexagons. Under the condition that sufficient in-plane uniformity within the collector mesa 20C can be maintained to ensure the current density of the collector current, they can also be made into convex hexagons by slightly distorting the regular hexagons.

[0086] [Third Embodiment]

[0087] Next, refer to Figure 13 The semiconductor device of the third embodiment will now be described. Hereinafter, the device will be described in relation to the referenced semiconductor device. Figure 11 , Figure 12A , Figure 12B The semiconductor device of the modified example of the second embodiment described herein has a general structure, and the description is omitted.

[0088] Figure 13 This is a top view of the semiconductor device of the third embodiment. The semiconductor device of the third embodiment includes a plurality of units 50. Each of the plurality of units 50 has a semiconductor device (as described in the modified example of the second embodiment) Figure 11 The same structure. Furthermore, the arrangement of the multiple collector mesa 20C in each of the units 50 is the same as... Figure 11 The configuration of the collector mesa 20C of the semiconductor device in the modified embodiment of the second embodiment shown is different. A base electrode 30B is provided for each cell 50, and the base electrodes 30B are not directly connected to each other between cells 50.

[0089] Each unit 50 is configured with first-layer base wiring 41B1, 41B2 connected to the base electrode 30B. Multiple base wirings 41B are connected to a general-purpose bias wiring 41Bias via base ballast resistor elements 41BR. Another base wiring 41B2 is connected to a general-purpose signal input wiring 42RF via an input capacitor 43.

[0090] Next, the superior effects of the third embodiment will be explained.

[0091] If the temperature of any one of the units 50 rises, the current concentrates in that unit 50, causing the temperature to rise further and potentially leading to thermal runaway. In the third embodiment, a base ballast resistor element 41BR is provided for each unit 50, thus suppressing the current concentration in the unit 50 where the collector current increases relatively. This results in the excellent effect of minimizing the occurrence of thermal runaway.

[0092] Next, a modified semiconductor device of the third embodiment will be described.

[0093] In the third embodiment, the base electrode 30B of each unit 50 is configured in a honeycomb shape, or as follows: Figure 8The base electrode 30B of the semiconductor device in the second embodiment shown is configured as a square grid with vertical and horizontal lines orthogonal.

[0094] [Example 4]

[0095] Next, refer to Figure 14 , Figure 15A , Figure 15B The semiconductor device of the fourth embodiment will now be described. Hereinafter, the device will be described in relation to the one referenced from... Figures 1 to 13 The semiconductor device structures of the first, second, and third embodiments described with reference to the accompanying drawings are general structures, and descriptions are omitted.

[0096] Figure 14 This is a cross-sectional view of the semiconductor device according to the fourth embodiment. The semiconductor device of the fourth embodiment includes a support substrate 60, which has sufficient support force at a mechanical level. As the support substrate 60, a substrate having a higher thermal conductivity than the emitter layer 20E is used. For example, a silicon-containing substrate (e.g., a silicon substrate) is used as the support substrate 60.

[0097] The semiconductor device of the fourth embodiment includes the semiconductor device of the first embodiment ( Figure 2 The component structure is the same as that of the component structure from the emitter electrode 30E to the collector wiring 41C and base wiring 41B of the first layer. Alternatively, it may include the same component structure as in the second embodiment (…). Figure 8 , Figure 10 ), and variations of the second embodiment ( Figure 11 ), 3rd embodiment ( Figure 13 The component structure is the same as that of semiconductor devices, etc.

[0098] An emitter wiring 61E is disposed on the surface of the support substrate 60 facing the first direction D1. The surface of the emitter electrode 30E of the semiconductor device of the first embodiment facing the second direction D2 is bonded to the emitter wiring 61E, and the emitter electrode 30E is electrically connected to the emitter wiring 61E. In top view, the support substrate 60 is larger than the emitter layer 20E, and the emitter wiring 61E extends to the outside of the emitter electrode 30E.

[0099] Viewed from the emitter wiring 61E, an emitter pad 45E for external circuit connection is arranged on the D1 side in the first direction. When viewed from above, the emitter pad 45E is positioned to overlap with the emitter wiring 61E but not with the emitter electrode 30E or the emitter layer 20E. An emitter wiring 42E is arranged between the emitter pad 45E and the emitter wiring 61E, and the emitter pad 45E is electrically connected to the emitter wiring 61E via the emitter wiring 42E.

[0100] A second-layer collector wiring 42C is disposed on the upper surface of the collector wiring 41C of the first layer, and a collector pad 45C is disposed on the upper surface of the collector wiring 42C of the second layer. The collector pad 45C is electrically connected to the collector electrode 30C via the collector wirings 42C and 41C. The collector wiring 42C and the emitter wiring 42E are disposed in the same wiring layer.

[0101] The semiconductor device of the fourth embodiment has its emitter pad 45E and collector pad 45C mounted on a module substrate or the like, opposite to the module substrate.

[0102] Next, refer to Figure 15A and Figure 15B The manufacturing method of the semiconductor device in the fourth embodiment will be described. Figure 15A and Figure 15B This is a cross-sectional view of the semiconductor device of the fourth embodiment during the manufacturing process.

[0103] like Figure 15A As shown, a device structure is fabricated from the emitter electrode 30E on the lower surface of the emitter layer 20E to the collector wiring 41C and base wiring 41B of the first layer. The fabrication method of this device structure is the same as that described in the reference. Figures 3A to 5B The manufacturing method of the semiconductor device of the first embodiment, which is described with reference to the accompanying drawings, is the same. An emitter wiring 61E is formed on one side of the surface of the support substrate 60.

[0104] like Figure 15B As shown, the emitter electrode 30E is positioned opposite the emitter wiring 61E, and the two are joined together. This joining is achieved by van der Waals bonding, hydrogen bonding, etc. Alternatively, electrostatic forces, covalent bonds, eutectic alloy bonding, etc., can also be used for joining.

[0105] After connecting the emitter electrode 30E to the emitter wiring 61E, as Figure 14 As shown, a second layer of emitter wiring 42E and collector wiring 42C is formed on the surface of the component structure and emitter wiring 61E facing the first direction, and emitter pad 45E and collector pad 45C are also formed. These formations are achieved using a typical multilayer wiring layer formation process.

[0106] Next, the superior effects of the fourth embodiment will be explained.

[0107] In the fourth embodiment, the support substrate 60, in addition to serving as a substrate for mechanically supporting the device structure including the HBT 20, also functions as a heat dissipation path for heat dissipation from the HBT 20. Generally, the thermal conductivity of the compound semiconductor constituting the emitter layer 20E, base layer 20B, and collector mesa 20C of the HBT 20 is lower than that of the silicon-containing support substrate 60. By bonding the device structure including the HBT 20 to the support substrate 60, which has relatively high thermal conductivity, good heat dissipation from the HBT 20 can be ensured.

[0108] Furthermore, the current path from the emitter pad 45E to the emitter layer 20E consists of emitter wirings 42E and 61E and the emitter electrode 30E formed of metallic material, and does not contain semiconductor material. Therefore, the increase in resistance from the emitter layer 20E to the external circuit connected to the emitter layer 20E can be suppressed.

[0109] [Version 5]

[0110] Next, refer to Figure 16 The semiconductor device of the fifth embodiment will now be described. Hereinafter, the device will be described in relation to the referenced semiconductor device. Figure 14 , Figure 15A , Figure 15B The semiconductor device in the fourth embodiment described herein has a general structure, and the description is omitted.

[0111] Figure 16 This is a cross-sectional view of the semiconductor device of the fifth embodiment. In the semiconductor device of the fourth embodiment ( Figure 14 In the first embodiment, when viewed from the emitter wiring 61E, an emitter pad 45E is provided on the first direction D1 side. In contrast, in the fifth embodiment, when viewed from the emitter wiring 61E, no emitter pad is provided on the first direction D1 side.

[0112] A multilayer wiring layer 65 is formed on the surface of the support substrate 60 facing the first direction D1. Emitter wiring 61E is disposed on the surface of the multilayer wiring layer 65 facing the first direction D1. The emitter layer 20E of the HBT20 is electrically connected to the ground conductor 65G in the multilayer wiring layer 65 via the emitter electrode 30E, the emitter wiring 61E, and a plurality of vias 65V in the multilayer wiring layer 65.

[0113] Next, the superior effects of the fifth embodiment will be explained.

[0114] In the fifth embodiment, similarly to the fourth embodiment, the support substrate 60 functions as a heat dissipation path for the HBT20. Furthermore, the emitter of the HBT20 can be connected to the ground conductor 65G formed on the support substrate 60 without the need for external circuit connection pads.

[0115] An emitter electrode 30E, made of a metallic material, is disposed over the entire lower surface region of the emitter layer 20E, and the entire lower surface region of the emitter electrode 30E is connected to the emitter wiring 61E. Furthermore, the emitter wiring 61E is connected to the ground conductor 65G via multiple vias 65V within the multilayer wiring layer 65. Therefore, the current path from the emitter layer 20E to the ground conductor 65G can be made low-resistance.

[0116] The above embodiments are illustrative, and it can be said that parts of the structures shown in different embodiments can be replaced or combined. The same effects resulting from the same structure in multiple embodiments are not mentioned sequentially in each embodiment. Furthermore, the present invention is not limited to the above embodiments. For example, it will be apparent to those skilled in the art that various changes, modifications, combinations, etc., can be made.

[0117] Based on the embodiments described in this specification, the following technical solutions are disclosed.

[0118] <1> A semiconductor device comprising:

[0119] The emitter layer contains a compound semiconductor of the first conductivity type;

[0120] A base layer disposed on the surface of the emitter layer facing a first direction contains a compound semiconductor of a second conductivity type opposite to the first conductivity type, and the base layer and the emitter layer are in a heterojunction.

[0121] At least one collector mesa disposed on the surface of the base layer facing the first direction, containing a compound semiconductor of the first conductivity type;

[0122] An emitter electrode, which is disposed on the surface of the emitter layer facing a second direction opposite to the first direction;

[0123] A base electrode, disposed on the surface of the base layer facing the first direction, continuously surrounds the collector mesa when viewed from above; and

[0124] Collector electrode, which is disposed on the surface of the collector mesa facing the first direction.

[0125] <2> The semiconductor device according to <1> wherein the shape of the collector mesa when viewed from above is circular, square or regular hexagonal.

[0126] <3> The semiconductor device according to <1>, wherein,

[0127] The collector mesa is discretely arranged in multiple ways.

[0128] The base electrode continuously surrounds each of the collector mesa, and the portion of the base electrode disposed between two adjacent collector mesa is shared by the two collector mesa.

[0129] <4> The semiconductor device according to <3>, wherein,

[0130] A portion of the base electrode, when viewed from above, has a lattice-like shape with orthogonal vertical and horizontal lines.

[0131] The plurality of collector mesa surfaces are respectively arranged in a grid-like array of cells enclosed by vertical and horizontal lines.

[0132] <5> The semiconductor device according to <3>, wherein,

[0133] A portion of the base electrode has a honeycomb-like shape when viewed from above.

[0134] The plurality of collector mesa surfaces are respectively disposed in a honeycomb-shaped plurality of cells.

[0135] <6> The semiconductor device according to <4> or <5>, wherein,

[0136] When viewed from above, the outer periphery of each of the plurality of collector mesa surfaces is spaced apart from the edge of the base electrode and has a shape that runs along the edge of the base electrode.

[0137] <7> The semiconductor device according to any one of <1> to <6>, wherein,

[0138] The base electrode comprises two layers, a first layer and a second layer, a portion of the first layer overlaps with a portion of the second layer, neither the first layer nor the second layer includes a closed pattern, and the first layer and the second layer continuously surround the collector mesa as a whole.

[0139] <8> The semiconductor device according to any one of <1> to <7>, wherein,

[0140] The semiconductor device also includes collector pads for external circuit connections.

[0141] The collector pad is positioned on the first direction side when viewed from the collector electrode, and is positioned at a position that partially overlaps with the collector electrode when viewed from above.

[0142] <9> The semiconductor device according to any one of <1> to <8>, wherein,

[0143] The semiconductor device further includes a support substrate disposed on the surface of the emitter electrode facing the second direction, the thermal conductivity of the support substrate being higher than that of the emitter layer.

[0144] <10> A method for manufacturing a semiconductor device, wherein,

[0145] A release layer is formed on the surface of the temporary substrate facing the first direction.

[0146] An emitter layer containing a compound semiconductor of a first conductivity type is formed on the surface of the release layer facing the first direction.

[0147] A base layer containing a compound semiconductor with a second conductivity type opposite to the first conductivity type is formed on the surface of the emitter layer facing the first direction.

[0148] At least one collector mesa containing the first conductivity type is formed on the surface of the base layer facing the first direction.

[0149] A base electrode is formed on the surface of the base layer facing the first direction.

[0150] A collector electrode is formed on the surface of the collector mesa facing the first direction.

[0151] The emitter layer is separated from the temporary substrate by etching to remove the release layer.

[0152] An emitter electrode is formed on the surface of the emitter layer in a second direction, which is opposite to the first direction.

[0153] The emitter electrode is bonded to the support substrate.

[0154] <11> The method for manufacturing a semiconductor device according to <10>, wherein,

[0155] The base electrode comprises two layers, a first layer and a second layer. Neither the first layer nor the second layer includes a closed pattern. The first layer and the second layer continuously surround the collector mesa.

[0156] When forming the base electrode, the first layer is formed using a stripping process, and the second layer is formed using other stripping processes.

Claims

1. A semiconductor device, wherein, This semiconductor device has: The emitter layer contains a compound semiconductor of the first conductivity type; A base layer disposed on the surface of the emitter layer facing a first direction contains a compound semiconductor of a second conductivity type opposite to the first conductivity type, and the base layer and the emitter layer are in a heterojunction. At least one collector mesa disposed on the surface of the base layer facing the first direction, containing a compound semiconductor of the first conductivity type; An emitter electrode, which is disposed on the surface of the emitter layer facing a second direction opposite to the first direction; A base electrode, disposed on the surface of the base layer facing the first direction, continuously surrounds the collector mesa when viewed from above; as well as Collector electrode, which is disposed on the surface of the collector mesa facing the first direction.

2. The semiconductor device according to claim 1, wherein, The shape of the collector platform when viewed from above is circular, square, or regular hexagonal.

3. The semiconductor device according to claim 1, wherein, The collector mesa is discretely arranged in multiple ways. The base electrode continuously surrounds each of the collector mesa. The portion of the base electrode disposed between two adjacent collector mesa is shared by both collector mesa.

4. The semiconductor device according to claim 3, wherein, A portion of the base electrode, when viewed from above, has a lattice-like shape with orthogonal vertical and horizontal lines. The plurality of collector mesa surfaces are respectively arranged in a grid-like array of cells enclosed by vertical and horizontal lines.

5. The semiconductor device according to claim 3, wherein, A portion of the base electrode has a honeycomb-like shape when viewed from above. The plurality of collector mesa surfaces are respectively disposed in a honeycomb-shaped plurality of cells.

6. The semiconductor device according to claim 4 or 5, wherein, When viewed from above, the outer periphery of each of the plurality of collector mesa surfaces is spaced apart from the edge of the base electrode and has a shape that runs along the edge of the base electrode.

7. The semiconductor device according to any one of claims 1 to 6, wherein, The base electrode comprises two layers, a first layer and a second layer, a portion of the first layer overlaps with a portion of the second layer, neither the first layer nor the second layer includes a closed pattern, and the first layer and the second layer continuously surround the collector mesa.

8. The semiconductor device according to any one of claims 1 to 7, wherein, The semiconductor device also includes collector pads for external circuit connections. The collector pad is positioned on the first direction side when viewed from the collector electrode, and is positioned at a position that partially overlaps with the collector electrode when viewed from above.

9. The semiconductor device according to any one of claims 1 to 8, wherein, The semiconductor device further includes a support substrate disposed on the surface of the emitter electrode facing the second direction, the thermal conductivity of the support substrate being higher than that of the emitter layer.

10. A method for manufacturing a semiconductor device, wherein, A release layer is formed on the surface of the temporary substrate facing the first direction. An emitter layer containing a compound semiconductor of a first conductivity type is formed on the surface of the release layer facing the first direction. A base layer containing a compound semiconductor with a second conductivity type opposite to the first conductivity type is formed on the surface of the emitter layer facing the first direction. At least one collector mesa containing the first conductivity type is formed on the surface of the base layer facing the first direction. A base electrode is formed on the surface of the base layer facing the first direction. A collector electrode is formed on the surface of the collector mesa facing the first direction. The emitter layer is separated from the temporary substrate by etching to remove the release layer. An emitter electrode is formed on the surface of the emitter layer in a second direction, which is opposite to the first direction. The emitter electrode is bonded to the support substrate.

11. The method of manufacturing a semiconductor device according to claim 10, wherein, The base electrode comprises two layers, a first layer and a second layer. Neither the first layer nor the second layer includes a closed pattern. The first layer and the second layer continuously surround the collector mesa. When forming the base electrode, the first layer is formed using a stripping process, and the second layer is formed using other stripping processes.

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