IGZO (Indium Gallium Zinc Oxide) thin film transistor inserted with atomic-level oxide intercalation and manufacturing method thereof
By inserting atomic-level oxide intercalation layers at the interfaces on both sides of the IGZO channel, the problems of metal diffusion and interface defects in IGZO DRAM devices during high-temperature annealing are solved, thereby improving the electrical performance and stability of the devices.
Patent Information
- Application Number
- CN202511085337.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-04
- Publication Date
- 2025-11-11
AI Technical Summary
During the high-temperature annealing process, IGZO DRAM devices experience metal electrode diffusion, increased interface defects, and reduced channel carrier mobility, which affects the stability and reliability of the devices.
Atom-level oxide intercalation layers smaller than 0.5 nm, including indium oxide, gallium oxide, zinc oxide, or aluminum oxide, are inserted at the interface on both sides of the IGZO channel to form an IGZO thin film transistor structure with top gate and bottom contact, thereby repairing interface defects and reducing contact resistance.
It improves the electrical performance of the device, enhances its stability and reliability, suppresses metal diffusion and interface oxidation reactions, and adapts to the stability of high-temperature processes.
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Figure CN120936074A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of thin-film transistor technology, and in particular to an IGZO thin-film transistor with atomic-level oxide intercalation and its fabrication method. Background Technology
[0002] Indium gallium zinc oxide (IGZO), a high-mobility amorphous oxide semiconductor material, has been widely used in the manufacture of high-resolution displays and large-area flexible electronic devices. In recent years, as the miniaturization of silicon-based DRAM devices is nearing its limit, IGZO, with its advantages of low leakage current, stackability, and good large-area uniformity, has gradually become one of the important choices for the research of new DRAM devices.
[0003] Currently, there has been considerable research in the industry on the single-device performance and array performance of IGZO DRAM devices, which has to some extent confirmed the feasibility of IGZO DRAM devices. There has also been much discussion on improving the single-device performance of IGZO devices, such as achieving higher mobility and lower leakage current. However, reports on how to improve the reliability and stability of single devices are still scarce. IGZO DRAM devices typically require a BEOL annealing process at 300–400℃ during integrated manufacturing. High temperatures can lead to metal electrode diffusion, increased interface defects, and reduced channel carrier mobility, thus severely affecting the stability and reliability of the device. One traditional solution is to repair interface defects through low-temperature annealing, but this method is not effective in repairing interface defects under extreme conditions, and increasing the annealing temperature exacerbates oxygen loss in the IGZO thin film. Another solution is to thicken the gate dielectric, but this method is not conducive to the miniaturization of IGZO transistors. Therefore, there is an urgent need to propose a new structural design scheme that balances high-temperature tolerance and electrical optimization. Summary of the Invention
[0004] Based on the above analysis, the present invention aims to provide an IGZO thin-film transistor with atomic-level oxide intercalation and its fabrication method, in order to solve the problem that high-temperature annealing may lead to metal electrode diffusion, increased interface defects, and reduced channel carrier mobility, thereby seriously affecting the stability and reliability of the device.
[0005] On one hand, embodiments of the present invention provide an IGZO thin-film transistor with an atomically intercalated oxide layer, comprising: an insulating substrate; a drain / source electrode located above the insulating substrate, wherein a channel is located between the source electrode and the drain electrode; a contact intercalation layer conformally located above a portion of the source electrode and a portion of the drain electrode and in the channel; an active layer located above the contact intercalation layer; a gate dielectric intercalation layer located above the active layer; and a gate stack located above the gate dielectric intercalation layer, wherein the contact intercalation layer and the gate dielectric intercalation layer are both atomically intercalated oxide layers.
[0006] The beneficial effects of the above technical solution are as follows: In the top-gate bottom contact IGZO thin film transistor structure, an oxide insertion layer of less than 0.5nm is inserted on both sides of the IGZO channel, that is, at the two interfaces between the channel and the source / drain electrodes and between the channel and the gate dielectric layer. The purpose is to reduce the contact resistance of the SD electrode and repair the defects at the interface between the IGZO channel and the gate dielectric, thereby improving the electrical performance of the device and improving the stability and reliability of the device.
[0007] Based on further improvements to the above-mentioned device, the active layer includes multiple oxide stacked structures, wherein each oxide stacked structure includes: an indium oxide layer; a gallium oxide layer located above the indium oxide layer; and a zinc oxide layer located above the gallium oxide layer.
[0008] Based on further improvements to the above-mentioned device, the atomic-level oxide layer is one of indium oxide, gallium oxide, zinc oxide or aluminum oxide, and the thickness of the contact insertion layer and the gate dielectric insertion layer is 0.3 nm to 0.5 nm.
[0009] Based on further improvements to the above-mentioned device, the gate stack includes: a gate dielectric layer located above the gate dielectric insertion layer, the gate dielectric layer being made of aluminum oxide, silicon oxide, or hafnium oxide, and having a thickness of 5 to 100 nm; and a gate electrode located above the gate dielectric layer, the gate electrode being made of indium zinc oxide, titanium nitride, molybdenum, or indium tin oxide.
[0010] Based on further improvements to the above-mentioned device, the outer walls of the contact insertion layer, the active layer, the gate dielectric insertion layer, and the gate dielectric layer are aligned in the vertical direction; the outer walls of the source and the drain are located outside the outer walls of the contact insertion layer, the active layer, the gate dielectric insertion layer, and the gate dielectric layer.
[0011] On the other hand, embodiments of the present invention provide a method for fabricating an IGZO thin-film transistor with an atomically intercalated oxide layer, comprising: forming opposing source and drain electrodes above an insulating substrate, wherein a channel is formed between the source and drain electrodes; conformally forming a contact intercalation layer, an active layer, and a gate dielectric intercalation layer sequentially above a portion of the source and drain electrodes and in the channel, wherein the contact intercalation layer and the gate dielectric intercalation layer are both atomically intercalated oxide layers; forming a gate stack above the gate dielectric intercalation layer; and sequentially patterning the gate dielectric intercalation layer, the active layer, and the contact intercalation layer by photolithography and dry etching.
[0012] Further improvements to the above method include forming opposing source and drain electrodes above the insulating substrate, which further comprises: forming an indium tin oxide (ITO) metal material layer above the insulating substrate; forming a mask material layer above the ITO metal material layer; performing photolithography on the mask material layer to form a source / drain mask; and performing dry etching on the ITO metal material layer using the source / drain mask to form opposing source and drain electrodes.
[0013] Further improvements to the above method include the following: The contact insertion layer, active layer, and gate dielectric insertion layer are conformally formed sequentially above a portion of the source and drain electrodes and within the channel. This further includes: conformally forming the contact insertion layer using atomic layer deposition above the portion of the source and drain electrodes and within the channel; conformally forming the active layer using atomic layer deposition above the contact insertion layer; and conformally forming the gate dielectric insertion layer using atomic layer deposition above the active layer. The materials of the contact insertion layer and the gate dielectric insertion layer are one of indium oxide, gallium oxide, zinc oxide, or aluminum oxide, and the thickness of the contact insertion layer and the gate dielectric insertion layer is 0.3 nm to 0.5 nm.
[0014] A further improvement to the above method, the conformal formation of the active layer over the contact insertion layer by atomic layer deposition further includes: conformally forming multiple oxide stack structures over the contact insertion layer by atomic layer deposition during multiple formation cycles, wherein, during the formation cycle of each oxide stack structure, an indium oxide layer is formed over the contact insertion layer or over a zinc oxide layer formed in the previous formation cycle by atomic layer deposition; a gallium oxide layer is formed over the indium oxide layer by atomic layer deposition; and a zinc oxide layer is formed over the gallium oxide layer by atomic layer deposition.
[0015] A further improvement to the above method, forming a gate stack above the gate dielectric insertion layer, further includes: forming a gate dielectric layer above the gate dielectric insertion layer; depositing a metal gate electrode above the gate dielectric layer; and sequentially patterning the metal gate electrode and the gate dielectric layer using photolithography and dry etching processes to form the gate stack.
[0016] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:
[0017] 1. In the top-gate-bottom-contact IGZO thin-film transistor structure, an oxide insertion layer of less than 0.5 nm is inserted on both sides of the IGZO channel, namely at the two interfaces between the channel and the source / drain electrodes, and between the channel and the gate dielectric layer. The purpose is to reduce the contact resistance of the SD electrode and repair the defects at the interface between the IGZO channel and the gate dielectric, thereby improving the electrical performance of the device and enhancing its stability and reliability.
[0018] 2. Suppress metal ion diffusion at the source / drain electrode interface; passivate surface defects at the gate dielectric interface to reduce interface state density; reduce oxygen vacancy reconstruction and electron trap formation caused by high-temperature processes.
[0019] In this invention, the above-described technical solutions can be combined with each other to achieve more preferred combinations. Other features and advantages of this invention will be set forth in the following description, and some advantages may become apparent from the description or be learned by practicing the invention. The objects and other advantages of this invention can be realized and obtained from what is particularly pointed out in the description and drawings. Attached Figure Description
[0020] The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Throughout the drawings, the same reference numerals denote the same parts.
[0021] Figure 1 This is a schematic cross-sectional view of an IGZO thin-film transistor structure with atomic-level oxide intercalation according to an embodiment of the present invention.
[0022] Figure 2 This is a schematic diagram illustrating the growth of IGZO using atomic layer deposition according to an embodiment of the present invention;
[0023] Figure 3 This is a schematic diagram of the AIT IGZO film layer according to an embodiment of the present invention;
[0024] Figure 4 The output curves of the unoptimized device exhibit a significant Schottky barrier.
[0025] Figure 5The optimized device output curve shows no obvious Schottky barrier.
[0026] Figure 6 The optimized device according to the embodiments of the present invention has an extremely low contact barrier, close to that of an ohmic contact;
[0027] Figure 7 To optimize stability (threshold voltage offset) for different oxide intercalations according to embodiments of the present invention, wherein the None curve represents a device without any intercalation;
[0028] Figure 8 This is a schematic diagram of ITO crystallization in the drain-source electrode according to an embodiment of the present invention;
[0029] Figure 9 This is a flowchart illustrating a method for fabricating an IGZO thin-film transistor with an atomic-level oxide intercalation layer according to an embodiment of the present invention. Detailed Implementation
[0030] Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings, which form part of this application and are used together with the embodiments of the present invention to illustrate the principles of the present invention, but are not intended to limit the scope of the present invention.
[0031] refer to Figure 1 A specific embodiment of the present invention discloses an IGZO thin film transistor with an atomic-level oxide intercalation layer, comprising: an insulating substrate, a drain / source electrode, a contact intercalation layer, an active layer, a gate dielectric intercalation layer, a gate stack, and a channel.
[0032] The drain / source is located above the insulating substrate, with the channel between the source and the drain.
[0033] The contact insertion layer is conformally located above part of the source and part of the drain and in the channel. The atomic-level oxide layer is one of indium oxide, gallium oxide, zinc oxide or aluminum oxide. The thickness of the contact insertion layer and the gate dielectric insertion layer is 0.3 nm to 0.5 nm.
[0034] The active layer is located above the contact insertion layer. Specifically, the active layer includes multiple oxide stack structures, wherein each oxide stack structure includes: an indium oxide layer; a gallium oxide layer located above the indium oxide layer; and a zinc oxide layer located above the gallium oxide layer.
[0035] The gate dielectric insertion layer is located above the active layer, the atomic-level oxide layer is one of indium oxide, gallium oxide, zinc oxide or aluminum oxide, and the thickness of the contact insertion layer and the gate dielectric insertion layer is 0.3 nm to 0.5 nm.
[0036] The gate stack is located above the gate dielectric insertion layer, wherein both the contact insertion layer and the gate dielectric insertion layer are atomic-level oxide layers. Specifically, the gate stack includes: a gate dielectric layer located above the gate dielectric insertion layer, the gate dielectric layer being made of aluminum oxide, silicon oxide, or hafnium oxide, with a thickness of 5 to 100 nm; and a gate electrode located above the gate dielectric layer, the gate electrode being made of indium zinc oxide, titanium nitride, molybdenum, or indium tin oxide.
[0037] The outer walls of the contact insertion layer, active layer, gate dielectric insertion layer, and gate dielectric layer are aligned in the vertical direction. The outer walls of the source and drain are located outside the outer walls of the contact insertion layer, active layer, gate dielectric insertion layer, and gate dielectric layer.
[0038] Compared with the prior art, the IGZO thin film transistor with atomic-level oxide intercalation provided in this embodiment, specifically for the top-gate-bottom-contact IGZO thin film transistor structure, has two interfaces on both sides of the IGZO channel, namely between the channel and the source / drain electrodes, and between the channel and the gate dielectric layer (see reference). Figure 7 A layer of oxide with a diameter of less than 0.5 nm is inserted at each of the SD electrodes. The purpose is to reduce the contact resistance of the SD electrodes and repair the defects at the interface between the IGZO channel and the gate dielectric, thereby improving the electrical performance of the device and enhancing its stability and reliability.
[0039] refer to Figure 9 Another specific embodiment of the present invention discloses a method for fabricating an IGZO thin film transistor with an atomic-level oxide intercalation layer, comprising the following multiple steps.
[0040] In step S901, opposing source and drain electrodes are formed above the insulating substrate, wherein a channel is formed between the source and drain electrodes. Specifically, forming opposing source and drain electrodes above the insulating substrate further includes: forming an indium tin oxide (ITO) metal material layer above the insulating substrate; forming a mask material layer above the ITO metal material layer; performing photolithography on the mask material layer to form a source / drain mask; and performing dry etching on the ITO metal material layer using the source / drain mask to form opposing source and drain electrodes.
[0041] In step S902, a contact insertion layer, an active layer, and a gate dielectric insertion layer are sequentially and conformally formed above a portion of the source and a portion of the drain, and in the channel, wherein the contact insertion layer and the gate dielectric insertion layer are both atomic-level oxide layers.
[0042] Specifically, the conformal formation of a contact insertion layer, an active layer, and a gate dielectric insertion layer above a portion of the source and a portion of the drain, and within the channel, further includes: conformally forming a contact insertion layer above a portion of the source and a portion of the drain, and within the channel, using atomic layer deposition; conformally forming an active layer above the contact insertion layer using atomic layer deposition; and conformally forming a gate dielectric insertion layer above the active layer using atomic layer deposition. The materials of the contact insertion layer and the gate dielectric insertion layer are one of indium oxide, gallium oxide, zinc oxide, or aluminum oxide, and the thickness of the contact insertion layer and the gate dielectric insertion layer is 0.3 nm to 0.5 nm.
[0043] The conformal formation of an active layer over the contact insertion layer by atomic layer deposition further includes: conformally forming multiple oxide stack structures over the contact insertion layer by atomic layer deposition during multiple formation cycles, wherein, during the formation cycle of each oxide stack structure, an indium oxide layer is formed over the contact insertion layer or over a zinc oxide layer formed in the previous formation cycle by atomic layer deposition; a gallium oxide layer is formed over the indium oxide layer by atomic layer deposition; and a zinc oxide layer is formed over the gallium oxide layer by atomic layer deposition.
[0044] In step S903, a gate stack is formed above the gate dielectric insertion layer. Specifically, forming the gate stack above the gate dielectric insertion layer further includes: forming a gate dielectric layer above the gate dielectric insertion layer; depositing a metal gate electrode above the gate dielectric layer; and sequentially patterning the metal gate electrode and the gate dielectric layer using photolithography and dry etching processes to form the gate stack.
[0045] In step S904, the gate dielectric insertion layer, active layer, and contact insertion layer are patterned sequentially by photolithography and dry etching.
[0046] Atom-scale oxide intercalation layers are added at two interfaces in a thin-film transistor: between the channel and the source / drain electrodes, and between the channel and the gate dielectric layer. (Reference) Figures 4 to 6 The optimized device has an extremely low source-drain electrode contact barrier and can stably withstand back-end annealing temperatures up to 400°C. It also has excellent high-temperature bias characteristics, which significantly improves the stability and compatibility of the device in advanced integrated processes. This is beneficial for manufacturing higher-performance IGZO transistors (IGZO indium gallium zinc oxide) in three-dimensional integrated high-density circuits.
[0047] There are two main methods for growing IGZO oxide channels: physical deposition (PVD) and atomic layer deposition (ALD). PVD deposits IGZO channels by physically bombarding a target to sputter the desired material onto the substrate, making it difficult to achieve atomic-level thickness adjustments. Atomic layer deposition deposits IGZO channel materials layer by layer, using InO, GaO, or ZnO. The specific process is as follows: Figure 2 As shown, the IGZO channel material consists of multiple formation cycles, in which InO, GaO, and ZnO are sequentially deposited in each formation cycle.
[0048] refer to Figure 2 Each formation cycle comprises three sub-cycles: an InO sub-cycle, a GaO sub-cycle, and a ZnO sub-cycle. Each sub-cycle includes the steps of providing an appropriate dose of precursor (i.e., a precursor suitable for generating InO, GaO, or ZnO), a purging step, a step of the precursor reacting to generate an InO layer, GaO layer, or ZnO layer, and a purging step.
[0049] This purging step is used in industrial processes such as chemical reactions, atomic layer deposition (ALD), and chemical vapor deposition (CVD) to remove residual gases, precursors, or reaction byproducts from reaction chambers or pipelines using inert gases (such as nitrogen, argon, etc.). Its main purposes are: (1) To prevent contamination: to avoid accidental reactions between residual gases or precursors and the next batch of reactants, affecting product quality. (2) To ensure safety: to remove potentially flammable, explosive, or toxic gases, reducing safety risks. (3) To improve efficiency: to ensure a stable gaseous environment within the reaction chamber, which is conducive to the smooth progress of subsequent reactions.
[0050] The purging steps are as follows: (1) Stop the reaction: After the reaction is complete, stop the supply of precursor or reaction gas. (2) Introduce inert gas: Introduce inert gas into the reaction chamber or pipeline through a pipeline, usually at a certain flow rate for a period of time. (3) Expel gas: Expel the gas in the chamber through the exhaust port to ensure that the residual gas is completely removed. (4) Monitor: Use equipment such as a gas analyzer to monitor the gas composition in the chamber to ensure that the concentration of residual gas drops to a safe level.
[0051] refer to Figure 3The method for adjusting IGZO growth involves adjusting the ratio of InO, GaO, and ZnO deposition layers in each small sub-cycle, thereby adjusting the overall composition of the IGZO. The unique aspect of this patent lies in inserting atomic-level oxide intercalations at the beginning and end of the IGZO ALD process. This involves inserting several cycles' worth of InO, AlO, etc., forming an intercalation layer smaller than 1 nm, which, together with the IGZO film itself, forms Atomic-Interlayer-Tuning IGZO (AIT-IGZO), thereby improving device stability and performance.
[0052] First, a 50 nm thick ITO metal layer is grown on a SiO2 substrate using magnetron sputtering via physical deposition. Then, the ITO source and drain electrodes are patterned using photolithography and dry etching. Next, a contact insertion layer (InO, less than 0.5 nm), an active layer (IGZO, 5 nm), and a gate dielectric insertion layer (InO / AlO / GaO, less than 0.5 nm) are deposited sequentially using atomic layer deposition. Then, a 10 nm HfO layer is deposited as the gate dielectric layer using atomic layer deposition. Then, a 25 nm IZO layer is deposited as the gate metal using atomic layer deposition. Finally, the gate metal, gate dielectric layer, and active layer are patterned sequentially using photolithography and dry etching.
[0053] refer to Figure 8 After fabrication, the device produced by this invention undergoes high-temperature rapid annealing (400℃, N2 atmosphere, annealing time 5 min) to simulate the high-temperature environment of the subsequent process. The source and drain ITO electrodes of the device, with InO intercalation layers inserted on both sides of the channel, exhibit a crystallized state, effectively suppressing the diffusion of metal into the IGZO layer.
[0054] It exhibits excellent subthreshold swing: 64 mV / dec. After 1000 s of testing with a normal temperature forward bias (overdrive voltage 3.5 V, temperature 298 K), the threshold voltage shift is only 3.4 mV. Under high temperature forward bias (overdrive voltage 3.5 V, temperature 353 K), the threshold voltage shift is less than 10 mV. In the more extreme case of annealing at 500 °C in an N2 atmosphere for 5 min, the device maintains the same subthreshold swing: 62 mV / dec, while after 1000 s of testing with a normal temperature forward bias (overdrive voltage 2.5 V, temperature 298 K), the threshold voltage shift is only 50.3 mV.
[0055] Therefore, the present invention has the following beneficial effects: (1) it significantly improves the thermal stability of the device under high-temperature processes; (2) it suppresses metal diffusion and interface oxidation reactions; (3) the structure is relatively simple, and it only involves adding a thin film layer of less than 0.5 nm containing the deposition elements to both sides of the active layer during the deposition process, which can be extended to all thin film transistor devices using metal oxide semiconductors. For example, it can be extended to high-temperature sensitive process platforms such as flexible displays and 3D integration.
[0056] Specifically, it can be applied to memory because threshold voltage drift is effectively controlled. It can be applied to display panels because stability is improved and it is compatible with existing processes. It can be applied to 3D integration because annealing stability in high-temperature back-end integration environments is improved, contact performance is good, and stability is high.
[0057] Those skilled in the art will understand that all or part of the processes of the methods described in the above embodiments can be implemented by a computer program instructing related hardware, and the program can be stored in a computer-readable storage medium. The computer-readable storage medium may be a disk, optical disk, read-only memory, or random access memory, etc.
[0058] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.
Claims
1. An IGZO thin-film transistor with atomic-level oxide intercalation, characterized in that, include: Insulating layer substrate; Drain / source, located above the insulating substrate, wherein a channel is located between the source and the drain; The contact insertion layer is conformally located above a portion of the source and a portion of the drain, and within the channel; An active layer is located above the contact insertion layer; A gate dielectric insertion layer is located above the active layer; and A gate stack is located above the gate dielectric insertion layer, wherein both the contact insertion layer and the gate dielectric insertion layer are atomic-level oxide layers.
2. The IGZO thin-film transistor with atomic-level oxide intercalation according to claim 1, characterized in that, The active layer comprises multiple oxide stack structures, wherein each oxide stack structure comprises: Indium oxide layer; A gallium oxide layer is located above the indium oxide layer; and A zinc oxide layer is located above the gallium oxide layer.
3. The IGZO thin-film transistor with atomic-level oxide intercalation according to claim 1, characterized in that, The atomic-level oxide layer is one of indium oxide, gallium oxide, zinc oxide, or aluminum oxide, and The thickness of the contact insertion layer and the gate dielectric insertion layer is 0.3 nm to 0.5 nm.
4. The IGZO thin-film transistor with atomic-level oxide intercalation according to claim 2, characterized in that, The gate stack includes: A gate dielectric layer, located above the gate dielectric insertion layer, wherein the gate dielectric layer is made of alumina, silicon oxide, or hafnium oxide, and has a thickness of 5 to 100 nm; and The gate electrode is located above the gate dielectric layer, and the material of the gate electrode is indium zinc oxide, titanium nitride, molybdenum, or indium tin oxide.
5. The IGZO thin-film transistor with atomic-level oxide intercalation according to claim 4, characterized in that, The contact insertion layer, the active layer, the gate dielectric insertion layer, and the outer wall of the gate dielectric layer are aligned in the vertical direction; The outer walls of the source and the drain are located outside the outer walls of the contact insertion layer, the active layer, the gate dielectric insertion layer, and the gate dielectric layer.
6. A method for fabricating an IGZO thin-film transistor with atomic-level oxide intercalation, characterized in that, include: Opposite source and drain electrodes are formed above the insulating substrate, wherein a channel is formed between the source and drain electrodes; A contact insertion layer, an active layer, and a gate dielectric insertion layer are sequentially and conformally formed above a portion of the source and a portion of the drain, and in the channel, wherein the contact insertion layer and the gate dielectric insertion layer are both atomic-level oxide layers; A gate stack is formed above the gate dielectric insertion layer; and The gate dielectric insertion layer, the active layer, and the contact insertion layer are patterned sequentially by photolithography and dry etching.
7. The method for fabricating an IGZO thin-film transistor with atomic-level oxide intercalation according to claim 6, characterized in that, Forming opposing source and drain electrodes above the insulating substrate further includes: An indium tin oxide metal material layer is formed above the insulating substrate; A masking material layer is formed above the indium tin oxide metal material layer; Photolithography is performed on the mask material layer to form a source / drain mask; The indium tin oxide metal material layer is dry etched using the source / drain mask to form opposing source and drain electrodes.
8. The method for fabricating an IGZO thin-film transistor with atomic-level oxide intercalation according to claim 7, characterized in that, The contact insertion layer, active layer, and gate dielectric insertion layer are conformally formed sequentially above a portion of the source and a portion of the drain, and within the channel, further comprising: A contact insertion layer is conformally formed above part of the source and part of the drain and in the channel using atomic layer deposition; An active layer is conformally formed above the contact insertion layer using atomic layer deposition; and A gate dielectric insertion layer is conformally formed above the active layer by atomic layer deposition, wherein the material of the contact insertion layer and the gate dielectric insertion layer is one of indium oxide, gallium oxide, zinc oxide or aluminum oxide, and the thickness of the contact insertion layer and the gate dielectric insertion layer is 0.3 nm to 0.5 nm.
9. The method for fabricating an IGZO thin-film transistor with atomic-level oxide intercalation according to claim 8, characterized in that, The conformal formation of the active layer over the contact insertion layer via atomic layer deposition further comprises: conformally forming multiple oxide stack structures over the contact insertion layer via atomic layer deposition during multiple formation cycles, wherein, during the formation cycle of each oxide stack structure... An indium oxide layer is formed on top of the contact insertion layer or on top of the zinc oxide layer formed in the previous formation cycle by atomic layer deposition; A gallium oxide layer is formed on top of the indium oxide layer by atomic layer deposition; and A zinc oxide layer is formed on top of the gallium oxide layer by atomic layer deposition.
10. The method for fabricating an IGZO thin-film transistor with atomic-level oxide intercalation according to claim 9, characterized in that, Forming a gate stack above the gate dielectric insertion layer further includes: A gate dielectric layer is formed above the gate dielectric insertion layer; A metal gate electrode is deposited over the gate dielectric layer; and The metal gate electrode and the gate dielectric layer are patterned sequentially using photolithography and dry etching processes to form the gate stack.