Formation method of semiconductor device

Abstract

The invention discloses a method for forming a semiconductor device, which comprises the following steps of: providing a substrate, forming a gate dielectric layer on the substrate, and forming a gate on the gate dielectric layer; forming a first oxide layer in the exposed region of the gate and the gate dielectric layer through an RTO process; forming a second oxide layer on the first oxide layer by an ALD process; halo ion implantation is carried out, first doped regions are formed in the portions, on the two sides of the grid electrode, of the substrate, and in the halo ion implantation process, the ion implantation direction is not parallel to the direction where the normal of the upper surface of the substrate is located. In the manufacturing process of the semiconductor device, after gate etching is completed, the first oxide layer is formed on the exposed surfaces of the gate and the gate dielectric layer through the RTO process, and then the second oxide layer is formed on the first oxide layer through the ALD process to increase the thickness of the oxide layer on the side wall of the gate. Therefore, the damage of subsequent halo ion implantation to the gate dielectric layer can be more effectively inhibited, and the NBTI characteristic and reliability of the device are improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor devices and integrated circuit technology, and in particular to a method for forming a semiconductor device. Background Technology

[0002] In related technologies, taking a metal-oxide-semiconductor field-effect transistor (MOSFET, referred to as "MOS" in this application) as an example, during the fabrication process, after the gate etching process, a rapid thermal oxidation (RTO) process is usually performed first, followed by a lightly doped drain (LDD) ion implantation process. Since the halo ion implantation process in LDD typically requires implanting the channel at a certain angle, it causes some damage to the peripheral region of the gate dielectric layer. The RTO process can reduce the damage to the gate dielectric layer caused by halo ion implantation.

[0003] However, in practical applications, the oxide layer formed by the RTO process is difficult to increase after reaching a certain thickness, and it is difficult to effectively suppress the damage to the gate dielectric layer caused by halo ion implantation, thereby affecting the negative bias temperature instability (NBTI) characteristics of the device and reducing the reliability of the device. Summary of the Invention

[0004] This application provides a method for forming a semiconductor device, which can solve the problem that the method for forming an oxide layer through RTO process to protect the gate dielectric layer from damage caused by halo implantation has limited effect in related semiconductor device fabrication methods. The method includes:

[0005] A substrate is provided, on which a gate dielectric layer is formed, and a gate is formed on the gate dielectric layer;

[0006] A first oxide layer is formed in the region exposed by the gate and the gate dielectric layer using an RTO process;

[0007] A second oxide layer is formed on the first oxide layer using an ALD process;

[0008] Halo ion implantation is performed to form a first doped region in the substrate on both sides of the gate. During the halo ion implantation process, the ion implantation direction is not parallel to the direction of the normal to the upper surface of the substrate.

[0009] In some embodiments, the thickness of the first oxide layer is 5 to 15 angstroms.

[0010] In some embodiments, during the formation of a first oxide layer in the region exposed by the gate and the gate dielectric layer via an RTO process, the temperature of the process chamber is between 700 and 900 degrees Celsius.

[0011] In some embodiments, the thickness of the second oxide layer is 10 to 30 angstroms.

[0012] In some embodiments, the method is applied to the fabrication process of MOS devices.

[0013] In some embodiments, after performing halo ion implantation, the method further includes:

[0014] LDD ion implantation is performed to form a second doped region in the substrate on both sides of the gate;

[0015] Source-drain ion implantation is performed to form heavily doped regions in the substrate on both sides of the gate. The second doped region is located between the heavily doped region and the first doped region. The conductivity type of the impurities doped in the second doped region is different from that of the impurities doped in the first doped region. The conductivity type of the impurities doped in the heavily doped region is the same as that of the impurities doped in the second doped region. The concentration of the impurities doped in the heavily doped region is greater than the concentration of the impurities doped in the first doped region and the second doped region.

[0016] The technical solution of this application has at least the following advantages:

[0017] By forming a first oxide layer on the exposed surfaces of the gate and gate dielectric layer using the RTO process after gate etching during the semiconductor device fabrication process, and then forming a second oxide layer on the first oxide layer using the ALD process to increase the oxide layer thickness of the gate sidewall, the damage to the gate dielectric layer caused by subsequent halo ion implantation can be more effectively suppressed, thereby improving the NBTI characteristics and reliability of the device. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0019] Figure 1 This is a flowchart of a method for forming a semiconductor device provided in an exemplary embodiment of this application;

[0020] Figures 2 to 6 This is a schematic diagram of the formation process of a semiconductor device provided in an exemplary embodiment of this application. Detailed Implementation

[0021] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0022] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0023] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0024] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0025] refer to Figure 1 It illustrates a flowchart of a method for forming a semiconductor device according to an exemplary embodiment of this application, which can be applied to the fabrication process of MOS devices, such as... Figure 1 As shown, the method includes:

[0026] Step S1: A substrate is provided, on which a gate dielectric layer is formed, and on which a gate is formed.

[0027] refer to Figure 2 This shows a schematic cross-sectional view before the formation of the first oxide layer. For example, as shown... Figure 2As shown, a cross-sectional view of the active area (AA) of a semiconductor device is used as an example for illustration. A gate dielectric layer 220 is formed on the substrate 210, and a gate 230 is formed on the gate dielectric layer 220. The gate dielectric layer 220 and the gate 230 are formed by etching the same photolithography process. The gate dielectric layer 220 is formed by in-situ steam generation (ISSG) process.

[0028] Step S2: A first oxide layer is formed in the region exposed by the gate and gate dielectric layer using the RTO process.

[0029] refer to Figure 3 It shows a schematic cross-sectional view after the formation of the first oxide layer. For example, as shown... Figure 3 As shown, during the formation of the first oxide layer 241 in the exposed areas of the gate 230 and gate dielectric layer 220 via the RTO process, the temperature of the process chamber is 700 degrees Celsius to 900 degrees Celsius, and the thickness is... Up to 15 Anglo-Zeit.

[0030] Step S3: Form a second oxide layer on the first oxide layer using the ALD process.

[0031] refer to Figure 4 This shows a schematic cross-sectional view after the formation of the second oxide layer. For example, as shown... Figure 4 As shown, the thickness of the second oxide layer 242 formed by atomic layer deposition (ALD) is 10 to 30 angstroms.

[0032] Step S4: Perform halo ion implantation to form the first doped region in the substrate on both sides of the gate. During the halo ion implantation process, the ion implantation direction is not parallel to the direction of the normal to the upper surface of the substrate.

[0033] refer to Figure 5 This shows a schematic cross-sectional view after halo ion implantation. For example, such as... Figure 5 As shown, during halo ion implantation, the ion implantation direction (e.g.) Figure 5 The direction of the ion implantation (indicated by the middle arrow) is not parallel to the direction of the normal to the upper surface of the substrate 210 (i.e., the ion implantation direction is not perpendicular to the substrate 210, but has a certain angle, and is inclined). After halo ion implantation, the first doped region 201 is formed in the substrate 210 on both sides of the gate 230.

[0034] After step S4, the method further includes: performing LDD ion implantation to form a second doped region in the substrate on both sides of the gate; and performing source drain (SD) ion implantation to form heavily doped regions in the substrate on both sides of the gate (when the device is in operation, the two heavily doped regions can serve as the source and drain of the device).

[0035] refer to Figure 6 It shows a schematic cross-sectional view after the formation of the second doped region and the heavily doped region. For example, as shown... Figure 6 As shown, the second doped region 202 is located between the heavily doped region 203 and the first doped region 201. The conductivity type of the impurities doped in the second doped region 202 is different from that of the impurities doped in the first doped region 201. The conductivity type of the impurities doped in the heavily doped region 203 is the same as that of the impurities doped in the second doped region 202. The concentration of the impurities doped in the heavily doped region 203 is greater than that of the impurities doped in the first doped region 201 and the second doped region 202.

[0036] In summary, in the embodiments of this application, during the fabrication of semiconductor devices, after gate etching is completed, a first oxide layer is first formed on the exposed surfaces of the gate and gate dielectric layers using the RTO process, and then a second oxide layer is formed on the first oxide layer using the ALD process to increase the oxide layer thickness of the gate sidewall. This can more effectively suppress the damage to the gate dielectric layer caused by subsequent halo ion implantation, thereby improving the NBTI characteristics and reliability of the device.

[0037] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.

Claims

1. A method for forming a semiconductor device, characterized in that, include: A substrate is provided, on which a gate dielectric layer is formed, and a gate is formed on the gate dielectric layer; A first oxide layer is formed in the region exposed by the gate and the gate dielectric layer using an RTO process; A second oxide layer is formed on the first oxide layer using an ALD process; Halo ion implantation is performed to form a first doped region in the substrate on both sides of the gate. During the halo ion implantation process, the ion implantation direction is not parallel to the direction of the normal to the upper surface of the substrate.

2. The method according to claim 1, characterized in that, The thickness of the first oxide layer is 5 to 15 angstroms.

3. The method according to claim 2, characterized in that, During the formation of the first oxide layer in the region exposed by the gate and the gate dielectric layer via the RTO process, the temperature of the process chamber is between 700 and 900 degrees Celsius.

4. The method according to claim 1, characterized in that, The thickness of the second oxide layer is 10 to 30 angstroms.

5. The method according to any one of claims 1 to 4, characterized in that, The method is applied in the fabrication process of MOS devices.

6. The method according to claim 5, characterized in that, After performing halo ion implantation, the procedure further includes: LDD ion implantation is performed to form a second doped region in the substrate on both sides of the gate; Source-drain ion implantation is performed to form heavily doped regions in the substrate on both sides of the gate. The second doped region is located between the heavily doped region and the first doped region. The conductivity type of the impurities doped in the second doped region is different from that of the impurities doped in the first doped region. The conductivity type of the impurities doped in the heavily doped region is the same as that of the impurities doped in the second doped region. The concentration of the impurities doped in the heavily doped region is greater than the concentration of the impurities doped in the first doped region and the second doped region.

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