Semiconductor device and forming method thereof

Abstract

The invention relates to a semiconductor device and a forming method thereof. A semiconductor device and a method of forming the same are provided. The semiconductor device may include a first source / drain region, a first nanostructure adjacent to the first source / drain region, a second source / drain region, a second nanostructure adjacent to the second source / drain region, a gate structure, a spacer, and a dielectric layer. The gate structure may include a gate electrode and a gate dielectric. The first portion of the gate electrode and the first portion of the gate dielectric may be between the first nanostructure and the second nanostructure. The first portion of the spacer may be between the first source / drain region and the second source / drain region. The first portion of the dielectric layer may be between the first portion of the gate dielectric and the first portion of the spacer. The dielectric layer may include a different material than a material of the gate dielectric and the spacer.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices and methods of forming the same. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material on a semiconductor substrate, and using photolithography to pattern the various material layers to form circuit components and elements thereon.

[0003] The semiconductor industry continuously improves the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by constantly reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, other problems arise that need to be addressed. Summary of the Invention

[0004] According to one aspect of this disclosure, a semiconductor device is provided, comprising: a first source / drain region; a first nanostructure adjacent to the first source / drain region; a second source / drain region; a second nanostructure adjacent to the second source / drain region; a gate structure surrounding the first and second nanostructures, wherein the gate structure includes a gate electrode and a gate dielectric, and wherein a first portion of the gate electrode and a first portion of the gate dielectric are between the first and second nanostructures; a spacer, wherein a first portion of the spacer is between the first and second source / drain regions; and a dielectric layer, wherein a first portion of the dielectric layer is between the first portion of the gate dielectric and the first portion of the spacer, and wherein the dielectric layer comprises a material different from the materials of the gate dielectric and the spacer.

[0005] According to another aspect of this disclosure, a semiconductor device is provided, comprising: a first nanostructure; a gate structure surrounding the first nanostructure, wherein the gate structure includes a gate electrode and a gate dielectric, and wherein a first portion of the gate electrode and a first portion of the gate dielectric are on the first nanostructure; a spacer, wherein a first portion of the spacer is on the first nanostructure; a first source / drain region in contact with the first nanostructure; and a dielectric layer, wherein a first portion of the dielectric layer is on the first nanostructure and the first portion of the gate dielectric, wherein the first portion of the dielectric layer is between the first portion of the gate dielectric and the first portion of the spacer, and wherein the dielectric layer comprises a material different from the materials of the gate dielectric and the spacer.

[0006] According to another aspect of this disclosure, a method for forming a semiconductor device is provided, the method comprising: forming a first nanostructure on a substrate; forming a dummy gate structure on the substrate, wherein the dummy gate structure includes a dummy gate and a dummy gate dielectric, and wherein the dummy gate dielectric is in contact with the first nanostructure; converting a first portion of the dummy gate at a sidewall of the dummy gate into a dielectric layer; removing the remaining portion of the dummy gate structure to form a first opening; and forming a gate structure in the first opening, wherein the gate structure includes a gate electrode and a gate dielectric, and wherein the gate dielectric is in contact with the first nanostructure and the dielectric layer. Attached Figure Description

[0007] Various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the art, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily enlarged or reduced.

[0008] Figure 1 An example of a nanostructured field-effect transistor (nanoFET) according to some embodiments is shown in a three-dimensional view.

[0009] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6A , Figure 6B , Figure 6C , Figure 6D , Figure 6E , Figure 7A , Figure 7B , Figure 7C , Figure 7D , Figure 7E , Figure 8A , Figure 8B , Figure 8C , Figure 8D , Figure 8E , Figure 9A , Figure 9B , Figure 9C , Figure 9D , Figure 9E , Figure 10A , Figure 10B , Figure 10C , Figure 10D , Figure 10E , Figure 11A , Figure 11B , Figure 11C , Figure 11D , Figure 11E , Figure 11F , Figure 12A , Figure 12B , Figure 12C , Figure 12D, Figure 12E , Figure 12F , Figure 12G , Figure 13A , Figure 13B , Figure 13C , Figure 13D , Figure 13E , Figure 14A , Figure 14B , Figure 14C , Figure 15A , Figure 15B , Figure 15C , Figure 15D , Figure 15E , Figure 16A , Figure 16B , Figure 16C , Figure 16D , Figure 16E , Figure 17A , Figure 17B , Figure 17C , Figure 17D , Figure 17E , Figure 17F , Figure 17G , Figure 18A , Figure 18B , Figure 18C , Figure 19A , Figure 19B , Figure 19C , Figure 20A , Figure 20B ,and Figure 20C This is a view of intermediate steps in the fabrication of a semiconductor device, including a nanoFET, according to some embodiments. Detailed Implementation

[0010] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. To simplify this disclosure, specific examples of components and arrangements are described below. These are, of course, merely examples and not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. Such repetition is for the purpose of brevity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0011] Furthermore, spatially related terms (e.g., "below," "under," "lower," "above," "higher," etc.) may be used herein to readily describe the relationship of one element or feature shown in the figure relative to another element(s) or feature(s). In addition to the orientations depicted in the figures, these spatially related terms are also intended to encompass different orientations of the device during use or operation. The device may be oriented in other directions (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein may be interpreted similarly accordingly.

[0012] Various embodiments provide semiconductor devices (e.g., nanoFETs) and methods of forming them. The methods may include forming an additional dielectric layer between the gate electrode and the source / drain regions by converting a portion of the dummy gate of the device into a dielectric layer before forming a gate spacer or removing a remaining dummy gate. Due to these dielectric layers (in addition to the gate spacer), the gate electrode can be positioned further away from the source / drain regions, and increased electrical insulation can be achieved between the gate electrode and the source / drain regions. Therefore, the risk of leakage current and parasitic capacitance between the gate electrode and the source / drain regions can be reduced, thereby improving the performance and reliability of the semiconductor device.

[0013] Some of the embodiments discussed herein are described in the context of semiconductor devices including nanoFETs. However, various embodiments can be applied to dies that include other types of transistors (e.g., fin field-effect transistors, vertical field-effect transistors, VFETs, complementary field-effect transistors, planar transistors, etc.) instead of or in combination with nanoFETs.

[0014] Figure 1An example of a nanoFET (e.g., nanowire FET, nanosheet FET, etc.) is shown in a three-dimensional view. The nanoFET includes nanostructures 55 (e.g., nanosheets, nanowires, etc.) on fins 66 on a substrate 50 (e.g., a semiconductor substrate), wherein the nanostructures 55 serve as channel regions for the nanoFET. The nanostructures 55 may include p-type nanostructures, n-type nanostructures, or combinations thereof. Shallow trench isolation (STI) regions 68 are disposed between adjacent fins 66, which may protrude above the adjacent STI regions 68. Although the STI regions 68 are described / shown as separated from the substrate 50, as used herein, the term "substrate" may refer only to the semiconductor substrate or to a combination of the semiconductor substrate and the STI regions. Furthermore, although the bottom portions of the fins 66 are shown as a single continuous material with the substrate 50, the bottom portions of the fins 66 and / or the substrate 50 may include a single material or multiple materials. In this context, fin 66 refers to the portion extending between adjacent STI regions 68.

[0015] Gate dielectric 100 is above the top surface of fin 66 and along the top, sidewalls, and bottom surface of nanostructure 55. Gate electrode 102 is above gate dielectric 100. Epitaxial source / drain regions 92 are disposed on fin 66 on opposite sides of gate dielectric 100 and gate electrode 102. (One or more) source / drain regions 92 may individually refer to the source or drain, or collectively to the source and drain, depending on the context.

[0016] Figure 1 Reference cross sections used in the following figures are also shown. Reference cross section A-A' is along the longitudinal axis of the gate electrode 102 and along a direction, for example, perpendicular to the current flow direction between the epitaxial source / drain regions 92 of the nanoFET. Reference cross section B-B' is parallel to reference cross section A-A' and extends through the epitaxial source / drain regions 92 of the plurality of nanoFETs. Reference cross section C-C' is perpendicular to reference cross section A-A' and parallel to the longitudinal axis of the fin 66 of the nanoFET and along, for example, the current flow direction between the epitaxial source / drain regions 92 of the nanoFET. For clarity, the following figures refer to these reference cross sections. Some embodiments discussed herein are discussed in the context of nanoFETs formed using a gate-last process. In other embodiments, a gate-first process may be used. Furthermore, some embodiments contemplate aspects used in planar devices (e.g., planar FETs) or FinFETs.

[0017] Figures 2 to 20C This is a view of intermediate steps in the fabrication of a semiconductor device, including a nanoFET, according to some embodiments. Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18A , Figure 19A and Figure 20A It shows along Figure 1 The cross-sectional view of the reference cross section A-A' is shown. Figure 6B , Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11B , Figure 12B , Figure 12F , Figure 13B , Figure 14B , Figure 15B , Figure 16B , Figure 17B , Figure 18B , Figure 19B and Figure 20B It shows along Figure 1 The cross-sectional view of the reference cross section B-B' is shown. Figure 6C , Figure 7C , Figure 8C , Figure 9C , Figure 10C , Figure 11C , Figure 11F , Figure 12C , Figure 12G , Figure 13C , Figure 14C , Figure 15C , Figure 16C , Figure 17C , Figure 18C , Figure 19C and Figure 20C It shows along Figure 1 The cross-sectional view of the reference cross section C-C' is shown.

[0018] exist Figure 2A substrate 50 is provided. The substrate 50 can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., and can be doped (e.g., doped with p-type or n-type dopant) or undoped. The substrate 50 can be a wafer, such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is disposed on the substrate (typically a silicon substrate or a glass substrate). Other substrates can also be used, such as multilayer substrates or gradient substrates. In some embodiments, the semiconductor material of the substrate 50 may include: silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium arsenide phosphide; or combinations thereof.

[0019] Substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form an n-type device (e.g., an NMOS transistor, such as an n-type nanoFET), and the p-type region 50P can be used to form a p-type device (e.g., a PMOS transistor, such as a p-type nanoFET). The n-type region 50N can be physically separated from the p-type region 50P (as shown by separator 20), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be provided between the n-type region 50N and the p-type region 50P. Although one n-type region 50N and one p-type region 50P are shown, any number of n-type regions 50N and p-type regions 50P can be provided.

[0020] In addition, Figure 2In this process, a multilayer stack 64 is formed on the substrate 50. The multilayer stack 64 includes alternating layers of first semiconductor layers 51A to 51C (collectively referred to as first semiconductor layer 51) and second semiconductor layers 53A to 53C (collectively referred to as second semiconductor layer 53). For illustrative purposes, as will be discussed in more detail below, the first semiconductor layer 51 will be removed, and the second semiconductor layer 53 will be patterned to form the channel region of the nanoFET in the n-type region 50N and the p-type region 50P. However, in some embodiments, the first semiconductor layer 51 may be removed, and the second semiconductor layer 53 may be patterned to form the channel region of the nanoFET in the n-type region 50N, and the second semiconductor layer 53 may be removed, and the first semiconductor layer 51 may be patterned to form the channel region of the nanoFET in the p-type region 50P. In some embodiments, the second semiconductor layer 53 may be removed, and the first semiconductor layer 51 may be patterned to form a channel region of the nanoFET in the n-type region 50N; and the first semiconductor layer 51 may be removed, and the second semiconductor layer 53 may be patterned to form a channel region of the nanoFET in the p-type region 50P. In some embodiments, the second semiconductor layer 53 may be removed, and the first semiconductor layer 51 may be patterned to form a channel region of the nanoFET in both the n-type region 50N and the p-type region 50P.

[0021] For illustrative purposes, the multilayer stack 64 is shown as comprising three layers each of a first semiconductor layer 51 and a second semiconductor layer 53. In some embodiments, the multilayer stack 64 may include any number of first semiconductor layers 51 and second semiconductor layers 53. Each layer of the multilayer stack 64 may be epitaxially grown using processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), or molecular beam epitaxy (MBE). In various embodiments, the first semiconductor layer 51 may be formed of a first semiconductor material (e.g., silicon, germanium, etc.), and the second semiconductor layer 53 may be formed of a second semiconductor material different from the first semiconductor material (e.g., silicon, silicon-doped carbon, etc.).

[0022] The first semiconductor material and the second semiconductor material can be materials with high etch selectivity relative to each other. This allows the first semiconductor layer 51 of the first semiconductor material to be removed without significantly removing the second semiconductor layer 53 of the second semiconductor material, thereby allowing the second semiconductor layer 53 to be patterned to form the channel region of the nanoFET. Similarly, in embodiments where the second semiconductor layer 53 is removed and the first semiconductor layer 51 is patterned to form the channel region, the second semiconductor layer 53 of the second semiconductor material can be removed without significantly removing the first semiconductor layer 51 of the first semiconductor material, thereby allowing the first semiconductor layer 51 to be patterned to form the channel region of the nanoFET.

[0023] According to some embodiments, in Figure 3 In this embodiment, fins 66 are formed in substrate 50, and nanostructures 55 are formed in multilayer stack 64. In some embodiments, nanostructures 55 and fins 66 can be formed in multilayer stack 64 and substrate 50, respectively, by etching trenches in multilayer stack 64 and substrate 50. Etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or combinations thereof. Etching can be anisotropic. Forming nanostructures 55 by etching multilayer stack 64 can further define first nanostructures 52A to 52C (collectively referred to as first nanostructures 52) from first semiconductor layer 51, and second nanostructures 54A to 54C (collectively referred to as second nanostructures 54) from second semiconductor layer 53. First nanostructures 52 and second nanostructures 54 can be collectively referred to as nanostructure 55.

[0024] The fins 66 and nanostructures 55 can be patterned using any suitable method. For example, one or more photolithography processes (including dual-patterning or multi-patterning processes) can be used to pattern the fins 66 and nanostructures 55. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, thereby allowing the production of patterns with, for example, spacing smaller than that achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate, and the sacrificial layer is patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fins 66.

[0025] For illustrative purposes, Figure 3 Fins 66 with substantially equal widths are shown in n-type region 50N and p-type region 50P. In some embodiments, the width of the fins 66 in n-type region 50N may be larger or thinner than the width of the fins 66 in p-type region 50P. Furthermore, while each fin 66 and each nanostructure 55 is shown to have a consistently consistent width, in other embodiments, the fins 66 and / or nanostructures 55 may have tapered sidewalls such that the width of each fin 66 and / or each nanostructure 55 continuously increases in the direction toward the substrate 50. In such embodiments, each nanostructure 55 may have a different width and be trapezoidal in shape.

[0026] exist Figure 4In the substrate 50, a shallow trench isolation (STI) region 68 is formed adjacent to the fin 66. The STI region 68 can be formed by depositing an insulating material on the substrate 50, fin 66, and nanostructure 55, and between adjacent fins 66. The insulating material can be an oxide (e.g., silicon oxide), a nitride, or a combination thereof, and can be formed by high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), or a combination thereof. Other insulating materials formed by any acceptable process can be used. In the illustrated embodiment, the insulating material is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process can be performed. In the embodiment, the insulating material is formed such that an excess of insulating material covers the nanostructure 55. Although the insulating material is shown as a single layer, some embodiments may use multiple layers. For example, in some embodiments, a liner (not shown separately) can be formed first along the surfaces of the substrate 50, fin 66, and nanostructure 55. A filler material, such as that discussed above, can then be formed on the liner.

[0027] Then, a removal process is applied to the insulating material to remove excess insulating material above the nanostructure 55. In some embodiments, a planarization process such as chemical mechanical polishing (CMP), etching back, or a combination thereof may be employed. The planarization process exposes the nanostructure 55 such that, after the planarization process is completed, the top surfaces of the nanostructure 55 and the insulating material can be substantially coplanar or flush.

[0028] The insulating material is then recessed to form STI regions 68. The insulating material is recessed such that the upper portions of the fins 66 in the n-type region 50N and p-type region 50P protrude from between adjacent STI regions 68. Furthermore, the top surface of the STI regions 68 can have a flat surface (as shown), a raised surface, a recessed surface (such as a dish shape), or a combination thereof. The top surface of the STI regions 68 can be formed as flat, raised, and / or recessed by appropriate etching. Acceptable etching processes can be used to recess the STI regions 68, for example, etching processes selective for the material of the insulating material (e.g., etching the material of the insulating material at a faster rate than etching the material of the fins 66 and nanostructures 55). For example, an oxide removal using, for example, dilute hydrofluoric acid can be used. Subsequently, an optional hard mask (not shown separately) can be formed over the top surface of the STI regions 68 to cover the STI regions 68. The hard mask may be made of nitride or other materials that have etch selectivity for STI region 68 (e.g., etch selectivity for the filling material of STI region 68).

[0029] The above text is about Figures 2 to 4The described process is an example of how the fins 66 and nanostructures 55 can be formed. In some embodiments, masking and epitaxial growth processes can be used to form the fins 66 and / or nanostructures 55. For example, a dielectric layer can be formed over the top surface of the substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. Epitaxial structures can be epitaxially grown in the trenches, and the dielectric layer can be recessed such that the epitaxial structure protrudes relative to the dielectric layer to form the fins 66 and / or nanostructures 55. The epitaxial structure can include alternating semiconductor materials discussed above, such as a first semiconductor material and a second semiconductor material. In some embodiments of epitaxial growth of the epitaxial structure, the material to be epitaxially grown can be in-situ doped during growth, which avoids prior and / or subsequent implantation, but in-situ doping and implantation doping can also be used together.

[0030] Furthermore, for illustrative purposes, the first semiconductor layer 51 (and the resulting first nanostructure 52) and the second semiconductor layer 53 (and the resulting second nanostructure 54) are shown and discussed herein as comprising the same material in the p-type region 50P and the n-type region 50N. In some embodiments, one or both of the first semiconductor layer 51 and the second semiconductor layer 53 may be different materials in the p-type region 50P and the n-type region 50N or may be formed in different orders in the p-type region 50P and the n-type region 50N.

[0031] exist Figure 5 In this process, a dummy dielectric layer 70 is formed on the fin 66, nanostructure 55, and / or STI region 68. The dummy dielectric layer 70 can be silicon oxide, silicon carbide, silicon nitride, combinations thereof, etc., and can be formed by a suitable deposition process. A dummy gate layer 72 is formed on the dummy dielectric layer 70, and a mask layer 74 is formed on the dummy gate layer 72. The dummy gate layer 72 can be deposited on the dummy dielectric layer 70, and then planarized, for example, by CMP. The mask layer 74 can be deposited on the dummy gate layer 72. The dummy gate layer 72 can be a conductive or non-conductive material, and can be selected from the group consisting of amorphous silicon, polysilicon, poly-SiGe, metal nitrides, metal silicides, metal oxides, and metals. The dummy gate layer 72 can be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques for depositing the selected material. The dummy gate layer 72 can be made of other materials that have high etch selectivity relative to the etching of the isolation region. The mask layer 74 can include, for example, silicon nitride, silicon oxynitride, etc. In this example, a single dummy gate layer 72 and a single mask layer 74 are formed across the n-type region 50N and the p-type region 50P.

[0032] Figures 6A to 20CCross-sectional and top views are shown illustrating various additional steps in the fabrication of semiconductor devices, including nanoFETs, according to some embodiments. Unless otherwise stated, Figures 6A to 20C The characteristics of either the n-type region 50N or the p-type region 50P are shown.

[0033] exist Figures 6A to 6E In this structure, a mask 78, a dummy gate 76, and a dummy gate dielectric 71 are formed. The dummy gate 76 and the dummy gate dielectric 71 can be collectively referred to as the dummy gate structure. Figure 6D It shows Figure 6A , Figure 6B and Figure 6C The diagram shows a top view of a portion of the structure including the second nanostructure 54A along a reference cross section D-D'. Figure 6E It shows Figure 6A , Figure 6B and Figure 6C The illustrated structure is a top view of a portion including the first nanostructure 52A along a reference cross section E-E'. The following discussion uses a top view of the second nanostructure 54A as an example of the second nanostructure 54, and a top view of the first nanostructure 52A above the same fin 66 as an example of the first nanostructure 52. The same or similar shapes, sizes, and properties may also apply to other second nanostructures 54 and first nanostructures 52.

[0034] The mask layer 74 can be patterned using appropriate photolithography and etching processes (see...). Figure 5 A mask 78 is formed. The pattern of the mask 78 can then be transferred to the dummy gate layer 72 and the dummy dielectric layer 70 using a suitable etching process to form the dummy gate 76 and the dummy gate dielectric 71, respectively. The dummy gate 76 covers the corresponding channel region of the fin 66. The pattern of the mask 78 can be used to separate each dummy gate 76 from the adjacent dummy gate 76 entities. The dummy gate 76 may also have a length direction substantially perpendicular to the length direction of the corresponding fin 66.

[0035] like Figure 6C As shown, the portion of the dummy gate 76 above the nanostructure 55 can have a width W1 in the range of about 10 nm to about 15 nm (e.g., about 13 nm). Figure 6D and Figure 6E As shown, after the etching process, the dummy gate 76 may have recessed sidewalls in the top view. The width of the portion of the dummy gate 76 between adjacent first nanostructures 52A (in the top view) may decrease as the dummy gate 76 extends away from the corresponding dummy gate dielectric 71. The width of the portion of the dummy gate 76 between adjacent second nanostructures 54A (in the top view) may decrease as the dummy gate 76 extends away from the corresponding dummy gate dielectric 71.

[0036] exist Figures 7A to 7E In this process, the portion of the dummy gate 76 at its sidewalls is converted into a dielectric layer 77. The dielectric layer 77 can increase the distance and electrical insulation between the subsequently formed source / drain regions and the gate electrode, as described in more detail below. Figure 7D It shows Figure 7A , Figure 7B and Figure 7C The diagram shows a top view of a portion of the structure including the second nanostructure 54A along a reference cross section D-D'. Figure 7E It shows Figure 7A , Figure 7B and Figure 7C The illustrated structure is a top view of a portion including the first nanostructure 52A along a reference cross section E-E'. The transition of these portions of the dummy gate 76 to the dielectric layer 77 can be accomplished by the reaction of these portions of the dummy gate 76 with oxygen. In embodiments where the dummy gate 76 comprises silicon (e.g., polycrystalline silicon), the dielectric layer 77 may comprise silicon oxide (e.g., silicon dioxide). In some embodiments, the dielectric layer 77 and the dummy gate dielectric 71 comprise different materials. In some embodiments, the dielectric layer 77 and the dummy gate dielectric 71 comprise the same material.

[0037] like Figure 7C As shown, after the dielectric layer 77 is formed, the portion of the dummy gate 76 above the nanostructure 55 can have a width W2 in the range of about 9 nm to about 14 nm (e.g., about 12.08 nm). Due to the transition of these portions of the dummy gate 76 to the dielectric layer 77, the width W2 can be smaller than that shown. Figure 6C The width W1 is shown. The dielectric layer 77 can have a width W3 in the range of about 0.8 nm to about 1.2 nm (e.g., about 1 nm). The dielectric layer 77 can be wider than the corresponding portion of the dummy gate 76 consumed in forming the dielectric layer 77. For example, a portion of the dummy gate 76 with a thickness of about 0.46 nm can be converted into a dielectric layer 77 with a thickness W3. The total width of the dummy gate 76 and the corresponding dielectric layer 77 can be in the range of about 11 nm to about 16 nm, for example, about 14.08 nm. Figure 7D and Figure 7E As shown, the dummy gate 76 has the same characteristics as the reference above. Figure 6D and Figure 6E The dummy gate 76 is described to have a similar shape, and some portions of the dielectric layer 77 may have an arcuate shape with a raised inner sidewall in contact with the dummy gate 76 and an exposed recessed outer sidewall.

[0038] In some embodiments, the conversion of these portions of the dummy gate 76 to the dielectric layer 77 is accomplished by performing an annealing process (e.g., a rapid thermal annealing (RTA) process) with oxygen. The annealing temperature can be in the range of about 600°C to about 800°C. The annealing time can be in the range of about 10 seconds to about 60 seconds. The annealing pressure can be in the range of about 1 Torr to about 760 Torr. The oxygen concentration in the annealing chamber can be in the range of about 500 ppm to about 1%.

[0039] In some embodiments, the conversion of these portions of the dummy gate 76 to the dielectric layer 77 is accomplished by performing an annealing process (e.g., an RTA process) using oxygen and oxygen plasma. The annealing temperature can range from about 200°C to about 550°C. The annealing time can range from about 10 seconds to about 60 seconds. The annealing pressure can range from about 0.1 Torr to about 5 Torr. The oxygen flow rate can range from about 100 sccm to about 1000 sccm. The oxygen plasma can be generated at a power range from about 2.5 kW to about 6 kW.

[0040] exist Figures 8A to 8E In this process, spacers 81 are formed on the sidewalls of the dielectric layer 77. Figure 8D It shows Figure 8A , Figure 8B and Figure 8C The diagram shows a top view of a portion of the structure including the second nanostructure 54A along a reference cross section D-D'. Figure 8E It shows Figure 8A , Figure 8B and Figure 8C The illustrated structure is a top view of a portion including the first nanostructure 52A along a reference cross section E-E'. The spacer 81 can protect the dummy gate dielectric 71 and the dummy gate 76 during subsequent etching processes. The spacer 81 can be a single layer of one material or multiple sublayers of different materials with different etching rates. In some embodiments, the spacer 81 comprises two sublayers of different materials with different etching rates, which may be selected from silicon carbide, silicon nitride, silicon oxynitride, silicon oxycarbide, etc. The material of the dielectric layer 77 and the material of the spacer 81 may be different.

[0041] The spacer 81 can be formed by: forming a spacer layer using a suitable deposition process (e.g., CVD, ALD, etc.), and then patterning the spacer layer using a suitable etching process (e.g., isotropic etching (e.g., wet etching), anisotropic etching (e.g., dry etching)). The spacer layer can be formed on: the top surface of the STI region 68; the top surface and sidewalls of the fin 66, nanostructure 55, and mask 78; and the sidewalls of the dummy gate 76, dummy gate dielectric 71, and dielectric layer 77. After the etching process, the spacer 81 can remain on: the sidewalls of the fin 66 and / or nanostructure 55, such as... Figure 8B As shown; and on the sidewalls of mask 78, dummy gate 76, dummy gate dielectric 71 and dielectric layer 77, as Figures 8C to 8E As shown.

[0042] exist Figures 9A to 9E In some embodiments, recesses 86 are formed in fin 66, nanostructure 55 and substrate 50. Figure 9D It shows Figure 9A , Figure 9B and Figure 9C The diagram shows a top view of a portion of the structure including the second nanostructure 54A along a reference cross section D-D'. Figure 9E It shows Figure 9A , Figure 9B and Figure 9C The illustrated structure is a top view of a portion including the first nanostructure 52A along a reference cross-section E-E'. Epitaxial source / drain regions can then be formed in the recess 86. The recess 86 can extend through the first nanostructure 52 and the second nanostructure 54, and into the substrate 50. Figure 9B As shown, the top surface of the STI region 68 may be flush with the bottom surface of the recess 86. In some embodiments, the bottom surface of the recess 86 is disposed below the top surface of the STI region 68, and so on.

[0043] The recess 86 can be formed by etching the fin 66, nanostructure 55, and substrate 50 using an anisotropic etching process (e.g., RIE, NBE, etc.). During the etching process used to form the recess 86, spacer 81 and mask 78 can mask portions of the fin 66, nanostructure 55, and substrate 50. Each layer of nanostructure 55 and / or fin 66 can be etched using a single-pass etching process or a multi-pass etching process. A timed etching process can be used to stop etching after the recess 86 reaches the desired depth.

[0044] exist Figures 10A to 10E In the middle, the first nanostructure 52 is replaced by the sacrificial layer 79. Figure 10D It shows Figure 10A , Figure 10B and Figure 10CThe diagram shows a top view of a portion of the structure including the second nanostructure 54A along a reference cross section D-D'. Figure 10E It shows Figure 10A , Figure 10B and Figure 10C The illustrated structure is a top view of a portion including the sacrificial layer 79 along a reference cross section E-E'. Replacing the first nanostructure 52 with the sacrificial layer 79 prevents defects from forming on the surface of the second nanostructure 54 adjacent to the first nanostructure 52 during subsequent annealing processes. The sidewalls of the sacrificial layer 79 may be recessed relative to the sidewalls of the second nanostructure 54. As an example, the sidewalls of the sacrificial layer 79 are... Figure 10C As shown in the middle as vertical, in some embodiments, the sidewalls of the sacrificial layer 79 may be recessed.

[0045] The sacrificial layer 79 can be formed through a suitable deposition process followed by a suitable etching process, whereby the etching process removes excess material from the deposited material. The deposition process can be CVD, ALD, etc. The etching process can be a dry etching process using one or more etchants (e.g., hydrofluoric acid, ammonia, etc.). The sacrificial layer 79 can include a dielectric material, such as silicon carbide, silicon nitride, silicon oxynitride, silicon oxycarbide, etc. The material of the dielectric layer 77 and the material of the sacrificial layer 79 can be different.

[0046] exist Figures 11A to 11E In the middle, an internal spacer 90 is formed on the side wall of the sacrificial layer 79. Figure 11D It shows Figure 11A , Figure 11B and Figure 11C The diagram shows a top view of a portion of the structure including the second nanostructure 54A along a reference cross section D-D'. Figure 11E It shows Figure 11A , Figure 11B and Figure 11C The illustrated structure is a top view of a portion including the sacrificial layer 79 along a reference cross section E-E'. The internal spacer 90 can serve as an isolation feature between the subsequently formed source / drain regions and the gate structure. As will be discussed in more detail below, the source / drain regions can be formed in the recess 86, and the sacrificial layer 79 can be replaced with a corresponding gate structure.

[0047] It can be done in Figures 10A to 10CAn internal spacer layer (not shown separately) is deposited on the structure shown, and then etched to form the internal spacer 90. The internal spacer layer can be deposited using a conformal deposition process (e.g., CVD, ALD, etc.). The internal spacer layer can comprise materials such as silicon nitride or silicon oxynitride, but any suitable material can be used, such as a low-k material with a k value less than about 3.5. The internal spacer layer can then be etched using an anisotropic etching process (e.g., RIE, NBE, etc.) to form the internal spacer 90. The internal spacer 90 can be used to protect subsequently formed source / drain regions during subsequent etching processes (e.g., etching processes for forming gate structures).

[0048] As an example, the outer wall of the inner spacer 90 is in Figure 11C The inner spacer 90 is shown flush with the sidewall of the second nanostructure 54, while the outer wall of the inner spacer 90 may extend beyond or be recessed relative to the sidewall of the second nanostructure 54. Furthermore, as an example, the outer wall of the inner spacer 90 is... Figure 11C The middle section is shown as vertical, while the outer wall of the inner spacer 90 may be recessed. Figure 11F An embodiment is shown in which the sidewalls of the sacrificial layer 79 are recessed, the outer sidewalls of the inner spacer 90 are recessed, and the inner spacer 90 is concave relative to the sidewalls of the second nanostructure 54.

[0049] exist Figures 12A to 12E In the middle, an epitaxial source / drain region 92 is formed in the recess 86. Figure 12D It shows Figure 12A , Figure 12B and Figure 12C The diagram shows a top view of a portion of the structure including the second nanostructure 54A along a reference cross section D-D'. Figure 12E It shows Figure 12A , Figure 12B and Figure 12C The illustrated structure is a top view of a portion including the sacrificial layer 79 along a reference cross-section E-E'. In some embodiments, the epitaxial source / drain region 92 can apply stress to the second nanostructure 54, thereby improving performance. Figure 12C As shown, an epitaxial source / drain region 92 is formed in the recess 86, such that each dummy gate 76 is disposed between corresponding adjacent pairs of the epitaxial source / drain regions 92. Figure 12D and Figure 12E As shown, the epitaxial source / drain region 92 is separated from the dielectric layer 77 by the spacer 81.

[0050] An epitaxial source / drain region 92 in an n-type region 50N (e.g., an NMOS region) can be formed by masking a p-type region 50P (e.g., a PMOS region). The epitaxial source / drain region 92 is then epitaxially grown in a recess 86 within the n-type region 50N. The epitaxial source / drain region 92 can comprise any acceptable material suitable for an n-type nano-FET. For example, if the second nanostructure 54 is silicon, the epitaxial source / drain region 92 can comprise a material to which tensile strain is applied to the second nanostructure 54, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, etc. The epitaxial source / drain region 92 can have a surface that protrudes relative to the corresponding upper surface of the nanostructure 55 and can have facets.

[0051] Epitaxial source / drain regions 92 in a p-type region 50P (e.g., a PMOS region) can be formed by masking an n-type region 50N (e.g., an NMOS region). The epitaxial source / drain regions 92 are then epitaxially grown in a recess 86 within the p-type region 50P. The epitaxial source / drain regions 92 can comprise any acceptable material suitable for a p-type nanoFET. For example, if the second nanostructure 54 is silicon, the epitaxial source / drain regions 92 can comprise a material that applies compressive strain to the second nanostructure 54, such as silicon-germanium, boron-doped silicon-germanium, germanium, germanium-tin, etc. The epitaxial source / drain regions 92 can also have surfaces that protrude relative to the corresponding surfaces of the multilayer stack 64 and can have small facets.

[0052] The epitaxial source / drain region 92, the second nanostructure 54, and / or the substrate 50 can be implanted with dopants to form the source / drain region, followed by annealing. The source / drain region can have a density of approximately 1 × 10⁻⁶. 19 atoms / cm 3 1×10 21 atoms / cm 3 The impurity concentrations between the two. The n-type and / or p-type impurities in the source / drain regions can be any suitable impurities. In some embodiments, the epitaxial source / drain regions 92 can be doped in situ during growth.

[0053] As a result of the epitaxial process used to form epitaxial source / drain regions 92 in n-type region 50N and p-type region 50P, the upper surface of the epitaxial source / drain regions 92 has small facets that extend laterally outward beyond the sidewalls of the nanostructure 55. In some embodiments, these small facets cause adjacent epitaxial source / drain regions 92 of the same nanoFET to merge, such as... Figure 12B As shown. In some embodiments, adjacent epitaxial source / drain regions 92 remain separated after the epitaxial process is completed, as... Figure 12F As shown. In Figure 12B and Figure 12FIn the illustrated embodiment, spacer 81 may be formed onto the top surface of STI region 68 to block epitaxial growth. In some embodiments, the etching process used to form spacer 81 may be adjusted to remove spacer material, thereby allowing the epitaxial growth region to extend to the surface of STI region 68.

[0054] The epitaxial source / drain region 92 may include one or more semiconductor material layers. In some embodiments, the epitaxial source / drain region 92 includes: a first liner layer 92A on the sidewall of the second nanostructure 54, a second liner layer 92B on the first liner layer 92A, and a filling layer 92C on the second liner layer 92B, such as Figure 12C As shown. The first liner layer 92A, the second liner layer 92B, and the fill layer 92C can be formed of different semiconductor materials and / or can be doped with different dopant concentrations. The first liner layer 92A can be grown first, the second liner layer 92B can be grown on the first liner layer 92A, and the fill layer 92C can be grown on the second liner layer 92B.

[0055] Figure 12G An embodiment is shown in which the sidewalls of the sacrificial layer 79 are recessed, the outer sidewalls of the inner spacer 90 are recessed, and the inner spacer 90 is recessed relative to the sidewalls of the second nanostructure 54. For example... Figure 12G As shown, the epitaxial source / drain region 92 can be formed to contact the internal spacer 90 and can extend over the sidewalls of the second nanostructure 54.

[0056] exist Figures 13A to 13E In Figures 12A to 12E The first interlayer dielectric (ILD) 96 is deposited on the structure shown. Figure 13D It shows Figure 13A , Figure 13B and Figure 13C The diagram shows a top view of a portion of the structure including the second nanostructure 54A along a reference cross section D-D'. Figure 13E It shows Figure 13A , Figure 13B and Figure 13C The diagram shows a top view of the portion of the structure including the sacrificial layer 79 along the reference cross section E-E'.

[0057] The first ILD 96 can be formed of a dielectric material and can be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process can be used. In some embodiments, a contact etch stop layer (CESL) 94 is disposed between the first ILD 96 and the epitaxial source / drain region 92, mask 78, and spacer 81. The CESL 94 may include a dielectric material (e.g., silicon nitride, silicon oxide, or silicon oxynitride, etc.) that has etch selectivity to the material of the overlying first ILD 96.

[0058] exist Figures 14A to 14C In this process, a planarization process (e.g., CMP) can be performed to make the top surface of the first ILD 96 flush with the top surfaces of the dummy gate 76, dielectric layer 77, and spacer 81. The planarization process can also remove the mask 78 on the dummy gate 76 and portions of the spacer 81 along the sidewalls of the mask 78. After the planarization process, the top surfaces of the dummy gate 76, dielectric layer 77, spacer 81, and first ILD 96 can be flush within a process variation. Thus, the top surfaces of the dummy gate 76 and dielectric layer 77 are exposed. In some embodiments, portions of the mask 78 are retained after the planarization process, in which case the planarization process makes the top surface of the first ILD 96 flush with the top surfaces of the mask 78 and spacer 81.

[0059] exist Figures 15A to 15E In one or more etching processes, the remaining portion of the dummy gate 76 and the dummy gate dielectric 71 is removed to form the third recess 98. Figure 15D It shows Figure 15A , Figure 15B and Figure 15C The diagram shows a top view of a portion of the structure including the second nanostructure 54A along a reference cross section D-D'. Figure 15E It shows Figure 15A , Figure 15B and Figure 15CThe illustrated structure is a top view of a portion of the structure including the sacrificial layer 79 along a reference cross section E-E'. The dummy gate 76 and dummy gate dielectric 71 can be removed by an anisotropic dry etching process. The etching process can use an etchant that selectively etches the dummy gate 76 and dummy gate dielectric 71, while the first ILD 96, internal spacers 90, and spacers 81 can remain substantially intact. In embodiments where the dielectric layer 77 and dummy gate dielectric 71 comprise different materials, the dielectric layer 77 is substantially intact after the etching process. In embodiments where the dielectric layer 77 and dummy gate dielectric 71 comprise the same material, the dielectric layer 77 is partially removed and has a reduced thickness remaining after the etching process. During the etching process, the dummy gate dielectric 71 can be used as an etch stop layer when removing the dummy gate 76 and can be removed after removing the dummy gate 76. After the etching process, the second nanostructure 54, sacrificial layer 79, internal spacers 90, and dielectric layer 77 can be exposed.

[0060] exist Figures 16A to 16E In the middle, the sacrificial layer 79 is removed, which causes the third recess 98 to extend. Figure 16D It shows Figure 16A , Figure 16B and Figure 16C The diagram shows a top view of a portion of the structure including the second nanostructure 54A along a reference cross section D-D'. Figure 16E It shows Figure 16A , Figure 16B and Figure 16C The diagram shows a portion of the structure as a top view along a reference cross section E-E'. The sacrificial layer 79 can be removed using one or more suitable etching processes (e.g., isotropic etching). The etching process can be a wet or dry etching process using fluorine-based chemicals as etchants. During the etching process, the sacrificial layer 79 can be selectively etched, while the second nanostructure 54, dielectric layer 77, spacer 81, internal spacer 90, and epitaxial source / drain region 92 can remain substantially intact.

[0061] exist Figures 17A to 17E In the third recess 98, a gate dielectric 100 and a gate electrode 102 are formed. Figure 17D It shows Figure 17A , Figure 17B and Figure 17C The diagram shows a top view of a portion of the structure including the second nanostructure 54A along a reference cross section D-D'. Figure 17E It shows Figure 17A , Figure 17B and Figure 17CThe diagram shows a portion of the structure as a top view along a reference cross section E-E'. A dielectric layer 77 is present between the gate dielectric 100 and the spacer 81. Due to the dielectric layer 77, the gate electrode 102 can be positioned further away from the epitaxial source / drain region 92, and increased electrical insulation can be achieved between the gate electrode 102 and the epitaxial source / drain region 92. Therefore, the risk of leakage current and parasitic capacitance between the epitaxial source / drain region 92 and the gate electrode 102 can be reduced, thereby improving the performance and reliability of the subsequently formed semiconductor device.

[0062] The gate dielectric 100 can be conformally deposited in the third recess 98. The gate dielectric 100 can be formed on the top surface and sidewalls of the substrate 50, and on the top surface, sidewalls, and bottom surface of the second nanostructure 54. The gate dielectric 100 can be deposited on the top surface of the first ILD 96, CESL 94, spacer 81, and STI region 68, on the bottom surface of dielectric layer 77, and on the sidewalls of spacer 81, dielectric layer 77, and internal spacer 90. Figure 17D and Figure 17E As shown, the gate dielectric 100 can contact the raised inner sidewall of the dielectric layer 77, and the second nanostructure 54A is separated from the dielectric layer 77 by the gate dielectric 100. The gate dielectric 100 includes one or more dielectric layers. In some embodiments, the gate dielectric 100 includes a high-k dielectric material, such as oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, or combinations thereof. The material of the dielectric layer 77 and the material of the gate dielectric 100 may be different. The gate dielectric 100 can be formed by a suitable deposition method (e.g., molecular beam deposition (MBD), ALD, PECVD, etc.).

[0063] The gate electrode 102 can be formed on the gate dielectric 100 by electroplating or the like and fill the remaining portion of the third recess 98. For example... Figure 17D As shown, the gate electrode 102 may have recessed sidewalls. The width of the portion of the gate electrode 102 between adjacent second nanostructures 54A may decrease as the gate electrode 102 extends away from the second nanostructures 54A. The gate electrode 102 may comprise a metallic material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, or combinations thereof. Figure 17A , Figure 17C , Figure 17D and Figure 17EA single-layer gate electrode 102 is shown as an example, but the gate electrode 102 may include any number of liner layers, any number of work function tuning layers, and fill material. After filling the third recess 98, a planarization process (e.g., CMP) may be performed to remove excess portions of material from the gate dielectric 100 and the gate electrode 102 above the top surface of the first ILD 96. The gate electrode 102 and the gate dielectric 100 may be collectively referred to as the gate structure 103.

[0064] The formation of the gate dielectric 100 in the n-type region 50N and the p-type region 50P can occur simultaneously, such that the gate dielectric 100 in each region is formed of the same material, and the formation of the gate electrode 102 can occur simultaneously, such that the gate electrode 102 in each region is formed of the same material. In some embodiments, the gate dielectric 100 in each region can be formed by different processes, such that the gate dielectric 100 can be made of different materials and / or have different numbers of layers, and / or the gate electrode 102 in each region can be formed by different processes, such that the gate electrode 102 can be made of different materials and / or have different numbers of layers. When using different processes, various masking steps can be used to mask and expose appropriate regions.

[0065] Figure 17F and Figure 17G The diagram illustrates the relationship between [various embodiments] and [other embodiments]. Figure 17D The structures shown are similar, wherein the same reference numerals denote the same features formed by the same process. Figure 17F and Figure 17G In the illustrated embodiment, an interface layer 101 is formed on the exposed surface of the second nanostructure 54 prior to the deposition of the gate dielectric 100. The interface layer 101 may be between and in contact with the gate dielectric 100 and the second nanostructure 54. The interface layer 101 may be in contact with the spacer 81. The interface layer 101 may include a dielectric material, such as silicon oxide. In some embodiments, the interface layer 101 and the dielectric layer 77 comprise the same material. The interface layer 101 may be formed by a suitable oxidation method (e.g., thermal oxidation, chemical oxidation, etc.). In some embodiments, the interface layer 101 and the dielectric layer 77 are formed by different processes. Figure 17F In the illustrated embodiment, the interface layer 101 is separated from the dielectric layer 77 by the gate dielectric 100. Figure 17G In the embodiment shown, the interface layer 101 is in contact with the dielectric layer 77.

[0066] Figures 3 to 17EAn embodiment is shown in which the first nanostructure 52 is initially replaced by a sacrificial layer 79, and then the sacrificial layer 79 is removed to form a space for the gate structure 103. In other embodiments, the first nanostructure 52 is not replaced by the sacrificial layer 79, and the first nanostructure 52 is removed to directly form a space for the gate structure 103.

[0067] exist Figures 18A to 18C In this design, the gate structure 103 is recessed, and a recess is formed directly above the gate structure 103 and between opposing portions of the spacer 81. A gate mask 104 comprising one or more layers of dielectric material (e.g., silicon nitride, silicon oxynitride, etc.) is filled into the recess, followed by a planarization process to remove excess dielectric material extending over the first ILD 96. The subsequently formed gate contacts can extend through the gate mask 104 to contact the top surface of the recessed gate electrode 102. Figures 18A to 18C Further shown, a second ILD 106 is deposited over the first ILD 96 and the gate mask 104. In some embodiments, the second ILD 106 is a flowable film formed by FCVD. In some embodiments, the second ILD 106 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., and can be deposited by any suitable method such as CVD or PECVD. In some embodiments, the gate mask 104 may be omitted, and the second ILD 106 is formed on the gate structure 103 and the first ILD 96.

[0068] exist Figures 19A to 19C In the process, the second ILD 106, the first ILD 96, CESL 94, and the gate mask 104 are etched to form a fourth recess 108, which exposes the epitaxial source / drain regions 92 and / or some of the surfaces of the gate structures 103. The fourth recess 108 can be formed by etching using an anisotropic etching process (e.g., RIE or NBE). In some embodiments, the fourth recess 108 can be etched through the second ILD 106 and the first ILD 96 using a first etching process; it can be etched through the gate mask 104 using a second etching process; and then it can be etched through the CESL 94 using a third etching process. A mask (e.g., photoresist) can be formed on the second ILD 106 and patterned to mask portions of the second ILD 106 in the first and second etching processes. In some embodiments, the fourth recess 108 extends into the epitaxial source / drain region 92 and / or some gate structures, and the bottom of the fourth recess 108 may be flush with the epitaxial source / drain region 92 and / or some gate structures (e.g., on the same horizontal plane or having the same distance to the substrate 50), or lower than the epitaxial source / drain region 92 and / or some gate structures (e.g., closer to the substrate 50).

[0069] After the fourth recess 108 is formed, a first silicide region 110 is formed over the epitaxial source / drain region 92. In some embodiments, the first silicide region 110 is formed by first depositing a metal (not shown separately) capable of reacting with the underlying semiconductor material (e.g., silicon, silicon-germanium, germanium) of the epitaxial source / drain region 92 to form a silicide or germanide region (e.g., nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals, or alloys thereof) over the exposed portion of the epitaxial source / drain region 92, and then performing a first thermal annealing process to form the first silicide region 110. Unreacted portions of the deposited metal are then removed, for example, by an etching process. Although the first silicide region 110 is referred to as a silicide region, it can also be a germanide region or a silicon-germanide region (e.g., a region comprising both silicide and germanide).

[0070] exist Figures 20A to 20C In the fourth recess 108, source / drain contacts 112 and gate contacts 114 (also referred to as conductive contacts) are formed. Figures 20A to 20C The structure shown may be referred to as semiconductor device 120. The source / drain contact 112 and gate contact 114 may each include one or more layers, such as a barrier layer, a diffusion layer, and a filler material. In some embodiments, the source / drain contact 112 and gate contact 114 each include a barrier layer and a conductive material, and are each electrically connected to the underlying conductive features (e.g., gate electrode 102 and / or first silicide region 110). Gate contact 114 is electrically connected to gate electrode 102, and source / drain contact 112 is electrically connected to first silicide region 110. The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process such as CMP may be performed to remove excess material from the surface of the second ILD 106.

[0071] The embodiments of this disclosure have several advantageous features. By forming the dielectric layer 77, the gate electrode 102 can be positioned further away from the epitaxial source / drain region 92, and increased electrical insulation can exist between the gate electrode 102 and the epitaxial source / drain region 92. Therefore, the risk of leakage and parasitic capacitance between the epitaxial source / drain region 92 and the gate electrode 102 can be reduced, thereby improving the performance and reliability of the semiconductor device 120.

[0072] In an embodiment, a semiconductor device includes: a first source / drain region; a first nanostructure adjacent to the first source / drain region; a second source / drain region; a second nanostructure adjacent to the second source / drain region; a gate structure surrounding the first and second nanostructures, wherein the gate structure includes a gate electrode and a gate dielectric, and wherein a first portion of the gate electrode and a first portion of the gate dielectric are between the first and second nanostructures; a spacer, wherein a first portion of the spacer is between the first and second source / drain regions; and a dielectric layer, wherein a first portion of the dielectric layer is between the first portion of the gate dielectric and the first portion of the spacer, and wherein the dielectric layer comprises a material different from the materials of the gate dielectric and the spacer. In an embodiment, the dielectric layer comprises silicon oxide. In an embodiment, the first portion of the dielectric layer is separated from the first and second nanostructures by the first portion of the gate dielectric. In an embodiment, the first portion of the dielectric layer is separated from the first and second source / drain regions by the first portion of the spacer. In an embodiment, in a top view, a first portion of the dielectric layer has a raised sidewall contacting a first portion of the gate dielectric and a recessed sidewall contacting a first portion of the spacer. In an embodiment, in a top view, the width of the first portion of the gate electrode decreases as the first portion of the gate electrode extends away from the first nanostructure and the second nanostructure. In an embodiment, a second portion of the dielectric layer, a second portion of the gate dielectric, and a second portion of the spacer are situated above the first nanostructure and the second nanostructure, wherein the second portion of the dielectric layer lies between the second portion of the gate dielectric and the second portion of the spacer.

[0073] In an embodiment, a semiconductor device includes: a first nanostructure; a gate structure surrounding the first nanostructure, wherein the gate structure includes a gate electrode and a gate dielectric, and wherein a first portion of the gate electrode and a first portion of the gate dielectric are on the first nanostructure; a spacer, wherein a first portion of the spacer is on the first nanostructure; a first source / drain region in contact with the first nanostructure; and a dielectric layer, wherein a first portion of the dielectric layer is on the first nanostructure and the first portion of the gate dielectric, wherein the first portion of the dielectric layer is between the first portion of the gate dielectric and the first portion of the spacer, and wherein the dielectric layer comprises a material different from the material of the gate dielectric and the spacer. In an embodiment, the first portion of the gate dielectric is between the first portion of the dielectric layer and the first nanostructure. In an embodiment, the bottom surface of the first portion of the dielectric layer is in contact with the first portion of the gate dielectric. In an embodiment, the first portion of the spacer is between the first portion of the dielectric layer and the first source / drain region. In one embodiment, in a top view, a second portion of the gate dielectric is in contact with the first nanostructure, wherein a second portion of the spacer is in contact with the second portion of the gate dielectric, and wherein a second portion of the dielectric layer is located between the second portion of the gate dielectric and the second portion of the spacer. In one embodiment, the dielectric layer comprises silicon oxide.

[0074] In an embodiment, a method of forming a semiconductor device includes: forming a first nanostructure on a substrate; forming a dummy gate structure on the substrate, wherein the dummy gate structure includes a dummy gate and a dummy gate dielectric, and wherein the dummy gate dielectric is in contact with the first nanostructure; converting a first portion of the dummy gate at a sidewall of the dummy gate into a dielectric layer; removing the remaining portion of the dummy gate structure to form a first opening; and forming a gate structure in the first opening, wherein the gate structure includes a gate electrode and a gate dielectric, and wherein the gate dielectric is in contact with the first nanostructure and the dielectric layer. In an embodiment, converting the first portion of the dummy gate at a sidewall of the dummy gate into a dielectric layer includes: performing an annealing process with oxygen. In an embodiment, the annealing process is further performed using oxygen plasma. In an embodiment, the dielectric layer and the gate dielectric comprise different materials. In an embodiment, the dummy gate comprises polysilicon, and the dielectric layer comprises silicon oxide. In one embodiment, in a top view, a first portion of the gate dielectric is in contact with the first nanostructure, wherein a first portion of the dielectric layer is in contact with the first portion of the gate dielectric, and wherein the first portion of the dielectric layer has an arcuate shape. In another embodiment, the first portion of the dielectric layer is separated from the first nanostructure by the first portion of the gate dielectric.

[0075] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should appreciate that they can readily use this disclosure as a basis for designing or modifying other processes and structures to perform the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

[0076] Example 1. A semiconductor device comprising: a first source / drain region; a first nanostructure adjacent to the first source / drain region; a second source / drain region; a second nanostructure adjacent to the second source / drain region; a gate structure surrounding the first nanostructure and the second nanostructure, wherein the gate structure includes a gate electrode and a gate dielectric, and wherein a first portion of the gate electrode and a first portion of the gate dielectric are located between the first nanostructure and the second nanostructure; a spacer, wherein a first portion of the spacer is located between the first source / drain region and the second source / drain region; and a dielectric layer, wherein a first portion of the dielectric layer is located between the first portion of the gate dielectric and the first portion of the spacer, and wherein the dielectric layer comprises a material different from the material of the gate dielectric and the spacer.

[0077] Example 2. The semiconductor device according to Example 1, wherein the dielectric layer comprises silicon oxide.

[0078] Example 3. The semiconductor device according to Example 1, wherein a first portion of the dielectric layer is separated from the first nanostructure and the second nanostructure by a first portion of the gate dielectric.

[0079] Example 4. The semiconductor device according to Example 1, wherein a first portion of the dielectric layer is separated from the first source / drain region and the second source / drain region by a first portion of the spacer.

[0080] Example 5. The semiconductor device according to Example 1, wherein, in a top view, a first portion of the dielectric layer has a raised sidewall that contacts a first portion of the gate dielectric and a recessed sidewall that contacts a first portion of the spacer.

[0081] Example 6. The semiconductor device according to Example 1, wherein, in a top view, the width of a first portion of the gate electrode decreases as the first portion of the gate electrode extends away from the first nanostructure and the second nanostructure.

[0082] Example 7. The semiconductor device according to Example 1, wherein a second portion of the dielectric layer, a second portion of the gate dielectric, and a second portion of the spacer are on the first nanostructure and the second nanostructure, and wherein the second portion of the dielectric layer is between the second portion of the gate dielectric and the second portion of the spacer.

[0083] Example 8. A semiconductor device comprising: a first nanostructure; a gate structure surrounding the first nanostructure, wherein the gate structure includes a gate electrode and a gate dielectric, and wherein a first portion of the gate electrode and a first portion of the gate dielectric are on the first nanostructure; a spacer, wherein a first portion of the spacer is on the first nanostructure; a first source / drain region in contact with the first nanostructure; and a dielectric layer, wherein a first portion of the dielectric layer is on the first nanostructure and the first portion of the gate dielectric, wherein the first portion of the dielectric layer is between the first portion of the gate dielectric and the first portion of the spacer, and wherein the dielectric layer comprises a material different from the material of the gate dielectric and the spacer.

[0084] Example 9. The semiconductor device according to Example 8, wherein a first portion of the gate dielectric is located between a first portion of the dielectric layer and the first nanostructure.

[0085] Example 10. The semiconductor device according to Example 9, wherein the bottom surface of the first portion of the dielectric layer is in contact with the first portion of the gate dielectric.

[0086] Example 11. The semiconductor device according to Example 8, wherein a first portion of the spacer is between a first portion of the dielectric layer and the first source / drain region.

[0087] Example 12. A semiconductor device according to Example 8, wherein, in a top view, a second portion of the gate dielectric is in contact with the first nanostructure, wherein a second portion of the spacer is in contact with a second portion of the gate dielectric, and wherein a second portion of the dielectric layer is between the second portion of the gate dielectric and the second portion of the spacer.

[0088] Example 13. The semiconductor device according to Example 8, wherein the dielectric layer comprises silicon oxide.

[0089] Example 14. A method of forming a semiconductor device, the method comprising: forming a first nanostructure on a substrate; forming a dummy gate structure on the substrate, wherein the dummy gate structure includes a dummy gate and a dummy gate dielectric, and wherein the dummy gate dielectric is in contact with the first nanostructure; converting a first portion of the dummy gate at a sidewall of the dummy gate into a dielectric layer; removing the remaining portion of the dummy gate structure to form a first opening; and forming a gate structure in the first opening, wherein the gate structure includes a gate electrode and a gate dielectric, and wherein the gate dielectric is in contact with the first nanostructure and the dielectric layer.

[0090] Example 15. The method according to Example 14, wherein converting the first portion of the dummy gate at the sidewall of the dummy gate into the dielectric layer comprises: performing an annealing process with oxygen.

[0091] Example 16. The method according to Example 15, wherein the annealing process is further performed using oxygen plasma.

[0092] Example 17. The method according to Example 14, wherein the dielectric layer and the gate dielectric comprise different materials.

[0093] Example 18. The method according to Example 14, wherein the dummy gate comprises polysilicon and the dielectric layer comprises silicon oxide.

[0094] Example 19. The method according to Example 14, wherein, in a top view, a first portion of the gate dielectric is in contact with the first nanostructure, wherein a first portion of the dielectric layer is in contact with a first portion of the gate dielectric, and wherein the first portion of the dielectric layer has an arcuate shape.

[0095] Example 20. The method according to Example 19, wherein a first portion of the dielectric layer is separated from the first nanostructure by a first portion of the gate dielectric.

Claims

1. A semiconductor device, comprising: First source / drain region; A first nanostructure adjacent to the first source / drain region; Second source / drain region; A second nanostructure adjacent to the second source / drain region; A gate structure surrounding a first nanostructure and a second nanostructure, wherein the gate structure includes a gate electrode and a gate dielectric, and wherein a first portion of the gate electrode and a first portion of the gate dielectric are located between the first nanostructure and the second nanostructure; A spacer, wherein a first portion of the spacer is located between the first source / drain region and the second source / drain region; and A dielectric layer, wherein a first portion of the dielectric layer is between a first portion of the gate dielectric and a first portion of the spacer, and wherein the dielectric layer comprises a material different from the material of the gate dielectric and the spacer.

2. The semiconductor device according to claim 1, wherein, The dielectric layer comprises silicon oxide.

3. The semiconductor device according to claim 1, wherein, The first portion of the dielectric layer is separated from the first nanostructure and the second nanostructure through the first portion of the gate dielectric.

4. The semiconductor device according to claim 1, wherein, The first portion of the dielectric layer is separated from the first source / drain region and the second source / drain region by the first portion of the spacer.

5. The semiconductor device according to claim 1, wherein, In the top view, the first portion of the dielectric layer has a raised sidewall that contacts the first portion of the gate dielectric and a recessed sidewall that contacts the first portion of the spacer.

6. The semiconductor device according to claim 1, wherein, In the top view, the width of the first portion of the gate electrode decreases as the first portion of the gate electrode extends away from the first nanostructure and the second nanostructure.

7. The semiconductor device according to claim 1, wherein, The second portion of the dielectric layer, the second portion of the gate dielectric, and the second portion of the spacer are on the first nanostructure and the second nanostructure, wherein the second portion of the dielectric layer is between the second portion of the gate dielectric and the second portion of the spacer.

8. A semiconductor device, comprising: First nanostructure; A gate structure surrounding the first nanostructure, wherein the gate structure includes a gate electrode and a gate dielectric, and wherein a first portion of the gate electrode and a first portion of the gate dielectric are on the first nanostructure; A spacer, wherein a first portion of the spacer is on the first nanostructure; The first source / drain region in contact with the first nanostructure; and A dielectric layer, wherein a first portion of the dielectric layer is above the first nanostructure and a first portion of the gate dielectric, wherein the first portion of the dielectric layer is between the first portion of the gate dielectric and the first portion of the spacer, and wherein the dielectric layer comprises a material different from the material of the gate dielectric and the spacer.

9. The semiconductor device according to claim 8, wherein, The first portion of the gate dielectric is located between the first portion of the dielectric layer and the first nanostructure.

10. A method of forming a semiconductor device, the method comprising: The first nanostructure is formed on the substrate; A dummy gate structure is formed on the substrate, wherein the dummy gate structure includes a dummy gate and a dummy gate dielectric, and wherein the dummy gate dielectric is in contact with the first nanostructure; The first portion of the dummy gate at the sidewall of the dummy gate is converted into a dielectric layer; Remove the remaining portion of the dummy gate structure to form a first opening; and A gate structure is formed in the first opening, wherein the gate structure includes a gate electrode and a gate dielectric, and wherein the gate dielectric is in contact with the first nanostructure and the dielectric layer.

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