Preparation method of metal silicide

Abstract

The invention provides a preparation method of metal silicide, which comprises the following steps of: sequentially depositing a first dielectric layer and a second dielectric layer on a substrate on which a source / drain region is formed; forming a photoresist pattern which covers the predetermined non-silicide forming region of the substrate and exposes the predetermined silicide forming region; etching to remove the second dielectric layer in the predetermined silicide forming region; carrying out pre-amorphization ion implantation on the predetermined silicide forming region; under the protection of the photoresist pattern, removing the first dielectric layer in the predetermined silicide forming region to expose the surface of the substrate in the predetermined silicide forming region; removing the photoresist pattern; depositing a metal layer and a covering layer on the metal layer on the substrate; and performing annealing treatment to form a metal silicide in the predetermined silicide forming region. According to the invention, the problems that the photoelectric conversion efficiency is influenced and dark current is caused due to defects possibly introduced by pre-amorphization injection in the traditional process are solved, and the problems of outward diffusion and poor uniformity of silicides are improved at the same time.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for preparing metal silicides. Background Technology

[0002] In advanced semiconductor manufacturing processes, especially with the continuous shrinking of device feature sizes (e.g., into 55nm and smaller nodes), the demand for nickel silicides (NiSi) with low resistivity, good thermal stability, and a smooth interface with silicon is increasingly prominent. For image sensor (CIS) applications, although the requirements for silicide processes may not be as stringent as for logic devices, obtaining low-resistivity NiSi remains crucial. However, low-resistivity NiSi is not the final thermodynamically stable phase; it is prone to agglomeration during high-temperature processing and can easily react with the silicon substrate to form a high-resistivity Ni₂Si phase. The Ni₂Si phase can also undergo epitaxial growth on the silicon substrate, leading to inverted pyramid-shaped defects and diffusion into the source / drain (S / D) region. Therefore, pre-amorphization implantation (PAI) is one of the important means to improve nickel silicide defects, enhance the smoothness of the nickel silicide-silicon interface, improve contact resistance uniformity, and enhance device performance uniformity.

[0003] Furthermore, in image sensor (CIS) devices, the core component is the photodiode, a structure highly sensitive to the integrity of the silicon dioxide (SiO2) surface and junction region. Traditional pre-amorphization implantation processes can introduce defects, affecting performance such as photoelectric conversion efficiency and dark current. Additionally, in some CIS processes, the use of oxide materials for the isolation structure can lead to highly uneven polysilicon silicide bottoms in the logic regions, causing significant leakage current. Simultaneously, silicide in the active region may extend into the channel, further increasing the risk of leakage for narrow-channel devices.

[0004] Therefore, how to effectively control the formation of nickel silicides, reduce defects, and improve their electrical performance and uniformity, especially in defect-sensitive CIS devices, is a technical problem that urgently needs to be solved in the current semiconductor field. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a method for preparing metal silicides to solve the problem that the pre-amorphization implantation process in the prior art may introduce defects, thereby affecting the photoelectric conversion efficiency and dark current performance.

[0006] To achieve the above and other related objectives, the present invention provides a method for preparing metal silicides, comprising:

[0007] Step 1: On the substrate where the source / drain regions have been formed, deposit the first dielectric layer and the second dielectric layer sequentially;

[0008] Step 2: Form a photoresist pattern, wherein the photoresist pattern covers a predetermined non-silicide formation area of ​​the substrate and exposes a predetermined silicide formation area;

[0009] Step 3: Etch away the second dielectric layer in the predetermined silicide formation region;

[0010] Step 4: Perform pre-amorphization ion implantation on the predetermined silicide formation region;

[0011] Step 5: Under the protection of the photoresist pattern, remove the first dielectric layer of the predetermined silicide formation region to expose the surface of the substrate in the predetermined silicide formation region;

[0012] Step 6: Remove the photoresist pattern;

[0013] Step 7: Deposit a metal layer and a capping layer thereon on the substrate; and

[0014] Step 8: Perform annealing to form metal silicide in the predetermined silicide formation region.

[0015] Preferably, in step one, the first dielectric layer is an oxide layer and the second dielectric layer is a nitride layer.

[0016] Preferably, the thickness of the oxide layer is 80 to 150 angstroms.

[0017] Preferably, the thickness of the nitride layer is 200 to 350 angstroms.

[0018] Preferably, in step four, the pre-amorphization ion implantation is germanium ion implantation.

[0019] Preferably, in step four, the energy of the pre-amorphized ion implantation is 2 kiloelectron volts to 4 kiloelectron volts.

[0020] Preferably, in step four, the dose of the pre-amorphized ion implantation is 1E14 ions / cm².

[0021] Preferably, in step five, the removal of the first dielectric layer is performed using wet etching.

[0022] Preferably, the wet etching is performed using a hydrofluoric acid solution.

[0023] Preferably, in step six, the photoresist pattern is removed using a combination of sulfuric acid and hydrogen peroxide mixture and standard cleaning solution 1.

[0024] Preferably, in step seven, the metal layer is a nickel-containing metal layer.

[0025] Preferably, the nickel-containing metal layer is a nickel-platinum alloy layer.

[0026] Preferably, in step seven, the covering layer is a titanium nitride layer.

[0027] Preferably, the platinum doping concentration in the nickel-platinum alloy layer is 8% to 12%.

[0028] Preferably, the thickness of the titanium nitride layer is 80 to 120 angstroms.

[0029] Preferably, in step seven, the deposition is performed using a physical vapor deposition method.

[0030] Preferably, the metal silicide is a nickel silicide.

[0031] Preferably, the thickness of the nickel silicide is 200 to 350 angstroms.

[0032] Preferably, in step eight, the annealing process includes: a first rapid thermal annealing at a temperature of 250°C to 350°C to form a high-resistivity nickel disilicide phase; and a second rapid thermal annealing, performed after the first rapid thermal annealing at a temperature of 350°C to 450°C.

[0033] Preferably, the substrate is a substrate for an image sensor.

[0034] Preferably, the predetermined silicide formation region is a non-pixel region of the image sensor, and the non-pixel region is a peripheral logic device region; the predetermined non-silicide formation region is a pixel region of the image sensor.

[0035] Preferably, the pixel region includes at least one photodiode and at least one first metal-oxide-semiconductor transistor.

[0036] Preferably, the peripheral logic device region includes at least one second metal-oxide-semiconductor transistor.

[0037] Preferably, the pre-amorphization ion implantation is used to pre-amorphize the substrate in the predetermined silicide formation region.

[0038] As described above, the method for preparing metal silicides of the present invention has the following beneficial effects:

[0039] This invention combines the advantages of pre-amorphous implantation with the protection of pixel regions in CMOS image sensors by adding a germanium ion implantation step after the metal silicide barrier layer and photoresist wet etching process. This solves the problems of defects introduced by pre-amorphous implantation in traditional processes, which can affect photoelectric conversion efficiency and cause dark current. It also improves the problems of silicide outward diffusion and poor uniformity. By precisely controlling the parameters of each process step, nickel silicides with low resistance, good thermal stability, and smooth interfaces can be fabricated. This has significant application value for advanced node semiconductor devices, especially high-performance image sensors. Attached Figure Description

[0040] Figure 1 The diagram shown is a schematic representation of the process flow of the present invention.

[0041] Figure 2 The diagram shows a schematic representation of the sequential deposition of a first dielectric layer and a second dielectric layer according to the present invention.

[0042] Figure 3 The diagram shown illustrates the formation of a photoresist pattern according to the present invention.

[0043] Figure 4 This is a schematic diagram showing the etching removal of the second dielectric layer in the predetermined silicide formation region according to the present invention.

[0044] Figure 5 The diagram shows a pre-amorphization ion implantation of a predetermined silicide formation region according to the present invention.

[0045] Figure 6 The diagram shown is a schematic representation of the photoresist removal pattern according to the present invention.

[0046] Figure 7 The diagram shows a metal layer deposited on a substrate and a capping layer thereon, according to the present invention.

[0047] Figure 8 The diagram shown illustrates the formation of a metal silicide in a predetermined silicide formation region according to the present invention. Detailed Implementation

[0048] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0049] This invention provides a method for preparing metal silicides.

[0050] Please see Figure 1In one specific embodiment, a method for preparing a metal silicide 112 includes the following steps:

[0051] Step 1: On the substrate 101 where the source / drain regions 105 have been formed, a first dielectric layer 106 and a second dielectric layer 107 are sequentially deposited to form a structure as shown in the figure. Figure 2 The structure shown is an example of this step, which lays the foundation for the subsequent selective formation of the metal silicide 112 region. Precise control of the dielectric layer deposition provides a favorable process window for subsequent photolithography and etching steps.

[0052] In some embodiments, in step one, the first dielectric layer 106 is an oxide layer and the second dielectric layer 107 is a nitride layer. The oxide layer typically serves as the bottom dielectric in contact with the substrate 101, while the nitride layer can serve as a hard mask or etch stop layer in subsequent etching steps. The combination of the two enables good process control.

[0053] Methods for forming oxide layers can include, but are not limited to, chemical vapor deposition, such as plasma-enhanced chemical vapor deposition (PECVD) or low-pressure chemical vapor deposition (LPCVD). PECVD is typically performed at lower temperatures (e.g., 200°C to 400°C) using silane (SiH4) and nitrous oxide (N2O) or oxygen (O2) as reactant gases, enabling the formation of dense silicon oxide films. LPCVD, on the other hand, is performed at higher temperatures and can provide better step coverage.

[0054] In some embodiments, high-density plasma chemical vapor deposition (HDP-CVD) may be used to obtain good trench filling capability, or atomic layer deposition (ALD) technology may be used to achieve angstrom-level thickness control and excellent conformality, which is particularly suitable for advanced process nodes.

[0055] Methods for forming nitride layers can also include chemical vapor deposition, such as PECVD or LPCVD. PECVD silicon nitride typically uses silane (SiH4) and ammonia (NH3) or nitrogen (N2) as reactant gases, deposited at relatively low temperatures, exhibiting good passivation properties and characteristics as a hard mask. LPCVD silicon nitride is often formed by reacting dichlorosilane (SiH2Cl2) and ammonia at higher temperatures, resulting in films with typically high density and low hydrogen content. Atomic layer deposition (ALD) can also be used to form highly conformal silicon nitride layers with precisely controlled thickness. The choice of specific deposition method and process parameters will depend on the overall process flow, device structure requirements, and specific requirements for film quality (such as density, stress, electrical properties, etc.).

[0056] In some embodiments, the thickness of the oxide layer is between 80 angstroms and 150 angstroms. This thickness range effectively protects the surface of the substrate 101 without causing excessive stress or impact on subsequent silicide formation.

[0057] In some embodiments, the thickness of the nitride layer is 200 to 350 angstroms. This thickness range provides sufficient etch selectivity and protection.

[0058] Step 2: Forming a photoresist pattern 108. The photoresist pattern 108 covers the predetermined non-silicide formation area of ​​the substrate 101 and exposes the predetermined silicide formation area, forming a pattern as shown in the figure. Figure 3 The structure shown is an example of this process. This step utilizes standard photolithography to precisely define which regions will form metal silicide 112 and which regions will not, thereby meeting the requirements of the device design.

[0059] Step 3: Etch away the second dielectric layer 107 in the predetermined silicide formation region to form a layer as shown in the figure. Figure 4 The structure shown. This step selectively removes the second dielectric layer 107 (e.g., a nitride layer) above the predetermined silicide formation region in preparation for subsequent exposure of the silicon surface of the substrate 101.

[0060] Step 4, please refer to Figure 5 Pre-amorphization ion implantation 109 is performed on the predetermined silicide formation region. Pre-amorphization ion implantation is a key step in improving the quality of the subsequently formed metal silicide 112. By disrupting the surface lattice structure of the substrate 101 in the predetermined silicide formation region through ion implantation, an amorphous layer is formed, which can effectively prevent irregular silicon growth during subsequent annealing, thereby reducing the risk of forming spike defects, significantly improving the uniformity of the silicide, and helping to better control the growth thickness of the silicide. This is crucial for improving the electrical performance and reliability of the device.

[0061] In some embodiments, step four involves germanium ion implantation for pre-amorphization. Germanium ions, being neutral and having a relatively large atomic mass, are a common and effective choice for pre-amorphizing silicon substrate 101. They achieve good amorphization results at lower energy and dosage levels while avoiding the introduction of unwanted electrical impurities. Adding germanium ion implantation after the self-aligned barrier layer (SAB) photoresist retaining wet etching (SAB with PR WET Etch) effectively prevents germanium ions from entering the highly defect-sensitive photodiode region, while significantly improving silicide diffusion and uniformity issues in image sensors (CIS). Besides germanium ions, other suitable ion types can also be used for pre-amorphization implantation depending on specific process requirements and substrate 101 materials. For example, silicon (Si) ions themselves can also be used for pre-amorphization, transforming crystalline silicon into amorphous silicon through ion implantation, sometimes referred to as self-ion implantation. Inert gas ions such as argon (Ar) ions are sometimes used for amorphization, but care must be taken to control potential defects they may cause during annealing. In certain specific applications, other heavier and electrically neutral ions, such as indium (In), may also be considered for pre-amorphization treatment. The main purpose is to effectively disrupt the crystal structure without introducing electrically active impurities. The choice of ion usually depends on its amorphization efficiency, compatibility with subsequent processes, and potential impact on the final electrical performance of the device.

[0062] In some embodiments, in step four, the energy of the pre-amorphization ion implantation is between 2 kiloelectron volts and 4 kiloelectron volts. This energy range ensures that the ion implantation forms an amorphous layer of appropriate depth on the surface of the substrate 101, achieving the purpose of pre-amorphization without causing excessive damage.

[0063] In some embodiments, in step four, the dose of pre-amorphized ion implantation is 1E14 ions / cm². This dose is sufficient to achieve effective amorphization, ensuring the formation of high-quality silicides subsequently.

[0064] Step 5: Under the protection of the photoresist pattern 108, remove the first dielectric layer 106 of the predetermined silicide formation region to expose the surface of the substrate 101 in the predetermined silicide formation region. This step thoroughly removes the dielectric layer in the predetermined silicide formation region, allowing the subsequently deposited metal to directly contact the clean silicon substrate 101 surface, creating the necessary conditions for the formation of the metal silicide 112. The presence of the photoresist pattern 108 ensures that the dielectric layer in the non-silicide formation region remains unaffected.

[0065] In some embodiments, in step five, the removal of the first dielectric layer 106 is performed using wet etching. Wet etching has good selectivity and can effectively remove the first dielectric layer 106 without damaging the underlying silicon substrate 101.

[0066] In some embodiments, wet etching is performed using a hydrofluoric acid (HF) solution. Hydrofluoric acid solution is a commonly used and efficient etchant for removing oxide layers (common first dielectric layer 106 material).

[0067] Step 6: Remove photoresist pattern 108 to form a shape like... Figure 6 The structure shown. After completing the area definition and surface treatment, the photoresist needs to be removed in order to proceed with subsequent global process steps.

[0068] In some embodiments, step six involves removing the photoresist pattern 108 using a combination of sulfuric acid-hydrogen peroxide solution (SPM) and standard cleaning solution 1 (SC1). SPM effectively removes most organic photoresist residue, while standard cleaning solution 1 (SC1) is used to further remove particulate contaminants and some metal ion contaminants. Standard cleaning solution 1 is typically a mixture of ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2), and deionized water (DIW) in a specific ratio, for example, a volume ratio of NH4OH:H2O2:DIW = 1:1:5 to 1:2:7, and is used at a temperature of, for example, approximately 70°C to 80°C. The cleaning mechanism is complex. On one hand, hydrogen peroxide, as a strong oxidant, effectively oxidizes and removes residual organic contaminants; on the other hand, the alkaline environment of the ammonium hydroxide solution, combined with the oxidizing effect of hydrogen peroxide, can slightly etch the surface of the silicon substrate 101 (typically less than a few angstroms). This micro-etching helps remove tiny particles physically adsorbed on the surface of the substrate 101 through a "lifting effect." Simultaneously, the SC1 solution imparts a negative charge to the surface of the silicon substrate 101 and most particle surfaces, preventing particles from re-adsorbing onto the substrate 101 surface during the cleaning process through electrostatic repulsion. Furthermore, the SC1 cleaning solution is effective in removing certain types of metallic contaminants (e.g., hydroxides formed from alkali metal ions and some transition metals), which may be oxidized to form soluble complexes or insoluble hydroxides, the latter of which can be removed by subsequent deionized water rinsing. The combined cleaning of SPM and SC1 yields a highly clean substrate 101 surface, which is crucial for subsequent high-quality thin film deposition, reducing interface defects, and improving the electrical properties and interface characteristics of the final metal silicide 112, thereby enhancing device reliability and yield.

[0069] Step 7: Deposit a metal layer 110 and a capping layer 111 thereon on the substrate 101 to form a structure as shown in the figure. Figure 7 The structure shown is as follows. The metal layer 110 is the core material for forming the metal silicide 112, while the capping layer 111 mainly serves to prevent the metal layer 110 from being oxidized or contaminated during subsequent annealing and to regulate the silicide formation reaction.

[0070] In some embodiments, in step seven, the metal layer 110 is a nickel-containing metal layer 110. Nickel is one of the preferred metals for forming low-resistivity silicides and is widely used in modern integrated circuit processes. For example, other metals that can be used to form metal silicides 112 include, but are not limited to, cobalt (Co), titanium (Ti), tungsten (W), platinum (Pt) (platinum is also often used as an alloying element, such as in nickel-platinum alloys), and metals such as hafnium (Hf) and erbium (Er) used in specific applications to control the work function. The choice of metal material generally depends on the resistivity, thermal stability, contact characteristics with silicon (e.g., contact height), compatibility with subsequent processes, and the need to control the threshold voltage of devices (e.g., MOS transistors) (via the work function of the silicide). For example, titanium silicide (TiSi2) was once a widely used silicide material, while cobalt silicide (CoSi2) was used in earlier process nodes due to its low resistivity and good lattice matching. Silicides formed from different metals have different physical and electrical properties, and those skilled in the art can select the most suitable metal layer 110 material according to the actual device design and process platform.

[0071] In some embodiments, the nickel-containing metal layer 110 is a nickel-platinum alloy (NiPt) layer. Doping nickel with platinum (Pt) can improve the thermal stability of silicide formation, inhibit nickel silicide aggregation, and help form a NiSi phase with a smoother interface, thereby further reducing contact resistance and improving device performance.

[0072] In some embodiments, in step seven, the capping layer 111 is a titanium nitride (TiN) layer. As the capping layer 111, titanium nitride not only prevents the underlying nickel-platinum alloy layer from oxidizing during annealing, but also acts as a diffusion barrier layer and, in some cases, helps to regulate the reaction process between silicon and metal.

[0073] In some embodiments, the platinum doping concentration in the nickel-platinum alloy layer is about 10% (e.g., 8% to 12%). This concentration of platinum doping is considered to be within the effective range for improving the properties of nickel silicides.

[0074] In some embodiments, the thickness of the titanium nitride layer is 80 to 120 angstroms. TiN layers of this thickness range are sufficient to provide protection and regulation without introducing excessive stress or processing complexity.

[0075] In some embodiments, in step seven, the deposition is performed using a physical vapor deposition (PVD) method. PVD is a mature thin film deposition technology capable of depositing the metal layer 110 and the capping layer 111 with high purity and good uniformity.

[0076] Step 8: Perform annealing to form metal silicide 112 in the predetermined silicide formation region, forming as shown in the figure. Figure 8The structure is shown. Annealing is a key heat treatment step that drives the solid-state reaction between the metal and silicon to form metal silicide 112. By precisely controlling the annealing temperature and time, the desired phase of metal silicide 112 can be formed.

[0077] In some embodiments, metal silicide 112 is nickel silicide.

[0078] In some embodiments, the thickness of the nickel silicide is 200 to 350 angstroms. This thickness range of nickel silicide can meet the requirements of device size reduction while providing low contact resistance.

[0079] In some embodiments, step eight, the annealing process includes: a first rapid thermal annealing (RTA1) at a temperature of 250°C to 350°C to form a high-resistivity nickel disilicide (Ni2Si) phase; and a second rapid thermal annealing (RTA2), performed after the first rapid thermal annealing, at a temperature of 350°C to 450°C to form a low-resistivity nickel monosilicide (NiSi) phase. The two-step annealing process is a common method for forming low-resistivity NiSi. The first step, low-temperature annealing, primarily forms Ni2Si or nickel-rich silicide phases, while the second step, higher-temperature annealing, transforms these phases into a lower-resistivity and more stable NiSi phase. This method helps to obtain more uniform NiSi films with fewer defects.

[0080] In some embodiments, substrate 101 is a substrate 101 for an image sensor. The method of the present invention is particularly suitable for the manufacture of image sensor (CIS) devices with high requirements for defects and uniformity.

[0081] Prior to performing the metal silicide 112 fabrication method described in this invention, several front-end process steps have typically been completed on the substrate 101, including forming key structures of a metal-oxide-semiconductor (MOS) transistor, such as source and drain regions, in the peripheral logic device region. The formation of the source / drain regions 105 in the peripheral logic device region typically follows a standard CMOS (complementary metal-oxide-semiconductor) process flow. Specifically, this generally involves the following steps:

[0082] First, after formation of, for example, trap region ion implantation and isolation structures (such as shallow trench isolation 102, STI), a gate dielectric layer (such as silicon dioxide, high-k dielectric material) is grown or deposited, followed by the deposition of a gate electrode material layer (such as polysilicon, metal gate). The gate structure is then defined using photolithography and etching processes.

[0083] Subsequently, to form the source / drain extension region, or lightly doped drain region, one or more low-dose ion implantations are performed. The type of impurity implanted depends on the transistor type (e.g., phosphorus or arsenic for NMOS transistors; boron for PMOS transistors). This step is typically performed after the gate sidewall oxide layer is formed but before the sidewalls are formed to control the junction depth and doping concentration of the source / drain extension region, thereby mitigating short-channel and hot carrier effects.

[0084] Next, dielectric sidewalls, such as silicon nitride sidewalls, are formed on the sidewalls of the gate structure. These sidewalls will serve as masks for subsequent high-dose source / drain ion implantation and help define the distance between the source / drain and the channel.

[0085] Then, high-dose source / drain ion implantation is performed to form low-resistance source and drain regions. The implantation energy and dose are optimized according to device performance requirements (such as on-resistance, junction depth, etc.). For advanced process nodes, additional implantation steps may be performed, such as bag implantation, which involves implanting ions at a specific angle near the source / drain extension region at the channel edge to further suppress short-channel effects.

[0086] Finally, the implanted impurities are activated through one or more annealing steps (e.g., rapid thermal annealing), allowing them to enter substitutional sites in the silicon lattice and become electrically active, while simultaneously repairing lattice damage caused during ion implantation. After these steps, the source and drain regions of the peripheral logic device area are formed.

[0087] In some embodiments, the predetermined silicide formation region is the non-pixel region of the image sensor, and the non-pixel region is the peripheral logic device region; the predetermined non-silicide formation region is the pixel region of the image sensor. In CIS devices, silicides are typically formed only in the peripheral logic circuit region to reduce contact resistance and improve device speed, while silicide formation is avoided in the noise- and defect-sensitive pixel region to protect the performance of the photodiode. The method of the present invention, through precise region definition, can meet this requirement and helps to improve problems in CIS devices that may be caused by conventional processes (such as oxide isolation layer Spacer1), such as uneven bottom of polysilicon silicides in the logic region, large leakage current, and silicide extension into the channel in the active region. Especially for narrow-channel devices, it can effectively reduce the risk of leakage current.

[0088] In some embodiments, the pixel region includes at least one photodiode and at least one first metal-oxide-semiconductor (MOS) transistor 103. This is a typical structure constituting a CIS pixel unit.

[0089] In some embodiments, the peripheral logic device region includes at least one second metal-oxide-semiconductor (MOS) transistor 104. The peripheral logic device is used to control the readout of the pixel array and the processing of image signals.

[0090] In some embodiments, pre-amorphization ion implantation is used to pre-amorphize the substrate 101 in the predetermined silicide formation region. As mentioned above, pre-amorphization is one of the key technical means of the present invention to improve silicide quality and enhance device performance. By introducing germanium ion implantation at a specific process step (i.e., after wet etching with the self-aligned barrier layer photoresist retained) as described in the present invention, not only can effective pre-amorphization be achieved, improving silicide uniformity (e.g., improving contact resistance uniformity by about 10%), controlling silicide thickness, and reducing spike defects, but also the potential adverse effects of germanium ions on the performance of photodiodes in the pixel region can be effectively avoided, thereby improving the overall performance and yield of CIS devices.

[0091] This invention combines the advantages of pre-amorphous implantation with the protection of pixel regions in CMOS image sensors by adding a germanium ion implantation step after the metal silicide barrier layer and photoresist wet etching process. This solves the problems of defects introduced by pre-amorphous implantation in traditional processes, which can affect photoelectric conversion efficiency and cause dark current. It also improves the problems of silicide outward diffusion and poor uniformity. By precisely controlling the parameters of each process step, nickel silicides with low resistance, good thermal stability, and smooth interfaces can be fabricated. This has significant application value for advanced node semiconductor devices, especially high-performance image sensors.

[0092] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0093] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for preparing a metal silicide, characterized in that, At least including: Step 1: On the substrate where the source / drain regions have been formed, deposit the first dielectric layer and the second dielectric layer sequentially; Step 2: Form a photoresist pattern, wherein the photoresist pattern covers a predetermined non-silicide formation area of ​​the substrate and exposes a predetermined silicide formation area; Step 3: Etch away the second dielectric layer in the predetermined silicide formation region; Step 4: Perform pre-amorphization ion implantation on the predetermined silicide formation region; Step 5: Under the protection of the photoresist pattern, remove the first dielectric layer of the predetermined silicide formation region to expose the surface of the substrate in the predetermined silicide formation region; Step 6: Remove the photoresist pattern; Step 7: Deposit a metal layer and a capping layer thereon on the substrate; and Step 8: Perform annealing to form metal silicide in the predetermined silicide formation region.

2. The method for preparing metal silicides according to claim 1, characterized in that: In step one, the first dielectric layer is an oxide layer, and the second dielectric layer is a nitride layer.

3. The method for preparing metal silicides according to claim 2, characterized in that: The thickness of the oxide layer is 80 to 150 angstroms.

4. The method for preparing metal silicides according to claim 2, characterized in that: The thickness of the nitride layer is 200 to 350 angstroms.

5. The method for preparing metal silicides according to claim 1, characterized in that: In step four, the pre-amorphization ion implantation is germanium ion implantation.

6. The method for preparing metal silicides according to claim 1 or 5, characterized in that: In step four, the energy of the pre-amorphized ion implantation is 2 kiloelectron volts to 4 kiloelectron volts.

7. The method for preparing metal silicides according to claim 1 or 5, characterized in that: In step four, the dose of the pre-amorphized ion implantation is 1E14 ions / cm².

8. The method for preparing metal silicides according to claim 1, characterized in that: In step five, the removal of the first dielectric layer is performed using wet etching.

9. The method for preparing metal silicides according to claim 8, characterized in that: The wet etching process uses a hydrofluoric acid solution.

10. The method for preparing metal silicides according to claim 1, characterized in that: In step six, the photoresist pattern is removed using a combination of sulfuric acid and hydrogen peroxide mixture and standard cleaning solution 1.

11. The method for preparing metal silicides according to claim 1, characterized in that: In step seven, the metal layer is a nickel-containing metal layer.

12. The method for preparing metal silicides according to claim 11, characterized in that: The nickel-containing metal layer is a nickel-platinum alloy layer.

13. The method for preparing metal silicides according to claim 1, characterized in that: In step seven, the covering layer is a titanium nitride layer.

14. The method for preparing metal silicides according to claim 12, characterized in that: The platinum doping concentration in the nickel-platinum alloy layer is 8% to 12%.

15. The method for preparing metal silicides according to claim 13, characterized in that: The thickness of the titanium nitride layer is 80 to 120 angstroms.

16. The method for preparing metal silicides according to claim 1, characterized in that: In step seven, the deposition is performed using a physical vapor deposition method.

17. The method for preparing metal silicides according to claim 11, 12, or 14, characterized in that: The metal silicide is a nickel silicide.

18. The method for preparing metal silicides according to claim 17, characterized in that: The thickness of the nickel silicide is 200 to 350 angstroms.

19. The method for preparing metal silicides according to claim 1, characterized in that: In step eight, the annealing process includes: a first rapid thermal annealing at a temperature of 250°C to 350°C to form a high-resistivity nickel disilicide phase; and a second rapid thermal annealing, performed after the first rapid thermal annealing at a temperature of 350°C to 450°C.

20. The method for preparing metal silicides according to any one of claims 1 to 19, characterized in that: The substrate is a substrate used for image sensors.

21. The method for preparing metal silicides according to claim 20, characterized in that: The predetermined silicide formation region is a non-pixel region of the image sensor, and the non-pixel region is a peripheral logic device region; the predetermined non-silicide formation region is a pixel region of the image sensor.

22. The method for preparing metal silicides according to claim 21, characterized in that: The pixel region includes at least one photodiode and at least one first metal-oxide-semiconductor transistor.

23. The method for preparing metal silicides according to claim 21, characterized in that: The peripheral logic device region includes at least one second metal-oxide-semiconductor transistor.

24. The method for preparing metal silicides according to claim 1, characterized in that: The pre-amorphization ion implantation is used to pre-amorphize the substrate in the predetermined silicide formation region.

Images