PN junction memristive synapse device capable of inducing nanocrystalline grain boundary fusion through aging and preparation method of PN junction memristive synapse device

Abstract

The invention belongs to the technical field of neuromorphic devices, and particularly relates to a PN junction memristive synapse device for aging-induced nanocrystalline grain boundary fusion and a preparation method of the PN junction memristive synapse device. A NiOx / SnO2 quantum dot heterojunction is prepared through a low-temperature solution method, a stable PN junction is formed by utilizing nanocrystalline interface atom reconstruction in the aging process, and the memristive synapse device of an ITO / NiOx / SnO2 / Ag structure is constructed. According to the device, interface atom diffusion is accelerated through aging or heat treatment at 80 DEG C for 12 hours, PN junction optimization is achieved, and the device has excellent biological synaptic function simulation capacity including long-term gain / inhibition effect, excitation / inhibition of post-synaptic current and the like. According to the method, the interface fusion of the nanocrystalline is regulated and controlled through aging, the limitation of a traditional high-temperature process is broken through, low-power-consumption and low-cost preparation is realized, and a novel device scheme is provided for brain-like calculation.

Description

Technical Field

[0001] This invention relates to the field of neuromorphic computing device technology, specifically to an aging-induced nanocrystal grain boundary fusion PN junction memristor synaptic device and its preparation method. Background Technology

[0002] As the core unit of neuromorphic computing, neural synaptic devices need to simulate the plasticity and nonlinear response characteristics of biological synapses. Currently, PN junction synaptic devices based on quantum dot nanocrystals face the following technical bottlenecks: The nanocrystal interface contains a large number of defect states (such as dangling bonds and adsorbed impurities), leading to severe charge recombination in the early stages of PN junction formation, significant interface barriers, and unstable device rectification characteristics and memristor performance; traditional fabrication processes struggle to control the nanocrystal grain boundary fusion process, resulting in low atomic diffusion efficiency at the NiOx and SnO2 contact interface, requiring long-term aging to form a stable PN junction, thus limiting device mass production efficiency; existing devices, when simulating biological synaptic functions (such as long-term gain / suppression effects), exhibit significant signal attenuation due to interface structural defects, resulting in high energy consumption and insufficient reliability. Summary of the Invention

[0003] Technical problems to be solved

[0004] To address the shortcomings of existing technologies, this invention provides an aging-induced grain boundary fusion PN junction memristor synaptic device and its fabrication method, which solves the problems of unstable device performance, long aging period, and low efficiency of biological synapse simulation caused by nanocrystalline interface defects.

[0005] Technical solution

[0006] To achieve the above objectives, the present invention provides the following technical solution:

[0007] A method for fabricating a PN junction memristor synaptic device with aging-induced nanocrystal grain boundary fusion includes the following steps:

[0008] A solution of nano-NiOx particles was spin-coated onto pretreated ITO conductive glass and dried; then an aqueous SnO2 solution was spin-coated onto the dried NiOx film and dried to obtain a NiOx / SnO2 heterojunction.

[0009] A silver electrode is fabricated on the surface of a NiOx / SnO2 heterojunction to form a device with the following structure: ITO / NiOx / SnO2 / electrode;

[0010] The device is aged to allow the nanocrystal interface atoms to reconstruct and form a PN junction, resulting in an aging-induced nanocrystal grain boundary fusion PN junction memristor synapse device.

[0011] Preferably, the preparation of the nano-NiOx particle solution includes the following steps: ultrasonically dispersing NiOx powder generated by precipitation in deionized water to form a nano-NiOx particle solution; the pretreatment includes: sequentially cleaning and drying the ITO conductive glass with detergent, deionized water, and anhydrous ethanol, followed by plasma treatment.

[0012] Preferably, the aging process specifically includes aging using a heat treatment method, wherein the relationship between the aging temperature and time satisfies the following formula:

[0013] t_{heat treatment}=t_{room temperature aging}×e^{-\frac{E_a}{RT}}

[0014] Where t_{heat treatment} is the heat treatment time, t_{room temperature aging} is the room temperature aging time, E_a is the interface atomic diffusion activation energy, R is the gas constant, T is the absolute temperature, and \frac{E_a}{RT} represents a fraction, where E_a is the numerator and RT is the denominator.

[0015] Preferably, the silver electrode is prepared on the surface of the heterojunction by thermal evaporation, and the specific aging process is heat treatment at 80°C for 12 hours.

[0016] This invention also provides an aging-induced nanocrystal grain boundary fusion PN junction memristor synaptic device, which is prepared by the aforementioned method. It includes a conductive glass substrate, a NiOx thin film and a SnO2 thin film deposited sequentially, and a top metal electrode. The NiOx thin film and the SnO2 thin film form a PN junction heterojunction structure. The NiOx and SnO2 particles are both nanoscale in size. The device has memristor characteristics and the ability to simulate biological synaptic functions.

[0017] Preferably, the PN junction interface is formed by aging-induced fusion of nanocrystal grain boundaries, and the amorphous layer of SnO2 achieves grain boundary fusion through the Ostwald ripening effect. The lattice spacing of the (200) crystal plane is 0.243 nm, and the lattice spacing of the (110) crystal plane is 0.338 nm. The device changes from a high-resistivity state to a low-resistivity state under forward bias and recovers to a high-resistivity state under reverse bias, exhibiting bipolar memristor characteristics.

[0018] Preferably, the device is used to simulate the long-term gain effect, long-term inhibition effect, excitation postsynaptic current, and inhibition postsynaptic current of biological synapses, and can reach saturation current under pulse stimulation.

[0019] This invention relates to a PN junction memristor synaptic device with a structure of ITO / NiOx / SnO2 / Ag, wherein the NiOx and SnO2 heterojunction interfaces are fused through aging treatment to form a stable PN junction. The device exhibits memristor characteristics that satisfy bipolar resistance switching behavior: it transitions from a high-resistivity state (HRS) to a low-resistivity state (LRS) at a forward bias of 0.45V (SET point), and recovers HRS at a reverse bias of -1.0V (RESET point), with a high-to-low resistance ratio ≥ 5.

[0020] Biological synaptic function simulation parameters: conductance growth rate ≥15% / s under long-term gain effect (LTP), conductance decay rate ≤10% / s under long-term inhibition effect (LTD), and response time of excitatory postsynaptic current (EPSC) and inhibitory postsynaptic current (IPSC) ≤1ms.

[0021] Beneficial effects

[0022] Compared with the prior art, the present invention provides a PN junction memristor synaptic device with aging-induced grain boundary fusion and its preparation method, which has the following beneficial effects:

[0023] Innovative interface reconstruction mechanism: By inducing the fusion of nanocrystal grain boundaries through aging, and using the high free energy of the SnO2 amorphous surface to drive atomic diffusion, the interface defects of NiOx are simultaneously promoted to be repaired, forming a PN junction interface without obvious potential barriers, which improves the device rectification ratio by 3 orders of magnitude and the charge transport efficiency by 70%.

[0024] Efficient control of aging process: A temperature-time equivalent model is established, and 12 hours of heat treatment at 80℃ can achieve the equivalent aging effect of 30 days at room temperature. By activating atomic interdiffusion at the NiOx-SnO2 interface, the device fabrication cycle is significantly shortened, which is suitable for mass production requirements.

[0025] Accurate simulation of synaptic function: The built-in electric field formed by grain boundary fusion (from SnO2 to NiOx) optimizes the carrier migration path, enabling the device to successfully simulate biological synaptic behaviors such as LTP, LTD, EPSC / IPSC. Among them, the resistance state switching under high-frequency pulse (10kHz) only requires 3 pulses, and the energy consumption is reduced by 65% ​​compared with traditional devices. Attached Figure Description

[0026] Figure 1 The diagram shows the device structure. The memristor device is a two-layer structure with a NiO / SnO2 heterojunction as the functional layer, and Ag lattice electrodes are deposited using a lattice template.

[0027] Figure 2Figure (a) shows the IV curves of the device after 0 days, 3 days, 7 days, 30 days, and 60 days of rest. The hysteresis becomes increasingly pronounced over time. Initially, the IV curves of the device exhibit a weak hysteresis under electrical signal stimulation. Applying the same magnitude and periodic electrical stimulation after seven days of vacuum placement yields a more significant hysteresis feedback. After a long period of rest (one month), the electrical stimulation current feedback of the device stabilizes at a relatively significant hysteresis state. This aging effect is attributed to the disordered atomic arrangement of NiO and SnO2 nanocrystals at the initial stage of device fabrication, resulting in stress at the nanocrystal interfaces. As this stress is released, interfacial atomic reconstruction occurs, reducing the resistance of charge transport between particles. Figure (b) shows the lg function graph of the IV characteristics of the stabilized device (30 days). When a forward voltage of 0.45V (SET point) is applied, the current increases sharply, and the device transitions from a high-resistivity state (HRS) to a low-resistivity state (LRS). This is because defects such as oxygen vacancies migrate and aggregate under the influence of the electric field, forming conductive filaments. When a reverse voltage of -1.0V (RESET) is applied, the current decreases sharply, and the device recovers to HRS, as the conductive filaments break or dissolve under the influence of the electric field and Joule heating. Figure (c) shows the IV curves after 1, 10, 30, 50, and 100 voltage cycles. Applying different numbers of voltage cycles to a device aged for one month, the hysteresis curve is unstable but tends to smooth out in the first 30 cycles, reaching a stable state after the 30th cycle and remaining stable within 100 cycles. Figure (d) shows the high and low resistance distribution after 100 cycles at 0.5V. Using high and low resistance data with a +0.5V input signal, although the macroscopic ratio of high to low resistance is greater than 5, the rising and falling edge data are evenly distributed, and the conductance fluctuations become smoother with increasing cycle count. This is because the interface atomic reconstruction forms a built-in electric field pointing from SnO2 to NiOx. After the initial equilibrium is broken by the external electric field, the internal electric field is in a chaotic state in the first few dozen cycles, causing the IV curve to fluctuate. After multiple cycles, the electron distribution tends to stabilize, the internal electric field reaches dynamic equilibrium, and the curve stabilizes.

[0028] Figure 3 The image shows the memristor curve of the device heat-treated at 80°C for 12 hours. The device heated to 80°C for 12 hours exhibits bipolar memristor-like characteristics, with a hysteresis loop area similar to that of a device aged at room temperature for 30 days, demonstrating that heat treatment can effectively accelerate atomic interface reconstruction. Heating activates atomic diffusion at the NiOx and SnO2 interface, accelerating pn junction formation, equivalent to the effect of aging at room temperature for one month.

[0029] Figure 4This is a simulation of biological synaptic function. Figure (a) simulates IPSC when an opposite polarity electrical stimulus of 0.5V with a period of 1ms is applied to the device. It was observed that when a +0.5V voltage stimulus is applied, the device exhibits a gradually increasing current feedback, i.e., from HRS to LRS, with the conductance continuously increasing during this process, logically representing a transition from 0 to 1, which simulates the situation of EPSC in neural communication. When a -0.5V voltage stimulus is applied, the device's feedback current gradually decreases to a stable value, i.e., from LRS to HRS, with the conductance continuously decreasing during this process, logically representing a transition from 1 to 0, which simulates the situation of IPSC in neural communication. Figure (b) shows the same signal. First, a positive bias voltage is applied. Over a sufficiently long time dimension, the device maintains a continuous increase in conductance as the high-frequency signal is applied. After 1s of positive bias, a reverse high-frequency pulse bias voltage is applied. At this time, the device's conductance gradually decays from the baseline conductance of the positive bias voltage, and the decay rate decreases with increasing time. This reflects the LTP and LTD characteristics in neural synapses, respectively. The first six data points (ten data points apart) of the rising edge of the LTP curve and the first six data points (ten data points apart) of the falling edge of the LTD curve are selected, referred to as the rising group and the falling group, respectively. For the six data points in the rising group, the conductance value of each subsequent data point is divided by the conductance value of the previous data point, and the decimal percentage is taken to obtain the paired-pulse facilitation (PPF) curve, as shown in Figure (c). It can be observed that the conductance values ​​of subsequent data points are generally greater than those of the former, but the increasing trend weakens. This can simulate the STM memory characteristics in neural synaptic memory; frequent signal stimulation in the short term strengthens individual memory, but the memory enhancement effect gradually weakens. The same calculation method is used for the six data points in the falling group to obtain its paired-pulse depression (PPD) characteristic curve within a single cycle, as shown in Figure (d). It can be observed that the conductivity values ​​of subsequent data points are generally lower than those of the former, but the reduction trend weakens over time. The decay rate drops rapidly from 30% to 10% in the second cycle, and the decay rate in subsequent cycles is consistent with the long-term forgetting curve (LTM) of human memory. Figure (e) shows that when a +0.5V long signal of 0.5s to 4s is applied, the current increases from 13.7mA to 17.8mA, but the growth rate slows down, which is consistent with the theory that interface electron migration tends to saturate. As time increases, the current feedback continues to increase, but the growth trend shows a weakening phenomenon, which is consistent with the previous PPF curve. Under the condition of applying a unidirectional bias voltage, although interface electrons will migrate due to the electric field force, the magnitude and state of the internal electric field will also change with the migration of electrons.For example, under forward bias, electrons cross the interface from the conduction band of SnO2 into the valence band of NiO, forming a current. A large number of electrons flow in and neutralize holes, leading to a reduction in holes in NiO and a loss of electrons from SnO2. Over time, this loss reduces the number of independent electrons and holes, causing the device to gradually approach saturation. Figure (f) shows that when +0.5V pulses with frequencies of 10kHz, 6.7kHz, and 1kHz are applied, the higher the frequency, the fewer pulses are required for the device to reach saturation current (only 3 pulses are needed at 10kHz). This demonstrates the effect of frequency on the switching speed of the resistor state and shows that the device can be kept in multiple resistance states through frequency control, providing feasibility for multi-state memories. Detailed Implementation

[0030] A method for fabricating a PN junction memristor synaptic device with aging-induced nanocrystal grain boundary fusion includes the following steps:

[0031] S1. Preparation of nano-NiOx sol

[0032] Mix 17.5g of nickel nitrate hexahydrate (Ni(NO3)2·6H2O) with 100mL of deionized water, and add 10mol / L sodium hydroxide solution dropwise under stirring until pH=10;

[0033] The mixture was stirred for 15 minutes and then sonicated for 15 minutes in sequence. After a green precipitate was formed, it was washed with deionized water until the pH was 7.

[0034] Black NiOx powder was obtained by drying at 80℃ for 12 hours and calcining at 260℃ for 2 hours.

[0035] The powder was dissolved in deionized water and ultrasonically dispersed for 15 min to obtain nano-NiOx ink.

[0036] S2. Substrate Pretreatment

[0037] The ITO conductive glass was ultrasonically cleaned in sequence with detergent, deionized water, and anhydrous ethanol, and then dried and treated with plasma.

[0038] S3. Device Layer Fabrication

[0039] Preparation of NiOx and SnO2 layers: Two inks were coated onto the layers, and then dried for 10 min.

[0040] S4. Electrode fabrication. Ag electrodes are deposited on the surface of the heterojunction using a thermal evaporation method (electrode dimensions are determined according to device requirements).

[0041] S5. Aging treatment. Accelerate the interfacial atomic reconstruction by aging at room temperature for 1-60 days or by heat treatment (such as heat treatment at 80℃ for 12 hours) to form a stable PN junction with grain boundary fusion.

[0042] The temperature-time relationship in step S5 of the aging process satisfies:

[0043] t_{heat treatment}=t_{room temperature aging}×e^{-\frac{E_a}{RT}}

[0044] Where t_{heat treatment} is the heat treatment time, t_{room temperature aging} is the room temperature aging time, E_a is the interface atomic diffusion activation energy, R is the gas constant, and T is the absolute temperature.

[0045] The amorphous layer of SnO2 achieves grain boundary fusion through the Ostwald ripening effect, with a lattice spacing of 0.243 nm (corresponding to the (200) crystal plane) and 0.338 nm (corresponding to the (110) crystal plane).

[0046] Example 1: Basic Process Preparation

[0047] NiOx sol preparation: Nano-NiOx ink was prepared according to step S1, and the particle size was measured to be 3-5 nm.

[0048] Device layer fabrication: A NiOx layer (wet film thickness of about 80 nm) was spin-coated on ITO glass, and after drying, a SnO2 layer (wet film thickness of about 200 nm) was spin-coated to form a 50 nm NiOx / 170 nm SnO2 heterojunction.

[0049] Aging treatment: After aging at room temperature for 30 days, the device's IV curve showed significant memristor hysteresis, and the rectification ratio reached 10. 3 .

[0050] Example 2: Accelerated Heat Treatment Process

[0051] Device fabrication: Same as step S5 in Example 1.

[0052] Aging treatment: After the NiOx and SnO2 layers were prepared, the device was heat-treated at 80℃ for 12 hours. XRD characterization showed that the diffraction peak intensity of the NiOx (111) crystal plane was enhanced, and the full width at half maximum (FWHM) of the SnO2 (200) crystal plane was reduced by 25%. The memristor characteristics of the device were comparable to those of Example 1. The device heat-treated at 80℃ for 12 hours exhibited the ability to simulate biological synaptic behaviors such as EPSC / IPSC and LTP / LTD as the device that was heat-treated for one month, proving its application in brain-like computing. When a +0.5V / ms pulse was applied, the current gradually increased over time, simulating the depolarization current caused by the release of excitatory neurotransmitters from the presynaptic membrane, corresponding to the device's transition from HRS to LRS. When a -0.5V / ms pulse was applied, the current gradually decreased and tended to stabilize, simulating the hyperpolarization potential caused by inhibitory neurotransmitters, corresponding to the transition from LRS to HRS. The fitting curves of EPSC and IPSC showed that the current change conformed to the electrochemical signal conversion dynamics of neural synapses. When a positive high-frequency pulse (e.g., 0.5V) is continuously applied, the conductance increases over time and tends to saturate, simulating the persistent effect of neuronal signal enhancement. Switching to a reverse high-frequency pulse, the conductance gradually decays from its saturation value, with the decay rate decreasing over time, reflecting the time-dependent nature of synaptic inhibition. Compared to the LTP / LTD curves aged at room temperature for 30 days, the curves after heat treatment show a consistent trend, verifying the accelerating effect of heat treatment on synaptic function simulation. When applying +0.5V pulses of 10kHz, 6.7kHz, and 1kHz, the higher the frequency, the fewer pulses required for the device to reach saturation current (only 3 pulses are needed at 10kHz), demonstrating the frequency's modulating effect on the resistance state switching speed. When the signal width increases from 0.5s to 4s, the current increases from 13.7mA to 17.8mA, but the growth rate gradually slows down.

[0053] Example 3: Fabrication of Flexible Devices

[0054] Substrate pretreatment: PET flexible substrate is selected, plasma treatment power is reduced to 180W, treatment time is 8min, and surface energy reaches 68mN / m.

[0055] Device layer fabrication: The spin coating speed was adjusted to 1800 rpm to form a 30 nm NiOx / 120 nm SnO2 heterojunction.

[0056] Aging treatment: After aging at room temperature for 20 days, the memristor hysteresis area decayed by less than 10% after 1000 cycles of 180° bending test, proving its flexibility and adaptability.

[0057] This invention constructs a high-performance PN junction memristor synaptic device through an aging-induced grain boundary fusion mechanism. Its interface modulation method and biosynaptic simulation capability provide a new technical path for neuromorphic computing hardware. The nanocrystalline interface reconstruction process in the device structure not only improves electrical performance but also lays the foundation for the construction of low-power, high-reliability neuromorphic systems.

[0058] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0059] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A method for fabricating a PN junction memristor synaptic device with aging-induced nanocrystal grain boundary fusion, characterized in that, Includes the following steps: A solution of nano-NiOx particles was spin-coated onto pretreated ITO conductive glass and dried; then an aqueous SnO2 solution was spin-coated onto the dried NiOx film and dried to obtain a NiOx / SnO2 heterojunction. A silver electrode is fabricated on the surface of a NiOx / SnO2 heterojunction to form a device with the following structure: ITO / NiOx / SnO2 / electrode; The device is aged to allow the nanocrystal interface atoms to reconstruct and form a PN junction, resulting in an aging-induced nanocrystal grain boundary fusion PN junction memristor synapse device.

2. The method for fabricating a PN junction memristor synaptic device with aging-induced nanocrystal grain boundary fusion as described in claim 1, characterized in that, The preparation of the nano-NiOx particle solution includes the following steps: ultrasonically dispersing NiOx powder generated by precipitation in deionized water to form a nano-NiOx particle solution; the pretreatment includes: sequentially cleaning and drying the ITO conductive glass with detergent, deionized water, and anhydrous ethanol, followed by plasma treatment.

3. The method for fabricating a PN junction memristor synaptic device with aging-induced nanocrystal grain boundary fusion as described in claim 1, characterized in that, The aging process specifically includes aging using heat treatment, and the relationship between aging temperature and time satisfies the following formula: t_{heat treatment}=t_{room temperature aging}×e^{-\frac{E_a}{RT}} Where t_{heat treatment} is the heat treatment time, t_{room temperature aging} is the room temperature aging time, E_a is the interface atomic diffusion activation energy, R is the gas constant, T is the absolute temperature, and \frac{E_a}{RT} represents a fraction, where E_a is the numerator and RT is the denominator.

4. The method for fabricating a PN junction memristor synaptic device with aging-induced nanocrystal grain boundary fusion as described in claim 1, characterized in that, Silver electrodes are prepared on the surface of the heterojunction by thermal evaporation, and the aging process specifically involves heat treatment at 80°C for 12 hours.

5. A PN junction memristor synaptic device with aging-induced nanocrystal grain boundary fusion, characterized in that, The device is prepared by the preparation method described in any one of claims 1-4, comprising a conductive glass substrate, a NiOx thin film and a SnO2 thin film deposited sequentially, a top metal electrode, and the NiOx thin film and SnO2 thin film forming a PN junction heterojunction structure. The NiOx and SnO2 particles are both nanoscale in size, and the device has memristor characteristics and the ability to simulate biological synaptic functions.

6. The memristor synaptic device according to claim 5, characterized in that, The PN junction interface is formed by the fusion of nanocrystal grain boundaries induced by aging, and the amorphous layer of SnO2 achieves grain boundary fusion through the Ostwald ripening effect. The lattice spacing of the (200) crystal plane is 0.243 nm, and the lattice spacing of the (110) crystal plane is 0.338 nm. The device changes from a high-resistivity state to a low-resistivity state under forward bias and recovers to a high-resistivity state under reverse bias, exhibiting bipolar memristor characteristics.

7. The memristor synaptic device according to claim 5, characterized in that, The device is used to simulate the long-term gain effect, long-term inhibition effect, excitation of postsynaptic current, and inhibition of postsynaptic current in biological synapses, and can reach saturation current under pulse stimulation.

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