Pre-read operations for memory devices with independent planes and groups of planes

Abstract

A storage device includes a storage array having a plurality of planes organized into a plane group, where the planes in the plane group receive and process commands in parallel. The storage device includes a storage controller that receives commands from a host controller. In response to receiving the command, the storage controller provides ready information for all planes to the host controller. The plurality of planes may optionally have an independent multi-plane read operation (IMPRO). Each plane group may have a first plane and a second plane, and the memory controller may optionally read data from the first plane in the plane group in response to a virtual ready signal for the first plane in the plane group before the second plane in the plane group is ready.

Description

[0001] Priority requirements

[0002] This application claims priority to U.S. Application No. 18 / 125,621, filed March 23, 2023, pursuant to 35 U.S.SC §365(c), which is incorporated herein by reference in its entirety. Technical Field

[0003] The instruction manual generally relates to storage devices, and more specifically, to storage devices having planes and groups of planes. Background Technology

[0004] Storage devices typically use non-volatile memory such as NAND flash memory. Increased non-volatile density allows the storage array to be addressed into distinct sections, called planes. Storage planes can be processed independently and simultaneously using Independent Multi-Plane Read Operations (IMPRO). Using independent operations, the host accesses each plane with separate status read commands to monitor the progress of the read operation.

[0005] Planes can be operated on as a group of planes. Using independent plane operations, the host can read planes simultaneously, but the read is delayed until all planes in the plane group have completed their read operations. Therefore, if the plane group contains different page types (e.g., single-level cell (SLC) and four-level cell (QLC)), the host will wait until the slowest read operation completes before performing the read. Attached Figure Description

[0006] The following description includes a discussion of the accompanying drawings, which are given as examples of embodiments. The drawings should be understood as examples, not limitations. As used herein, references to one or more examples should be understood as describing a particular feature, structure, or characteristic included in at least one embodiment of the invention. Phrases such as "in one example" or "in an alternative example" appearing herein provide examples of embodiments of the invention and do not necessarily refer to the same embodiments. However, these phrases are not necessarily mutually exclusive.

[0007] Figure 1 This is a block diagram of an example of a system with multi-plane storage devices.

[0008] Figure 2 It represents the read level of non-volatile memory.

[0009] Figure 3 It is a block diagram of an example of a plane in the form of a group of planes and a system that operates rapidly.

[0010] Figures 4A-4BProvides a representation of the command operations for reading turbo status.

[0011] Figures 5A-5B Provides a representation of read-ahead access command operations.

[0012] Figure 6 It represents an advance read access operation.

[0013] Figure 7 This is a flowchart of an instance of the process used to read the turbo status.

[0014] Figure 8 This is a flowchart of an instance of a process used for advance read access.

[0015] Figure 9A This is a block diagram of an example of a system with a solid-state drive (SSD), the SSD having a plane in the form of a group of planes that support fast operation.

[0016] Figure 9B This is a block diagram of an example of a system with a solid-state drive (SSD) having a controller for managing fast operations of a plane in the form of a plane group.

[0017] Figure 10 This is a block diagram of an example of a computational system that can perform fast operations on nonvolatile planes in the form of plane groups.

[0018] Figure 11 This is a block diagram of an example of a mobile device that can perform rapid operations on a non-volatile plane in the form of a group of planes.

[0019] Figure 12 This is a block diagram of an example of a multi-node network in which fast operations on a nonvolatile plane in the form of a plane group can be implemented.

[0020] The following is a description of certain details and implementation schemes, including a non-limiting description of the accompanying drawings, which may depict some or all instances as well as other potential implementation schemes. Detailed Implementation

[0021] As described herein, a storage device includes a storage array having multiple planes organized as a group of planes, wherein the planes in the group of planes receive and process commands in parallel. The storage device includes a storage controller that receives commands from a host controller. In response to receiving a command, the storage controller provides readiness information for all planes to the host controller. The multiple planes may optionally have independent multi-plane read operations (IMPRO). Each group of planes may have a first plane and a second plane, and the storage controller may optionally read data from a first plane in the group of planes in response to a virtual readiness signal of the first plane in the group of planes before the second plane in the group of planes becomes ready.

[0022] Reading readiness information from all planes, and reading another plane in a plane group before another plane in the group becomes ready, can both be referred to as fast operations. More specifically, reading readiness information from all planes can be called a turbo state read operation for the IMPRO system. Reading another plane before another plane in the same group becomes ready can be called an early readout operation.

[0023] As part of IMPRO and eIMPRO operations, the host can queue read operations on all planes simultaneously. Furthermore, planes, even within the same plane group, may have different page types. Different page types can include single-level cells (SLC) and any kind of multi-level cells, including two-level cells (commonly referred to as multi-level cells (MLC)), three-level cells (TLC), four-level cells (QLC), or other multi-level cells. Page types can include MLCs operating in SLC On-Time (OTF) mode, where the plane temporarily operates in SLC mode.

[0024] Commands typically consist of a command plus address (CMD+ADDR) sent from the host to the non-volatile medium (NVM). For the CMD latency (tWC) and ADDR latency (tWHR), the command may have associated latency of approximately 25ns + 80ns, respectively. This latency can significantly impact read performance because the state of each plane needs to be read separately. By utilizing turbo state read commands, the readiness state of all planes can be read with a single command; therefore, by eliminating the need to read each group of planes multiple times, the polling overhead of the channel can be reduced.

[0025] Using turbo state reads, the host can monitor the readiness (RDY) of each plane of a logic unit (LUN) with a single state read command, eliminating the need to read the state of each plane group separately. The memory die (e.g., a NAND die) sets the RDY for the plane that has completed a read operation. The host can use turbo state polling to track the readiness status of each plane. Once a plane is RDY, the host can read the data while simultaneously using a single state read command to continue monitoring the state of other planes.

[0026] The readiness state provided by turbo read can be virtual ready (VRDY). Non-volatile memory can have multiple readiness states. Array ready (ARDY) can refer to the medium completing a read and all cleanup operations, meaning the storage medium is ready to handle another access request. Ready (RDY) can refer to a readiness state where the array has transferred data to the read buffer so that the host can access the contents of the buffer, while the medium performs the operations necessary to prepare the array for subsequent access requests (e.g., becoming ARDY). Virtual ready (VRDY or VIRT_RDY) can refer to a readiness state where one plane in a plane group has completed its read operation, or one plane in a plane group has completed the read level operation and moved the data into the buffer. Therefore, when applied to a single plane in a plane group, VIRT_RDY can be compared with RDY without referring to whether other planes in the plane group have reached the RDY (or VIRT_RDY) state.

[0027] Early readout can be applied to any system with multiple planes and plane groups. The system may have IMPRO operation or other configurations. Early readout allows for the simultaneous reading of different page types on each plane within a plane group, not limited to the slowest plane in the group. Readout from the fastest plane (shortest tR) can be performed immediately after the plane is ready, without waiting for the latency of the slowest plane (longest tR) in the plane group.

[0028] Early readout, also known as proactive readout, allows the host to proactively read faster planes within a plane group, while slower planes continue to be read. In one instance, the memory die uses a status register to provide virtual RDY information for the planes within the plane group. The host can track the state of each plane by polling the status register and begin reading data immediately after asserting VIRT_RDY for a specific plane.

[0029] Figure 1 This is a block diagram of an example of a system with a multi-plane storage device. System 100 includes a host 110, which represents the host system to which the storage device 130 is connected. The storage device 130 provides storage resources to store data for the host 110.

[0030] Host 110 includes processor 122, storage controller 124, and memory 126. Processor 122 represents the host processor or computing device of host 110. Processor 122 can be a single-core device or a multi-core device. Storage controller 124 represents the controller in host 110 that manages access to storage device 130. Storage controller 124 can perform scheduling and manage timing and data transfer with storage device 130.

[0031] In one instance, storage controller 124 manages polling of the readiness status of different planes and plane groups of storage device 130. In one instance, storage controller 124 may issue a Turbo read command to storage device 130 to access the readiness status information of all planes of the storage device. In one instance, storage controller 124 may issue an advance read command to access data in one plane of a plane group, even if another plane in the group is not ready to read.

[0032] Memory 126 represents operable memory in host 110. Operable memory is typically volatile memory, which has an indeterminate state if power to the memory is interrupted. Alternatively, operable memory can be non-volatile memory, which has a deterministic state even when power to the memory is interrupted. Memory 126 typically stores data and code for use by processor 122. Data read from storage device 130 is typically stored in memory 126 for use by processor 122.

[0033] Host 110 includes input / output (I / O) 112, which represents hardware that interfaces with external devices (e.g., storage device 130, which may represent a peripheral device). I / O 132 represents hardware in storage device 130 that interfaces with host 110 via I / O 112. In one example, the interconnect between I / O 112 and I / O 132 may include a command connection, command link, or command bus, as indicated by CMD 114. The link / bus may be a signal line through which host 110 sends commands to storage device 130. The interconnect may include a data bus, indicated by DQ 116.

[0034] Storage device 130 includes a NAND controller 134, which represents a controller on the storage device for managing non-volatile memory (NVM) resources. As shown, storage device 130 includes a plurality of NAND dies 140. In one example, the NAND die 140 includes an array 144 having QLC media capable of operating in SLC OTF mode.

[0035] NAND die 140 includes I / O 142, which represents interconnect hardware for connecting to I / O 132. Controller 150 represents control logic on NAND die 140 for managing access to different planes of array 144. Plane 146 represents a separate portion of array 144. Plane 146 refers to a portion of array 144 that can be individually addressed and accessed. In one instance, plane 146 has an IMPRO operation. In one instance, array 144 contains 4 planes, 6 planes, or some other number of planes. In one instance, array 144 represents an array of three-dimensional (3D) NAND, which refers to NAND created in a vertical stack with vertical channels opposite to conventional horizontal channels.

[0036] In one instance, plane 146 includes logic 160 for accessing the plane's storage units to perform read or write operations, such as column and row decoding / encoding logic. Latch 162 represents a latch used to store readiness information. Therefore, latch 162 can indicate readiness or virtual readiness information when data in the plane is ready to be accessed. In one instance, latch 162 represents VRDY information for each plane 146.

[0037] In one instance, in response to the completion of a read operation (e.g., detection of stored data based on the applied read level), the plane triggers latch 162. In response to latch 162, the NAND controller 134 can update the ready state register (not specifically shown) with the plane's ready state information.

[0038] Buffer 164 represents a temporary storage area for data read from plane 146. In response to a read command, plane 146 accesses the array (e.g., a portion of array 144 within plane 146) and places data in buffer 164. Host 110 can access the data in buffer 164 while the array continues to perform read-related operations.

[0039] In one example, each NAND die 140 includes a controller 150 with a read control 152. The read control 152 may represent control logic within the controller 150 of the storage device 130 that enables the controller 150 to manage state information in response to a turbo state read command. The read control 152 may also represent control logic within the controller 150 of the storage device 130 that enables the controller 150 to manage read data for advance reading of selected planes in a plane group.

[0040] In one example, storage controller 124 includes read control 128, which represents logic on the host side for managing the generation and sending of status commands, which may include turbo status reads. Read control 128 enables storage controller 124 to perform advance access to data on one plane in a plane group, which is ready to read before the other planes in the group. More specifically, using a turbo status read command allows for the use of a single status command instead of multiple status commands.

[0041] When a turbo status read command or an advance read command is sent from storage controller 124 to storage device 130, CMD 114 displays the encoding of the command. In response to the command, DQ 116 displays the data in response to the specific command, where the timing between the command and data patterns indicates what data is sent.

[0042] In one example, plane 146 is part of a 3D NAND array. System 100 illustrates an example of a 3D stacked memory device. In one example, memory cell 172 represents a NAND memory cell for a NAND device. In one example, memory cell 172 represents a charge trapping cell that traps (stores) a charge layer between the gate and the channel. In one example, memory cell 172 represents a floating gate cell having a floating gate structure for storing charge. Other architectures are also possible. The stored charge indicates one or more bit values.

[0043] Based on the detectable different charge levels stored within the cell, the cell can be programmed according to various encoding schemes (e.g., SLC (single-level cell), MLC (multi-level cell), TLC (three-level cell), QLC (four-level cell), or other encoding schemes). The threshold voltage (Vt) of each cell indicates the data stored in the cell.

[0044] The array comprises N word lines (WL[0] to WL[N-1]). Access to columns, pillars, or strings of memory cells 172 can be addressed via row (word line or WL) addresses and column (bit line or BL) addresses, and is gated using control gate signals. In one instance, the array is organized into multiple sub-blocks of cells, which is not explicitly shown.

[0045] The array comprises multiple vertical stacks, each corresponding to a bit line (e.g., BL[0], BL[1], ...). The vertical stacks contain vertical channels passing through the various word lines, where the channels are controlled by control gate signals. The control gate signals can be referred to as switching signals that provide gating control for the channels. For example, the various pillars can be controlled by a select gate drain (SGD) signal line and a select gate source (SGS) signal line. The SGD and SGS signals are gated by switch 174. The SGD signal line selectively couples the column to the bit line (BL). The SGS signal line selectively couples the column to the source line (SL). The source line (SL) can be a source material layer integrated onto a semiconductor substrate.

[0046] The array comprises M bit lines (BL[0] to BL[M-1]). In one example, each memory cell 172 within plane 146 is addressed or selected by asserting word lines and bit lines in combination with a gate selection switch 174 (marked only on the SGD, but the SGS switch can be considered included in the control) to enable columns. Word lines span multiple serial strings of the memory device. Sensing circuitry 176 detects the state of the memory cell by sensing the voltage or current on the selected bit lines.

[0047] Figure 2 This is a representation of the read levels of non-volatile memory. More specifically, Figure 200 illustrates four read states of an MLC (two-level) NAND device, which may be a device with two levels of cells. For each two-level cell, the cell may store one of four states: 11, 10, 00, and 1. Figure 200 shows level 0 (L0) corresponding to erase state 11, level 1 (L1) corresponding to the first programming level 10, level 2 (L2) corresponding to the second programming level 00, and level 3 (L3) corresponding to programming level 1.

[0048] In one instance, a cell state configured to store multiple bits can form part of multiple distinct pages, where each bit of the cell corresponds to a different page. For example, for a cell entering a state storing 2 bits (e.g., using MLC encoding), one bit may correspond to the parent page (UP) and another bit to the child page (LP). For a cell entering a state storing 3 bits (e.g., using TLC encoding), one bit may correspond to LP, one bit to UP, and another bit to an extra page (XP). For a cell storing 4 bits (e.g., using QLC encoding), one bit may correspond to LP, another bit to UP, another bit to XP, and the last bit to the top-level page (TP). Each page (e.g., LP, UP, XP, TP) may contain an aggregation of corresponding bits stored by multiple distinct cells of a word line. Different bits may have different labels in different systems.

[0049] A programming sequence for a cell group can involve programming the desired pages into the cell group. The programming sequence can include one or more programming passes, where each programming pass programs one or more pages. A programming pass can include one or more programming cycles. A programming pass typically involves applying one or more valid programming voltages to the cells to be programmed, followed by applying one or more verification voltages to the cells to determine which cells have been programmed. The system can be configured to skip either the programming voltage or the verification voltage for cells that have passed programming verification, or both the programming voltage and one or more verification voltages. Applying a valid programming voltage to a cell can involve changing the voltage difference between the cell's control gate and channel, thereby changing the cell's Vt. Therefore, the controller can apply voltages to the word line (coupled to the control gate of the target cell) and / or to the cell's channel to set the valid programming voltage.

[0050] Figure 3 This is a block diagram of an example of a planar system in the form of a group of planes and a system with fast operation. System 300 provides an example of a system based on an example of system 100. System 300 includes a host 310 coupled to storage device 320.

[0051] Storage device 320 includes a memory medium for storing data, represented by NAND die 340. NAND die 340 can be organized into multiple planes in the form of plane groups. As shown, NAND die 340 includes six planes in three plane groups. While the specific organization may vary depending on the implementation, system 300 shows a plane group PG0 with planes 0 and 3, a plane group PG1 with planes 1 and 4, and a plane group PG2 with planes 2 and 5. Thus, as shown, each plane group has a first plane and a second plane. Other implementations may have more planes per plane group.

[0052] The planes in a plane group have at least some operations that are bound together, such as executing the same command. Therefore, the planes within the plane group can receive and process commands in parallel. NAND die 340 can represent multiple dies in the storage device 320.

[0053] Storage device 320 is communicatively coupled to host 310 via a link formed between interface 312 of host 310 and interface 322 of storage device 320. In one instance, interface 312 is part of a peripheral control hub (PCH). In another instance, interface 312 is part of a root complex. In yet another instance, the link between interfaces conforms to a communication standard such as high-speed PCI (PCIe), Serial Advanced Technology Attachment (ATA), Parallel ATA, Universal Serial Bus (USB), or other interface protocols.

[0054] Storage device 320 includes one or more registers 328. Registers 328 may include registers for storing configuration information controlling the operating mode of storage device 320. Registers 328 may include registers for storing readiness information of the plane of NAND die 340. Registers 328 may include status registers. In one instance, the register containing readiness information may be located within NAND die 340. In the case where the readiness information register is located within NAND die 340, controller 330 can read the register information and provide it to host 310.

[0055] In one example, storage device 320 includes memory 324, which may represent volatile or non-volatile memory storing code to be executed by controller 330. Firmware 326 represents code for managing the operation of storage device 320, which may be executed by controller 330.

[0056] System 300 does not explicitly show the storage controller of host 310. Host 310 includes a storage controller for managing the transmission of commands from the host side to storage device 320. Controller 330 represents a controller on storage device 320 for receiving and processing commands from the host. Controller 330 can generate internal operations in response to commands from host 310 to execute the commands. In one instance, controller 330 is an application-specific integrated circuit (ASIC). In another instance, controller 330 is a microcontroller or microprocessor.

[0057] Control logic 332 represents the control logic of controller 330 that enables the controller to control access to NAND die 340. Controller 330 can manage read operations, write operations, erase operations, and status requests from host 310 (e.g., from a storage controller on the host).

[0058] In one instance, control logic 332 is software / firmware, such as firmware 326. In another instance, control logic 332 represents a hardware logic circuit system, such as one or more state machine logic circuits, programmable logic circuit systems (e.g., field-programmable gate arrays (FPGAs), programmable logic arrays (PLAs)), or a combination of hardware circuit systems and software / firmware.

[0059] NAND die 340 can be organized into cell blocks, where a block is the smallest erasable unit of the array. Some NAND memory devices equip the entire NAND die with a single state machine, thereby restricting read operations to occur on one plane at a time, with one plane performing the operation while other planes remain idle. Multi-plane operation (e.g., IMPRO devices) allows operations to be performed independently on multiple planes in parallel / simultaneously. To support IMPRO, controller 330 may contain separate state machines for different planes.

[0060] In one example, NAND die 340 includes independent operations across a group of planes. Planes within a group of planes can be restricted to performing the same array operations, such as programming data to the array, reading data from the array, erasing blocks, or other operations on the array. For example, PG 0 can perform different array operations than PG 1. Within PG 0, both plane 0 and plane 3 can perform the same array operations.

[0061] Using read-ahead, reads from planes within a plane group can occur at different times, based on the plane that triggers the readiness signal. By using different readiness signal timings, planes within the plane group can provide read data from the same read command based on different timings. Using read-ahead, host 310 (e.g., via controller 330) can read data from another plane before one plane in the plane group is ready to read. In one example, host 310 can send status commands and receive information from all planes in the NAND die 340, allowing the host to know the status of all planes without polling the planes individually.

[0062] Figures 4A-4B Provides a representation of the command operations for reading turbo status.

[0063] refer to Figure 4A Table 402 represents the ready state table to be stored in the registers of a memory device with multiple planes. Multiple planes support the IMPRO operation. Table 402 assumes the use of 6 planes. It should be understood that memory devices with different numbers of planes can have different structures. In practice, Table 402 can have several bits to indicate the plane status as interpreted according to Table 402. In one example, as shown in the diagram, the register can have eight bits.

[0064] Table 402 contains three columns: Status Bits, Description, and Notes. The Status Bits column indicates the bits representing the status information. The Description column provides labels for the status bits in the first column. The Notes provide a more explicit explanation of these bits. In one example, Table 402 represents the status information for the command CMD_73h, which refers to a command with the hexadecimal code '73'. It should be understood that command codes may vary depending on the communication / interface protocol.

[0065] Lines 412 of SR7 and 414 of SR6 can be reserved for devices containing 6 planes instead of 8. Line 416 indicates SR5 as VIRT_RDY_5, the virtual ready signal for plane 5. Line 418 indicates SR4 as VIRT_RDY_4, the virtual ready signal for plane 4. Line 420 indicates SR3 as VIRT_RDY_3, the virtual ready signal for plane 3. Line 422 indicates SR2 as VIRT_RDY_2, the virtual ready signal for plane 2. Line 424 indicates SR1 as VIRT_RDY_1, the virtual ready signal for plane 1. Line 426 indicates SR0 as VIRT_RDY_0, the virtual ready signal for plane 0.

[0066] Table 402 indicates the virtual read information for each plane. Once the corresponding plane completes the read operation, the NAND die can update the Ready (RDY) state of each plane. Using the turbo state read command, the NAND can latch the RDY state of each plane into a unique status bit.

[0067] In one instance, Table 402 contains more bits, enough to indicate one or more pieces of information in addition to virtual readiness information. For example, the memory die can hold other useful information such as array readiness, power reset, thermal alarm, or other information.

[0068] RDY indicates when data from a read operation is ready to be accessed, while ARDY is longer than RDY, thus indicating when the array itself is ready to process another command. Therefore, ARDY indicates the end of array operations and array cleanup operations. PERESET can provide information related to handling low-power conditions that occur during array operations.

[0069] refer to Figure 4BFigure 404 illustrates the command sequence for receiving status information from table 402. During eIMPRO operation, the host can queue different page types to facilitate simultaneous reading in each plane. Additionally, some planes or plane groups can be in OTF SLC mode. Therefore, some planes will complete read operations faster than others. In legacy IMPRO status commands, status data was limited to specific planes or plane groups. Therefore, in legacy systems, the host could only obtain status information for all planes by issuing read status commands separately on each plane or plane group to monitor the status of the read operation.

[0070] In diagram 404, the host issues a turbo status read, indicated by command code 73h. Loop 430 describes the command sequence, where t0 is the command, followed by address information at t1, and data output (DOUT) at t2. DQ 440 describes the possible values ​​for the command sequence corresponding to loop 430. Similarly, at t0, the turbo status read command is indicated by command code 73h. At t1, the address information can indicate the target of the command. In one instance, the address information bits can contain plane information (PL) represented by bits 6:4 and logical unit number (LUN) represented by bits 2:0.

[0071] A complete command can be viewed as a command plus address information. After a certain delay from the command, the storage device can provide status information in response to the status command. Therefore, Figure 404 illustrates the delay tWHR between t1 and t2, where tWHR is the time it takes for the storage device to respond to the command. SR_Px at time t2 represents the status register (SR) plane information. In one example, each device includes a trigger that enables the plane to store ready information, allowing the device to send all status data to the host at once. The storage controller can read the triggers of each plane and write the ready status information to a host-accessible register.

[0072] In one implementation, the total time from sending a status command to receiving the status is approximately 10⁵ ns. Accessing the status information of all planes with a single command reduces the overhead of status polling, which would otherwise require repeating the polling for each plane / group of planes to be polled. The host can use the turbo status command to monitor the “RDY” status of all planes / groups of planes within a selected LUN with a single status read operation. In one instance, the host can queue the data read from planes that have been asserted as “RDY”.

[0073] Figures 5A-5B Provides a representation of read-ahead access command operations.

[0074] refer to Figure 5ATable 502 represents a table of state information to be stored in registers of a storage device with multiple planes. In one instance, the multiple planes support the IMPRO operation. In another instance, the multiple planes do not have the IMPRO operation. In practice, Table 502 may have several bits to indicate the state information required for the plane / plane group. In one instance, as indicated in Table 502, the register may have eight bits containing information to be interpreted according to the illustrated layout.

[0075] Table 502 contains three columns: Status Bits, Description, and Notes. The Status Bits column indicates the bits representing the status information. The Description column provides labels for the status bits in the first column. The Notes provide a more explicit explanation of these bits. In one instance, Table 502 represents the status information for the command CMD_72h, which refers to a command with the hexadecimal code '72'. It should be understood that command codes may vary depending on the communication / interface protocol.

[0076] Although the commands described in Reference Table 402 provide status information for all planes, Table 502 represents a table of commands issued per plane or per group of planes according to the implementation scheme. Therefore, the status bit indication "_Px" in Table 502 indicates different information representing the applicable per plane / group of planes.

[0077] Lines 512 of SR7_Px and 522 of SR2_Px can be reserved for information not indicated in Table 502. Line 514 indicates SR6_Px as RDY_PGx, the read / data ready signal for the plane group. Line 516 indicates SR5_Px as ARDY_PGx, the array ready signal for the plane group. Line 518 indicates SR4_Px as PERESET / WP#, the power reset signal for the LUN / device. Line 520 indicates SR3_Px as a thermal alarm, indicating that the plane group has reached a thermal threshold. Line 524 indicates SR1_Px as VIRT_RDY_PG_MSB, the virtual ready signal for the higher plane within the plane group, assuming each plane group has two planes. Line 526 indicates SR0_Px as VIRT_RDY_PG_LSB, the virtual ready signal for the lower plane within the plane group, assuming each plane group has two planes.

[0078] refer to Figure 5BFigure 504 illustrates the command sequence for receiving status information from table 502. In Figure 504, the host issues a status read, indicated by command code 72h. Cycle 530 describes the command sequence, where t0 is the command, followed by address information at t1, and data output (DOUT) at t2. DQ 540 describes the possible values ​​of the command sequence corresponding to cycle 530. Similarly, at t0, the status read command is indicated by command code 72h. At t1, the address information may indicate the target of the command. In one instance, the address information may contain plane information (PL) represented by bits 6:4 and logical unit number (LUN) represented by bits 2:0.

[0079] A complete command can be viewed as a command plus address information. After a certain delay from the command, the storage device can provide status information in response to a status command. Therefore, Figure 504 illustrates the delay tWHR between t1 and t2. SR_Px at time t2 represents the status register (SR) plane information. In one instance, the virtual readiness information of the planes individually informs the host of the read / data status of each plane in the plane group.

[0080] Using virtual readiness information, a host can access another plane in the same plane group before one plane in the group is ready to read. Therefore, the host can read from one plane while the other completes its read operation. In older systems, readiness information was limited to each plane group (RDY), which restricted data reading until the last plane had completed its read operation. Using the illustrated CMD_72h, the host can read data from a selected plane in the plane group without waiting for another (other) plane in the group.

[0081] Figure 6 This represents an advance read access operation. Diagram 600 shows the timing diagram of the read operations of the system according to an instance of system 100 or system 300. It should be understood that the amount of time between adjacent timing indicators t0, t1, t2, t3, t4, t5, t6, t7, and t8 is not necessarily uniform.

[0082] First, consider the signals at the bottom of the diagram. The four signals represented are VIRT_RDY_P_0, VIRT_RDY_P_1, RDY_PG, and ARDY_PG. VIRT_RDY_P_0 represents the virtual ready signal for plane 0 in the plane group. VIRT_RDY_P_1 represents the virtual ready signal for plane 1 in the plane group. RDY_PG represents the ready signal for the plane group. ARDY_PG represents the array ready signal for the plane group. The curve at the top of the diagram represents the read operation for plane 0. Below the curve for plane 0 is the curve representing the read operation for plane 1.

[0083] During an eIMPRO operation, the page types on planes within a plane group may differ. In legacy systems, the readout of any plane was gated by IMPRO operations on all planes within the plane group. Figure 600 illustrates a system that allows readout when one plane is ready, even if another (other) plane in the plane group is not ready.

[0084] In response to a read operation, the system can deassert VIRT_RDY_P_0, VIRT_RDY_P_1, RDY_PG, and ARDY_PG. In the read operation curve, times t0 to t1 constitute the prologue phase of the read operation. At time t1, the system can apply VCC. At time t2, the system can apply a read voltage, which ramps up to the selected voltage level 'SV' upon application of the programming voltage, and thereafter ramps down with the application of the programming voltage.

[0085] NAND reads involve applying a selection voltage, followed by the read step. Considering that plane 0 completes the read operation faster than plane 1, at time t3, plane 0 applies read levels L1 and L3 for LP pages and XP pages respectively. Plane 1 applies read level L2 for UP. At time t4, plane 0 can apply L7 / L5 for XP / LP pages respectively, and plane 1 can apply L4 for UP.

[0086] Considering that plane 0 has completed its read operation after applying L7 / L5, the NAND controller can assert VIRT_RDY_P_0 at time t5. In one instance, at time t5, plane 0 may have LP / XP (e.g., Pa SDC) on the buffer used for plane 0. Since the read for plane 1 is not yet complete, at time t5, plane 1 applies read level L6, which completes the read operation for plane 1. Therefore, at time t6, plane 1 may have UP (e.g., Pb SDC) on the buffer used for plane 1.

[0087] In one instance, the NAND (e.g., through its internal controller) indicates the status of the fastest plane by asserting VIRT_RDY for all planes within the plane group via a status register (SR). Once a faster plane in the plane group has completed a data transfer from the memory array (e.g., a NAND flash array) to the buffer, the controller can assert VIRT_RDY for the plane that has completed a page read operation.

[0088] As shown in Figure 600, the system asserts VIRT_RDY_P_0 at time t5 and VIRT_RDY_P_1 at time t6. Therefore, Pa reads RDY at t5, while Pb reads RDY at t6. The read time (tR) of LP / XP, tR_LP / XP, lasts from t0 to t5. The read time of UP, tR_UP, lasts from t0 to t6. It will be observed that the time to reach RDY=1 also lasts from t0 to t6, because t6 is the time when both planes in the plane group are ready. It will be observed that the virtual ready signal of plane 0 occurs earlier than the RDY of the plane group. RDY=1 occurs with the longest duration. The RDY signal is asserted at time t7, which is after the epilogue that occurs after all read operations are completed.

[0089] In one instance, the host monitors the VIRT_RDY state of each plane group via an eIMPRO state command (e.g., CMD_72h described above), which indicates the virtual readiness state of the planes in the plane group. In another instance, the host uses a turbo state command (e.g., CMD_73h described above) to monitor the VIRT_RDY state of each plane. Once the device asserts VIRT_RDY for a plane, the host can issue an IMPRO read operation on the plane that has completed the read operation, while the slower planes continue their read operations. It should be understood that the host uses VIRT_RDY to indicate the readiness state for data readout, but not the readiness state for executing new commands. To queue the next array operation (e.g., a subsequent eIMPRO command) on any plane group, the host needs to wait for all planes in the plane group to complete their IMPRO operations (e.g., ARDY=1).

[0090] The references to LP, UP, and XP in Figure 600 indicate a TLC NAND implementation used for illustration. Figure 600 shows the difference DIFF1 between the reads of plane 0 and plane 1 between t5 and t6. If plane 0 is in SLC mode, it can complete its read at t4, thus making it take even longer for plane 1 to complete its read, as shown in DIFF2.

[0091] It should be understood that in a QLC implementation, the time difference between the completion of read operations on planes within the same plane group can be significantly larger. While TLC is shown as having 3 read levels, QLC has more read levels, which can result in a longer latency between VIRT_RDY_P_0 and VIRT_RDY_P_1. On the other hand, the latency between VIRT_RDY_P_0 and VIRT_RDY_P_1 may be no different, depending on what value is written to the memory array.

[0092] Figure 7 This is a flowchart of an example of a process for performing a turbo state read. Process 700 represents a process for performing a turbo state read according to any example herein. In one example, at 702, the host storage controller determines to check read statistics for the IMPRO non-volatile media (NVM). This determination may be part of a polling process in which the host polls the storage device after sending a read command.

[0093] In one example, at 704, the host determines that it needs to issue a turbo status read command to the NVM controller. At 706, the NVM controller on the storage device can acquire virtual read-read information for all planes in response to the turbo status read command. At 708, the NVM controller can populate the VRDY information into the read status register, which the host storage controller can then read to determine the read status.

[0094] Figure 8 This is a flowchart illustrating an example of a read-ahead access process. Process 800 indicates that the processor performs a read-ahead access on one plane in a plane group, which is ready to be read before another plane in the group. At 802, the host may issue a read command to the plane group. At 804, the plane in the plane group will perform the read operation. In the IMPRO system, the planes in the plane group perform read operations in parallel with each other.

[0095] At 806, the internal controller on the storage device can issue a first read level. At 808, the controller determines whether the read operation at the current read level is complete. For any plane that has not yet completed the read operation at the current read level, at the "No" branch at 810, the plane that has not yet completed the read operation will continue the read operation at 812. At 814, the controller can increase the read level and issue the next read level at 806.

[0096] For any plane that has completed a read operation at the current read level, at the "Yes" branch at 810, the plane completes the read operation at 816. At 818, the plane stores the accessed data in the read buffer and triggers a Virtual Ready (VRDY) signal. At 820, the controller indicates the VRDY information to the host. At 822, in response to the VRDY information, the host may optionally issue a read from the buffer of the ready plane, while other planes continue their read operations.

[0097] Figure 9AThis is a block diagram of an example of a system with a solid-state drive (SSD) having a plane in the form of a cluster of planes supporting fast operation. System 902 represents a component of a storage system according to an example of system 100 or system 300. System 902 may be a 3D NAND storage device that supports turbo state reads or early read access, or both turbo state reads and early read access.

[0098] System 902 includes an SSD 920 coupled to host 910. Host 910 refers to the host hardware platform connected to SSD 920. Host 910 includes a CPU (Central Processing Unit) 912 or other processor as a host processor or host processor device. CPU 912 refers to any host processor that generates requests to access data stored on SSD 920 to read data or write data to the storage area. Such a processor may include a single-core or multi-core processor, a primary processor for a computing device, a graphics processor, a peripheral processor, or a supplementary or auxiliary processor, or a combination thereof. CPU 912 can execute a host OS and other applications to cause system 902 to operate.

[0099] Host 910 includes chipset 914, which represents the hardware components that may be included in the connection between CPU 912 and SSD 920. For example, chipset 914 may include interconnect circuitry and logic for enabling access to SSD 920. Therefore, host 910 may include a hardware platform driver interconnect for coupling SSD 920 to host 910. Host 910 includes hardware for interconnecting to the SSD. Similarly, SSD 920 includes corresponding hardware for interconnecting to host 910.

[0100] The host 910 includes a controller 916, which represents a storage controller or memory controller on the host side for controlling access to the SSD 920. In one instance, the controller 916 is contained within the chipset 914. In another instance, the controller 916 is contained within the CPU 912. The controller 916 may be referred to as an NV memory controller or storage controller that enables the host 910 to schedule and organize commands to the SSD 920 for reading and writing data.

[0101] SSD 920 refers to a solid-state drive or other storage system or module containing non-volatile (NV) media 930 for storing data. NV media 930 can be, for example, a 3D NAND array. SSD 920 includes HW (hardware) interface 922, which represents a hardware component for interfacing with host 910. For example, HW interface 922 can interface with one or more buses to implement high-speed interface standards such as NVMe (High-Speed ​​Non-Volatile Memory) or PCIe (High-Speed ​​Peripheral Component Interconnect).

[0102] In one example, the NV medium 930 is implemented as multiple dies, shown as N dies, dies [0:(N-1)]. N can be any number of devices and is typically a binary number. The SSD 920 includes a controller 940 for controlling access to the NV medium 930. The controller 940 represents the hardware and control logic within the SSD 920 for performing control over the media. The controller 940 is located within the non-volatile storage device or module and is separate from the controller 916 of the host 910.

[0103] The NV die of the NV medium 930 includes a 3D NV array 932, which is a three-dimensional array of memory cells based on the NV medium. In one example, the NV array 932 includes memory areas arranged as planes 934 and plane groups 936. Each plane group 936 may have two or more planes 934.

[0104] In one instance, controller 940 includes read control 942 for implementing state and access operations. In one instance, read control 942 enables SSD 920 to provide turbo state read information as described in any instance herein. In one instance, read control 942 enables SSD 920 to provide advance read access as described in any instance herein.

[0105] Figure 9B This is a block diagram of an example of a system with a solid-state drive (SSD), the SSD having a controller for managing fast operations of a plane in the form of a plane group. System 904 provides according to Figure 9A System 904 illustrates a logical layer of the host and SSD based on the hardware platform of system 902. System 904 may represent the software and firmware components, as well as the physical components, of an instance of system 902. In one instance, host 950 provides an instance of host 910. In one instance, SSD 960 provides an instance of SSD 920.

[0106] In one instance, host 950 contains host OS 952, which represents the host operating system or software platform used by the host. Host OS 952 can contain applications, services, agents, and / or other software that execute on it and are executed by the processor. File system 954 represents the control logic used to control access to NV media. File system 954 can manage what address or memory location is used to store what data. Many known file systems exist, and file system 954 can implement known file systems or other proprietary systems. In one instance, file system 954 is part of host OS 952.

[0107] Storage drive 956 represents one or more system-level modules that control the hardware of host 950. In one instance, drive 956 contains software applications that interface with and thus control the hardware of SSD 960. Storage drive 956 can provide a communication interface between the host and the SSD.

[0108] The SSD 960's controller 970 includes firmware 974, which represents the control software / firmware used by the controller. In one instance, the controller 970 includes a host interface 972, which represents the interface of the host 950. In another instance, the controller 970 includes a media interface 976, which represents the interface of the NAND die 962. The NAND die 962 represents a specific instance of NV media and contains the associated 3D NAND array.

[0109] Media interface 976 represents controls executed on the hardware of controller 970. It should be understood that controller 970 includes hardware for interfacing with host 950, which can be considered as being controlled by host interface software / firmware 974. Similarly, it should be understood that controller 970 includes hardware for interfacing with NAND die 962. In one instance, the code for host interface 972 may be part of firmware 974. In one instance, the code for media interface 976 may be part of firmware 974.

[0110] In one example, controller 970 includes error control 980 for handling data errors in the accessed data and for handling edge cases related to signaling and communication interfaces. Error control 980 may be implemented in hardware or firmware form, or a combination of hardware and software.

[0111] In one instance, the NAND die 962 has a plane group 966 and a plane 964. In one instance, the plane supports IMPRO operations. In one instance, the controller 970 includes a read control 990 for implementing state and access operations. In one instance, the read control 990 enables the SSD 960 to provide turbo state read information according to any instance herein. In one instance, the read control 990 enables the SSD 960 to provide early read access according to any instance herein.

[0112] Figure 10 This is a block diagram of an example of a computing system in which fast operations on nonvolatile planes in the form of a plane group can be implemented. System 1000 represents a computing device according to any example herein and can be a laptop computer, desktop computer, tablet computer, server, game or entertainment control system, embedded computing device or other electronic device.

[0113] System 1000 represents a system having a storage area according to an instance of System 100 or System 300. In one instance, storage area 1084 has a plane group with planes. In one instance, the planes support IMPRO operations. In one instance, controller 1082 includes read control 1090 for implementing state and access operations. In one instance, read control 1090 enables storage area 1084 to provide turbo state read information according to any instance herein. In one instance, read control 1090 enables storage area 1084 to provide advance read access according to any instance herein.

[0114] System 1000 includes processor 1010, which may include any type of microprocessor, central processing unit (CPU), graphics processing unit (GPU), processing core, or other processing hardware or combinations thereof, for enabling system 1000 to process or execute instructions. Processor 1010 may be a host processor device. Processor 1010 controls the overall operation of system 1000 and may be or include one or more programmable general-purpose or special-purpose microprocessors, digital signal processors (DSPs), programmable controllers, application-specific integrated circuits (ASICs), programmable logic devices (PLDs), or combinations thereof.

[0115] System 1000 includes boot / configuration 1016, which represents a storage area for storing boot code (e.g., Basic Input / Output System (BIOS)), configuration settings, security hardware (e.g., Trusted Platform Module (TPM)), or other system-level hardware operating outside the host OS. Boot / configuration 1016 may include non-volatile storage devices such as read-only memory (ROM), flash memory, or other memory devices.

[0116] In one example, system 1000 includes an interface 1012 coupled to processor 1010, which may represent a higher-speed or high-throughput interface for system components requiring higher bandwidth connections, such as memory subsystem 1020 or graphical interface component 1040. Interface 1012 represents interface circuitry, which may be a standalone component or integrated onto the processor die. Interface 1012 may be integrated as circuitry onto the processor die or as a component onto a system-on-a-chip. In the presence of graphical interface 1040, the graphical interface interfaces with the graphical component to provide a visual display to a user of system 1000. Graphical interface 1040 may be a standalone component or integrated onto the processor die or system-on-a-chip. In one example, graphical interface 1040 may drive a high-definition (HD) or ultra-high-definition (UHD) display that provides output to a user. In one example, the display may include a touchscreen display. In one example, graphical interface 1040 generates a display based on data stored in memory 1030, or based on operations performed by processor 1010, or both.

[0117] Memory subsystem 1020 represents the main memory of system 1000 and provides storage for code to be executed by processor 1010 or data values ​​to be used during routine execution. Memory subsystem 1020 may include one or more random access memories (RAMs), such as DRAM, 3DXP (3D Cross Point), or other memory devices, or combinations thereof. Memory 1030 specifically stores and hosts operating system (OS) 1032 to provide a software platform for executing instructions in system 1000. Additionally, application program 1034 can execute on the software platform of OS 1032 in memory 1030. Application program 1034 represents a program with its own operating logic to perform one or more functions. Process 1036 represents an agent or routine that provides auxiliary functions to OS 1032 or one or more application programs 1034 or combinations thereof. OS 1032, application programs 1034, and process 1036 provide software logic, thereby providing functionality to system 1000. In one example, memory subsystem 1020 includes memory controller 1022, which is a memory controller for generating commands and issuing commands to memory 1030. It should be understood that memory controller 1022 may be a physical part of processor 1010 or a physical part of interface 1012. For example, memory controller 1022 may be an integrated memory controller integrated into circuitry having processor 1010, such as integrated into a processor die or system-on-a-chip.

[0118] Although not specifically shown, it should be understood that system 1000 may include one or more buses or bus systems between devices, such as memory buses, graphics buses, interface buses, or other buses. Buses or other signal lines can communicatively or electrically couple components together, or both communicatively and electrically couple components. Buses may include physical communication lines, point-to-point connections, bridges, adapters, controllers, or other circuit systems, or combinations thereof. Buses may include one or more of, for example, system buses, peripheral component interconnect (PCI) buses, HyperTransport or Industry Standard Architecture (ISA) buses, small computer system interface (SCSI) buses, universal serial buses (USB), or other buses, or combinations thereof.

[0119] In one instance, system 1000 includes interface 1014, which can be coupled to interface 1012. Interface 1014 may be a lower-speed interface than interface 1012. In one instance, interface 1014 represents interface circuitry, which may include individual components and integrated circuit systems. In one instance, multiple user interface components or peripheral components, or both, are coupled to interface 1014. Network interface 1050 provides system 1000 with the ability to communicate with remote devices (e.g., servers or other computing devices) over one or more networks. Network interface 1050 may include an Ethernet adapter, wireless interconnect component, cellular network interconnect component, USB (Universal Serial Bus), or other wired or wireless standard-based interfaces or proprietary interfaces. Network interface 1050 can exchange data with remote devices, which may include sending data stored in memory or receiving data to be stored in memory.

[0120] In one instance, system 1000 includes one or more input / output (I / O) interfaces 1060. I / O interface 1060 may include one or more interface components through which a user interacts with system 1000 (e.g., audio, alphanumeric, haptic / touch, or other interfacings). Peripheral interface 1070 may include any hardware interface not specifically mentioned above. Peripheral devices generally refer to devices that are independently connected to system 1000. Dependent connection means that system 1000 provides a software platform or hardware platform, or both, on which operations are performed and with which the user interacts.

[0121] In one instance, system 1000 includes a storage subsystem 1080 for storing data in a non-volatile manner. In one instance, in some system implementations, at least some components of storage area 1080 may overlap with components of memory subsystem 1020. Storage subsystem 1080 includes storage device 1084, which may be or include any conventional medium for storing large amounts of data in a non-volatile manner, such as one or more disks, solid-state disks, NAND disks, 3DXP disks, or optical disks, or combinations thereof. Storage area 1084 retains code or instructions and data 1086 in a persistent state (i.e., values ​​are retained despite a power outage of system 1000). Storage area 1084 can generally be considered "memory," but memory 1030 is generally execution or operational memory used to provide instructions to processor 1010. Although storage area 1084 is non-volatile, memory 1030 may include volatile memory (i.e., the value or state of data is indeterminate if there is a power outage of system 1000). In one instance, storage subsystem 1080 includes controller 1082 for interfacing with storage area 1084. In one instance, controller 1082 is a physical part of interface 1014 or processor 1010, or may include circuitry or logic from both processor 1010 and interface 1014.

[0122] Power source 1002 provides power to the components of system 1000. More specifically, power source 1002 typically interfaces with one or more power supplies 1004 in system 1000 to provide power to the components of system 1000. In one example, power supply 1004 includes an AC to DC adapter for plugging into a wall outlet. This AC power source may be a renewable energy source (e.g., solar energy) 1002. In one example, power source 1002 includes a DC power source, such as an external AC to DC converter. In one example, power source 1002 or power supply 1004 includes wireless charging hardware for charging via proximity charging. In one example, power source 1002 may include an internal battery or fuel cell source.

[0123] Figure 11 This is a block diagram of an example of a mobile device in which rapid operation with respect to a group of non-volatile planes can be implemented. System 1100 represents a mobile computing device, such as a computing tablet computer, mobile phone or smartphone, wearable computing device, or other mobile device, or embedded computing device. It should be understood that some components are shown in general, and not all components of such a device are shown in system 1100.

[0124] System 1100 represents a system having a storage area according to an example of system 100 or system 300. In one example, memory 1162 includes an NV array 1166, which may contain non-volatile memory with a group of planes. In one example, the planes support IMPRO operations. Controller 1190 represents an internal controller in a storage device. In one example, controller 1190 includes a read control 1192 for implementing state and access operations. In one example, read control 1192 enables memory 1162 to provide turbo state read information for the non-volatile storage area according to any example herein. In one example, read control 1192 enables memory 1162 to provide early read access for the non-volatile storage area according to any example herein.

[0125] System 1100 includes processor 1110, which performs the main processing operations of system 1100. Processor 1110 may be a host processor device. Processor 1110 may include one or more physical devices, such as a microprocessor, application processor, microcontroller, programmable logic device, or other processing element. The processing operations performed by processor 1110 include executing an operating platform or operating system, on which application and device functions are executed. Processing operations include operations related to I / O (input / output) of human users or other devices, operations related to power management, operations related to connecting system 1100 to another device, or combinations thereof. Processing operations may also include operations related to audio I / O, display I / O, or other interfaces, or combinations thereof. Processor 1110 can execute data stored in memory. Processor 1110 can write to or edit data stored in memory.

[0126] In one example, system 1100 includes one or more sensors 1112. Sensor 1112 represents an interface to an embedded sensor or an external sensor, or a combination thereof. Sensor 1112 enables system 1100 to monitor or detect one or more conditions of the environment or apparatus in which system 1100 is implemented. Sensor 1112 may include environmental sensors (e.g., temperature sensors, motion detectors, light detectors, cameras, chemical sensors (e.g., carbon monoxide, carbon dioxide, or other chemical sensors)), pressure sensors, accelerometers, gyroscopes, medical or physiological sensors (e.g., biosensors, heart rate monitors, or other sensors for detecting physiological attributes) or other sensors, or combinations thereof. Sensor 1112 may also include sensors for biometric identification systems, such as fingerprint recognition systems, facial detection or recognition systems, or other systems for detecting or identifying user characteristics. Sensor 1112 should be understood broadly and is not limited to the many different types of sensors that can be implemented with system 1100. In one example, one or more sensors 1112 are coupled to processor 1110 via front-end circuitry integrated with processor 1110. In one instance, one or more sensors 1112 are coupled to processor 1110 via another component of system 1100.

[0127] In one example, system 1100 includes an audio subsystem 1120, which represents hardware (e.g., audio hardware and audio circuitry) and software (e.g., drivers, codecs) components associated with providing audio functionality to a computing device. The audio functionality may include speaker or headphone output and microphone input. Devices for this functionality may be integrated into or connected to system 1100. In one example, a user interacts with system 1100 by providing audio commands received and processed by processor 1110.

[0128] Display subsystem 1130 represents hardware (e.g., display device) and software components (e.g., drivers) for providing a visual display to a user. In one example, the display includes a tactile component or touchscreen element for the user to interact with a computing device. Display subsystem 1130 includes display interface 1132, which includes a specific screen or hardware device for providing a display to the user. In one example, display interface 1132 includes logic (e.g., a graphics processor) separate from processor 1110 for performing at least some display-related processing. In one example, display subsystem 1130 includes a touchscreen device that provides both input and output to the user. In one example, display subsystem 1130 includes a high-definition (HD) or ultra-high-definition (UHD) display that provides output to the user. In one example, display subsystem includes or drives a touchscreen display. In one example, display subsystem 1130 generates display information based on data stored in memory or based on operations performed by processor 1110, or both.

[0129] I / O controller 1140 represents hardware devices and software components related to user interaction. I / O controller 1140 can be used to manage hardware that is part of audio subsystem 1120 or display subsystem 1130, or both. Additionally, I / O controller 1140 shows connection points for attachable devices to system 1100 through which the user can interact with the system. For example, devices that can be attached to system 1100 may include microphone devices, speakers or stereo systems, video systems or other display devices, keyboards or keypad devices, buttons / switches, or other application-specific I / O devices such as card readers or other devices.

[0130] As mentioned above, the I / O controller 1140 can interact with the audio subsystem 1120 or the display subsystem 1130, or both. For example, input via a microphone or other audio device can provide input or commands to one or more applications or functions of the system 1100. Additionally, audio output can be provided as an alternative to or supplement to display output. In another instance, if the display subsystem includes a touchscreen, the display device also acts as an input device, which can be managed at least partially by the I / O controller 1140. Additional buttons or switches may also be present on the system 1100 to provide I / O functions managed by the I / O controller 1140.

[0131] In one instance, I / O controller 1140 manages an accelerometer, camera, light sensor or other environmental sensor, gyroscope, Global Positioning System (GPS) or other hardware or sensor 1112 that may be included in system 1100. Input can be part of direct user interaction or it can be providing environmental input to the system to affect the system's operation (e.g., filtering noise, adjusting the display for brightness detection, applying a flash to the camera, or other functions).

[0132] In one example, system 1100 includes power management 1150 for managing battery power usage, battery charging, and functions related to power-saving operations. Power management 1150 manages power from power source 1152, which supplies power to the components of system 1100. In one example, power source 1152 includes an AC-to-DC adapter for plugging into a wall socket. This AC power can be renewable energy (e.g., solar, motion-based energy). In one example, power source 1152 includes only DC power, which can be provided by an external AC-to-DC converter or other DC power source. In one example, power source 1152 includes wireless charging hardware for charging via proximity charging. In one example, power source 1152 may include an internal battery or fuel cell source.

[0133] Memory subsystem 1160 includes memory device 1162 for storing information in system 1100. Memory subsystem 1160 may include non-volatile (its state does not change in the event of a power interruption) or volatile (its state is uncertain in the event of a power interruption) memory devices, or combinations thereof. Memory 1160 may store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of applications and functions of system 1100. In one example, memory subsystem 1160 includes memory controller 1164 (which can also be considered part of the control of system 1100 and can potentially be considered part of processor 1110). Memory controller 1164 includes a scheduler for generating and issuing commands to control access to memory device 1162.

[0134] Connection 1170 includes hardware devices (e.g., wireless or wired connectors and communication hardware, or a combination of wired and wireless hardware) and software components (e.g., drivers, protocol stacks) for enabling system 1100 to communicate with external devices. External devices can be standalone devices, such as other computing devices, wireless access points or base stations, and peripheral devices such as headsets, printers, or other devices. In one example, system 1100 exchanges data with external devices for storage in memory or display on a display device. The exchanged data may include data to be stored in memory or data already stored in memory, for reading, writing, or editing.

[0135] Connection 1170 can encompass various different types of connections. In general, system 1100 is shown as having cellular connection 1172 and wireless connection 1174. Cellular connection 1172 typically refers to a cellular network connection provided by a wireless operator, such as a cellular network connection provided via GSM (Global System for Mobile Communications) or its variants or derivatives, CDMA (Code Division Multiple Access) or its variants or derivatives, TDM (Time Division Multiplexing) or its variants or derivatives, LTE (Long Term Evolution, also known as "4G"), 5G, or other cellular service standards. Wireless connection 1174 refers to a non-cellular wireless connection and can include personal area networks (e.g., Bluetooth), local area networks (e.g., WiFi), or wide area networks (e.g., WiMax) or other wireless communications, or combinations thereof. Wireless communication refers to the transmission of data through a non-solid medium using modulated electromagnetic radiation. Wired communication is conducted through a solid communication medium.

[0136] Peripheral connection 1180 includes hardware interfaces and connectors, as well as software components (e.g., drivers, protocol stacks) for making peripheral connections. It should be understood that system 1100 can be either a peripheral device (“connected to” 1182) or has peripheral devices connected to it (“accepting connections” 1184). System 1100 typically has a “dock” connector for connecting to other computing devices for, for example, managing (e.g., downloading, uploading, modifying, synchronizing) content on system 1100. Additionally, the dock connector may allow system 1100 to connect to certain peripheral devices that allow system 1100 to control content output, for example, to audiovisual or other systems.

[0137] In addition to proprietary docking connectors or other proprietary connection hardware, system 1100 can also be peripherally connected 1180 via common or standards-based connectors. Common types may include Universal Serial Bus (USB) connectors (which may contain any of several different hardware interfaces), display ports including Micro DisplayPort (MDP), High Definition Multimedia Interface (HDMI), or other types.

[0138] Figure 12 This is a block diagram of an example of a multi-node network in which fast operation of a non-volatile plane in the form of a plane group can be implemented. System 1200 represents a network of nodes that can apply adaptive ECC. In one instance, System 1200 represents a data center. In another instance, System 1200 represents a server farm. In yet another instance, System 1200 represents a data cloud or processing cloud.

[0139] System 1200 represents a system having a storage area according to an example of system 100 or system 300. In one example, storage node 1224 has storage area 1288, which may contain non-volatile memory with a plane group having planes. In one example, the planes support IMPRO operations. Controller 1286 represents an internal controller in the storage device. In one example, controller 1286 includes read control 1290 for implementing state and access operations. In one example, read control 1290 enables storage area 1288 to provide turbo state read information for the non-volatile storage area according to any example herein. In one example, read control 1290 enables storage area 1288 to provide early read access for the non-volatile storage area according to any example herein.

[0140] One or more clients 1202 send requests to system 1200 via network 1204. Network 1204 represents one or more local networks, wide area networks, or combinations thereof. Client 1202 can be a human or machine client that generates requests for operations to be performed by system 1200. System 1200 executes the application or data computation task requested by client 1202.

[0141] In one instance, system 1200 includes one or more racks, representing the structure and interconnect resources for housing and interconnecting multiple computing nodes. In one instance, rack 1210 includes multiple nodes 1230. In one instance, rack 1210 hosts multiple blade assemblies, namely blades 1220[0], ..., blades 1220[N-1], collectively referred to as blades 1220. Hosting refers to providing power, structural or mechanical support, and interconnection. Blade 1220 may refer to computing resources on a printed circuit board (PCB), where the PCB houses hardware components for one or more nodes 1230. In one instance, blade 1220 does not include a chassis or enclosure or other "box" other than the enclosure or shell or other "box" provided by rack 1210. In one instance, blade 1220 includes an enclosure with exposed connectors for connection to rack 1210. In one instance, system 1200 does not include rack 1210, and each blade 1220 includes a chassis or enclosure that can be stacked or otherwise reside near other blades and allows interconnection of nodes 1230.

[0142] System 1200 includes network architecture 1270, which represents one or more interconnectors for nodes 1230. In one instance, network architecture 1270 includes multiple switches 1272 or routers or other hardware for routing signals between nodes 1230. Additionally, network architecture 1270 may couple system 1200 to network 1204 for access by client 1202. Besides routing devices, network architecture 1270 may also be considered as including cables or ports or other hardware devices for coupling nodes 1230 together. In one instance, network architecture 1270 has one or more associated protocols for managing signal routing through system 1200. In one instance, the one or more protocols depend at least in part on the hardware devices used in system 1200.

[0143] As shown in the figure, rack 1210 contains N blades 1220. In one instance, in addition to rack 1210, system 1200 also contains rack 1250. As shown in the figure, rack 1250 contains M blade assemblies, namely blades 1260[0], ..., blades 1260[M-1], collectively referred to as blades 1260. M is not necessarily the same as N; therefore, it should be understood that various different hardware device components can be used, and said hardware device components are coupled together to system 1200 through network architecture 1270. Blade 1260 can be the same as or similar to blade 1220. Node 1230 can be any type of node and is not necessarily all of the same type. System 1200 is not limited to being homogeneous or non-homogeneous.

[0144] Nodes in system 1200 may include compute nodes, memory nodes, storage nodes, accelerator nodes, or other nodes. Rack 1210 is represented by having memory node 1222 and storage node 1224, which represent shared system memory resources and shared persistent storage areas, respectively. One or more nodes in rack 1250 may be memory nodes or storage nodes.

[0145] Node 1230 represents an instance of a compute node. For simplicity, only the compute nodes in blade 1220[0] are shown in detail. However, other nodes in system 1200 may be the same or similar. At least some nodes 1230 are compute nodes having a processor (proc) 1232 and memory 1240. A compute node is a node that has processing resources (e.g., one or more processors) that execute an operating system and can receive and process one or more tasks. In one instance, at least some nodes 1230 are server nodes, where a server is a processing resource represented by processor 1232 and memory 1240.

[0146] Memory node 1222 represents an instance of a memory node, where the system memory is external to the compute node. A memory node may include a controller 1282, which represents a processor on the node for managing access to the memory. The memory node includes memory 1284 as a memory resource to be shared among multiple compute nodes.

[0147] Storage node 1224 represents an instance of a storage server. A storage node is a node that has more storage resources than a compute node but no processor for performing tasks. The storage server includes processing resources for managing access to the storage nodes within the storage server. A storage node may include a controller 1286 for managing access to the storage area 1288 of the storage node.

[0148] In one instance, node 1230 includes interface controller 1234, which represents logic for controlling node 1230's access to network architecture 1270. This logic may include hardware resources for interconnecting to physical interconnect hardware. The logic may also include software or firmware logic for managing the interconnect. In one instance, interface controller 1234 is or includes a host network architecture interface, which can be the network architecture interface of any instance described herein. Interface controllers for memory node 1222 and storage node 1224 are not explicitly shown.

[0149] Processor 1232 may include one or more individual processors. Each individual processor may include a single processing unit, a multi-core processing unit, or a combination thereof. A processing unit may be a primary processor such as a CPU (Central Processing Unit), a peripheral processor such as a GPU (Graphics Processing Unit), or a combination thereof. Memory 1240 may be or include a memory device represented by memory 1240 and a memory controller represented by controller 1242.

[0150] Generally, for the purposes of the description herein, in one aspect, the first storage device comprises: a storage array having a plurality of planes having independent multi-plane read operations (IMPRO), the plurality of planes being organized into a plane group, wherein the planes in the plane group are used to receive and process commands in parallel; and a storage controller for receiving commands from a host controller and, in response to receiving commands, providing readiness information of all planes to the host controller.

[0151] According to an example of the first storage device, the readiness information includes virtual readiness information indicating that at least one plane in the plane group is ready to be read. According to any of the foreseeable examples of the first storage device, in one example, the storage controller updates the readiness state of a plane in response to a plane completing a read operation. According to any of the foreseeable examples of the first storage device, in one example, the plurality of planes comprises planes of different plane types, including single-level cell (SLC) and multi-level cell (MLC). According to any of the foreseeable examples of the first storage device, in one example, the plurality of planes comprises at least one plane having an instantaneous SLC mode. According to any of the foreseeable examples of the first storage device, in one example, the storage controller writes virtual readiness state information to a status register. According to any of the foreseeable examples of the first storage device, in one example, the storage controller further writes thermal alarm information together with the virtual readiness state information to the status register. According to any of the foreseeable examples of the first storage device, in one example, the storage controller further writes power reset information together with the virtual readiness state information to the status register.

[0152] Generally, for the purposes of the description herein, in one aspect, a first computer system includes: a host controller; and a storage device including: a three-dimensional (3D) NAND die having a storage array having a plurality of planes having independent multi-plane read operations (IMPRO), the plurality of planes being organized into a plane group, wherein the planes in the plane group are used to receive and process commands in parallel; and a storage controller for receiving commands from the host controller and, in response to receiving commands, providing the host controller with readiness information for all planes.

[0153] According to an example of the first computer system, the readiness information includes virtual readiness information indicating that at least one plane in the plane group is ready to be read. According to any of the foreseeable examples of the first computer system, in one example, the storage controller updates the readiness state of a plane in response to a plane completing a read operation. According to any of the foreseeable examples of the first computer system, in one example, the plurality of planes comprises planes of different plane types, said plane types including single-level cell (SLC) and multi-level cell (MLC). According to any of the foreseeable examples of the first computer system, in one example, the storage controller writes virtual readiness state information and thermal alarm information to a status register, and writes power information to the status register. According to any of the foreseeable examples of the first computer system, in one example, the computer system includes one or more of the following: a multi-core processor; a display communicatively coupled to the processor; a network interface communicatively coupled to the processor; or a battery that powers the computer system.

[0154] Generally, for the purposes of the description herein, in one aspect, the second storage device includes: a storage array having a plurality of planes organized as a group of planes, wherein the planes in the group of planes are used to receive and process commands in parallel, each group of planes having a first plane and a second plane; and a storage controller for reading data from the first plane in response to a virtual ready signal of the first plane in the group of planes before the second plane in the group of planes is ready.

[0155] According to an example of a second storage device, a first plane and a second plane are used to process read operations, wherein the first plane is used to signal virtual readiness with fewer read levels than the second plane after the read operation is completed. According to any of the foreseeable examples of a second storage device, in one instance, the second plane is used to continue the read operation after the first plane has completed its read operation. According to any of the foreseeable examples of a second storage device, in one instance, multiple planes have independent multi-plane read operations (IMPRO). According to any of the foreseeable examples of a second storage device, in one instance, each plane group in the storage array has two planes. According to any of the foreseeable examples of a second storage device, in one instance, the second storage device includes a buffer for storing read data from the first plane before providing the read data from the storage device to the host device.

[0156] Generally, for the purposes of the description herein, in one aspect, the first storage controller includes: input / output (I / O) hardware for coupling to a storage device having multiple planes having independent multi-plane read operations (IMPRO), the multiple planes being organized into a plane group, wherein the planes in the plane group are used to receive and process commands in parallel; and a read control for sending a command requesting readiness information for all planes.

[0157] According to an example of a first storage controller, the readiness information includes virtual readiness information indicating that at least one plane in the plane group is ready for reading. According to any of the foreseeable examples of the first storage controller, in one example, the storage device includes registers that are updated with the readiness state of the plane in response to a plane completing a read operation. According to any of the foreseeable examples of the first storage controller, in one example, the register includes a status register. According to any of the foreseeable examples of the first storage controller, in one example, the status register is further used to store thermal alarm information along with the virtual readiness state information. According to any of the foreseeable examples of the first storage controller, in one example, the status register is further used to store write power reset information along with the virtual readiness state information. According to any of the foreseeable examples of the first storage controller, in one example, the plurality of planes includes planes of different plane types, said plane types including single-level cell (SLC) and multi-level cell (MLC). According to any of the foreseeable examples of the first storage controller, in one example, the plurality of planes includes at least one plane having an instant SLC mode.

[0158] Generally, for the purposes of the description herein, in one aspect, the first method comprises: sending a command from a host controller to a storage device having multiple planes having independent multi-plane read operations (IMPRO), the multiple planes being organized into a plane group, wherein the planes in the plane group are used to receive and process the command in parallel; and receiving readiness information for all planes from the storage device.

[0159] According to an example of the first method, the readiness information includes virtual readiness information indicating that at least one plane in the plane group is ready for reading. According to any of the foreseeable examples of the first method, in one example, the first method further includes the storage device updating the readiness state of a plane in response to a plane completing a read operation. According to any of the foreseeable examples of the first method, in one example, the plurality of planes comprises planes of different plane types, said plane types including single-level cell (SLC) and multi-level cell (MLC). According to any of the foreseeable examples of the first method, in one example, the plurality of planes comprises at least one plane having an instantaneous SLC mode. According to any of the foreseeable examples of the first method, in one example, the storage device writes virtual readiness state information to a status register. According to any of the foreseeable examples of the first method, in one example, the storage device writes thermal alarm information together with the virtual readiness state information to the status register. According to any of the foreseeable examples of the first method, in one example, the storage device writes power reset information together with the virtual readiness state information to the status register.

[0160] Generally, for the purposes of the description herein, in one aspect, the second method comprises: receiving a command at a storage device from a host controller, the storage device having multiple planes having independent multi-plane read operations (IMPRO), the multiple planes being organized into a plane group, wherein the planes in the plane group are used to receive and process the command in parallel; and sending readiness information of all planes to the host controller.

[0161] According to an example of the second method, the readiness information includes virtual readiness information indicating that at least one plane in the plane group is ready for reading. According to any of the foreseeable examples of the second method, in one example, the second method further includes the storage device updating the readiness state of a plane in response to a plane completing a read operation. According to any of the foreseeable examples of the second method, in one example, the plurality of planes comprises planes of different plane types, said plane types including single-level cell (SLC) and multi-level cell (MLC). According to any of the foreseeable examples of the second method, in one example, the plurality of planes comprises at least one plane having an instantaneous SLC mode. According to any of the foreseeable examples of the second method, in one example, the storage device writes virtual readiness state information to a status register. According to any of the foreseeable examples of the second method, in one example, the storage device writes thermal alarm information together with the virtual readiness state information to the status register. According to any of the foreseeable examples of the second method, in one example, the storage device writes power reset information together with the virtual readiness state information to the status register.

[0162] Generally, for the purposes of the description herein, in one aspect, the second computer system includes: a host controller; and a storage device comprising: a three-dimensional (3D) NAND die according to any of the foregoing instances of the second storage device.

[0163] Generally, for the purposes of the description herein, in one aspect, the third storage device comprises: a storage array having a plurality of planes organized as a group of planes, wherein the planes in the group of planes are used to receive and process commands in parallel, each group of planes having a first plane and a second plane; and a storage controller for reading data from the first plane in response to a virtual ready signal of the first plane in the group of planes before the second plane in the group of planes is ready.

[0164] According to an example of a third storage device, a first plane and a second plane are used to process read operations, wherein the first plane is used to signal virtual readiness with fewer read levels than the second plane after the read operation is completed. According to any of the foregoing examples of a third storage device, in one example, the second plane is used to continue the read operation after the first plane has completed the read operation. According to any of the foregoing examples of a third storage device, in one example, multiple planes have independent multi-plane read operations (IMPRO). According to any of the foregoing examples of a third storage device, in one example, each plane group in the storage array has two planes. According to any of the foregoing examples of a third storage device, in one example, the storage device includes a buffer for storing read data before providing read data from the first plane from the storage device to the host device. Generally, for the purposes of the description herein, in one aspect, a second computer system includes a host controller; and a storage device comprising a three-dimensional (3D) NAND die according to any of the foregoing examples of a third storage device.

[0165] Generally, for the purposes of the description herein, in one aspect, the second storage controller includes: input / output (I / O) hardware for coupling to a storage device having a plurality of planes organized as a group of planes, wherein the planes in the group of planes are used to receive and process commands in parallel, each group of planes having a first plane and a second plane; and a read control for sending a command to read data from the first plane in response to a virtual ready signal of the first plane in the group of planes before the second plane in the group of planes is ready.

[0166] According to an example of a second storage controller, a first plane and a second plane are used to process read operations, wherein the first plane is used to signal virtual readiness with fewer read levels than the second plane after a read operation is completed. According to any of the foreseeable examples of a second storage controller, in one instance, the second plane is used to continue a read operation after the first plane has completed its read operation. According to any of the foreseeable examples of a second storage controller, in one instance, multiple planes have independent multi-plane read operations (IMPRO). According to any of the foreseeable examples of a second storage controller, in one instance, each plane group in the storage array has two planes. According to any of the foreseeable examples of a second storage controller, in one instance, the storage device includes a buffer for storing read data from the first plane before providing read data from the storage device to the host device.

[0167] Generally speaking, for the purposes of the description herein, in one aspect, the second computer system includes: a host controller according to any of the foregoing instances of the second storage controller; and a storage device comprising: a three-dimensional (3D) NAND die.

[0168] Generally, for the purposes of the description herein, in one aspect, the third method comprises: receiving a command at a storage array having a plurality of planes organized as plane groups, wherein the planes in the plane groups are used to receive and process the command in parallel, each plane group having a first plane and a second plane, the command being to read data from the first plane in response to a virtual ready signal of the first plane in the plane group; and sending data to a host controller before the second plane in the plane group is ready.

[0169] According to an example of the third method, a first plane and a second plane are used to process read operations, wherein the first plane is used to signal virtual readiness with fewer read levels than the second plane after the read operation is completed.

[0170] According to any of the foregoing examples of the third method, in one instance, the second plane is used to continue the read operation after the first plane has completed the read operation. According to any of the foregoing examples of the third method, in one instance, multiple planes have independent multi-plane read operations (IMPRO). According to any of the foregoing examples of the third method, in one instance, each plane group in the storage array has two planes. According to any of the foregoing examples of the third method, in one instance, the method includes storing the read data before providing the read data from the first plane from the storage device to the host device.

[0171] Generally, for the purposes of the description herein, in one aspect, the fourth method comprises: sending a command from a host controller to a storage device having a storage array having a plurality of planes organized as a group of planes, wherein the planes in the group of planes are used to receive and process commands in parallel, each group of planes having a first plane and a second plane, the command being to read data from the first plane in response to a virtual ready signal of the first plane in the group of planes; and receiving data at the host controller before the second plane in the group of planes becomes ready.

[0172] According to an example of the fourth method, a first plane and a second plane are used to process read operations, wherein the first plane is used to signal virtual readiness with fewer read levels than the second plane after the read operation is completed. According to any of the foreseeable examples of the fourth method, in one instance, the second plane is used to continue the read operation after the first plane has completed its read operation. According to any of the foreseeable examples of the fourth method, in one instance, multiple planes have independent multi-plane read operations (IMPRO). According to any of the foreseeable examples of the fourth method, in one instance, each plane group in the storage array has two planes. According to any of the foreseeable examples of the fourth method, in one instance, the method includes storing read data before providing read data from the first plane from the storage device to the host device.

[0173] The flowcharts illustrated herein provide examples of sequences of various process actions. Flowcharts can indicate operations to be performed via software or firmware routines, as well as physical operations. Flowcharts can illustrate examples of implementations of the states of a finite state machine (FSM), which can be implemented in hardware and / or software. Although shown in a specific order or sequence, the order of actions may be modified unless otherwise specified. Therefore, the illustrated diagrams should be understood as examples only, and the processes may be performed in different orders, and some actions may be performed in parallel. Furthermore, one or more actions may be omitted; therefore, not all implementations will perform all actions.

[0174] With respect to the various operations or functions described herein, they can be described or defined as software code, instructions, configuration, and / or data. The content can be directly executable (in the form of an "object" or "executable file"), source code, or differential code ("incremental" or "patch" code). The software content described herein can be provided by an artifact storing the content or by operating a communication interface to send data via said communication interface. A machine-readable storage medium can enable a machine to perform the described functions or operations and includes any mechanism that stores information in a machine-accessible form, such as recordable / non-recordable media (e.g., read-only memory (ROM), random access memory (RAM), disk storage media, optical storage media, flash memory devices, etc.). A communication interface includes any mechanism that interfaces with any of hardwired media, wireless media, optical media, etc., to communicate with another device (e.g., memory bus interface, processor bus interface, Internet connection, disk controller, etc.). The communication interface can be configured by providing configuration parameters and / or sending signals to prepare the communication interface to provide data signals describing the software content. The communication interface can be accessed via one or more commands or signals sent to the communication interface.

[0175] The components described herein can be building blocks used to perform the described operations or functions. Each component described herein comprises software, hardware, or a combination thereof. Components can be implemented as software modules, hardware modules, special-purpose hardware (e.g., special-purpose hardware, application-specific integrated circuits (ASICs), digital signal processors (DSPs), etc.), embedded controllers, hardwired circuit systems, etc.

[0176] In addition to the content described herein, various modifications may be made to the disclosure and embodiments of the invention without departing from the scope of the invention. Therefore, the descriptions and examples herein are to be interpreted in an illustrative rather than restrictive sense. The scope of the invention should be measured only by reference to the appended claims.

Claims

1. A storage device, comprising: A storage array having multiple planes organized as plane groups, wherein the planes in the plane groups are used to receive and process commands in parallel, and each plane group has a first plane and a second plane; and A storage controller for reading data from the first plane in response to a virtual readiness signal of the first plane in the plane group prior to the second plane in the plane group being ready.

2. The storage device of claim 1, wherein the first plane and the second plane are used to process a read operation, wherein the first plane is used to signal the virtual readiness with fewer read levels than the second plane after the read operation is completed.

3. The storage device according to claim 2, wherein the second plane is configured to continue the read operation after the first plane has completed the read operation.

4. The storage device according to any one of claims 1 to 3, wherein the plurality of planes have independent multiplane read operations (IMPRO).

5. The storage device according to any one of claims 1 to 4, wherein each plane group in the storage array has two planes.

6. The storage device according to any one of claims 1 to 5, further comprising: A buffer is used to store the read data before it is provided from the storage device to the host device.

7. A storage controller, comprising: Input / output (I / O) hardware for coupling to a storage device having multiple planes organized as a group of planes, wherein the planes in the group of planes are used to receive and process commands in parallel, and each group of planes has a first plane and a second plane; as well as Control logic for sending a command to read data from the first plane in response to a virtual ready signal of the first plane in the plane group before the second plane in the plane group is ready.

8. The storage controller of claim 7, wherein the first plane and the second plane are used to process read operations, wherein the first plane is used to signal the virtual readiness with fewer read levels than the second plane after the read operation is completed.

9. The storage controller according to any one of claims 7 to 8, wherein the second plane is configured to continue the read operation after the first plane has completed the read operation.

10. The storage controller according to any one of claims 7 to 9, wherein the plurality of planes have independent multiplane read operations (IMPRO).

11. The storage controller according to any one of claims 7 to 10, wherein each plane group in the storage array has two planes.

12. The storage controller according to any one of claims 7 to 11, wherein the storage device includes a buffer for storing the read data before providing read data from the first plane from the storage device to the host device.

13. A method for managing a storage device, comprising: Commands are sent from the host controller to a storage device having a storage array having multiple planes organized as plane groups, wherein the planes in the plane groups are used to receive and process commands in parallel, each plane group having a first plane and a second plane, the command being to read data from the first plane in response to a virtual ready signal in the first plane of the plane group; as well as The data is received at the host controller before the second plane in the plane group is ready.

14. The method of claim 13, wherein the first plane and the second plane are used to process a read operation, wherein the first plane is used to signal the virtual readiness with fewer read levels than the second plane after the read operation is completed.

15. The method according to any one of claims 13 to 14, wherein the second plane is used to continue the read operation after the first plane has completed the read operation.

16. The method according to any one of claims 13 to 15, wherein the plurality of planes have independent multiplane readout operations (IMPRO).

17. The method according to any one of claims 13 to 16, wherein each plane group in the memory array has two planes.

18. The method according to any one of claims 13 to 17, further comprising: The read data is stored before it is provided from the storage device to the host device.

19. A computer system comprising: Host controller; as well as Storage device, comprising: A three-dimensional (3D) NAND die having a memory array having multiple planes having independent multi-plane read operations (IMPRO), the multiple planes being organized into a plane group, wherein the planes in the plane group are used to receive and process commands in parallel; as well as A storage controller is configured to receive commands from the host controller and, in response to receiving the commands, provide the host controller with readiness information for all planes.

20. A storage device, comprising: A storage array having multiple planes organized as plane groups, wherein the planes in the plane groups are used to receive and process commands in parallel, and each plane group has a first plane and a second plane; and A storage controller for reading data from the first plane in response to a virtual readiness signal of the first plane in the plane group prior to the second plane in the plane group being ready.

21. A method comprising: Commands are sent from the host controller to the storage device, which has multiple planes and independent multi-plane read operations (IMPRO). The multiple planes are organized into a plane group, wherein the planes in the plane group are used to receive and process commands in parallel. as well as Receive readiness information for all planes from the storage device.

Images