Techniques for efficient complex vector multiplication

Abstract

Processing circuitry to perform a vector operation and instruction decoder circuitry to decode an instruction from an instruction set to control the processing circuitry to perform the vector operation specified by the instruction are provided. An array storage device having storage elements for storing data blocks is used to store at least one two-dimensional array of data blocks, the processing circuitry being accessible to the at least one two-dimensional array of data blocks when the vector operation is performed. The instruction set includes a complex numerical outer product instruction specifying a first source operand, a second source operand, and a destination operand, where each of the first source operand and the second source operand is a vector operand including a plurality of source data elements, each source data element being a complex number formed by a real part and an imaginary part, and the destination operand identifies a given two-dimensional array of data blocks within the array storage device. The processing circuitry, in response to the complex value outer product instruction, performs an outer product operation using the source data element of the first source operand and the source data element of the second source operand to produce a plurality of result data elements, where each result data element is a complex number formed by a real part and an imaginary part, and wherein each real part and each imaginary part of each result data element are associated with one of the data blocks in the given two-dimensional array of data blocks and are used to update the value of the associated data block.

Description

Background Technology

[0001] This technology relates to the field of data processing, and more specifically to techniques for efficiently performing complex multiplication.

[0002] To improve performance, one could offer multiple complex numbers within a single vector by processing them in parallel, thus enabling vector computations. However, performing computations on complex numbers still has a significant performance impact because multiple vector instructions are typically required to execute the necessary calculations.

[0003] Many computational tasks require complex numerical arithmetic, such as in digital signal processing (DSP) algorithms, 5G applications in communications infrastructure, and high-performance computing (HPC) applications. Complex number multiplication is often required, and given the computational resource demands typically associated with performing such operations, there is a desire to provide techniques to accelerate these multiplication operations, thereby improving performance / throughput. Summary of the Invention

[0004] In one example arrangement, an apparatus is provided, comprising: processing circuitry for performing vector operations; instruction decoder circuitry for decoding instructions from an instruction set to control the processing circuitry to perform the vector operation specified by the instructions; and an array storage device including storage elements for storing data blocks, the array storage device being arranged to store at least one two-dimensional array of data blocks, wherein the processing circuitry can access the at least one two-dimensional array of data blocks when the vector operation is performed; wherein: the instruction set includes a complex-valued outer product instruction specifying a first source operand, a second source operand, and a destination operand, wherein the first source operand and the second source operand... Each of the operands is a vector operand comprising multiple source data elements, each source data element being a complex number formed by real and imaginary parts, and the destination operand identifies a given two-dimensional array of data blocks within the array storage device; and the processing circuit, in response to the complex value outer product instruction, performs an outer product operation using the source data elements of the first source operand and the source data elements of the second source operand to produce multiple result data elements, wherein each result data element is a complex number formed by real and imaginary parts, and wherein each real and each imaginary part of each result data element is associated with a data block in the given two-dimensional array of data blocks and is used to update the value of the associated data block.

[0005] In another example arrangement, a method is provided, comprising: performing a vector operation using processing circuitry; decoding an instruction from an instruction set to control the processing circuitry to perform the vector operation specified by the instruction; and employing an array storage device including storage elements for storing data blocks, the array storage device being arranged as at least one two-dimensional array of data blocks, wherein the processing circuitry can access the at least one two-dimensional array of data blocks when the vector operation is performed; wherein: the instruction set includes a complex-valued outer product instruction specifying a first source operand, a second source operand, and a destination operand, wherein each of the first source operand and the second source operand comprises a plurality of source operands. The method includes: using the processing circuitry in response to the complex value outer product instruction to perform an outer product operation using the source data elements of the first source operand and the source data elements of the second source operand to produce a plurality of result data elements, wherein each result data element is a complex number formed by real and imaginary parts, and wherein each real part and each imaginary part of each result data element is associated with a data block in the given two-dimensional array of data blocks and is used to update the value of the associated data block.

[0006] In another example arrangement, a computer program is provided for controlling a host data processing device to provide an instruction execution environment. The computer program includes: processing program logic for performing vector operations; instruction decoding program logic for decoding instructions from an instruction set to control the processing program logic to perform the vector operation specified by the instructions; and array storage device emulation program logic for emulating an array storage device including storage elements for storing data blocks, the array storage device being arranged as at least one two-dimensional array of data blocks, wherein the processing program logic can access the at least one two-dimensional array of data blocks when the vector operation is performed; wherein the instruction set includes specifying a first source operand. A complex-valued outer product instruction for a first source operand and a second source operand, wherein each of the first and second source operands is a vector operand comprising a plurality of source data elements, each source data element being a complex number formed by real and imaginary parts, and the destination operand identifies a given two-dimensional array of data blocks within the array storage device; and the processing logic, in response to the complex-valued outer product instruction, performs an outer product operation using the source data elements of the first and second source operands to produce a plurality of result data elements, wherein each result data element is a complex number formed by real and imaginary parts, and wherein each real and each imaginary part of each result data element is associated with a data block in the given two-dimensional array of data blocks and is used to update the value of the associated data block. Such a computer program can be set on any known transient computer-readable medium (such as transmitting code via a network in a wired or wireless manner) or non-transitory computer-readable medium (such as semiconductors, disks, or optical discs). Attached Figure Description

[0007] The present technology will be further described by way of example only, with reference to examples illustrated in the accompanying drawings, wherein:

[0008] Figure 1 This is a block diagram of a data processing device;

[0009] Figure 2 Examples of architectural registers that can be provided within a device, including vector registers for storing vector operands and array registers for storing arrays of 2D data elements, are shown, including examples of physical implementations of the array registers;

[0010] Figure 3A and Figure 3B This schematically illustrates how access can be performed on a square 2D array within an array storage device;

[0011] Figure 4A Example of outer product operation;

[0012] Figure 4B Example of matrix multiplication operation;

[0013] Figure 5 It is a block diagram of an embodiment of an example, illustrating how processing circuitry can be used to perform an outer product operation on a complex vector;

[0014] Figure 6 It is a flowchart illustrating the steps to be performed according to a specific example, in order to perform an outer product operation on a complex vector;

[0015] Figure 7 Examples of dot product circuits that can be used to perform dot product operations on real numbers;

[0016] Figure 8 Examples of how it can be used Figure 7 Two examples of dot product circuits, multiplying two complex numbers as part of the complex numerical cross product and accumulation operation performed on two complex vectors;

[0017] Figure 9 Examples of using multiple dot product circuits to perform an outer product operation on two complex vectors are shown.

[0018] Figure 10 The example implementation illustrates how input operation circuitry can be associated with a dot product circuit to adjust how the real and imaginary parts of at least one source data element are provided to the associated dot product circuit.

[0019] Figure 11 It is a more detailed illustration of the input operation circuitry used in a specific implementation of an example;

[0020] Figures 12A to 12C Examples of how it can be used with, for example Figure 8 The illustrated pair of dot product circuits are associated with data manipulation circuitry to allow for various other variations of complex-valued outer product operations;

[0021] Figure 13 The example implementation illustrates how multiplier-based circuit arrays can be used to support the outer product operation on real vectors, and how these circuit pairs can be combined to support the dot product calculation used when performing the outer product operation on complex vectors.

[0022] Figure 14 An octagonal dot product circuit is schematically illustrated for use when performing a dot product operation on two octagonal real vectors.

[0023] Figure 15 The illustrations demonstrate, based on a specific example implementation, multiple instances of such an octagonal dot product circuit that can be used when performing an outer product sum operation on complex vectors;

[0024] Figure 16 Examples of using multiple dot product circuits to perform the outer product sum operation on two complex vectors;

[0025] Figure 17 This illustrative example illustrates, based on a specific implementation, how the real and imaginary parts of a complex number in one of the vectors can be manipulated before being provided to a pair of dot product circuits when performing an outer product sum operation; and

[0026] Figure 18 Examples of available simulator implementations are provided. Detailed Implementation

[0027] According to the technology described herein, an apparatus is provided comprising: a processing circuit for performing vector operations; and an instruction decoder circuit for decoding instructions from an instruction set to control the processing circuit to perform the vector operation specified by the instructions. For example, the instruction decoder circuit may generate a control signal in response to an instruction in the instruction set, and the control signal may control the processing circuit to perform the vector operation.

[0028] Vector operations are operations performed on vector operands (e.g., operands comprising multiple data elements). Vector operations can include any operation involving at least one vector operand, such as a load or store operation (e.g., loading a vector from or storing a vector into a storage location) or an arithmetic operation (e.g., addition, multiplication) performed on vector operands. In this technology, the processing circuitry is capable of performing vector operations including at least an outer product operation. Vector operands may (but do not necessarily need to) be stored in vector registers, wherein a single vector register may store the entire vector operand, or wherein a single vector operand may be distributed among multiple vector registers (and therefore a single vector register may store elements from multiple vector operands).

[0029] According to the technology described herein, an array storage device is also provided, which includes storage elements for storing data blocks and is arranged as at least one two-dimensional array of data blocks, wherein the processing circuitry is able to access the at least one two-dimensional array of data blocks when the vector operation is performed.

[0030] Furthermore, according to the technique described herein, the instruction set includes complex numerical outer product instructions that specify a first source operand, a second source operand, and a destination operand. Each of the first and second source operands is a vector operand comprising a plurality of source data elements, and each source data element is a complex number formed by real and imaginary parts. The destination operand is arranged to identify a given two-dimensional array of data blocks within the array storage device. It should be noted that the terms "first" and "second" are merely labelling, and the first and second source operands do not necessarily need to be first and second operands respectively specified by the complex numerical outer product instructions. Rather, the first and second operands can be identified by the complex numerical outer product instructions in any order.

[0031] In response to the complex outer product instruction, the processing circuit performs an outer product operation using the source data elements of the first source operand and the second source operand to produce multiple result data elements. Each result data element is a complex number formed by real and imaginary parts, and each real and imaginary part of each result data element is associated with a data block in a given two-dimensional array of data blocks and is used to update the value of the associated data block.

[0032] In some cases, there may be a one-to-one correspondence between the real part of a resulting data element and its associated data block in the 2D array (and similarly between the imaginary part of a resulting data element and its associated data block in the 2D array), and therefore the value in any given data block can be updated based on the associated real or imaginary part of one of the resulting data elements. However, in some other cases, such as when performing complex numerical outer product sum operations (discussed in more detail later), the real parts of multiple resulting data elements may be associated with a corresponding data block in the 2D array (and similarly, the imaginary parts of multiple resulting data elements may be associated with a corresponding data block in the 2D array), and in this case, the value in any given data block is updated based on multiple associated real parts or multiple associated imaginary parts.

[0033] By defining an instruction (a complex-valued outer product instruction) that enables the outer product operation on a complex vector in response to a single instance of the instruction, performance and throughput can be significantly improved when performing tasks that require extensive use of complex-related multiplication operations. Specifically, with this approach, the execution of a single instruction can be used to perform the multiplication of complex vectors, whereas previously multiple instructions were required to perform the computations needed to generate the multiplication result. Furthermore, processing resources can be used efficiently by arranging the required multiplications via outer product operations, where the results are used to update a two-dimensional array of data blocks provided within an array storage device. For example, this allows for the easy merging of accumulation (or subtraction) operations during computation, providing numerous additional benefits. For instance, by using the same destination operand (i.e., the same two-dimensional array of data blocks) for multiple instances of the complex-valued outer product instruction, a particularly efficient mechanism can be provided for performing matrix multiplication on complex vectors.

[0034] In one example implementation, both the first and second source operands are configured to interleave the real and imaginary parts of the plurality of source data elements. By allowing the data elements required by various computational blocks within the processing circuitry to be logically grouped and provided to these computational blocks, this enables a particularly efficient implementation when performing outer product operations. Specifically, in one example implementation, separate computational blocks can be used to produce each part (real or imaginary) of each resulting data element, and each computational block will require the input of the real and imaginary parts of at least two data elements (from at least one of each source operand), and thus this allows for a reduction in the complexity of the routing circuitry providing the required input to each computational block by interleaving the real and imaginary parts of the plurality of source data elements within each source operand.

[0035] Furthermore, in one example implementation, within at least one dimension of the given two-dimensional array of the data block, the real and imaginary parts of a plurality of resulting data elements are associated with the data block such that the real and imaginary parts of the plurality of resulting data elements are interleaved. Similarly, this enables a particularly efficient implementation, reducing the routing complexity between computation blocks and associated data blocks within the two-dimensional array.

[0036] The processing circuitry can be configured in various ways to enable the performance of outer product operations. However, in one example implementation, the processing circuitry includes a dot product circuitry associated with each data block in the given two-dimensional array of data blocks. The dot product circuitry associated with a given data block can be arranged to perform a dot product operation using the real and imaginary parts of at least one source data element of a first source operand and at least one source data element of a second source operand to generate the required portion (which may be the real or imaginary part depending on the dot product circuitry considered) of at least one result data element to be used to update the value of the given data block. By using multiple instances of dot product circuitry, this allows for a particularly efficient implementation of the required circuitry within the processing circuitry to perform outer product operations on complex vectors. In practice, in some implementations, such dot product circuitry may already exist within devices for other purposes or can be easily instantiated by combining groups of components already provided for other purposes.

[0037] In one example implementation, the apparatus further includes input operation circuitry associated with each data block in the given two-dimensional array of data blocks, wherein the input operation circuitry associated with the given data block is controlled according to the complex numerical outer product instruction to perform input operation operations to adjust how the real and imaginary parts of at least one source data element are provided to the dot product circuitry associated with the given data block, thereby ensuring that the execution of the dot product operation generates the required portion of the at least one result data element to be used to update the value of the given data block. Specifically, in order for the dot product circuitry to generate the desired output, it may be necessary to invert one of the input portions (e.g., real or imaginary) of at least one source data element and / or reorder the real and imaginary parts of at least one source data element, and such functions can be easily performed by the input operation circuitry. Furthermore, providing such input operation circuitry provides additional flexibility, such as enabling the processing of the complex numerical outer product instruction to be adjusted according to a specific variant of the complex numerical outer product instruction before providing different portions of the source data element to the dot product circuitry, allowing the same dot product circuitry to be used to implement various different variants of the complex numerical outer product instruction.

[0038] While in some implementations the input operation circuitry can be used to manipulate data elements in either the first or second source operand, in a specific implementation the input operation circuitry is associated with only one of the two source operands, and only manipulates the data elements of that associated source operand as needed, without needing to manipulate the data elements of the other source operand. This approach can lead to particularly efficient and lower-cost designs, for example, due to reduced hardware complexity and power consumption.

[0039] The input operation circuit may take various forms, but in one example implementation it includes: an inverter circuit for inverting the value of at least one portion of the at least one source data element; and / or a reordering circuit for swapping the order of the real and imaginary parts of the at least one source data element.

[0040] In one example implementation, the device supports multiple variants of the complex numerical outer product instruction, and the input operation performed by the input operation circuitry associated with the given data block is based on the variant of the complex numerical outer product instruction being executed, ensuring that the dot product operation performed by the dot product circuitry associated with the given data block generates the required portion of the at least one resulting data element to be used to update the value of the given data block. Therefore, by appropriately designing the input operation circuitry, the use of multiple variants of the complex numerical outer product instruction can be accommodated even using the same basic computing hardware.

[0041] The input operation circuitry can be arranged in various ways, but in one example implementation, the input operation circuitry associated with each given data block is arranged to generate multiple candidate variants of the real and imaginary parts of at least one source data element, and further includes a multiplier circuitry controlled according to the variant of the complex-valued outer product instruction being executed, to select which candidate variants are provided to the dot product circuitry associated with the given data block. This provides a particularly efficient implementation.

[0042] In one example implementation, several variations of the complex numerical outer product instruction include: a non-conjugate variation, wherein the complex number forming the source data elements of both the first and second source operands is used when performing the outer product operation; and at least one conjugate variation, wherein the conjugate of the complex number forming the source data elements of at least one of the first and second source operands is used when performing the outer product operation. As will be understood by those skilled in the art, when forming the conjugate of a complex number, the sign of the imaginary part of the complex number is reversed. Using the conjugate version of the complex number is useful for various applications (e.g., data processing in communication systems), and therefore supporting such variations of the complex numerical outer product instruction is beneficial. Complex numerical outer product instructions with such conjugate variations can be easily adapted by properly configuring the input operation circuitry, while reusing the same basic computing hardware.

[0043] While in one example implementation, such a conjugation variant may result in the use of conjugation on complex numbers of source data elements forming two source operands, in another example implementation, such a conjugation variant may result in the use of conjugation only on complex numbers of source data elements forming one source operand, while the complex numbers of source data elements forming the other source operand use their original form.

[0044] As another example of the different complex-valued outer product instruction variants that can be supported, such variants may include: an accumulation variant, wherein each real and each imaginary part of each resulting data element is added to the current value of the associated data block to form an updated value of the associated data block; and a subtraction variant, wherein each real and each imaginary part of each resulting data element is subtracted from the current value of the associated data block to form an updated value of the associated data block. Similarly, the same basic computational hardware can be used to accommodate both variants by appropriately configuring the input operation circuitry.

[0045] As previously mentioned, in one example implementation, the input operation circuitry associated with the given data block can be arranged to operate on at least one source data element of either the first source operand or the second source operand to be used by the dot product circuitry associated with the given data block. This provides a particularly efficient and cost-effective solution while still allowing support for many variations of different complex numerical outer product instructions.

[0046] In one example implementation, the techniques described herein can also be used to support the performance of outer product sum operations on complex numbers (where the number of bits forming each source data element is less than the number of bits forming each result data element). Specifically, complex numerical outer product instructions (or at least one variant thereof) may take the form of complex numerical outer product sum instructions. When such instructions are executed, the real parts of multiple result data elements have the same associated data block within the two-dimensional array of data blocks, and the processing circuitry is configured to combine these real parts of the multiple result data elements to update the value of the same associated data block. Similarly, the imaginary parts of multiple result data elements have another identical associated data block within the two-dimensional array of data blocks, and the processing circuitry is configured to combine these imaginary parts of the multiple result data elements to update the value of the other identical associated data block.

[0047] In some example implementations, hardware for processing outer product operations of real vectors has been provided and can be reused to support outer product operations of complex vectors. For example, the processing circuitry can be arranged to provide a plurality of multiplier-based circuits for performing a real outer product operation using a first vector and a second vector of real numbers in response to a real outer product instruction, such that each multiplier-based circuit generates a real result data element within the resulting matrix of real result data elements when performing the real outer product operation. The dot product circuitry previously mentioned as associated with each data block in the given two-dimensional array of data blocks (i.e., the dot product circuitry used when executing complex outer product instructions) can be arranged to reuse a plurality of the multiplier-based circuitry and a combination circuitry for combining the outputs from the multiplier-based circuitry to generate the required portion of the at least one result data element to be used to update the value of the given data block. In a specific example implementation, such circuitry can be reconfigured in real time to handle real or complex cross product operations as needed. Therefore, the same basic hardware can be used to perform cross product operations on real or complex numbers, with the result stored in a two-dimensional array of data blocks in each case, resulting in a particularly efficient and flexible implementation.

[0048] Multiplier-based circuits are reused to perform the required functionality when executing complex value outer product instructions, and they can take various forms. For example, multiplier-based circuits can take the form of multiply-accumulate circuits used when performing real value outer product operations, and these multiply-accumulate circuits can be combined to form dot product circuits used when performing complex value outer product operations. Similarly, dot product-accumulate circuits can be used when performing real value outer product sum operations, and these dot product-accumulate circuits can be combined to form the dot product circuits required when performing complex value outer product sum operations.

[0049] If necessary, predicates may be used on one or more source operands, depending on an example implementation. Specifically, the complex numerical outer product instruction may include at least one predicate operand that enables one or more source data elements to be excluded from the outer product operation. Although in some implementations, a predicate operand may be provided for only one source operand, in one example implementation, separate predicate operands are provided for each source operand, thereby allowing the exclusion of one or more source data elements from any one or both source operands from the outer product operation.

[0050] Each predicate operand can take various forms and, in one example implementation, may include multiple bits, each bit being associated with a source data element in the corresponding source operand and used to indicate whether an outer product operation should be performed on that data element. Various methods are available for handling any data element to be excluded. For example, the execution of an operation involving that data element can be prohibited, or alternatively, the operation can be performed, but no result based on that data element can subsequently be used to update the corresponding data block in the two-dimensional array.

[0051] Specific examples will now be described with reference to the accompanying drawings.

[0052] Figure 1 A data processing system 10 is schematically illustrated, comprising a processor 20 coupled to a memory 30 storing data values ​​32 and program instructions 34. The processor 20 includes an instruction fetching unit 40 for fetching program instructions 34 from the memory 30 and providing the fetched program instructions to an instruction decoder circuit 50. The decoder circuit 50 decodes the fetched program instructions and generates control signals to control a processing circuit 60 to perform processing operations on the data values ​​held in storage elements of a register storage device 65, as specified by the decoded vector instructions. Figure 1 As shown, register storage device 65 may be formed from multiple different blocks. For example, a scalar register file 70 may be provided, which includes multiple scalar registers that can be specified by instructions, and similarly, a vector register file 80 may be provided, which includes multiple vector registers that can be specified by instructions.

[0053] like Figure 1 As shown, processor 20 can access array storage device 90. In Figure 1 In the example shown, array memory device 90 is provided as part of processor 20, but this is not required. In various examples, the array memory device may be implemented as any one or more of the following: architecturally addressable registers; non-architecturally addressable registers; high-speed temporary storage; and cache.

[0054] In one example implementation, processing circuitry 60 may include both vector processing circuitry and scalar processing circuitry. The general differences between scalar and vector processing are as follows: Vector processing may involve applying a single vector processing instruction to a data element of a data vector having multiple data elements at corresponding positions within the data vector. The processing circuitry may also perform vector processing to perform operations on multiple vectors within a two-dimensional array (which may also be referred to as a subarray) of data elements stored within the array storage device 90. Scalar processing effectively operates on a single data element rather than on a data vector. Vector processing can be used in instances where processing operations are performed on many different instances of data to be processed. In a vector processing arrangement, a single instruction can be applied to multiple data elements (of a data vector) simultaneously. This improves the efficiency and throughput of data processing compared to scalar processing.

[0055] The processor 20 may be arranged to process a two-dimensional array of data elements stored in the array storage device 90. In at least some examples, the two-dimensional array may be accessed in multiple directions as one-dimensional vector data elements. In one example embodiment, the array storage device 90 may be arranged to store one or more two-dimensional arrays of data elements, and each two-dimensional array of data elements may form a square array portion of larger or even higher-dimensional array data elements in memory.

[0056] Register storage device 65 also includes predicate register file 75. This stores predicate information (e.g., masking) for use in data processing operations (e.g., to mask out certain data elements of a vector so that these data elements are excluded from a particular processing operation).

[0057] Figure 2 An example of an architecture register 65 of processor 20, which may be provided in one example embodiment, is shown. The architecture registers (as defined in an instruction set architecture (ISA)) may include a set of scalar registers 95 (labeled X0 to X30 in this example) that serve as general-purpose registers for handling operations performed by scalar processing circuitry within processing circuitry 60. A set of predicate registers 100 for storing predicate information is also provided, such as the 16 registers P0 to P15 in this example.

[0058] Furthermore, the architecture registers available for selection by program instructions in the ISA supported by decoder 50 may include a number of vector registers 105 (labeled Z0 to Z31 in this example). Of course, it is not necessary to follow... Figure 2The number shown provides scalar, predicate, and / or vector registers, and other examples provide different numbers of registers that can be specified by program instructions. Each vector register can store vector operands comprising a variable number of data elements, where each data element can represent an independent data value. In response to vector processing (SIMD) instructions, processing circuitry can perform vector processing on the vector operands stored in the registers to produce a result. For example, vector processing can include channel-by-channel operations, where correspondence operations are performed on each element channel of one or more operand vectors to produce corresponding results for the elements of a result vector. When performing vector or SIMD processing, each vector register can have a certain vector length VL, where vector length refers to the number of bits in a given vector register. The vector length VL used in vector processing modes can be fixed or variable for a given hardware implementation. An ISA supported by processor 20 can support variable vector lengths, allowing different processor implementations to be selected to implement vector registers of different sizes, but the ISA can be vector length independent, such that instructions are designed so that program code can run correctly regardless of the specific vector length implemented on a given CPU executing the program.

[0059] Vector registers Z0 to Z31 can also be used as operand registers for storing vector operands, which provide input to the processing and accumulation operations performed by the processing circuit 60 on the two-dimensional array of data elements stored in the array storage device 90.

[0060] like Figure 2 As shown, the architecture registers also include a number of NA array registers 110 forming the previously mentioned array storage devices 90 (ZA0 to ZA(NA-1)). Each array register can be viewed as a set of register storage devices used to store a single 2D array data element (e.g., the result of processing and accumulation operations). However, processing and accumulation operations may not be the only operations that can use array registers. Array registers can also be used to store square arrays while performing row / column transposes of array structures in memory. When a program instruction refers to one of the array registers 110, it is referred to as a single entity using the array identifier ZAi, but some types of instructions (e.g., data transfer instructions) can also select a sub-part of the array (e.g., a horizontal / vertical group of elements) by defining an index value to select a portion of the array.

[0061] In practice, the physical implementation of the register storage device corresponding to the array register may include a certain number of NR array vector registers ZAR0 to ZAR(NR-1), such as Figure 2As shown. The array vector registers ZAR forming the array register storage device 110 can be a different set of registers from the vector registers Z0 to Z31 used for SIMD processing and vector inputs to array processing. Each array vector register ZAR can have a vector length VL, so each array vector register ZAR can store a 1D vector of length VL, which can be logically divided into a variable number of data elements. For example, if VL is 512 bits, this could be a set of 64 8-bit elements, 32 16-bit elements, 16 32-bit elements, 8 64-bit elements, or 4 128-bit elements. It should be understood that not all of these options need to be supported in a given specific implementation. By supporting variable element sizes, this provides flexibility in handling computations involving data structures of varying precision. To represent a 2D data array, the array vector registers ZAR0 to ZAR(NR-1) can be logically considered as a single entity assigning one of the array register identifiers ZA0 to ZA(NA-1), such that the 2D array is formed by elements extending within a single vector register corresponding to one dimension of the array and elements in another dimension of the array that spans multiple vector registers.

[0062] As discussed above, the processing circuit 60 is arranged to access the scalar register 70, the vector register 80, and / or the array memory device 90 under the control of instructions decoded by the decoder circuit 50. References will now be made to... Figure 3A Further details of the latter arrangement are described, which only provide an illustrative example of how the array storage device can be accessed, particularly considering access to a square 2D array within the array storage device.

[0063] In the illustrated example, the square 2D array within the array storage device 90 is arranged as an array 205 of n×n storage elements / locations 200, where n is an integer greater than 1. In this example, n is 16, which implies that the granularity of access to storage location 200 in any horizontal or vertical array direction is 1 / 16 of the total storage of the 2D array.

[0064] From the perspective of the processing circuit, an array of n×n locations can be accessed as n linear (one-dimensional) vectors in a first direction (e.g., the horizontal direction as shown) and n linear vectors in a second array direction (e.g., the vertical direction as shown). Therefore, from the perspective of the processing circuit 60, the n×n storage locations can be accessed as 2n linear vectors, each with n data elements.

[0065] Under the control of control circuitry 250, which communicates with at least processing circuitry 60 and optionally decoder circuitry 50, the array of storage locations 200 can be accessed by access circuitry 210, 220, column selection circuitry 230, and row selection circuitry 240.

[0066] Reference Figure 3B In the case of the example square 2D array designated "ZA1" (note that, as discussed below, more than one such 2D array may be provided in the array storage device 90, for example, ZA0, ZA1, ZA2, and so on), each of the n linear vectors in the first direction (such as the horizontal or "H" direction shown) has 16 data elements 0...F (represented in hexadecimal notation), and in this example, can be referenced as ZA1H0...ZA1H15. Stored in 256 entries (16×16 entries) of the array storage device 90 (i.e., Figure 3B The same basic data for ZA1 can alternatively be referenced as ZA1V0...ZA1V15 in a second direction (such as the vertical or "V" direction shown). It should be noted that, for example, data element 260 is item F referenced as ZA1H0, not item 0 of ZA1V15. It should be noted that the use of "H" and "V" does not indicate any spatial or physical layout requirements regarding the storage of the data elements comprising the array storage device 90, nor does it have any relation to whether the 2D array within the array storage device stores row or column data in any example application.

[0067] Figure 4A Example of outer product operation. The outer product operation takes two vectors A and B as input, which can be stored in a vector register file as discussed above. The result of the outer product operation is a matrix (e.g., a 2D array), denoted as... As shown in the figure, each data element in the output matrix is ​​obtained by multiplying the corresponding data elements in each input vector. For example, the top-left element in the result matrix is ​​obtained by multiplying element a0 of vector A and element b0 of vector B. When filling the result matrix, each data element in vector A is multiplied by each data element in vector B; therefore, the result of calculating the outer product of a vector with n elements and a vector with m elements is an n×m matrix.

[0068] Figure 4B This demonstrates matrix multiplication. Specifically, Figure 4B The diagram illustrates the operation involving multiplying two matrices C and D (which may, for example, be stored in vector registers (e.g., a row or a column is held in each register) or in an array memory device circuit) to produce a matrix CD. As can be seen from the diagram, multiplying two n×n matrices results in an n×n matrix (more generally, multiplying an n×k matrix by a k×m matrix will yield an n×m matrix).

[0069] There are several ways to compute the elements of the output matrix CD, but the technique generally used by processors is to perform multiple outer product operations and sum the results together. For example, to execute... Figure 4BIn the matrix multiplication example shown, the processing circuit can first calculate the outer product of the leftmost column i of matrix A and the top row w of matrix B to produce 16 outer product results, and use these results to fill a 4×4 array in the array storage device. The processing circuit can then calculate the outer product of the next column j of matrix A and the next row x of matrix B to produce another 16 outer product results added to the already stored outer product results. This process can then be applied to the last two pairs of vectors ( and Repeat this process to produce the final result CD.

[0070] Therefore, it can be seen that matrix multiplication can be performed by executing multiple outer product operations and summing the results; for example, this can be done by executing one or more multi-outer product instructions. It should be noted that the order of multiplication of the vector pairs is not limited to the order described above; the outer product can be calculated in any order. Furthermore, the outer product operations do not need to be executed sequentially.

[0071] Based on the techniques described herein, apparatus and methods are provided for performing outer product operations on complex vectors. As previously mentioned, many computational tasks require complex numerical arithmetic, such as in digital signal processing (DSP) algorithms, 5G communication infrastructure applications, and high-performance computing (HPC) applications. Complex number multiplication is typically required, and given the computational resource demands generally required to perform such complex number multiplication operations, it is desirable to provide techniques for accelerating these multiplication operations, thereby improving performance / throughput. By supporting the performance of outer product operations using complex numbers, performance can be significantly improved, for example, in cases requiring a large number of complex numerical multiplication operations.

[0072] According to the techniques described herein, one or more variations of complex numerical outer product instructions are provided for execution by a data processing apparatus. Such complex numerical outer product instructions specify a first source vector operand and a second source vector operand, each comprising a plurality of source data elements, wherein each source data element is a complex number formed by real and imaginary parts. Furthermore, the complex numerical outer product instruction specifies a two-dimensional array of data blocks within an array storage device 90 as the destination operand. In response to such a complex numerical outer product instruction, processing circuitry 60 performs an outer product operation using the source data elements of the two source operands to produce a plurality of result data elements. Each result data element is a complex number formed by real and imaginary parts, and each real and imaginary part of each result data element is associated with a data block in the specified two-dimensional array of data blocks and is used to update the value of the associated data block. For example, an accumulation or subtraction variation may be specified such that each real and imaginary part of each result data element is added to or subtracted from the value currently stored in the associated data block.

[0073] In the first variant of the complex-valued outer product instruction, a normal outer product operation can be specified, resulting in a one-to-one correspondence between each part of each resulting data element and the associated data block in the two-dimensional array. In the alternative or additional variant of the complex-valued outer product instruction, the outer product sum operation can be specified by the instruction, and in this event, the real parts (and similarly imaginary parts) of multiple resulting data elements can be associated with the same data block in the two-dimensional array and used to update the value in that data block.

[0074] By specifying a single instruction, the post-processing circuitry performs an outer product operation on complex vectors, significantly improving performance. Prior to this technique, multiple vector instructions were typically required to perform multiplication on complex vectors. Given the limitations of the instruction encoding space, the judicious use of instructions within that space is crucial. The format of the instruction encoding and the function represented by each instruction are defined according to the Instruction Set Architecture (ISA). An ISA represents an agreement between the hardware manufacturer that produces the processing hardware for a specific implementation of a given processor and the software developer who writes program code to execute on that hardware, ensuring that program code written according to the ISA will run correctly on hardware that supports the ISA.

[0075] When designing an ISA, significant design challenges may arise in determining the set of processing operations to be supported in the ISA and the encoding of the instructions representing those operations. In principle, a wide variety of processing operations may be helpful in supporting certain program applications, but within the available encoding space, it is unlikely that every feasible data processing operation might be useful to a particular programmer. There may be limitations on the number of bits available to encode each instruction because increasing the instruction bit width incurs additional circuit area and power consumption, regardless of where the instruction is stored within the processor or transmitted via wired processing paths between logic elements. To limit hardware and power costs, the instruction bit width may need to be selected, which, when considering the need to encode operand values ​​via register specifiers and / or immediate values, makes the arithmetic code space insufficient to represent every possible data processing operation that might be required. Therefore, design decisions must be made regarding which operator sets most need to be supported, and any operation that cannot be supported by a single instruction must be executed using multiple instruction sets with equivalent functionality. Thus, design decisions made by ISA designers when planning the instruction encoding of an ISA can have a significant impact on the actual performance achieved by the processing hardware when executing a particular program, depending on whether the instruction is available to support the required operations.

[0076] Therefore, when the ISA is subsequently implemented on hardware, any technique that improves the efficiency of representing a given set of operations within the instruction set's code space is extremely valuable for improving overall performance. If coding efficiency can be improved, even by saving just one bit of code space so that it can be reused for other purposes (e.g., adding an extra operand bit, and thus doubling the number of different processing operations that can be represented), it will be extremely valuable because the increased number of supported processing operation types can then be utilized by the programmer to perform more operations in a single instruction to improve processing performance. Thus, even a seemingly small improvement in coding efficiency, resulting in only one extra bit of available code space, actually has a significant impact on the performance implemented by the processing device. Providing complex outer product instructions within the ISA has been found to significantly improve coding efficiency. Furthermore, providing such complex outer product instructions within the ISA can lead to significant performance improvements because the number of instructions required to perform the desired function is reduced.

[0077] Secondly, in addition to the aforementioned benefits of using a single instruction, the instructions defined in this paper also allow for the performance of outer products on complex vectors and the accumulation of the results into a two-dimensional array. This enables efficient use of processing resources and provides a highly flexible approach. For example, such an approach easily allows for the merging of accumulation or subtraction operations during computation. This is particularly beneficial in many example scenarios requiring the performance of numerous complex multiplications. For instance, by using the same destination operand (i.e., the same two-dimensional array of data blocks) for multiple instances of the complex numerical outer product instruction, this provides a particularly efficient mechanism for performing matrix multiplication operations using complex vectors.

[0078] According to the technique described herein, within each source vector operand, the real and imaginary parts of the individual source data elements are interleaved with each other. This allows the source data elements required by various computational blocks within the processing circuit to be logically grouped and provided to these computational blocks, resulting in a particularly efficient implementation. Furthermore, within at least one dimension of the two-dimensional array forming the destination operand, the real and imaginary parts of multiple result data elements are associated with data blocks such that the real and imaginary parts of the result data elements are interleaved. This similarly improves the efficiency of the implementation by reducing the routing complexity between computational blocks and associated data blocks within the two-dimensional array.

[0079] Now use Figure 5 block diagram and Figure 6 The flowchart, implemented using a specific example, illustrates the operations performed by the processing circuit when executing a complex value outer product instruction. For example... Figure 5As shown, vector register file 80 provides multiple vector registers that can be used to store vectors of data elements. Complex value outer product instructions are arranged to identify a first source vector operand 300 and a second source vector operand 320, wherein each source vector operand includes multiple source data elements, and each source data element is a complex number formed by real and imaginary parts. As previously discussed, in some implementations, the complex value outer product instructions may also be able to specify one or more predicate registers 325 within predicate register file 75, each specified predicate register being associated with one of the source vector operands and used to indicate whether any data elements in the data elements of that source vector operand should be excluded from the data processing operation to be performed.

[0080] like Figure 6 As illustrated, when a complex value outer product instruction (or complex value outer product sum instruction) is encountered, it is decoded by decoder circuit 50 at step 400 to generate a control signal to be sent to processing circuit 60. This control signal identifies the type of outer product operation to be performed and also identifies the vector registers 300 and 320 that provide the source data elements for the first and second source operands, and any predicate register 325 that provides predicate information. At step 405, the predicate information is evaluated to determine whether any source data elements should be excluded from the outer product operation (or outer product sum operation).

[0081] At step 410, the input operation circuitry 340, provided in association with the processing circuitry 60, selects an appropriate input for each dot product circuit 350 provided by the processing circuitry 60. This selection is made according to a variant of the outer product instruction to be executed. (See below for further details.) Figure 11 The discussion focuses on the input operation circuitry used in one example implementation, but in one example implementation, it is possible to invert the real and / or imaginary parts of one or more source data elements, and also to reverse the order of the real and imaginary parts of one or more source data elements as needed, to ensure that the dot product circuit 350 subsequently generates the appropriate result data element according to the type of outer product operation being performed.

[0082] At step 415, a dot product operation is then performed using dot product circuit 350 to generate multiple result data elements, each consisting of a real part and an imaginary part. If any predicate information indicates that one or more source data elements should not be operated on, the dot product circuit with excluded source data elements can be used. This dot product circuit can be configured not to perform a dot product operation using the excluded source data elements, or it can be configured to operate normally, but in which case the result data elements based on the excluded source data elements are subsequently prevented from updating the contents of the two-dimensional array 380 within the array storage device 90.

[0083] Subsequently, at step 420, each real and imaginary part of each resulting data element (except for either excluded by predicate information) is used to update the value in each associated data block of the two-dimensional array 380. In one example embodiment, this is achieved using an accumulator circuit 360 that accumulates the resulting data element with existing values ​​in the two-dimensional array to generate an updated value, which is stored within the two-dimensional array 380 using an array update circuit 370. If a variant of the complex numerical extra product instruction that requires subtracting the result from the existing contents of the two-dimensional array is used, in one example embodiment, this is achieved by appropriately manipulating the input by the input operation circuit 340 before providing the input to the dot product circuit 350, such that the resulting data element generated by the dot product circuit 350 can subsequently be added to existing values ​​within the two-dimensional array by the accumulator circuit 360 to generate an updated value corresponding to the value generated by the specified subtraction operation.

[0084] In one example implementation, the processing circuitry uses multiple instances of dot product circuits to perform complex-valued outer product operations. A bidirectional dot product circuit 450 is used in... Figure 7 The diagram illustrates this schematically, and the execution also... Figure 7 The calculation is illustrated in the example. As can be seen, the value in the destination data block Z is updated by adding it to x1*y1 and x2*y2 (note that the accumulator circuit (not in the example)). Figure 7 (As explicitly shown in the diagram) the output of the bidirectional dot product circuit will be used to accumulate the existing data value of data block Z. To reduce the complexity of the following diagrams, such an accumulation circuit has been omitted from these diagrams, but it should be understood that this accumulation circuit will be provided in conjunction with various dot product circuits to perform the required accumulation of the dot product output with the corresponding existing data value.

[0085] like Figure 8 As shown, a pair of such bidirectional dot product circuits 455 and 460 can be used to generate the real and imaginary parts of the resulting data element "c" generated by multiplying a first complex number "a" by a second complex number "b". As can be seen, each dot product circuit 455 and 460 receives the real and imaginary parts of two complex numbers "a" and "b". The first dot product circuit 455 inverts the imaginary part of the complex number "b" by performing... Figure 8 The updated real part (c_re) of the resulting data element "c" is generated by the calculation shown below element 455. Similarly, since the dot product circuit 460 receives the real and imaginary parts of the complex number "b" in reverse order, the dot product circuit performs... Figure 8 The calculation below element 460 generates the updated imaginary part (c_im) of the resulting data element "c" (as previously mentioned, the required accumulation circuitry is not explicitly shown in the figure). The real and imaginary parts of the calculated result can thus be accumulated into the corresponding data block of the two-dimensional array to update any existing real and imaginary values ​​stored within that data block.

[0086] like Figure 9 The diagram illustrates that, Figure 8 The dot product circuits can be replicated as needed to provide an associated computation block for each data block within the two-dimensional array 490, wherein each dot product circuit receives the real and imaginary parts of a source data element from a first source vector register 470 and the real and imaginary parts of a source data element from a second source vector register 480. For example... Figure 9 As shown, predicate registers 475 and 485, if needed, can be provided associated with each source vector register, specifying predicate information for each data element. Figure 9 In the example shown, it can be seen that each source vector contains two data elements, and therefore provides two terms containing predicate information for each source vector. Furthermore, each source data element includes a real part and an imaginary part. This can be seen from... Figure 9 As seen in the diagram, each of the eight dot product circuits performs a dot product operation, resulting in four updated result data elements, each of which includes a real part and an imaginary part.

[0087] Figure 10 An input operation circuit 510, which can be associated with each pair of dot product circuits 500, 505, is schematically illustrated. This dot product circuit generates the real and imaginary parts of the resulting data elements for updating values ​​in corresponding data blocks within a two-dimensional array. In this example, the input operation circuit 510 is used to perform a previously referenced... Figure 8 The operations required for the computation discussed, and therefore the imaginary part of the second data element b1 is inverted before being provided to the dot product circuit 500, and the real and imaginary parts of the second data element b1 are swapped before being provided to the dot product circuit 505.

[0088] In a more general implementation, the input operation circuitry can be organized such that it can use the same basic dot product circuitry to support the execution of multiple different complex-valued outer product instruction variants. One such implementation is achieved through… Figure 11The example is illustrated below. As can be seen, the input operation circuit 520, provided in association with the first dot product circuit used to calculate the real part of the resulting data element, produces an initial and inverted version of the real and imaginary parts of the input data element (the inverted version is produced using inverters 535 and 545), wherein the multitasking circuits 540 and 550 then select the appropriate real and imaginary part values ​​to be passed to the associated dot product circuit according to the variant of the instruction being executed. The input operation circuit 530, provided in association with the second dot product circuit in a pair of dot product circuits (which is used to produce the imaginary part of the resulting data element), operates in a similar manner, also producing an initial and inverted version of the real and imaginary parts of the input data element (the inverted version is produced using inverters 555 and 565). However, the order of the real and imaginary parts of the input data element is reversed by the input operation circuit 530. Similar to input operation circuit 520, input operation circuit 530 then uses multitasking circuits 560, 570 to select appropriate real and imaginary values ​​to pass to the associated dot product circuit according to the variant of the instruction being executed.

[0089] In addition to previous references Figure 8 In addition to the variants discussed, using Figure 11 The input operation circuit can therefore also implement a reference. Figures 12A to 12C Any of the instruction variants illustrated schematically. Although Figure 8 The arrangement shown allows for the execution of complex numerical outer products with accumulation operations (e.g., when...). Figure 8 The dot product circuit is as follows Figure 9 (as shown, copied), but as Figure 12A As shown, the same pair of dot product circuits can be used to allow the execution of complex numerical outer products with subtraction operations, and specifically, dot product circuits 455 and 460 will perform... Figure 12A The calculation shown below the block is an inversion performed by inverters 600, 605, and 610, which swaps the real and imaginary parts before providing the data element "b" to the second dot product circuit 460.

[0090] Similarly, such as Figure 12B As shown, by using Figure 11 The input operation circuitry also enables the execution of complex outer products with accumulation operations, where the operand "a" is conjugate. As previously discussed, the conjugation of a complex number is formed by inverting the sign of the imaginary part. The effective conjugation of operand "a" is... Figure 12B In the example, this is actually achieved by performing appropriate operations on the operand "b". Specifically, as shown, the imaginary part of operand "b" is not inverted before being provided to the dot product circuit 455 (and...). Figure 8The method used is the opposite of that used in the previous example), and the real part of operand "b" is inverted by inverter 610 before being provided to dot product circuit 460 (similar to the method used in the previous example). Figure 8 The method used is the opposite of that used in [the previous example]. As a result, the two dot product circuits 455 and 460 perform in [the following example]. Figure 12B The calculations are shown below the components in the diagram.

[0091] In addition, such as Figure 12C As shown, by using Figure 11 The input operation circuitry also enables the execution of complex numerical outer products with subtraction, where the operand "a" is conjugate. Similarly, the effective conjugate of operand "a" is... Figure 12C In the example, this is actually achieved by performing appropriate operations on the operand "b". Specifically, as shown, the real and imaginary parts of operand "b" are inverted by inverters 600 and 615 before being provided to the dot product circuit 455, and the imaginary part of operand "b" is inverted by inverter 605 before being provided to the dot product circuit 460. As a result, the two dot product circuits 455 and 460 perform... Figure 12C The calculations are shown below the components in the diagram.

[0092] In one exemplary implementation, each dot product circuit required to perform the above operations can be implemented by reusing existing multiplier-based circuitry already provided by the device to support the performance of outer product operations with respect to real number vectors. Through this illustrative example, Figure 13 A 4×4 two-dimensional array 670 of data blocks is shown, in which a multiply-accumulate circuit (“P”) is provided associated with each data block. An outer product operation can then be performed on two source vector operands 650, 660, each comprising four real-valued data elements, to generate an updated value for the 4×4 two-dimensional array 670 of data blocks. If needed, predicate registers 655, 665 can be provided for each source vector operand, as each vector comprises four data elements, and each predicate register can provide four predicate information items.

[0093] like Figure 13 The diagram schematically illustrates that the multiply-accumulate circuit 675 can be combined with adder circuits to combine the outputs of these circuits to implement... Figure 9 Each bidirectional dot product circuit is schematically illustrated in the diagram. (By comparison...) Figure 13 and Figure 9 As can be seen, when performing complex-valued outer product operations using the same circuitry, two vectors with two complex-valued data elements can be provided as input, instead of two vectors with four real-valued data elements. This provides a particularly efficient implementation because it allows the same basic circuitry to be used to perform outer product operations on both real and complex vectors simply by appropriately reconfiguring the basic circuitry blocks as needed.

[0094] In one exemplary implementation, the apparatus described herein can also perform outer product sum operations related to complex vectors, and specifically, the apparatus can be arranged to execute complex numerical outer product sum instructions. Similarly, dot product circuits can also be used for this purpose. Figure 14 An example of an octagonal dot product circuit is provided, which can perform a dot product operation on two vectors of real data elements, each vector comprising eight real data elements. For example... Figure 15 As shown, a pair of such circuits can also be used to produce the real and imaginary parts of the resulting data elements based on the four data elements of the first vector operand and the four data elements of the second vector operand, each of these data elements being a complex number and therefore having both a real and an imaginary part. Thus, a pair of eight-way dot product circuits is used to compute the complex-valued four-way dot product. Each of the dot product circuits 705 and 710 therefore performs the operation in... Figure 15 The calculations shown below the components are in combination with an accumulation circuit, which, as previously mentioned, is not explicitly shown in the figure.

[0095] Therefore, when such an array of dot product circuits is used in conjunction with a two-dimensional array 740 (such as...), Figure 16 As shown, an outer product sum operation can be performed on source vector operands 720 and 730 of two complex numerical data elements, and predicate registers 725 and 735 can also be specified in association with each source vector operand if needed. Figure 16 In the specific example shown, each source vector operand comprises eight data elements, and therefore each predicate register 725, 735 provides eight predicate information items. The resulting data elements are then accumulated within the two-dimensional array 740 shown.

[0096] Figure 17 A block of circuit 750 is schematically illustrated, comprising two instances of octagonal dot product circuits 705' and 710', and associated input operation circuitry for reordering and inverting relevant portions of the source data elements of one of the source vector operands input to the dot product circuit. It should be understood that this circuit can be replicated four times for implementation. Figure 16 The functionality shown.

[0097] Despite Figures 15 to 17 In the examples, it is assumed that each dot product circuit uses four data elements from each source operand, but this is not a hard requirement, and it should be understood that in other examples, each dot product circuit may consume a different number of source data elements. Generally speaking, when performing an outer product sum operation, the size of the source data elements is smaller than the size of the result data elements, and the number of complex numerical products generated is given by the ratio of the element-size widths of the result data elements and the input data elements. Figures 15 to 17In the example, the resulting data element has four times the width of the input data element, and thus generates four complex value results.

[0098] Figure 18 Examples of emulator implementations that can be used are illustrated. While the examples described above implement the invention with respect to apparatus and methods for operating specific processing hardware that supports the relevant technology, it is also possible to provide an instruction execution environment implemented using a computer program, based on the examples described herein. Such computer programs are often called emulators because they provide a software-based implementation of a hardware architecture. Types of emulator computer programs include simulators, virtual machines, models, and binary translators (including dynamic binary translators). Generally, an emulator implementation can run on a host processor 815 that optionally runs a host operating system 810 and supports an emulator program 805. In some arrangements, there may be multiple layers of emulation between the hardware and the provided instruction execution environments and / or multiple dissimilar instruction execution environments provided on the same host processor. Historically, powerful processors have been required to provide emulator implementations that execute at a reasonable speed, but this approach may be justified in certain situations, such as when it is desirable to run code native to another processor for compatibility or reuse reasons. For example, an emulator implementation may provide an instruction execution environment with additional functionality not supported by the host processor hardware, or provide an instruction execution environment generally associated with a different hardware architecture. A review of the simulation is given in "Some Efficient Architecture Simulation Techniques" (Robert Bedichek, Winter 1990, USENIX Conference, pp. 53-63).

[0099] Where examples have been described previously with reference to specific hardware architectures or features, equivalent functionality can be provided in a simulated implementation through suitable software architectures or features. For example, specific circuitry can be provided as computer program logic in a simulated implementation. Similarly, memory hardware (such as registers or caches) can be provided as software data structures in a simulated implementation. Furthermore, the physical address space for accessing memory 30 in hardware device 10 can be simulated as a virtual address space mapped by simulator 805 to the virtual address space used by host operating system 810. One or more of the hardware elements mentioned in the previously described examples exist in an arrangement on host hardware (e.g., host processor 815), and some simulated implementations may utilize the host hardware where appropriate.

[0100] The simulator program 805 may be stored on a computer-readable storage medium (which may be a non-transitory medium) and provides a virtual hardware interface (instruction execution environment) to the target code 800 (which may include applications, operating systems, and virtual machine monitoring programs), the virtual hardware interface being identical to the hardware interface of the hardware architecture modeled by the simulator program 805. Therefore, the program instructions of the target code 800 can be executed within the instruction execution environment using the simulator program 805, enabling the host computer 815, which does not actually possess the hardware features of the device 10 discussed above, to emulate these features. The simulator program may include: processing program logic 820 for emulating the behavior of the processing circuit 60; instruction decoding program logic 825 for emulating the behavior of the instruction decoder circuit 50; and array memory device emulation program logic 822 for maintaining data structures to emulate the array memory device 90. Therefore, the techniques described herein... Figure 18 The example can be executed in software using the simulator program 805.

[0101] In this application, the term "configured as..." is used to mean that the elements of the device have a configuration capable of performing the defined operation. In this context, "configuration" means the arrangement or manner of interconnection of hardware or software. For example, the device may have dedicated hardware that provides the defined operation, or a processor or other processing device may be programmed to perform the function. "Configured as" does not mean that the elements of the device need to be changed in any way to provide the defined operation.

[0102] While exemplary embodiments of the invention have been described in detail herein with reference to the accompanying drawings, it should be understood that the invention is not limited to these precise embodiments, and various changes, additions, and modifications can be made therein by those skilled in the art without departing from the scope and spirit of the invention as defined in the appended claims. For example, the features of the independent claims can be combined with the features of the appended claims in various ways without departing from the scope of the invention.

Claims

1. An apparatus, the apparatus comprising: Processing circuitry, the processing circuitry being used to perform vector operations; An instruction decoder circuit is used to decode instructions from an instruction set to control the processing circuit to perform the vector operation specified by the instructions; and An array storage device includes storage elements for storing data blocks, the array storage device being arranged as at least one two-dimensional array of data blocks, and the processing circuit being able to access the at least one two-dimensional array of data blocks when the vector operation is performed. in: The instruction set includes a complex numerical outer product instruction specifying a first source operand, a second source operand, and a destination operand, wherein each of the first and second source operands is a vector operand comprising multiple source data elements, each source data element being a complex number formed by real and imaginary parts, and the destination operand identifies a given two-dimensional array of data blocks within the array storage device; and The processing circuit, in response to the complex value outer product instruction, performs an outer product operation using the source data elements of the first source operand and the source data elements of the second source operand to produce a plurality of result data elements, wherein each result data element is a complex number formed by real and imaginary parts, and wherein each real and each imaginary part of each result data element is associated with a data block in the given two-dimensional array of data blocks and is used to update the value of the associated data block.

2. The apparatus of claim 1, wherein both the first source operand and the second source operand are configured to interleave the real parts of the plurality of source data elements with the imaginary parts of the plurality of source data elements.

3. The apparatus of claim 1 or claim 2, wherein, within at least one dimension of the given two-dimensional array of the data block, the real and imaginary parts of a plurality of resulting data elements are associated with the data block such that the real and imaginary parts of the plurality of resulting data elements are interleaved.

4. The apparatus according to any of the preceding claims, wherein: The processing circuitry includes a dot product circuitry associated with each data block in the given two-dimensional array of data blocks; and The dot product circuit associated with a given data block is arranged to perform a dot product operation using the real and imaginary parts of at least one source data element of the first source operand and at least one source data element of the second source operand to generate the required portion of at least one result data element to be used to update the value of the given data block.

5. The apparatus of claim 4, further comprising input operation circuitry associated with each data block in the given two-dimensional array of data blocks, wherein the input operation circuitry associated with the given data block is controlled according to the complex numerical outer product instruction to perform input operation operations to adjust how the real and imaginary parts of at least one source data element are provided to the dot product circuitry associated with the given data block, thereby ensuring that the execution of the dot product operation generates the required portion of the at least one result data element to be used to update the value of the given data block.

6. The apparatus of claim 5, wherein the input operation circuitry comprises at least one of the following: An inverter circuit, the inverter circuit being used to invert the value of at least one portion of the at least one source data element; and A reordering circuit for swapping the order of the real and imaginary parts of the at least one source data element.

7. The apparatus of claim 5 or claim 6, wherein the apparatus supports multiple variants of the complex-valued outer product instruction, and the input operation performed by the input operation circuitry associated with the given data block ensures, according to the variant of the complex-valued outer product instruction being executed, that the dot product operation performed by the dot product circuitry associated with the given data block will generate the required portion of the at least one resulting data element to be used to update the value of the given data block.

8. The apparatus of claim 7, wherein the input operation circuitry associated with the given data block is arranged to generate a plurality of candidate variants of the real and imaginary parts of the at least one source data element, and the input operation circuitry further includes a multiplier circuitry controlled according to the variants of the complex-valued outer product instruction being executed, to select which candidate variants of the candidate variants are provided to the dot product circuitry associated with the given data block.

9. The apparatus of claim 7 or claim 8, wherein the plurality of variations of the complex numerical outer product instruction comprises: A non-conjugate variant, wherein when performing the outer product operation, the complex number forming the source data elements of both the first source operand and the second operand is used; and at least one conjugate variant, wherein when performing the outer product operation, the conjugate of the complex number of the source data elements forming at least one of the first source operand and the second source operand is used.

10. The apparatus according to any one of claims 7 to 9, wherein the plurality of variations of the complex numerical outer product instruction comprises: An accumulative variant, in which each real and imaginary part of each resulting data element is added to the current value of the associated data block to form the updated value of the associated data block; And a subtraction variant, wherein each real and each imaginary part of each resulting data element is subtracted from the current value of the associated data block to form the updated value of the associated data block.

11. The apparatus according to any one of claims 5 to 10, wherein the input operation circuitry associated with the given data block is arranged to operate on at least one source data element of only one of the first source operand and the second source operand to be used by the dot product circuitry associated with the given data block.

12. The apparatus according to any of the preceding claims, wherein: The complex value outer product instruction includes the complex value outer product instruction; The real parts of multiple result data elements have the same associated data block within the two-dimensional array of data blocks, and the processing circuit is configured to combine the real parts of the multiple result data elements to update the value of the same associated data block; and The imaginary parts of multiple result data elements have another identical associated data block within the two-dimensional array of data blocks, and the processing circuit is configured to combine the imaginary parts of the multiple result data elements to update the value of the other identical associated data block.

13. The apparatus according to any of the preceding claims, when subordinate to claim 4, wherein: The processing circuitry is arranged to provide a plurality of multiplier-based circuits, which are arranged to perform a real cross product operation using the real numbers in response to a real cross product instruction for a first vector and a second vector of real numbers, such that each multiplier-based circuit generates a real result data element within the resulting real result data element matrix when performing the real cross product operation; and The dot product circuit associated with each data block in the given two-dimensional array of data blocks is arranged to reuse multiple multiplier-based circuits among the multiple multiplier-based circuits, and a combination circuit for combining the outputs from the multiple multiplier-based circuits, in response to the complex value outer product instruction, to generate the required portion of the at least one resulting data element to be used to update the value of the data block.

14. The apparatus according to any of the preceding claims, wherein the complex value outer product instruction includes at least one predicate operand, the at least one predicate operand being configured to enable one or more source data elements to be identified as excluded from the outer product operation.

15. A method, the method comprising: Vector operations are performed using processing circuitry; Decode instructions from the instruction set to control the processing circuitry to perform the vector operation specified by the instructions; as well as An array storage device is employed, the array storage device including storage elements for storing data blocks, the array storage device being arranged as at least one two-dimensional array for storing data blocks, and the processing circuit being able to access the at least one two-dimensional array of data blocks when the vector operation is performed. in: The instruction set includes a complex numerical outer product instruction specifying a first source operand, a second source operand, and a destination operand, wherein each of the first and second source operands is a vector operand comprising multiple source data elements, each source data element being a complex number formed by real and imaginary parts, and the destination operand identifies a given two-dimensional array of data blocks within the array storage device; and The method includes: in response to the complex numerical outer product instruction, employing the processing circuitry to perform an outer product operation using the source data elements of the first source operand and the source data elements of the second source operand to produce a plurality of result data elements, wherein each result data element is a complex number formed by real and imaginary parts, and wherein each real and each imaginary part of each result data element is associated with a data block in the given two-dimensional array of data blocks and is used to update the value of the associated data block.

16. A computer program for controlling a host data processing device to provide an instruction execution environment, the computer program comprising: The processing logic is used to perform vector operations; Instruction decoding program logic, which is used to decode instructions from the instruction set in order to control the processing program logic to perform the vector operation specified by the instruction; and An array storage device simulation program logic is used to simulate an array storage device, the array storage device including storage elements for storing data blocks, the array storage device being arranged as at least one two-dimensional array for storing data blocks, and the processing program logic being able to access the at least one two-dimensional array of data blocks when the vector operation is executed. in: The instruction set includes a complex numerical outer product instruction specifying a first source operand, a second source operand, and a destination operand, wherein each of the first and second source operands is a vector operand comprising multiple source data elements, each source data element being a complex number formed by real and imaginary parts, and the destination operand identifies a given two-dimensional array of data blocks within the array storage device; and The processing logic, in response to the complex numerical outer product instruction, performs an outer product operation using the source data elements of the first source operand and the source data elements of the second source operand to produce a plurality of result data elements, wherein each result data element is a complex number formed by real and imaginary parts, and wherein each real and each imaginary part of each result data element is associated with a data block in the given two-dimensional array of data blocks and is used to update the value of the associated data block.

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