Method for operating flying capacitor multilevel converter

Abstract

The invention relates to a method for operating a flying capacitor multi-level converter (1), comprising at least one half-bridge (HB1 to HB3), which comprises an upper branch having a plurality of semiconductor switches (H1, H2, H (N-2), H (N-1)) connected in series and a lower branch having a plurality of semiconductor switches (L1, L2, L (N-2), L (N-1)) connected in series, the upper branch and the lower branch being connected in series in order to connect phases (P1, P2,..., P2). P3) are connected to each other at a connection point (VP), in which a pair of semiconductor switches (H1, H2, H (N-2), H (N-1), L1, L2, L (N-2), L (N-1)) from the upper and lower branches is bridged at the terminals of the pair facing away from the connection point (VP) by a respective capacitor (CFC1, CFC2, CFC (N-2), CDC) or by a respective series circuit of capacitors (CFC1, CFC2, CFC (N-2), CDC) at the same distance from the connection point (VP), the semiconductor switches (H1, H2, H (N-2), H (N-1), L1, L2, L (N-2), L (N-1)) are driven with a pulse width modulated signal at a switching frequency (fsw), the switching frequency (fsw) being briefly increased in the event of an overload.

Description

Technical Field

[0001] This invention relates to a method for operating a flying capacitor multilevel converter. Background Technology

[0002] Flying capacitor multilevel converters are known in the prior art. These converters are equipped with so-called flying capacitors, the required capacitance value of which affects the converter's power density and cost. If the capacitors are chosen too small, voltage fluctuations (also known as voltage ripple) across these capacitors will increase, leading to a rise in the voltage load on the semiconductor switches. Therefore, if the capacitors are chosen too small, excessively high voltage fluctuations across the individual capacitors in the flying capacitors will affect the converter's reliability.

[0003] To achieve reliable design of flying capacitor multilevel converters, the capacitance value of the capacitor must be appropriately selected to ensure that its voltage changes only slightly during operation, i.e., low voltage fluctuation. If this voltage fluctuation is too large, the semiconductor switches will experience a decrease in reliability due to the higher voltage load. Therefore, existing solutions typically determine the minimum required capacitance based on the maximum possible current.

[0004] The paper "An Optimized Phase Shifted Pulse Width Modulation (PWM) for Flying Capacitor Multilevel Converter" by KHAN WAQAR A et al., presented at the 2019 IEEE Energy Conversion Conference & Exhibition (ECCE), IEEE (Institute of Electrical and Electronics Engineers), 29. September 2019 (2019-09-29), pp. 5104-5108, XP033666348, DOI:10.1109 / ECCE.2019.8912530, describes a novel modulation method for reducing voltage ripple in the flying capacitor (FC) of a flying capacitor multilevel converter (FCML). This method is based on an improvement to the conventional phase-shifted pulse width modulation (PSPWM) method. Compared to the conventional PSPWM method, the proposed method reduces the required capacitance while maintaining the same voltage ripple constraint. A variable frequency phase-shift pulse width modulation (VF-PSPWM) method is proposed, which adjusts the frequency of the carrier signal according to the amplitude of the load current. Reduced voltage fluctuations decrease the need for capacitors in the design, thereby enabling designs with higher power density. Summary of the Invention

[0005] The purpose of this invention is to propose a novel operating method for a flying capacitor multilevel converter.

[0006] This objective is achieved by a method having the features of claim 1.

[0007] Advantageous embodiments of the present invention are covered by the dependent claims.

[0008] A flying capacitor multilevel converter includes at least one half-bridge comprising an upper branch with multiple series-connected semiconductor switches and a lower branch with multiple series-connected semiconductor switches. The upper and lower branches are interconnected at a connection point for connecting phases. Pairs of corresponding semiconductor switches from the upper and lower branches are bridged by corresponding capacitors or series circuits of capacitors at terminals opposite to the connection point, at the same distance from the connection point. In the method of the invention, the semiconductor switches of the flying capacitor multilevel converter are driven by a pulse-width modulated signal having a certain switching frequency, wherein, in the event of an overload, the switching frequency is briefly increased. The duration of the brief overload depends on the overload characteristics. Typical overload characteristics range from milliseconds to seconds.

[0009] By employing the solution according to the present invention, overload characteristics with high overload can be achieved even without over-specification design of the converter.

[0010] A significant advantage of the solution according to the invention is the ability to reduce the capacitance of the required capacitor. For example, when doubling the switching frequency to achieve twice the overload, the following advantages can be obtained:

[0011] • The required capacitor is halved.

[0012] • Capacitor size can be halved (e.g., scalable via MLCCs (multilayer ceramic capacitors)).

[0013] • Capacitor costs halved

[0014] • It halve the space required, thereby increasing power density and reducing the probability of failure due to the reduced number of components.

[0015] • Easy to implement (the switching frequency increases linearly with the actual value of power or phase current from the normal operating point, for example, under rated load).

[0016] • For extremely short-duration but high-amplitude overloads, it can be achieved without over-specification design of the converter.

[0017] • It can achieve extremely short-term but high-amplitude overload characteristics without requiring the converter to be designed beyond specifications.

[0018] According to the present invention, a rated switching frequency is used at the normal operating point, and in the case of overload, the switching frequency is increased from the normal operating point, for example, linearly, because the switching frequency participates in the calculation of the capacitance required for the flying capacitor in a linear manner.

[0019] In one implementation, the normal operating point is set to the rated power, but it can also be adjusted to other positions.

[0020] According to the present invention, the switching frequency is kept constant or maintained constant below the normal operating point.

[0021] In one embodiment, all pairs of semiconductor switches from the upper and lower branches are bridging each other at the terminals of the pair away from the connection point by a corresponding capacitor or a corresponding series circuit of a capacitor at the same distance from the connection point. The two outermost semiconductor switches of the entire half-bridge are connected together at their terminals away from the connection point to a grounded DC bus capacitor or a series circuit of a grounded DC bus capacitor and to the supplied DC voltage.

[0022] In one embodiment, the flying capacitor multilevel converter includes at least three half-bridges for supplying three phases. According to the invention, each phase is connected to an inductor and a filter unit respectively to ensure electromagnetic compatibility.

[0023] In one implementation, the semiconductor switch is implemented as an insulated gate bipolar transistor (IGBT) or a field-effect transistor, particularly a metal-oxide-semiconductor field-effect transistor (MOSFET) or a gallium nitride high electron mobility transistor (GaNHEMT). Attached Figure Description

[0024] The features, characteristics, and advantages of the present invention described above, as well as the means of achieving these advantages, will become more apparent from the following detailed description of the embodiments and the accompanying drawings. The figures show:

[0025] Figure 1 This is a schematic diagram of a typical three-phase flying capacitor multilevel converter structure.

[0026] Figure 2 This is a schematic diagram showing that the switching frequency of the semiconductor switches in the converter depends on the normalized power.

[0027] Figure 3 This is a schematic diagram illustrating an exemplary loss distribution in a semiconductor switch.

[0028] Figure 4 This is a schematic diagram of the switching losses of a semiconductor switch.

[0029] Figure 5 This is a schematic diagram of the total losses of a semiconductor switch.

[0030] Figure 6 This is a schematic diagram of an exemplary power characteristic curve for a chassis.

[0031] The corresponding components are labeled with the same reference numerals in all drawings. Detailed Implementation

[0032] Figure 1 A schematic diagram of a typical structure of converter 1, designed as a three-phase flying capacitor multilevel converter, is shown.

[0033] Converter 1 includes three half-bridges HB1, HB2, and HB3, which provide AC voltage U to each phase P1, P2, and P3 respectively. N,1 U N,2 U N,3 Each half-bridge HB1, HB2, HB3 has an upper branch and a lower branch, and the corresponding phases P1, P2, P3 are connected between the upper branch and the lower branch of the corresponding half-bridge.

[0034] Each phase P1, P2, and P3 can be connected to the inductor L respectively. DM1 L DM2 L DM3 Connect to filter modules F1, F2, and F3 to ensure electromagnetic compatibility (EMV).

[0035] The upper branch includes several upper semiconductor switches H1, H2, H3 connected in series. (N-2) H (N-1) The lower branch includes the same number of lower semiconductor switches L1, L2, and L3 connected in series. (N-2) L (N-1) . Figure 1 The quantities shown are for illustrative purposes only. In other embodiments, different numbers of semiconductor switches H1, H2, and H3 can be provided. (N-2) H (N-1) L1, L2, L (N-2) L (N-1) .

[0036] For example, semiconductor switches H1, H2, H (N-2) H (N-1) L1, L2, L (N-2) L (N-1) It can be implemented as an insulated gate bipolar transistor (IGBT) or a field-effect transistor, especially a metal-oxide-semiconductor field-effect transistor (MOSFET) or a gallium nitride high electron mobility transistor (GaNHEMT).

[0037] In the context of this application, the term "inner terminal" is used to refer to semiconductor switches H1, H2, and H3. (N-2) H (N-1) L1, L2, L (N-2) L (N-1) The following terminals are connected to the corresponding half-bridge HB1, HB2, HB3 connection points VP, i.e., the corresponding phases P1, P2, P3 are connected to the connection points. Accordingly, the term "outer terminal" is used to refer to semiconductor switches H1, H2, H...(N-2) H (N-1) L1, L2, L (N-2) L (N-1) The following terminals are located away from the connection points VP of their respective half-bridges HB1, HB2, and HB3.

[0038] The two innermost semiconductor switches H1 and L1, i.e., the upper and lower branches, are directly connected to each other at the connection point VP using their inner terminals and connected to the corresponding phases P1, P2, and P3. A capacitor C is connected to their outer terminals. FC1 (i.e., the so-called flying capacitor) bridging.

[0039] The next two outward-facing semiconductor switches H2 and L2, which are away from the connection point VP, in the upper and lower branches, are also connected to capacitor C at their outer terminals. FC2 (i.e., the so-called flying capacitor) is connected across. Similarly, except for the two outermost semiconductor switches H (N-1) L (N-1) In addition, all semiconductor switches at the next level further out... (N-2) L (N-2) At its external terminals, each capacitor C is also connected. FC(N-2) (i.e., the so-called flying capacitor) bridging.

[0040] The two outermost semiconductor switches H of all half-bridge HB1, HB2, and HB3 (N-1) L (N-1) Together at their external terminals, they are connected to the corresponding DC bus capacitor C connected to ground GND. DC Connection. Two DC bus capacitors C DC Therefore, it is connected in series and connected to the power supply DC voltage U. DC .

[0041] The flying capacitor C at voltage potential in converter 1 FC1 C FC2 C FC(N-2) The required capacitance (flying capacitor) determines the power density and cost of converter 1. If the selected capacitor is too small, these capacitors C FC1 C FC2 C FC(N-2) Voltage fluctuations (also known as voltage ripple) on the semiconductor switches H1, H2, and H3 will increase, thereby affecting the operation of the semiconductor switches. (N-2) H (N-1) L1, L2, L (N-2) L (N-1)The voltage load on the capacitor will also increase accordingly. Therefore, if the selected capacitor capacitance is too small, it will cause the capacitor C to fly over. FC1 C FC2 C FC(N-2) The voltage U of each capacitor FC1 U FC2 U FC(N-2) Excessive voltage fluctuations will reduce the reliability of converter 1.

[0042] To achieve a reliable design for the flying capacitor multilevel converter 1, capacitor C must be... FC1 C FC2 C FC(N-2) The capacitance is designed so that its capacitor voltage U FC1 U FC2 U FC(N-2) Only minor changes occur during operation, namely small voltage fluctuations ΔU. FC,max When the voltage fluctuates by ΔU FC,max When the value is too large, semiconductor switches H1, H2, and H... (N-2) H (N-1) L1, L2, L (N-2) L (N-1) The reliability of the capacitor decreases with increasing voltage load. Therefore, in existing known solutions, capacitor C... FC1 C FC2 C FC(N-2) The required minimum capacitance C FC,min The design is based on the maximum possible current. In industrial applications, this corresponds to the peak overload current I according to formula (1). ac,pk .

[0043]

[0044] N FC In formula (1), the number of voltage levels is represented, and f SW The set switching frequency.

[0045] According to the present invention, in order to reduce the capacitor (and correspondingly reduce cost, component quantity, and size), it is recommended to briefly increase the switching frequency f under overload conditions. SW Therefore, at the operating point under overload conditions, semiconductor switches H1, H2, and H... (N-2) H (N-1) L1, L2, L (N-2) L (N-1) The losses increase. However, since these losses only occur for a short period of time, the advantage of reducing capacitance is more significant. But for semiconductor switches H1, H2, H... (N-2) H (N-1) L1, L2, L (N-2) L(N-1) When designing a heat sink, the increased losses should be considered. This is because the switching frequency f... SW Because it linearly incorporates the required capacitance into the calculation, it is possible to calculate the capacitance from the selected normal operating point BP. n Linearly increase the switching frequency f SW It is advantageous. This is in Figure 2 The example provided is illustrated below.

[0046] Figure 2 The switching frequency f depends on the normalized power P / Pn. SW A schematic diagram.

[0047] The normal operating point BPn is the point at which the switching frequency begins to increase, f SW In this example, it is set to the rated power Pn, but it can be adjusted to other positions. Below the normal operating point BPn, the switching frequency f SW Due to filter design considerations, the switching frequency f should not be reduced further; therefore, the switching frequency f SW The position in the example shown remains constant from the beginning.

[0048] This does not necessarily lead to semiconductor switches H1, H2, H (N-2) H (N-1) L1, L2, L (N-2) L (N-1) The losses double. Figure 3 The image shows semiconductor switches H1, H2, and H... (N-2) H (N-1) L1, L2, L (N-2) L (N-1) An exemplary loss distribution is shown. Here, the loss V is represented by the normalized power P / Pn. Curve K1 represents the conduction loss, curve K2 represents the switching loss, and curve K3 represents the semiconductor switches H1, H2, and Hn. (N-2) H (N-1) L1, L2, L (N-2) L (N-1) Total loss.

[0049] It can be seen that, under normal conditions, switching losses increase linearly with power P, while conduction losses increase with the square of power P. When the switching frequency f... SW As the switching loss increases linearly, it also increases quadratically. The comparison of this change in switching loss SV is shown in... Figure 4 This is illustrated schematically. Here, the switching loss SV is expressed as a function of the normalized power P / Pn.

[0050] Curve K4 illustrates semiconductor switches H1, H2, and H... (N-2) H (N-1) L1, L2, L (N-2) L(N-1) Switching losses SV without switching frequency regulation. Curve K5 shows the switching losses SV of semiconductor switches H1, H2, and H3. (N-2) H (N-1) L1, L2, L (N-2) L (N-1) According to the present invention, the switching frequency is adjusted, that is, the switching frequency f is increased linearly. SW Switching loss SV at that time.

[0051] However, this increase is small in relation to total losses. Figure 5 For semiconductor switches H1, H2, H (N-2) H (N-1) L1, L2, L (N-2) L (N-1) The total loss GV depends on the normalized power P / Pn variation. Curve K6 represents the semiconductor switches H1, H2, and H6 without switching frequency adjustment. (N-2) H (N-1) L1, L2, L (N-2) L (N-1) The total loss GV. Curve K7 represents the switching frequency regulation described in this invention, i.e., the linearly increasing switching frequency f. SW At that time, semiconductor switches H1, H2, and H (N-2) H (N-1) L1, L2, L (N-2) L (N-1) The total loss GV. As shown in the example, under a three-fold overload condition, the total loss GV only increases by about 30%, while the capacitance of the capacitor can be reduced to one-third of its original value. Therefore, for this example, the capacitor C FC1 C FC2 C FC(N-2) The cost and space required can also be reduced by one-third.

[0052] This approach is particularly advantageous because typical power characteristic curves for positioning applications often exhibit overloads with extremely short durations but extremely high amplitudes. Figure 6 This is a schematic diagram of an exemplary power characteristic curve of a driving mechanism, where the change of power P with time t is represented.

[0053] If the solution of this invention is not adopted, then according to the prior art, capacitor C FC1 C FC2 C FC(N-2) These high overload currents must always be considered in the design. By employing the solution of this invention, it is possible to achieve this even in the event of high overloads occurring over a very short period of time, without requiring significant over-specification design of converter 1.

[0054] Although the present invention has been described and illustrated in detail through preferred embodiments, the present invention is not limited to the disclosed embodiments, and those skilled in the art can derive other modifications without departing from the scope of protection of the present invention.

Claims

1. A method for operating a flying capacitor multilevel converter (1), the converter comprising at least one half-bridge (HB1 to HB3), the half-bridge comprising a plurality of series-connected semiconductor switches (H1, H2, H3). (N-2) H (N-1) The upper branch of the circuit and the multiple series-connected semiconductor switches (L1, L2, L...) (N-2) L (N-1) The lower branch of ) among which, The upper branch and the lower branch are interconnected at the connection point (VP) for connecting phases (P1, P2, P3), wherein a semiconductor switch (H1, H2, H3) from each of the upper branch and the lower branch is connected. (N-2) H (N-1) L1, L2, L (N-2) L (N-1) The pair formed by the capacitor (C) is located at the terminal of the pair away from the connection point (VP) at the same distance from the connection point (VP). FC1 C FC2 C FC(N-2) C DC ) or by capacitor (C FC1 C FC2 C FC(N-2) C DC The corresponding series circuit is connected across, wherein the pulse width modulation signal is used at the switching frequency (f SW ) drives the semiconductor switches (H1, H2, H (N-2) H (N-1) L1, L2, L (N-2) L (N-1) ), wherein, under overload conditions, the switching frequency (f) is... SW A brief increase, wherein the phases (P1, P2, P3) are respectively connected to the inductor (L) DM1 L DM2 L DM3 The connection is characterized in that the phases (P1, P2, P3) are respectively connected to the filter modules (F1, F2, F3) to ensure electromagnetic compatibility, wherein, at the normal operating point (BP) n Using the rated switching frequency (f) SW ), and in the event of overload, from the normal operating point (BP) n ) begin increasing the switching frequency (f SW ), wherein the normal operating point (BP) n The switching frequency (f) has been set or is set to the rated power (Pn), wherein the switching frequency (f) is... SW At the normal operating point (BP) n The following remain constant or are maintained constant.

2. The method according to claim 1, wherein, The normal operating point (BP) n It has been set or is set to the rated power (Pn).

3. The method according to any one of the preceding claims, wherein, All are composed of one semiconductor switch (H1, H2, H3) from the upper branch and one from the lower branch. (N-2) H (N-1) L1, L2, L (N-2) L (N-1) The pair formed by the capacitor (C) is located at the terminal of the pair away from the connection point (VP) at the same distance from the connection point (VP). FC1 C FC2 C FC(N-2) C DC ) or by capacitor (C FC1 C FC2 C FC(N-2) C DC The corresponding series circuits of the half-bridge (HB1, HB2, HB3) are connected, wherein the two outermost semiconductor switches (H) of all the half-bridges (HB1, HB2, HB3) are connected. (N-1) L (N-1) At the terminals of the two semiconductor switches opposite to the connection point (VP), they share a common grounded (GND) DC bus capacitor (C). DC ) or grounded (GND) DC bus capacitor (C DC The series circuit is connected to the supply DC voltage (U) DC )connect.

4. The method according to any one of the preceding claims, wherein, The flying capacitor multilevel converter (1) includes at least three half-bridges (HB1, HB2, HB3) for supplying three phases (P1, P2, P3).

5. The method according to any one of the preceding claims, wherein, The semiconductor switches (H1, H2, H) (N-2) H (N-1) L1, L2, L (N-2) L (N-1) It is implemented as an IGBT or a field-effect transistor, particularly a MOSFET.

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