Method, system and apparatus for coding bit reduction in polarization coding

Abstract

Polarization codes for wireless communications are constructed to accommodate channel conditions. An input bit is encoded by a polar code to obtain a plurality of encoded bits, and a reduced number of encoded bits is decoded to obtain a decoded input bit. The polar code provides or includes bit indices for bit values, the bit indices including a first set of bit indices for values of input bits and a second set of bit indices for predetermined bit values. The coded bits in a subset are interleaved, the subset comprising less than all coded bits, and used to reduce the number of coded bits.

Description

[0001] Cross-reference to related applications

[0002] This application relates to the following Patent Cooperation Treaty (PCT) applications filed together by the same applicant on the same date:

[0003] PCT application entitled “Methods, Systems, and Apparatus for Non-Sequential Decoding of Polar Codes”;

[0004] PCT application entitled “Methods, Systems, and Apparatus for Bit Value Placement in Polar Coding”;

[0005] PCT application entitled "Methods, Systems, and Apparatus for Protograph-based Low Density Parity Check Coding"

[0006] This application also relates to the following U.S. provisional patent applications filed on the same date:

[0007] A U.S. provisional patent application entitled “Methods, Systems, and Apparatus for Partial Code Rate Reduction in Polar Coding”;

[0008] A U.S. provisional patent application entitled “Methods, Systems, and Apparatus for Rateless Polar Coding”;

[0009] A U.S. provisional patent application entitled “Methods, Systems, and Apparatus for Rateless Polar Coding and Low-complexity Decoding”;

[0010] A U.S. provisional patent application entitled “Methods, Systems, and Apparatus for Rateless Polar Coding and Incremental Redundancy”;

[0011] A U.S. provisional patent application entitled "Methods, Systems, and Apparatus for Channel-dependent Error Correction Coding". Technical Field

[0012] This application relates to coding, and more particularly to reducing the number of coded bits in polar coding. Background Technology

[0013] In wireless communication, channel conditions change rapidly and slowly due to fading effects and other factors. Therefore, channel coding is usually designed to adapt to channel conditions. Adaptive modulation and coding schemes (MCS) are a powerful method to combat constantly changing channel conditions, in which the modulation order, code length, and code rate can be changed in real time.

[0014] Adapting to channel conditions requires channel coding that can flexibly change code length and code rate in a fine-grained manner, while maintaining good error correction performance in all possible configurations. This fine-grained flexibility in channel coding remains a challenge.

[0015] Low-density parity-check (LDPC) codes and other probabilistic codes resemble random codes more naturally, making them suitable for flexibility. However, algebraic codes such as Reed-Muller (RM) codes and Bose-Chaudhuri-Hocquenghem (BCH) codes are less flexible than probabilistic codes. This is because their inherent coding structure may be disrupted when the code length or code rate changes. Polar codes possess characteristics of both probabilistic and algebraic codes. Therefore, the flexibility of polar codes lies between that of probabilistic and algebraic codes.

[0016] Rate matching (including techniques such as puncturing and shortening) is a technique used to achieve rate-compatible polar codes, such as those used in the fifth-generation (5G) new radio (NR) 3GPP standard. However, the flexibility offered by traditional polar code rate matching methods is insufficient to support more advanced communication features, such as fine-grained incremental-redundancy hybrid automatic repeat request (IR-HARQ).

[0017] A more flexible channel coding method is needed. Summary of the Invention

[0018] This invention includes embodiments related to bit reduction in polar coding, such as partially interleaved coding via rate matching. Some embodiments may also, or alternatively, relate to a form of encoding that adaptively allocates bits to sub-channels or bit positions, referred to herein primarily as information bit reclamation. For example, these embodiments and features disclosed herein may be useful in providing rate-compatible polar codes with good performance.

[0019] According to one aspect of the invention, a method involves encoding input bits using a polar code to obtain a plurality of encoded bits, interleaving a subset of the encoded bits, and outputting a reduced number of encoded bits. The polar code includes a plurality of bit indices for placing the value of the input bit before encoding, and the bit indices include a first set of bit indices for the value of the input bit and a second set of bit indices for the predetermined bit value. The subset includes fewer encoded bits than all encoded bits and is used to reduce the number of encoded bits.

[0020] Another approach involves encoding input bits using polar codes to obtain multiple encoded bits and outputting a reduced number of encoded bits. The polar codes include multiple bit indices for placing the values ​​of the input bits before encoding, and the bit indices include a first set of bit indices for the values ​​of the input bits and a second set of bit indices for predetermined bit values. The encoded bits include a subset containing fewer encoded bits than all coded bits, used to reduce the number of encoded bits. The bit indices include a corresponding first bit index, where the value of the corresponding input bit is placed, rather than a corresponding second bit index, which corresponds to the bit index of each encoded bit in the subset.

[0021] According to another aspect of the invention, a method involves: obtaining an ordered sequence, the ordered sequence indicating multiple bit indices of polar codes in rank order, the multiple bit indices being used to place the values ​​of input bits, the input bits being encoded by polar codes to obtain multiple encoded bits; encoding the input bits by polar codes according to the ordered sequence to obtain multiple encoded bits; and outputting a reduced number of encoded bits. The bit indices include: a first set of bit indices with the highest rank according to the ordered sequence, used to place the values ​​of the input bits before encoding; and a second set of bit indices with lower rank than the highest rank according to the ordered sequence, used to place predetermined bit values. The rank order is used to reduce the number of encoded bits.

[0022] The invention also includes a method involving: receiving a reduced number of coded bits encoded by a polar code, and decoding the reduced number of coded bits to obtain decoded input bits. The polar code includes a plurality of bit indices for placing the values ​​of the input bits, and the bit indices include a first set of bit indices for the values ​​of the input bits and a second set of bit indices for predetermined bit values. The received reduced number of coded bits includes the bits remaining after reducing the number of coded bits in an interleaved subset of all coded bits.

[0023] Another method involves receiving a reduced number of coded bits encoded using a polar code, the polar code comprising multiple bit indices for placing the values ​​of input bits, the bit indices comprising a first set of bit indices for the values ​​of the input bits and a second set of bit indices for predetermined bit values; and decoding the reduced number of coded bits to obtain decoded input bits. The received reduced number of coded bits includes the remaining bits after reducing the number of coded bits in a subset of coded bits that is less than all coded bits. The bit indices include a corresponding first bit index, where the value of the corresponding input bit is placed, rather than where the value of the corresponding input bit is placed, at a corresponding second bit index, the corresponding second bit index corresponding to the bit index of each coded bit in the subset.

[0024] According to another aspect of the invention, a method involves: receiving a reduced number of encoded bits encoded by a polar code, and decoding the reduced number of encoded bits to obtain decoded input bits. The polar code includes a plurality of bit indices for placing the values ​​of the input bits, which are used to encode to obtain the plurality of encoded bits. The bit indices include: a first set of bit indices with the highest rank according to an ordered sequence, used to place the values ​​of the input bits before encoding; and a second set of bit indices with lower rank according to the ordered sequence, used to place predetermined bit values. The ordered sequence indicates the plurality of bit indices in rank order, the plurality of bit indices being used to place the values ​​of the input bits, and the rank order being used to reduce the number of encoded bits to the reduced number of encoded bits.

[0025] Embodiments of the device were also disclosed.

[0026] The apparatus may include an encoder, an interleaver, and an interface. The encoder encodes input bits using polar codes to obtain multiple encoded bits. The polar codes include multiple bit indices for placing the values ​​of the input bits before encoding, and the bit indices include a first set of bit indices for the values ​​of the input bits and a second set of bit indices for predetermined bit values. The interleaver is coupled to the encoder and is used to interleave a subset of the encoded bits. This subset includes fewer encoded bits than all encoded bits and is used to reduce the number of encoded bits. The interface is coupled to the encoder and is used to output the reduced number of encoded bits.

[0027] Another embodiment of the apparatus includes an encoder and an interface. The encoder is used to encode input bits using polar codes to obtain a plurality of encoded bits. As in other embodiments, the polar codes include a plurality of bit indices for placing the values ​​of the input bits before encoding, and the bit indices include a first set of bit indices for the values ​​of the input bits and a second set of bit indices for predetermined bit values. The encoded bits include a subset containing fewer encoded bits than all encoded bits, the subset being used to reduce the number of encoded bits. The bit indices include a corresponding first bit index, where the value of a corresponding input bit is placed at the corresponding first bit index, instead of the value of the corresponding input bit being placed at a corresponding second bit index, the corresponding second bit index corresponding to the bit index of each encoded bit in the subset. The interface is coupled to the encoder for outputting the reduced number of encoded bits.

[0028] According to another aspect of the invention, an apparatus includes an encoder and an interface. The encoder is used to acquire an ordered sequence and encode input bits using polar codes according to the ordered sequence to obtain a plurality of encoded bits. The ordered sequence indicates a plurality of bit indices of polar codes in rank order, the bit indices being used to place the values ​​of the input bits, which are then encoded using polar codes to obtain the plurality of encoded bits. The bit indices include: a first set of bit indices with the highest rank according to the ordered sequence, used to place the values ​​of the input bits before encoding; and a second set of bit indices with lower rank according to the ordered sequence, used to place predetermined bit values. The rank order is used to reduce the number of encoded bits. The interface is coupled to the encoder for outputting the reduced number of encoded bits.

[0029] The apparatus may include an interface and a decoder. The interface is used to receive a reduced number of coded bits encoded by a polar code. The polar code includes multiple bit indices for placing the values ​​of input bits, and the bit indices include a first set of bit indices for the values ​​of the input bits and a second set of bit indices for predetermined bit values. The received reduced number of coded bits includes the bits remaining after reducing the number of coded bits by less than the number of coded bits in an interleaved subset of all coded bits. The decoder is coupled to the interface for decoding the reduced number of coded bits to obtain decoded input bits.

[0030] According to another aspect, an apparatus includes an interface for receiving a reduced number of coded bits encoded by a polar code. The polar code includes a plurality of bit indices for placing values ​​of input bits, and the bit indices include a first set of bit indices for the values ​​of the input bits and a second set of bit indices for predetermined bit values. The received reduced number of coded bits includes the remaining bits after reducing the number of coded bits in a subset of coded bits by less than the total number of coded bits. The bit indices include a corresponding first bit index, where the value of a corresponding input bit is placed, rather than where the value of a corresponding input bit is placed, and the corresponding second bit index corresponds to the bit index of each coded bit in the subset. The apparatus may further include a decoder coupled to the interface for decoding the reduced number of coded bits to obtain decoded input bits.

[0031] Another apparatus includes a port for receiving a reduced number of encoded bits encoded by a polar code. The polar code includes multiple bit indices for placing the values ​​of input bits, which are encoded to obtain multiple encoded bits. The bit indices include: a first set of bit indices with the highest rank according to an ordered sequence, used to place the values ​​of the input bits before encoding; and a second set of bit indices with lower rank according to an ordered sequence, used to place predetermined bit values. The ordered sequence indicates multiple bit indices in rank order for placing the values ​​of the input bits, the rank order being used to reduce the number of encoded bits to a reduced number of encoded bits. The apparatus may also include a decoder coupled to the interface for decoding the reduced number of encoded bits to obtain decoded input bits.

[0032] In other device embodiments, the device may include a processor for causing the device to perform the methods disclosed herein.

[0033] The apparatus may include a processor and a non-transitory computer-readable storage medium coupled to the processor and storing a program for execution by the processor.

[0034] Storage media do not necessarily need to be implemented in or in conjunction with such a device. For example, a computer program product may be or include a non-transitory computer-readable medium that stores a program for execution by a processor.

[0035] A program stored in a computer-readable storage medium may include instructions for performing or causing a processor to perform any of the methods disclosed herein.

[0036] A system is also disclosed, which may include a first communication device and a second communication device. The first communication device is used to transmit a reduced number of coded bits encoded by polar codes. The polar codes include a plurality of bit indices for placing the values ​​of input bits, and the bit indices include a first set of bit indices for the values ​​of the input bits and a second set of bit indices for predetermined bit values. The reduced number of coded bits includes the bits remaining in the coded bits after reducing the number of coded bits by less than the number of coded bits in an interleaved subset of all coded bits. The second communication device is used to receive the reduced number of coded bits from the first communication device and decode the reduced number of coded bits to obtain decoded input bits.

[0037] System embodiments may include communication devices that perform, implement, support, or enable any other features disclosed herein.

[0038] This invention includes these and other aspects or embodiments. Attached Figure Description

[0039] To gain a more complete understanding of the present embodiments and their advantages, reference is now made to the following description taken by way of example, in conjunction with the accompanying drawings.

[0040] Figure 1 This is a simplified diagram of a communication system.

[0041] Figure 2 yes Figure 1 A block diagram of an exemplary communication system.

[0042] Figure 3 Examples of exemplary electronic devices and base stations are shown.

[0043] Figure 4 The unit or module in the device is shown.

[0044] Figure 5 This is a trellis diagram of an example of a polar code.

[0045] Figure 6 This is a diagram illustrating the use of a cyclic buffer for punching and shortening.

[0046] Figure 7 This is a diagram illustrating the partial interlacing and perforation according to an embodiment.

[0047] Figure 8 This is a diagram illustrating partial interlacing and perforation according to another embodiment.

[0048] Figure 9 This is a diagram illustrating partial interlacing and perforation according to yet another embodiment.

[0049] Figure 10 This is a diagram illustrating partial interlacing and punching according to an embodiment having multiple different interlacers.

[0050] Figure 11 This is a diagram illustrating the line-by-line writing and column-by-column reading to interleave partial code bits according to an embodiment.

[0051] Figure 12 This is a diagram illustrating the punching and transmission information set in partially interleaved codewords.

[0052] Figure 13 This is a diagram illustrating the copying of information bits from the punched information set to the transmitted information set according to an embodiment.

[0053] Figure 14 Includes a grid diagram illustrating the recycling of information bits according to an embodiment.

[0054] Figure 15 Includes a grid diagram illustrating information bit recycling and partial interleaving according to an embodiment.

[0055] Figure 16 This includes more aggressive information bit recycling and partially interleaved mesh diagrams according to embodiments.

[0056] Figure 17 This is a flowchart of a more general exemplary method according to an embodiment.

[0057] Figure 18 This is a block diagram of an apparatus according to an embodiment. Detailed Implementation

[0058] For the purpose of illustration, specific exemplary embodiments will be explained in detail with reference to the accompanying drawings.

[0059] The embodiments described herein represent information sufficient to practice the claimed subject matter and illustrate methods for practicing such subject matter. Upon reading the following description with reference to the accompanying drawings, those skilled in the art will understand the concepts of the claimed subject matter and will recognize that the application of these concepts is not specifically described herein. It should be understood that these concepts and applications are within the scope of the invention and the appended claims.

[0060] refer to Figure 1 A simplified schematic diagram of a communication system is provided as an illustrative example and not a limitation. Communication system 100 includes a radio access network 120. Radio access network 120 may be a next-generation (e.g., sixth-generation, 6G or later) radio access network or a traditional (e.g., 5G, 4G, 3G, or 2G) radio access network. In radio access network 120, one or more electric devices (EDs) 110a, 110b, 110c, 110d, 110e, 110f, 110g, 110h, 110i, 110j (generally referred to as 110) may be interconnected with each other or connected to one or more network nodes (170a, 170b, generally referred to as 170). Core network 130 may be part of the communication system and may depend on or be independent of the radio access technology used in communication system 100. Communication system 100 also includes a public switched telephone network (PSTN) 140, the Internet 150, and other networks 160.

[0061] Figure 2An exemplary communication system 100 is illustrated. Typically, the communication system 100 enables multiple wireless or wired components to transmit data and other content. The purpose of the communication system 100 may be to provide content, such as voice, data, video, and / or text, via broadcast, multicast, and unicast. The communication system 100 can operate by sharing resources (e.g., carrier spectrum bandwidth) among its constituent components. The communication system 100 may include terrestrial communication systems and / or non-terrestrial communication systems. The communication system 100 can provide a wide range of communication services and applications (e.g., earth monitoring, remote sensing, passive sensing and positioning, navigation and tracking, autonomous delivery, and mobility). The communication system 100 can provide high availability and robustness through the joint operation of terrestrial and non-terrestrial communication systems. For example, integrating a non-terrestrial communication system (or components thereof) into a terrestrial communication system can enable a heterogeneous network comprising multiple layers. Compared to traditional communication networks, heterogeneous networks can achieve better overall performance through efficient multi-link joint operation, more flexible function sharing, and faster physical layer link switching between terrestrial and non-terrestrial networks.

[0062] Terrestrial communication systems and non-terrestrial communication systems can be considered subsystems of a communication system. Figure 2 In the example shown, communication system 100 includes electronic devices (EDs) 110a, 110b, 110c, and 110d (commonly referred to as ED 110), radio access networks (RANs) 120a and 120b, a non-terrestrial communication network 120c, a core network 130, a public switched telephone network (PSTN) 140, the Internet 150, and other networks 160. RANs 120a and 120b include corresponding base stations (BSs) 170a and 170b, which are commonly referred to as terrestrial transmit and receive points (T-TRPs) 170a and 170b. The non-terrestrial communication network 120c includes access nodes 172, which are commonly referred to as non-terrestrial transmit and receive points (NT-TRPs) 172.

[0063] Alternatively or additionally, any ED 110 can be used to access, connect to, or communicate with any T-TRP 170a, 170b, and NT-TRP 172, Internet 150, core network 130, PSTN 140, other network 160, or any combination thereof. In some examples, ED 110a can transmit uplink and / or downlink traffic with T-TRP 170a via terrestrial air interface 190a. In some examples, ED 110a, ED 110b, ED 110c, and 110d can also communicate directly with each other via one or more sidelink air interfaces 190b. In some examples, ED 110d can transmit uplink and / or downlink traffic with NT-TRP 172 via non-terrestrial air interface 190c.

[0064] Air interfaces 190a and 190b can use similar communication technologies, such as any suitable wireless access technology. For example, communication system 100 can implement one or more channel access methods in air interfaces 190a and 190b, such as code division multiple access (CDMA), space division multiple access (SDMA), time division multiple access (TDMA), frequency division multiple access (FDMA), orthogonal FDMA (OFDMA), or single-carrier FDMA (SC-FDMA). Air interfaces 190a and 190b can use other higher-dimensional signal spaces, which may involve combinations of orthogonal and / or non-orthogonal dimensions.

[0065] The non-terrestrial air interface 190c enables communication between the ED 110d and one or more NT-TRP 172s via a wireless link (or simply a link). For some examples, the link is a dedicated connection for unicast transmission, a connection for broadcast transmission, or a connection for multicast transmission between a group of ED 110s and one or more NT-TRP 175s.

[0066] RAN 120a and RAN 120b communicate with core network 130 to provide various services, such as voice, data, and other services, to ED 110a, ED 110b, and ED 110c. RAN 120a and RAN 120b and / or core network 130 may communicate directly or indirectly with one or more other RANs (not shown), which may (or may not) be directly served by core network 130 and may (or may not) use the same radio access technology as RAN 120a, RAN 120b, or both. Core network 130 may also serve as a gateway between (i) RAN 120a and RAN 120b, or ED 110a, ED 110b, ED 110c, or both, and (ii) other networks (e.g., PSTN 140, Internet 150, and other networks 160). In addition, some or all of ED 110a, ED 110b, and ED 110c may include the ability to communicate with different wireless networks via different wireless links using different wireless technologies and / or protocols. Instead of wireless communication (or other than wireless communication), ED 110a, ED 110b, and ED 110c may also communicate with service providers or exchanges (not shown) via wired communication channels and with the Internet 150. PSTN 140 may include a circuit-switched telephone network for providing plain old telephone service (POTS). The Internet 150 may include computer networks and / or subnets (internal networks) and include protocols such as Internet Protocol (IP), Transmission Control Protocol (TCP), and User Datagram Protocol (UDP). ED 110a, ED 110b, and ED 110c may be multimode devices capable of operating according to multiple wireless access technologies and may include multiple transceivers required to support these technologies.

[0067] Figure 3Another example of an ED 110 and base stations 170a, 170b, and / or 170c is shown. The ED 110 is used to connect people, things, machines, etc. The ED 110 can be widely used in various scenarios, such as cellular communication, device-to-device (D2D), vehicle-to-everything (V2X), peer-to-peer (P2P), machine-to-machine (M2M), machine-type communication (MTC), Internet of Things (IoT), virtual reality (VR), augmented reality (AR), industrial control, autonomous driving, telemedicine, smart grids, smart furniture, smart offices, smart wearables, smart transportation, smart cities, drones, robots, remote sensing, passive sensing, positioning, navigation and tracking, autonomous delivery, and mobility.

[0068] Each ED 110 represents any suitable end-user equipment used for wireless operation and may include (or be referred to as) devices such as: user equipment (UE), wireless transmit / receive unit (WTRU), mobile station, fixed or mobile subscriber unit, cellular phone, station (STA), machine-type communication (MTC) device, personal digital assistant (PDA), smartphone, laptop, computer, tablet, wireless sensor, consumer electronics device, smartbook, vehicle, automobile, truck, bus, train, IoT device, industrial equipment, or devices within the aforementioned devices (e.g., communication modules, modems, or chips). Next-generation ED 110 may be referred to using other terms. Base stations 170a and 170b are both T-TRPs and are referred to hereinafter as T-TRP 170. Also... Figure 3 As shown, NT-TRP is referred to as NT-TRP 172 below. Each ED 110 connected to T-TRP 170 and / or NT-TRP 172 may be dynamically or semi-statically enabled (i.e., established, activated, or enabled), disabled (i.e., released, deactivated, or disabled), and / or configured in response to one or more of the following: connection availability and connection necessity.

[0069] ED 110 includes a transmitter 201 and a receiver 203 coupled to one or more antennas 204. Only one antenna 204 is shown. Alternatively, one, some, or all of the antennas 204 may be panels. For example, the transmitter 201 and receiver 203 may be integrated as a transceiver. The transceiver is used to modulate data or other content for transmission by at least one antenna 204 or by a network interface controller (NIC). The transceiver may also be used to demodulate data or other content received by at least one antenna 204. Each transceiver includes any suitable structure for generating signals for wireless or wired transmission and / or for processing signals received wirelessly or wiredly. Each antenna 204 includes any suitable structure for transmitting and / or receiving wireless or wired signals.

[0070] ED 110 includes at least one memory 208. Memory 208 stores instructions and data used, generated, or acquired by ED 110. For example, memory 208 may store software instructions or modules executable by one or more processing units (e.g., processor 210) for implementing some or all of the functions and / or embodiments described herein. Each memory 208 includes one or more of any suitable volatile and / or non-volatile storage and retrieval devices. Any suitable type of memory can be used, such as random access memory (RAM), read-only memory (ROM), hard disk, optical disk, subscriber identity module (SIM) card, memory stick, secure digital (SD) memory card, on-processor cache, etc. ED 110 may also include one or more input / output devices (not shown) or interfaces (e.g., Figure 1 (Wired interface of Internet 150 in the network). Input / output devices can interact with users or other devices in the network. Each input / output device includes any suitable structure for providing or receiving information from a user, such as a speaker, microphone, keypad, keyboard, display, or touchscreen, including network interface communication.

[0071] ED 110 includes a processor 210 for performing operations including: those related to preparing transmissions for uplink transmissions to NT-TRP 172 and / or T-TRP 170; those related to processing downlink transmissions received from NT-TRP 172 and / or T-TRP 170; and those related to processing sidelink transmissions to and from another ED 110. Processing operations related to preparing transmissions for uplink transmissions may include operations such as encoding, modulation, transmit beamforming, and generating symbols for transmission. Processing operations related to processing downlink transmissions may include operations such as receive beamforming, demodulation, and decoding of received symbols. According to an embodiment, receiver 203 may receive downlink transmissions (possibly using receive beamforming), and processor 210 may extract signaling from the downlink transmissions (e.g., by detecting and / or decoding signaling). Examples of signaling may be reference signals transmitted by NT-TRP 172 and / or T-TRP 170. In some embodiments, processor 210 performs transmit beamforming and / or receive beamforming based on beam direction indications (e.g., beamangle information (BAI)) received from T-TRP 170. In some embodiments, processor 210 may perform operations related to network access (e.g., initial access) and / or downlink synchronization, such as operations related to detecting synchronization sequences, decoding, and acquiring system information. In some embodiments, processor 210 may perform channel estimation using reference signals received from NT-TRP 172 and / or T-TRP 170.

[0072] Although not shown, processor 210 may form part of transmitter 201 and / or receiver 203. Although not shown, memory 208 may form part of processor 210.

[0073] The processing components of processor 210, transmitter 201, and receiver 203 may each be implemented by the same or different processors, which execute instructions stored in memory (e.g., memory 208). Alternatively, some or all of the processing components of processor 210, transmitter 201, and receiver 203 may each be implemented using dedicated circuitry, such as a programmable field-programmable gate array (FPGA), a graphics processing unit (GPU), or an application-specific integrated circuit (ASIC).

[0074] In some implementations, T-TRP 170 may be known by other names, such as base station, basetransceiver station (BTS), wireless base station, network node, network device, network-side device, transmit / receive node, NodeB, evolved NodeB (eNodeB or eNB), home eNodeB, next-generation NodeB (gNB), transmission point (TP), site controller, access point (AP) or wireless router, relay station, ground node, ground network device, ground base station, baseband unit (BBU), remote radio unit (RRU), active antenna unit (AAU), remote radio head (RRH), central unit (CU), distributed unit (DU), positioning node, etc. T-TRP 170 can be a macro base station, pico base station, relay node, host node, or a combination thereof. T-TRP 170 may refer to the aforementioned equipment or a device within the aforementioned equipment (e.g., a communication module, modem, or chip).

[0075] In some embodiments, portions of T-TRP 170 may be distributed. For example, some modules of T-TRP 170 may be located remotely from the device housing the antenna 256 for T-TRP 170 and may be coupled to the device housing the antenna 256 via a communication link (not shown) sometimes referred to as a fronthaul (e.g., a common public radio interface, CPRI). Therefore, in some embodiments, the term T-TRP 170 may also refer to modules on the network side that perform processing operations such as determining the location of ED 110, resource allocation (scheduling), message generation, and encoding / decoding, and are not necessarily part of the device housing the antenna 256 of T-TRP 170. These modules may also be coupled to other T-TRPs. In some embodiments, T-TRP 170 may actually be multiple T-TRPs that work together, for example, using coordinated multicast transmissions, to serve ED 110.

[0076] T-TRP 170 includes at least one transmitter 252 and at least one receiver 254 coupled to one or more antennas 256. Only one antenna 256 is shown. Alternatively, one, some, or all of the antennas 256 may be a panel. The transmitter 252 and receiver 254 may be integrated as a transceiver. T-TRP 170 also includes a processor 260 for performing operations, including operations related to: preparing transmissions for downlink transmission to ED 110; processing uplink transmissions received from ED 110; preparing transmissions for backhaul transmission to NT-TRP 172; and processing transmissions received from NT-TRP 172 via backhaul. Processing operations related to preparing transmissions for downlink or backhaul transmission may include operations such as encoding, modulation, precoding (e.g., multiple input multiple output (MIMO) precoding), transmit beamforming, and generating symbols for transmission. Processing operations related to receiving transmissions in the uplink or via backhaul may include operations such as receive beamforming, demodulating received symbols, and decoding received symbols. Processor 260 may also perform operations related to network access (e.g., initial access) and / or downlink synchronization, such as generating the contents of a synchronization signal block (SSB), generating system information, etc. In some embodiments, processor 260 also generates beam direction indications, such as a BAI, which can be scheduled by scheduler 253 for transmission. Processor 260 performs other network-side processing operations described herein, such as determining the location of ED 110, determining where to deploy NT-TRP 172, etc. In some embodiments, processor 260 may generate signaling, for example, to configure one or more parameters of ED 110 and / or one or more parameters of NT-TRP 172. Any signaling generated by processor 260 is transmitted by transmitter 252. It should be noted that the term "signaling" as used herein may alternatively be referred to as control signaling. Dynamic signaling can be transmitted in the control channel (e.g., the physical downlink control channel, PDCCH), while static or semi-static higher-layer signaling can be included in data packets transmitted in the data channel (e.g., the physical downlink shared channel, PDSCH).

[0077] Scheduler 253 may be coupled to processor 260. Scheduler 253 may be included within T-TRP 170 or operate separately from T-TRP 170. Scheduler 253 may schedule uplink, downlink, and / or backhaul transmissions, including issuing scheduling authorizations and / or configuring schedule-free (“configured authorizations”) resources. T-TRP 170 also includes memory 258 for storing information and data. Memory 258 stores instructions and data used, generated, or acquired by T-TRP 170. For example, memory 258 may store software instructions or modules executed by processor 260 for implementing some or all of the functions and / or embodiments described herein.

[0078] Although not shown, processor 260 may form part of transmitter 252 and / or receiver 254. Furthermore, although not shown, processor 260 may implement scheduler 253. Although not shown, memory 258 may form part of processor 260.

[0079] The processing components of processor 260, scheduler 253, transmitter 252, and receiver 254 can each be implemented by one or more processors, which may be the same or different, to execute instructions stored in memory (e.g., memory 258). Alternatively, some or all of the processing components of processor 260, scheduler 253, transmitter 252, and receiver 254 can be implemented using dedicated circuitry such as FPGAs, GPUs, or ASICs.

[0080] It should be noted that the NT-TRP 172 is shown as an example of a drone only, and the NT-TRP 172 can be implemented in any suitable non-terrestrial form. Furthermore, the NT-TRP 172 may use other names in some implementations, such as a non-terrestrial node, a non-terrestrial network device, or a non-terrestrial base station. The NT-TRP 172 includes a transmitter 272 and a receiver 274 coupled to one or more antennas 280. Only one antenna 280 is shown. Alternatively, one, some, or all of the antennas may be panels. The transmitter 272 and receiver 274 may be integrated as a transceiver. The NT-TRP 172 also includes a processor 276 for performing operations, including operations related to: preparing transmissions for downlink transmissions to ED 110; processing uplink transmissions received from ED 110; preparing transmissions for backhaul transmissions to T-TRP 170; and processing transmissions received from T-TRP 170 via backhaul. Processing operations related to preparing a transmission for downlink or backhaul transmission may include operations such as encoding, modulation, precoding (e.g., MIMO precoding), transmit beamforming, and generating symbols for transmission. Processing operations related to processing transmissions received in the uplink or received via backhaul may include operations such as receive beamforming, demodulating the received signal, and decoding the received symbols. In some embodiments, processor 276 performs transmit beamforming and / or receive beamforming based on beam direction information (e.g., BAI) received from T-TRP 170. In some embodiments, processor 276 may generate signaling, for example, to configure one or more parameters of ED 110. In some embodiments, NT-TRP 172 implements physical layer processing but does not implement higher-level functions such as medium access control (MAC) or radio link control (RLC) layer functions. Since this is only an example, more generally, NT-TRP 172 may implement higher-level functions in addition to physical layer processing.

[0081] The NT-TRP 172 also includes a memory 278 for storing information and data. Although not shown, a processor 276 may form part of the transmitter 272 and / or the receiver 274. Although not shown, the memory 278 may form part of the processor 276.

[0082] The processing components of processor 276, transmitter 272, and receiver 274 may each be implemented by the same or different one or more processors, which execute instructions stored in memory (e.g., memory 278). Alternatively, some or all of the processing components of processor 276, transmitter 272, and receiver 274 may be implemented using dedicated circuitry such as a programmable FPGA, GPU, or ASIC. In some embodiments, NT-TRP 172 may actually be multiple NT-TRPs that work together, for example, through coordinated multipoint transmissions, to serve ED 110.

[0083] T-TRP 170, NT-TRP 172 and / or ED 110 may include other components, but for clarity these components are omitted.

[0084] according to Figure 4 One or more steps of the methods in the embodiments provided herein may be performed by the corresponding units or modules. Figure 4 The diagram illustrates units or modules within a device (e.g., in ED 110, T-TRP 170, or NT-TRP 172). For example, signals may be transmitted by a transmitting unit or a transmitting module. Signals may be received by a receiving unit or a receiving module. Signals may be processed by a processing unit or a processing module. Other steps may be performed by artificial intelligence (AI) or machine learning (ML) modules. The respective units or modules may be implemented using hardware, one or more components or devices executing software, or a combination thereof. For example, one or more of the units or modules may be integrated circuits, such as a programmable FPGA, GPU, or ASIC. It should be understood that if the aforementioned modules are implemented using software executed by a processor, etc., these modules may be acquired by the processor, in whole or in part, for processing in single or multiple instances, individually or together, and these modules themselves may include instructions for further deployment and instantiation.

[0085] Additional details regarding ED 110, T-TRP 170, and NT-TRP 172 are known to those skilled in the art. Therefore, for clarity, these details are omitted herein.

[0086] Having considered communication more generally above, we now turn to specific exemplary embodiments.

[0087] Successive cancellation (SC) is a fundamental decoding algorithm for polar codes. In SC decoding, all frozen bits and information bits are decoded bit-by-bit according to the defined decoding order of the polar code. By convention, the decoding order is the natural order of the polar code bit indices where all frozen bits and information bits are placed. Therefore, this traditional decoding order is called the "natural order." Before decoding the current bit, the bits preceding the natural order are always decoded first.

[0088] The successive cancellation list (SCL) is an enhanced decoding algorithm for polar codes, in which multiple (L) SCL decoding instances are performed. Each instance is called a "decoding path". During decoding of each binary bit, both the "0" and "1" branches are expanded to each path, creating 2L paths. All 2L paths are then compared, with the L most likely paths retained and the L least likely paths discarded (or pruned). Path expansion and pruning operations are performed during the decoding of each information bit until all information bits have been decoded. Finally, the most likely path is selected as the decoded output.

[0089] The working principle of CRC-aided successive cancellation list (CA-SCL) decoding is almost the same as that of SCL, except that in the last step, the path most likely to pass the CRC check is selected as the decoding output.

[0090] The working principle of parity-check successive cancellation list (PC-SCL) decoding is almost the same as that of SCL. The difference is that when decoding parity-check (PC) bits, the parity check value of the preceding associated bits is used as the bit decision result. In code construction, in addition to frozen bits and information bits, PC bits are also generated.

[0091] Polar codes are linear block codes. For a polar code of length N, its generator matrix is ​​G. N Its encoding process is as follows in, And it is a binary input vector. And it is a binary code vector. The N×N binary generator matrix is... in, and is the polarization kernel matrix (also known as the Arikan kernel or Arikan matrix), denotes the Kronecker product, and n = log2N.

[0092] By encoding K information bits into N code bits, and K < N, a code rate of R = K / N < 1 is obtained. This means that only a portion of is used to carry information bits, the remaining bits of are typically set to fixed values and are called frozen bits. The set of information bits (or information set) can be denoted by I, and the set of frozen bits (or frozen set) can be denoted by F. Sometimes there is also an additional set of PC bits, denoted by P. The frozen bits are known and are usually set to all zeros before decoding, so they do not carry any information. The PC bits are parity check bits for a subset of the information bits, and thus are known once the associated information bits are decoded. The decoding of a polar code attempts to recover all the information bits.

[0093] The code length M can be but is not necessarily always a power of 2, in which case M < N. In fact, the number of transmitted code bits is reduced from N to M through puncturing and shortening. For convenience, in this article, N is referred to as the mother code length and M as the code length. Specifically, the punctured bits of the mother code are untransmitted bits unknown to the decoder, while the shortened bits are untransmitted bits known to the decoder (usually all zeros).

[0094] Figure 5 is a trellis diagram of an example of a polar code, where N = 8 and K = 4. Each "butterfly structure" in the figure is a polarization, and Figure 5 a butterfly structure is shown by example on the right side of, where in the shown example, the unshaded circles on the left represent the information set I = {u4, u6, u7, u8}, and the shaded circles represent the frozen set F = {u1, i2, i3, u5}.

[0095] Figure 5 the input vector u on the left side in and Figure 5 the code vector x on the right side in each include multiple bit positions. The bit positions in the input vector are indexed by the corresponding bit indices, and the bit values are placed on these bit indices or bit positions for encoding. These bit indices or bit positions are sometimes also referred to as bit channels or sub-channels. As disclosed in this article, placing the bit values on the bit indices can also be stated in other ways, such as placing the bits or bit values on the bit indices, bit positions, bit channels or sub-channels; or assigning the bit values or bits to the bit indices, bit positions, bit channels or sub-channels. Other terms can be used to represent how the bit values or bits are provided as inputs for encoding.

[0096] Thus, polar codes can be considered to provide or include bit indices, bit positions, bit channels, or sub-channels for bit values. These bit indices, bit positions, bit channels, or sub-channels are not necessarily used only for the bits to be encoded. For example, vector elements u1…u N It is also referenced in decoding, so the decoded bit value can be similarly associated with bit index, bit position, bit channel, or sub-channel.

[0097] exist Figure 5 To the right of the code vector x, there are also multiple elements located at bit positions or bit indices. The bit value at the i-th bit index in the input vector u has some influence on multiple code bits in the code vector x, but the bit value at the i-th bit index in the input vector u is the main contributor to the value of the corresponding code bit at the i-th bit index in the code vector x. In this sense, for polar codes, the input vector bit index or bit position can be considered to correspond to, be associated with, or be related to the code vector bit index or bit position. This is the case for polar codes; for other types of codes, there may be different input / code bit correspondences, relationships, or associations.

[0098] Regarding encoding, the encoding process can be represented in any of a variety of ways. For example, encoding can be described as encoding bits to obtain encoded bits or generating encoded bits. For example, the encoding process described above... This can be represented as generating or otherwise acquiring an encoded input (input vector u in this example) including bits or bit values ​​for encoding, to acquire or generate multiple encoded bits (code vector x in this example).

[0099] From an encoding perspective, for example, the bit value of an element in an input vector u can be called the value to be encoded or a bit, or the value or bit used for encoding. A block of bits or bit values ​​used for encoding is sometimes also called a code block. For example, the bit value of an element in a code vector x can be called an encoded bit or coded bit, and such a block of bits can be called a codeword.

[0100] From a decoding perspective, decoding can be referred to as decoding encoded bits, codewords, or codes, or, for example, decoding, obtaining, or recovering (encoded) bits or bit values ​​from encoded bits, codewords, or codes. In the context of decoding, the bit values ​​of elements in vector u can be referred to as decoded or recovered bits or bit values.

[0101] Rate-compatible polar coding is a key technology for wireless applications.

[0102] A technique called quasi-uniform puncturing (QUP) is proposed (see K. Niu, K. Chen, and J.-R. Lin, “Beyond turbo codes: Rate-compatible punctured polar codes,” 2013 IEEE International Conference on Communications (ICC), pp. 3423-3427, doi:10.1109 / ICC.2013.6655078), in which the reliability of all polarimetric subchannels is calculated according to the puncturing pattern using density evolution with a Gaussian approximation (DE / GA). Consider starting from a length of N=2 n The parent polar code constructs a punctured polar code of length M and information length K. A puncture pattern P of size N–M is selected as the first N–M bits of the codeword. The information set I of size K and the information set F of size N–K are determined by DE / GA, tracking the average of the log-likelihood ratio (LLR) or L-density.

[0103] Based on this method, the punch vector is initialized. We select the SNR (cSNR) such that the puncturing position (puncture location) in the puncturing pattern is 1, while other positions are 0. We calculate the reliability of each synthesized channel using DE / GA, which involves hardware-intensive floating-point computations. We then determine the frozen set F as the set of N–K indices of the synthesized channel with the lowest reliability.

[0104] While QUP rate matching offers excellent performance and involves only puncturing, its implementation is highly complex due to the DE / GA computations required to determine channel reliability. Alternatively, performance can be significantly impacted if a predefined information / freeze set is used to avoid this complexity.

[0105] In 5G NR, a combination of puncturing, shortening, and repetition, along with a fixed reliability sequence, is used to balance performance and complexity. See the 3rd Generation Partnership Project (3GPP), “Multiplexing and Channel Coding,” 3GPP 38.212 V.15.3.0, 2018. More importantly, the DE / GA scheme is not addressed. Specifically, sub-block interleaving (also known as interleaving) is used for both puncturing and shortening. The puncturing and shortening modes are complementary and together form a symmetrical (relative to the polar code sequence) rate-matching scheme.

[0106] With a mother code length of N and a code length of M, the specific rate matching scheme used in 5G NR is as follows:

[0107] Repeat, when M>N;

[0108] Drilling, when K / M≤7 / 16;

[0109] Shorten when K / M > 7 / 16.

[0110] Sub-block interleaving is performed before puncturing and shortening. The interleaver divides the master code of length N into 32 sub-blocks of size N / 32 and interleaves them. Punching starts from the first bit of the codeword, also referred to as the code bit or coded bit in this paper, and shortening starts from the last code bit. The rate matching module is implemented efficiently using a circular buffer. All master code bits are placed in the circular buffer, and puncturing is done by selecting bits in a clockwise order, while shortening is done by selecting bits in a counterclockwise order.

[0111] Figure 6 This is a diagram illustrating the use of a circular buffer for punching and shortening. Figure 6 At position 602, the codeword bits are shown in a vertical column, including punched bits and shortened bits, as shown in the figure. At position 604, Figure 6 The diagram illustrates a circular buffer and the reading of code bits without punching or shortening. The next two circles represent the circular buffer respectively; at 606, the dashed line indicates punching from the beginning of the buffer, and at 608, the dashed line indicates shortening from the end of the buffer.

[0112] These existing rate-matching schemes for polar codes offer a degree of flexibility. However, they have several drawbacks.

[0113] For example, the punch-only technique described above requires complex online (i.e., real-time) computation (DE / GA), while other techniques may only be applicable to very low bitrates.

[0114] Current 5G NR rate matching methods employ numerous shortened bits that are known at the receiver, thus preventing the transmission of additional information about the source bits when the code length needs to be increased. This drawback reduces the flexibility of 5G NR rate matching schemes.

[0115] This method also uses a combination of puncturing and shortening, with the choice between puncturing or shortening based on the bitrate. This rate-dependent rate matching introduces additional hardware logic, thus slowing down encoding and decoding.

[0116] Another potential problem with the example provided above is the presence of many frozen bits in current PC polar codes. These frozen bits are typically set to zero (or another known value) and do not carry any information, which can negatively impact code performance.

[0117] Some of the embodiments disclosed herein aim to address technical issues related to providing more flexible rate-compatible polar codes. 5G NR has already adopted rate-related rate matching schemes, but their flexibility can be compromised, at least to some extent, by shortening, and the methods employed have relatively high implementation complexity. In some embodiments, puncturing is superior to a combination of puncturing and shortening. In some embodiments, rate compatibility, as disclosed herein, involves operations or features in polar coding prior to the polarization transformation, which can provide greater flexibility regarding how code bits are used, rather than after the polarization transformation.

[0118] The disclosed embodiments may also, or alternatively, relate to the technical problem of avoiding the severe performance loss in puncturing-only schemes. Punching-only rate matching can offer the advantage of low-complexity hardware implementation if computationally intractable DE / GA schemes are not used. However, such rate matching for medium- to high-rate codes (R > 1 / 3) may still present challenges. Some embodiments not only avoid DE / GA computations but also maintain good performance on medium- and high-rate codes.

[0119] This invention includes embodiments involving a partially interleaved puncturing pattern or an equivalent partially interleaved transmission pattern. Flexible and fine-grained partially interleaving patterns can be supported through parameterized configuration and / or parameter-based descriptions.

[0120] In some embodiments, a method mainly referred to herein as information bit recycling is used to determine an information set / frozen set and thus place bit values on bit indices for polar coding.

[0121] In an embodiment of the present invention, partial interleaving refers to interleaving only a part of a codeword rather than the entire codeword, which may also be referred to as a code vector and is denoted by c. For example, the code bits in a codeword c can be divided into two parts, c0 and c1. The part can also or alternatively be referred to as a subset, a block. For example, as used herein, a "subset" generally refers to a part, a block of coded bits or a codeword that includes fewer coded bits than all the coded bits of the codeword. In this example, there are two subsets, c0 and c1, but there may generally be more than two subsets.

[0122] Partial interleaving, in the context of dividing the code bits of a codeword into two subsets, means that one of these subsets is not interleaved (at least not interleaved for rate matching), while the other is interleaved. For ease of reference, assume that c0 is not interleaved and c1 is interleaved. Then rate matching is performed, and the partially interleaved codeword is rate matched by puncturing, for example, for a code length M < N, and in this example, P = N - M bits are punctured. Puncturing is performed from the interleaved part.

[0123] As used in the context of the embodiments disclosed herein, interleaving refers to changing the order of the elements of a subset. Interleaving is mainly used herein, but more generally aims to include such a change in order and may also or alternatively be referred to as recombination, reordering, scrambling, interleaving, etc. An interleaved subset includes the same elements as the subset before interleaving but with a different order within the subset.

[0124] One potential benefit of reducing the number of coded bits by rate matching (e.g., puncturing) is to allocate capacity to the entire codeword. The bit indices corresponding to the punctured coded bits have zero capacity, while the bit indices corresponding to the transmitted coded bits have a capacity that depends on the signal to noise ratio (SNR).

[0125] Combining partial interleaving with a reduction in the number of coded bits allows for a more precise allocation of capacity to where it is most needed. For a subset of coded bits in a codeword where the number of coded bits is not reduced, interleaving is unnecessary. Full interleaving (e.g., as implemented in 5G NR) would change the order of all coded bits, so puncturing would effectively apply to the entire codeword, as coded bits initially located anywhere in the codeword might appear at punctured positions after interleaving. It is preferable to more selectively reduce the number of coded bits through puncturing or other methods, such that coded bits are removed only from certain portions of the codeword, thus only portions of certain bit indices or code blocks have reduced capacity. Other portions of the codeword and code blocks are not adversely affected, or at least not significantly adversely affected. In other words, interleaving is best restricted to these portions when only certain portions of the code or codeword are punctured.

[0126] In summary, the potential advantages of partial interleaving compared to interleaving all coded bits include, for example, the ability to achieve more targeted and finer-tuned reduction of coded bits through puncturing. The disclosed embodiments also provide lower descriptive and implementation complexity.

[0127] For the length of one or more interleaved subsets of a codeword, there are several options. For example, the ratio of one or more interleaved subsets to the current mother code length of c is denoted by ε, which can be a parameter configured by communication standards or specifications or by control signaling such as downlink control information (DCI) and / or uplink control information (UCI) signaling.

[0128] In some embodiments, ε is 1 / X, where X is a power of 2. When the mother code length is a power of 2, this type of power-of-2 reciprocal of the value of parameter ε may be preferred, making it easier to form shorter polar codes from the resulting proportional length of the coded bit subset and the number of coded bits reduced after puncturing.

[0129] Regarding one or more locations of one or more interleaved subsets within a codeword, in one embodiment, the subsets are evenly distributed within the codeword. Figure 7 This is a block diagram of partial interlacing and perforation according to this embodiment.

[0130] refer to Figure 7 In the case of two equal-length subsets of encoded bits in a codeword, the two subsets c1 and c0 can be the first and second halves of the codeword c shown. For a codeword c of length N, c1 = c[1, 2…N / 2], c0 = c[N / 2+1, N / 2+2…N]. The interleaved subset can be represented by π(c1) and concatenated with the non-interleaved subset (c0 in this example) to generate a partially interleaved codeword c' = [π(c1), c0].

[0131] In fact, the bits in c' can be written sequentially into the circular buffer. Figure 7 In the diagram, the circular buffer is shown at 702, and arrows 704 and 706 indicate that π(c1) and c0 are written to the circular buffer sequentially. Transmission begins at bit N and proceeds counter-clockwise to bit (P+1) in the sense of the circular buffer, as shown by arrow 708 in the example. Equivalently, transmission can begin at bit (P+1) and proceed clockwise to bit N in the sense of the circular buffer 708. Therefore, bits 1 through P of the interleaved codeword portion π(c1) are not transmitted, meaning these bits are punctured. Punching occurs in... Figure 7 The dashed arrow 710 is shown in the middle.

[0132] exist Figure 7 In the example shown, c1 is an example of a subset of coded bits in codeword c. This subset contains fewer coded bits than all coded bits in c. In the example shown, the coded bits in subset c1 are interleaved, and the number of coded bits in the interleaved subset π(c1) is reduced by puncturing. Therefore, at least in this sense, subset c1 is used to reduce the number of coded bits. The reduced number of coded bits can be output, for example, for transmission.

[0133] Figure 8 This is a block diagram of partial interleaving and puncturing according to another embodiment, wherein the subset to be interleaved, c1, is partially "sandwiched" between coded bits in the non-interleaved subset, c0. This illustrates that codeword subsets such as c0 and c1 are not necessarily consecutive or sequential, but can be interleaved within codeword c.

[0134] Figure 8 The example shown illustrates an embodiment in which codeword c is divided or segmented into S shorter blocks. In some embodiments, the number S of shorter blocks is a power of 2, which may be preferred when the mother code length is a power of 2, so that the length of the interleaved codeword subset and the reduced number of coded bits remaining after puncturing will more easily form shorter polar codes. For the same reason, shorter blocks of equal length may also be preferred.

[0135] One or more shorter blocks (including the two shorter blocks in the example shown) are selected for interleaving, while other shorter blocks are not interleaved. When a shorter block is selected for interleaving, that shorter block is a subset of the coded bits used for interleaving. Multiple shorter blocks selected for interleaving can be aggregated into a subset and interleaved, and the interleaved subset can be moved to the front of a partially interleaved codeword, or the shorter blocks can remain in their original positions within the codeword, but their coded bits are in interleaving order. Figure 8In the example shown, S = 4, the first and third shorter blocks are selected and aggregated into a subset for interleaving, and moved to the front of the partially interleaved codeword c' = [π(c1), c0]. Figure 8 The example in the example shows a subset of coded bits that are not in a contiguous order within the codeword.

[0136] Figure 9 This is a block diagram of partial interleaving and punching according to yet another embodiment, wherein (in a codeword subset c1) the coded bits to be interleaved are selected, inserted, or otherwise located or "sandwiched" between the coded bits in c0. Here, c1 is interleaved but remains in its original position. Figure 9 The example in the example shows a subset in which the encoded bits in the codeword are preceded and followed by other encoded bits.

[0137] Interleaving is not limited to a single interleaver or interleaving type in any way. For example, multiple interleavers can be used to interleave multiple coded bit subsets of a codeword separately. This feature supports the design of finer-grained puncturing patterns, which helps to better accommodate different code rates and lengths.

[0138] Consider a code vector c that is divided into multiple subsets c0, c1, c2...c B Where B is the number of subsets. Partial interleaving refers to interleaving only one or more subsets, rather than all subsets, where the coded bits of one or more other subsets and codewords remain uninterleaved.

[0139] Figure 10 This is a block diagram illustrating partial interlacing and punching according to an embodiment having multiple different interlacers. Figure 10 In this example, codeword c is divided into B = 3 subsets, denoted by c0, c1, and c2. Subsets c1 and c2 are interleaved in two different interleavers, π1 and π2. The interleaved subsets are π1(c1) and π2(c2), respectively. c0 is not interleaved. Partially interleaved codewords are concatenations of π1(c2), π2(c1), and c0. This illustrates an embodiment in which multiple unique subsets (containing fewer coded bits than all coded bits) are interleaved. In this embodiment, the subsets to be interleaved together also include coded bits fewer than all coded bits, such that even when multiple subsets of coded bits are interleaved, the interleaving remains partially interleaved.

[0140] Different types of interleaving are also possible. For partial interleaving, multiple types of interleavers or interleaving can be supported; several illustrative examples are described in this article.

[0141] In block interleaving, raw code bits are written to and read from the block interleaver in rows RI (the number of rows in the interleaver, RI) and columns CI (the number of columns in the interleaver, CI). Row-in write / column-read and in-column write / row-out read, or both, can be supported.

[0142] Without losing generality, partial code bits, i.e. the encoded bits to be interleaved, can be written row by row and read column by column to obtain the interleaved partial code bits. Figure 11 This is a block diagram illustrating the line-by-line writing and column-by-column reading of the embodiment, interleaving partial code bits. Figure 11 The horizontal arrows indicate writing line by line, and the vertical arrows indicate reading partial bits column by column.

[0143] For mother code lengths that are powers of 2, the number of rows RI or the number of columns CI, or both (both powers of 2), may be preferred, but other block interleaver sizes are also possible. Figure 11 In the example shown, RI is a power of 2, such as 2, 4, 8, 16, etc.

[0144] Partial code bits are represented as c1[1], c1[2]...c1[W], where W is the size of the partial block to be interleaved, and c is the partial code bits to be interleaved. π1 [1]、c π1 [2]……c π1 [W] can be generated based on the following exemplary pseudocode:

[0145]

[0146]

[0147] Each row and / or column can also be permuted (or written / read in a different order). The permutation sequence used for row and / or column permutations, combined with block interleaving, can be generated or otherwise obtained according to, for example, bit-reversed order or pseudo-random order. The pseudo-random order can be specified, for example, by polynomials, tables, or by transforms such as Fourier transform, Hadamard transform, discrete cosine transform, or wavelet transform.

[0148] Bit reversal interleaving can be implemented using block interleaving as described above, but in some embodiments it can be implemented alternatively without block interleaving.

[0149] Suppose that W partial code bits will be interleaved, and the bit indices of these code bits in the mother polar code are i1, i2, ..., i WThis is expressed as follows. Without loss of generality, we further assume i1, i2...i W In ascending order. This is just an example; the code bits that need to be interleaved do not need to be consecutive.

[0150] In one embodiment, bit inversion interleaving may involve writing a subset of code bits into the interleaver, wherein bit indices i1, i2, ..., i W Sort in ascending order. The numbers 0, 1...W-1 are respectively matched with those having indices i1, i2...i... W The partial code bits are associated. The inverted values ​​0, 1...W–1 are then calculated or otherwise determined as BitRev(0), BitRev(1)...BitRev(W–1). Then, the interleaved partial code bits are read from the bit indices associated with the numbers BitRev(0), BitRev(1)...BitRev(W–1) in this order.

[0151] The bit-reversed value of integer x is shown below. First, convert integer x to its binary expansion form [b0, b1… b n Then the binary expansion is inverted to [b] n ...b1,b0], and convert them to integers y. The bit reversal in this example can be represented by y = BitRev(x).

[0152] The embodiments are not limited in any way to these specific types of interleavers or interleaving, or even to a single type of interleaving. For example, different types of interleavers or interleaving can be applied to different subsets of codewords, and the method may be referred to as hybrid interleaving or using a hybrid interleaver. The partial codebits to be interleaved can be further segmented or divided into multiple subsets of codebits. Subsets can be interleaved individually, for example by using one or more block interleavers or interleavings on one or more subsets, and one or more bit-inverse interleavers or interleavings on one or more other subsets. The interleaved subsets are then concatenated together to obtain a hybrid interleaved block. Hybrid interleaving is not necessarily limited to subdivided partial codebits and can also be applied to different subsets, for example... Figure 10 c2 and c1 in the example.

[0153] Therefore, the interleaving of coded bit subsets can involve block interleaving, bit-inverted interleaving, or other types of interleaving. In the case of multiple coded bit subsets to be interleaved, each subset can be interleaved separately, and separate interleaving can involve the same or different types of interleaving of different subsets.

[0154] Another aspect of the invention relates to what is referred to herein primarily as information bit reclamation. Reducing the number of code bits to be transmitted by performing rate matching (e.g., puncturing or shortening) will result in a reduction in the capacity of polarized subchannels. For example, puncturing P code bits will cause P subchannels to drop to zero or near-zero capacity. See L. Zhang, Z. Zhang, X. Wang, Q. Yu and Y. Chen, “On the puncturing patterns for punctured polar codes,” IEEE International Workshop on Information Theory 2014, 2014, pp. 121-125, doi:10.1109 / ISIT.2014.6874807. If these reduced subchannels are chosen as information subchannels, their zero or near-zero capacity will result in a severe performance loss, which is unacceptable.

[0155] Therefore, it is preferable not to place information bits on the zero-capacity bit indices corresponding to zero-capacity sub-channels. Instead, according to some embodiments disclosed herein, these zero-capacity bit indices are marked as frozen bit indices. However, this increases the number of frozen bit indices and means that any information bits to be placed on these bit indices for transmission, for example, on the corresponding sub-channel, are actually discarded because the frozen bit indices are set to frozen bit values. To address this issue, in some embodiments, the same number of bit indices with non-zero capacity are additionally marked as information bit indices, and information bits discarded on the marked frozen bit indices are instead placed on the additionally marked information bit indices. Thus, input bit values ​​are placed on different bit indices, rather than on bit indices affected by the reduction in the number of coded bits. Unless otherwise specifically stated, zero-capacity channels or indices mentioned herein should be understood to include near-zero capacity channels, very low-capacity channels, or other practical or functional equivalents.

[0156] This method is generally referred to as information bit recycling in this paper. Information bits that would otherwise be discarded are placed at different bit indices with higher capacity. They are discarded because they are mapped to bit positions with zero (or very low) capacity due to the reduction in the number of encoded bits, for example, for rate matching. In this sense, the information bits or the original declining information bit indices can be considered recycled. In another sense, this method can be considered a form of information bit replenishment, as information bits or information bit indices lost or discarded due to the reduction in the number of encoded bits are replenished by additionally marked information bit indices.

[0157] The following notation may be useful in further describing embodiments related to information bit recycling:

[0158] Q = [Q1, Q2, ..., Q] N [Q] represents the reliability sequence, ordered in ascending order of reliability, where Q i It is the bit index of the bit position with the lowest reliability in the reliability sequence.

[0159] The set of information in the master code (without any puncturing or shortening) is denoted by I, and includes the last K (i.e., the K most reliable) bit indices in Q, such that I = {Q} N–K+1 Q N–K+2 …Q N}

[0160] A puncture set (for embodiments including punctures) is a set of puncture bit indices, denoted herein by P, and is determined based on the specific puncture pattern to be applied to rate matching. Punching can be partially interleaved puncturing as disclosed herein, or, for example, fully interleaved puncturing. Information bit recycling can be implemented in conjunction with interleaving, but is independent of interleaving. Information bit recycling is also not associated with puncturing in any way and can be more generally applied to reduce the number of coded bits. However, embodiments including puncturing and / or interleaving can still benefit from information bit recycling.

[0161] In this paper, the information subchannels that still have non-zero capacity after punching are referred to as "transmitted information sets" or I. T The notation is for ease of reference only and in the context of coded bits being output for transmission. However, it should be noted that the embodiments are not limited to the transmission of coded bits. The information bit retrieval features and other features disclosed herein can be applied more generally to other embodiments that may involve outputting coded bits (e.g., outputting coded bits to a storage medium), and are not necessarily required to involve the transmission of coded bits.

[0162] The information bit index corresponding to the subchannel whose capacity drops to zero due to puncturing is referred to in this paper as the "punctured information set", denoted by I. P express.

[0163] I = I T ∪I P , Φ=I T ∩I P , where Φ is the empty set.

[0164] The newly added non-zero capacity bit index is called the "replenished information set," denoted by I. R express.

[0165] Information bit recycling can involve determining I P and I T Determine I R And the copy information bits, each of which is described in further detail in this article (at least below) by way of examples.

[0166] About I P and I T Given P punctured bit indices, the bit index corresponding to the resulting zero-capacity sub-channel can be represented as I0. The punctured information set I... P The intersection of I and I0 can be represented as I P =I∩I0. The set of transmitted information is I within I. P The complement of can be represented as

[0167] In most cases, the bit index corresponding to the zero-capacity subchannel I0 is expected to be the same as the bit index in the puncture set P. In these cases, I P =I∩P. In other words, it is expected that the bit at the i-th bit index in the codeword or mother code will be punctured to reduce the number of encoded bits, causing the i-th bit index in the input vector to decrease to zero capacity.

[0168] The number of punched information bits is represented by |I P | indicates.

[0169] Figure 12 It is the set of punch information I in the partially interleaved codeword π(c) P and transmission information set I T The block diagram. However, it should be noted that this is an example using partially interleaved codewords. And determining I P and I T The relevant features, and more generally the features related to information bit recycling, are not in any way related to partial interleaving or any other type of interleaving.

[0170] Supplementary information set I can be identified or selected. R As the most reliable |I with non-zero subchannel capacity P |Frozen bit index. These|I P |The frozen bit index, if marked or selected as, converted to, or otherwise reassigned, will be discarded|I P |Information bit index of information bits.

[0171] When I0 = P, the supplementary information set I can be obtained in a manner consistent with the following exemplary pseudocode. R .

[0172]

[0173] Previously placed (or to be placed) in I P The information bits at the bit index in I are now placed in I R The bit indexes in the code can be used for rate matching (e.g., by puncturing and / or shortening). This can be pre-determined based on, for example, a known or determined configuration or target code length. Therefore, sub-channels that would drop to zero or very low capacity due to rate matching (and should be avoided for carrying information bits) (and equivalently, their corresponding bit indices for encoding) can be determined before encoding. While the information set and frozen set can be initially determined based on the number of information bits to be encoded and a reliability sequence (e.g., Q above), the values ​​of the input bits placed at the bit indices corresponding to the zero-capacity sub-channels can be copied, or otherwise placed at the bit indices initially included as part of the frozen set. This can involve copying these bit values ​​between bit indices, moving these bit values ​​between bit indices, or placing these bit values ​​at newly designated or marked information bit indices if they were not previously placed at bit indices that dropped to zero capacity due to rate matching.

[0174] This might be possible Figure 13 The best example is shown in the text. Figure 13 This is a block diagram illustrating the copying of information bits from the punched information set to the transmitted information set according to an embodiment. Figure 13 In the middle, information bits placed at zero-capacity bit indices due to rate matching (such as...) Figure 13 I in P (As shown) is copied to I R The new bit index in. Figure 13 The example shown references bit copying and can illustrate how information bit recycling can be implemented in various embodiments; however, information bit recycling is not limited to embodiments involving explicit "copying" operations. While copying is a feasible method for placing information bit values ​​onto additionally labeled or reassigned information bit indices, it should be understood that information bit values ​​can alternatively be placed onto newly labeled or reassigned information bit indices without first placing them onto zero-capacity bit indices. Typically, placement or movement operations can be accomplished in other ways that do not involve index-to-index copying.

[0175] Typically, if there are P punctured bit indices where the encoded bits are punctured or otherwise reduced, there will be exactly P bit indices with zero capacity. For example, puncturing or otherwise reducing the first P encoded bits at the first P bit indices of a polar code codeword will most significantly decrease the first P bit indices in the input vector. Similarly, for many other puncturing or bit reduction patterns, the zero-capacity (or near-zero-capacity) bit indexing pattern is the same as the puncturing or bit reduction pattern, such that the bit indices in the encoded input vector affected by bit reduction are the same as the bit indices where the encoded bits are punctured or otherwise reduced. There can be exceptions, such as when puncturing from the end of the codeword, and for such scenarios, the affected input vector bit indexing pattern or its relationship to the puncturing or bit reduction pattern can be defined or specified, for example, in a communication standard.

[0176] There is a relationship between the bit indices of the coded bits that are punctured or otherwise reduced in rate matching and the bit indices used for encoding, where the bit indices used for encoding are the bit indices of the input vector most significantly affected by the number of coded bits reduced. The correspondence between the number of coded bits reduced and the number of bit positions in the encoded input vector, and the correspondence between the reduced coded bit indices and the bit indices of the encoded input vector, are examples of relatively simple deterministic relationships, but the present invention is not limited in any way to such relationships.

[0177] The above examples of information bit recycling identify information bits or information bit indices that will be affected by the reduction in the number of coded bits. Information bit indices corresponding to polar codes that have been punctured or otherwise reduced in size are recycled. Another embodiment involves a more aggressive recycling of information bits.

[0178] As in the previous example, suppose the mother codeword is divided or segmented into subsets. These subsets can be divided into two categories: one or more punctured subsets and one or more non-punctured subsets. Specifically, a subset is a punctured subset if any one or more coded bits in it are punctured or otherwise reduced. On the other hand, a non-punctured subset has no punctured or otherwise reduced coded bits, and all of its coded bits are retained even after the number of coded bits has been reduced.

[0179] Radical information bit reclamation can be achieved using a modified information set I' P and I' T To describe. All information bit indices in the punched subset are included in the punched information set I' P This is a more radical approach than the previous example, because I' PSome bit indices may still have non-zero subchannel capacity, but their subchannel capacity is very low. Transmitting information bits on these subchannels by placing information bit values ​​on the corresponding bit indices may still lead to performance degradation. The set of transmitted information in this example is I'. T =I\I' P .

[0180] The supplementary information set I' that can be used for aggressive information bit reclamation R Identified as the most reliable |I' in one or more non-hole-punching subsets P | A frozen bit index.

[0181] Similar to the previous example of information bit recycling, the information bit previously placed at the bit index in the punched information set (for aggressive information bit recycling, it is I' P It is now copied, moved, or otherwise placed in I' R On the bit index in.

[0182] The subset size used to identify punctured and non-punctured subsets can be calculated, determined, or otherwise obtained in any of a variety of ways. For example, the subset size for aggressive information bit recycling can be specified in a communication standard or specification. For shorter subset sizes, aggressive information bit recycling can approximate earlier examples of information bit recycling, since shorter subsets are unlikely to include anything other than the punctured information set I. P Additional information bits beyond the associated information bits are simply due to the shorter subset size. A longer subset size increases the likelihood of more information bits being recycled. Aggressive information bit recycling can have better performance because more information bits are placed on bit indices with larger capacities, but this increases the complexity of subset splitting and punctured / non-punctured subset identification, and requires copying, moving, or otherwise placing more information bit values ​​on different bit indices.

[0183] A simple and uniform description method is important for describing code sets that may include thousands of (N, K) codes. For example, in communication standards or specifications, such description efficiency may be a primary concern.

[0184] Another aspect of the invention relates to parameterized configuration and / or parameter-based description, which may be particularly convenient and efficient for fine-grained partial interleaving. The fine-grained partial interleaving disclosed herein involves individual interleaving subsets of codewords, possibly using different types of interleavers and interleaving.

[0185] For example, for parameterized configurations and / or parameter-based descriptions of fine-grained interleaving, two parameter vectors may be sufficient to describe a wide range of partial interleaving patterns.

[0186] A subset size vector [W1, W2, W3…], where each element specifies the size W of the subset to be interleaved individually, can be used to configure and / or describe the size of the subsets to be interleaved individually. The subset size can be indicated or represented in any of a variety of ways, such as as an absolute number of coded bits per subset, or as a relative quantity or metric. For example, a relative quantity with respect to the mother codeword length N can indicate that the subset size is a fraction of the mother codeword length; for example, 1 / 4 indicates a subset size of N / 4. An equivalent relative metric is the number of subsets of equal size per mother codeword; in this case, for example, a value of 4 also indicates a subset size of N / 4.

[0187] An interleaver type or interleaving type vector [RI1, RI2, RI3…], where each element specifies the number of rows RI of the block interleaver, can also be used in some embodiments. Special cases can be represented by specific values ​​of RI. For example, two special cases can be as follows: RI = 1, or other special values ​​or symbols, indicating that no interleaver or interleaving is used (because a block interleaver with only one row is equivalent to no interleaving); RI = 0, or another special value or symbol, indicating that a bit-inverted interleaver or interleaving is used. In the case of block interleaving, the number of columns of the block interleaver for a subset can be determined based on the subset size and the number of interleaver rows.

[0188] Table 1 below provides an example of a configuration or description format based on two vector parameters for fine-grained partial interleaving.

[0189] Table 1: Example of a bi-vector partial interleaving parameter table

[0190] Subset size <![CDATA[W1]]> <![CDATA[W2]]> <![CDATA[W3]]> …… Interleaver type <![CDATA[RI1]]> <![CDATA[RI2]]> <![CDATA[RI3]]> ……

[0191] Table 2 below is filled with parameter values, for example, where the codeword will be divided into three subsets with lengths of N / 4, N / 4 and N / 2 respectively, and the first subset will be interleaved by a block interleaver with 2 rows and (N / 4) / 2 = N / 8 columns, the second subset will be interleaved by another block interleaver with 4 rows and (N / 4) / 4 = N / 16 columns, and the third subset will not be interleaved.

[0192] Table 2: Exemplary parameters for partial interleaving of three subsets

[0193] 1 / 4 1 / 4 1 / 2 2 4 1

[0194] Table 3 below is filled with parameter values, for example, where the codeword will be divided into four subsets with lengths of N / 8, N / 8, N / 4 and N / 2 respectively, and the first subset is not interleaved, the second subset will be interleaved by a block interleaver with 8 rows, the third subset will be interleaved by another bit-inverting interleaver, and the fourth subset is not interleaved.

[0195] Table 3: Exemplary parameters for partial interleaving of four subsets

[0196] 1 / 8 1 / 8 1 / 4 1 / 2 1 8 0 1

[0197] Tables 1 through 3 are merely examples. The present invention is not limited in any way to these specific examples.

[0198] The various features have been described above; more detailed illustrative examples are provided below. Detailed examples are used for information bit reclamation, including and excluding partial interleaving, and demonstrate that information bit reclamation can be implemented independently of or in conjunction with partial interleaving. Similarly, partial interleaving can be implemented independently of or in conjunction with information bit reclamation. Information bit reclamation and partial interleaving each have their respective advantages, and they are independent of each other in no way.

[0199] Figure 14 This includes a trellis diagram illustrating the information bit recovery according to an exemplary (M=12, K=9) polar code, an information set with a mother code length of N=16 and I={4,7,8,11,12,13,14,15,16}, and a frozen set F={1,2,3,5,6,9,10}, for continuous puncturing of non-interleaved codewords. The puncturing set is P={1,2,3,4}.

[0200] In this punctured code construction, the fourth input bit u4 to the polarization code corresponds to the punctured coded bit in the punctured set, and in this sense can be considered and called the punctured information bit or punctured information bit index, which has zero capacity. Placing the information bit value at this bit index will result in a severe performance penalty. Therefore, the fourth bit u4 can be marked as a frozen bit, and / or bit index 4 can be marked as a frozen bit index.

[0201] For information bit reclamation, the most reliable frozen bit index identifies the non-zero capacity. This is the 10th bit. 10 Accordingly, the 10th bit u, which was previously a frozen bit, 10 It can be labeled as an information bit, for example, it can be referred to as a supplementary information bit. Equivalently, index 10 can be labeled as an information bit index, and can be referred to as, for example, a supplementary information bit index.

[0202] During encoding, the input or source bit that would have been placed at bit index 4 is now placed at bit index 10. Frozen bit values ​​(e.g., 0) are now placed at bit index 4.

[0203] The following example involves information bit recycling and partial interleaving.

[0204] Figure 15This includes a trellis diagram of information bit recovery and partial interleaving based on an exemplary (M=11, K=7) polar code, an information set with a mother code length of N=16 of I={7,8,12,13,14,15,16}, and a frozen set of F={1,2,3,4,5,6,9,10,11}. Partial interleaving puncturing is applied using the parameters in Table 4 below.

[0205] Table 4: Partial Interleaving Parameters for Illustrative Examples

[0206] 1 / 2 1 / 2 4 1

[0207] In this exemplary (N=16, M=11, K=7) polar code puncturing scheme, the puncture set is P={1,2,3,5,7}. In this example, block interleaving is applied to a first subset of size N·W1=N / 2=8, and the number of block interleaving rows RI1=4, and the number of block interleaving columns CI1=W1 / RI1=2. Figure 15 The result of the block interleaver shown in the middle, with the bits read out in column form, will correspond to the bit index set {1,3,5,7,2,4,6,8}. The downstream rate-matching operation can conveniently puncture the first five (N–M) bit positions of the partially interleaved codeword to perform the puncturing scheme of this exemplary code.

[0208] In this code construction, the 7th bit u7 is a punched information bit, and bit index 7 has zero capacity. Placing an information bit value at this bit index would result in a severe performance penalty. Therefore, the 7th bit u7, initially defined or identified as an information bit, will be redefined as a frozen bit. In other words, bit index 7, initially defined or identified as the information bit index in the information set, will be redefined as the frozen bit index in the frozen set.

[0209] The most reliable frozen bit index with non-zero capacity is identified; in this example, it is the 11th bit, u. 11 The bit index is 11. Correspondingly, the 11th bit u... 11 The bit marked as supplementary information, or in other words, bit index 11 becomes I. R The information bit index in the middle.

[0210] During encoding, input or source bit values ​​that would normally be placed at bit index 7 are now placed at bit index 11. Frozen bit values ​​(e.g., 0) are instead placed at bit index 7. The results of these operations are as follows: Figure 15 As shown on the right.

[0211] The third example involves more aggressive information bit reclamation and partial interleaving. Figure 16 It is a block diagram that includes a mesh diagram illustrating such an embodiment.

[0212] Figure 16 Consistent with the (M=10, K=6) polar code, the information set with a mother code length N=16 is I={8,12,13,14,15,16}, and the frozen set is F={1,2,3,4,5,6,7,9,10,11}. Partial interleaving puncturing is applied using the same parameters as in Table 4 above. In this exemplary polar code puncturing scheme, the puncturing set P={1,2,3,4,5,7}. For example... Figure 16 As shown in the block interleaver, the bits read out in column form will correspond to the bit index set {1,3,5,7,2,4,6,8}. The downstream rate-matching operation can conveniently puncture the first six (N–M) bit positions of the partially interleaved codeword to perform the puncturing scheme of this exemplary code.

[0213] In this example, bit 8, u8, is not a punched information bit and has a non-zero capacity. However, with a block size of N / 2 = 8, it belongs to the punched subset (bits 1:8), so the 8th bit index of u8 has a very low capacity. Placing an information bit value at this bit index would result in a significant performance penalty. Therefore, through more aggressive information bit recycling, bit 8, u8, is marked as a frozen bit, and bit index 8 becomes the frozen bit index.

[0214] In this example, the most reliable frozen bit index in the non-punched subset (bits 9:16) is identified as bit u. 11 The 11th bit index. Accordingly, the 11th bit u... 11 Marked as supplementary information bits, bit index 11 becomes I R The information bit index in the middle.

[0215] During encoding, the input or source bit value that would normally be placed at bit index 8 is now placed at bit index 11, while the frozen bit value (e.g., 0) is placed at bit index 8. The result of these operations is as follows: Figure 16 As shown on the right.

[0216] Various aspects of the invention have been described above and are illustrated by way of example in the accompanying drawings. Figure 17 This is a flowchart of a more general exemplary method according to an embodiment. On the left, Figure 17 1700 in the diagram illustrates operations or features that can be provided or supported at the encoder or transmitter-side device, and on the right, 1750, illustrates operations or features that can be provided or supported at the decoder or receiver-side device. For ease of reference, the following description... Figure 17 In the description, a device that can implement or support encoding and / or transmission features is referred to as a first communication device, and a device that can implement or support decoding and / or reception features is referred to as a second communication device. Embodiments may involve any one or both of these devices.

[0217] Referring first to 1700, from the perspective of the transmitting device, at 1708, the output of coded bits can involve transmitting coded bits. The coded bits can be output through or via any type of interface, including communication interfaces in the case of transmitting coded bits. The embodiments are not limited in any way to any particular type of interface. For example, at 1708, a first communication device can transmit coded bits to a second communication device in a wireless communication network. The coded bits are obtained by encoding the input bits using polar codes at 1704 and can be referred to as coded bits encoded using polar codes. For example, the encoding at 1704 can be implemented or executed by an encoder or processor. The encoding at 1704 can also include a subset of interleaved coded bits. The subset of bits used for interleaving includes bits not intended for transmission, such as bits intended for puncturing.

[0218] Polar codes include or provide bit indices for placing the values ​​of input bits before encoding. The bit indices include a first set of bit indices for placing the values ​​of input bits and a second set of bit indices for placing predetermined bit values. Placing bit values ​​on bit indices does not... Figure 17 It is shown separately and can be considered as part of the encoding at position 1706.

[0219] For example, at 1706, the encoder or rate matching module can perform rate matching to reduce the number of coded bits acquired by encoding at 1704. This could involve, for example, puncturing and / or shortening. According to embodiments disclosed herein, rate matching is performed to reduce the number of coded bits in a subset of the interleaved coded bits. The examples provided above relate to blocks of codewords, and partial interleaving of only, and not all, such blocks. Therefore, it should be understood that a block includes only a portion of the coded bits acquired by encoding the input bits. The reference herein to a subset of coded bits may more directly convey the property that the subset includes fewer coded bits than all the coded bits acquired by encoding at 1704. Features disclosed herein in the context of subsets of coded bits, code bits, or codewords can also or alternatively apply to blocks or portions of coded bits, code bits, code bits, or codewords.

[0220] Rate matching at 1706 is performed, at least partially, on an interleaved subset of the coded bits. This reduces the number of coded bits in the subset, which is then used to reduce the overall number of coded bits. Figure 9 As shown in the example, rate matching via puncturing in this example does not have to be performed only on the interleaved subset of the coded bits. Figure 9 The example in the text illustrates puncturing the non-interleaved subset c0 and the interleaved subset π(c1). A subset of the encoded bits can be completely punctured, as shown in the example. Figure 9c0 and Figure 10 As shown in π(c2), or partially drilled, such as Figure 8 As shown in the example, such as Figure 9 and Figure 10 As shown in π(c1). Therefore, performing rate matching or more generally reducing the number of coded bits involves reducing the number of coded bits in a subset that includes fewer coded bits than all coded bits, but it can also involve reducing the number of coded bits in other subsets.

[0221] Reducing the number of encoded bits does not require changing the number of encoded bits obtained through encoding at position 1704. Figure 17 In the example shown, rate matching is performed at 1706, the input bits are encoded to obtain encoded bits, and then the number of encoded bits is reduced. The fact that the number of encoded bits transmitted or output in some other way at 1708 is reduced does not change the number of encoded bits obtained through encoding at 1704. For example, the reduction in the number of encoded bits at 1706 does not reduce it to... Figures 7 to 10 The number of encoded bits obtained for each codeword c in the sequence.

[0222] At 1702, another operation that may involve acquiring coded bits is shown. For example, acquiring input bits may involve collecting or otherwise receiving data output from one or more devices and / or services, or accessing data in memory.

[0223] As shown at 1708, the method can also involve outputting a reduced number of coded bits. For example, after the reduction in the number of coded bits at 1706, the remaining reduced number of coded bits can be output for storage in memory and / or transmission.

[0224] Implementations may include any or all of the operations shown at 1700. For example, in some implementations, the method may involve encoding as shown at 1704, and transmitting or otherwise outputting a reduced number of encoded bits at 1708. Other implementations may involve transmitting or otherwise outputting a reduced number of encoded bits obtained by encoding input bits with polar codes at 1708. Such implementations are not mutually exclusive, and the method may involve acquisition, encoding, and rate matching at 1702, 1704, 1706, and also outputting encoded bits as shown at 1708.

[0225] It can also provide or support other features.

[0226] For example, the coded bits encoded by polar codes at 1704 can be sequential, and a subset can include coded bits that are not consecutive in that sequence. Figure 8An example is shown where discontinuous encoded bits in codeword c are aggregated into subsets and interleaved before puncturing.

[0227] In another embodiment, the coded bits encoded by polar codes at 1704 can also be sequential, but in this order, the subset used for interleaving is preceded and followed by other coded bits. See, for example, [link to documentation]. Figure 9 In this case, the second subset c1 is interleaved, and is preceded and followed by other coded bits. This can also be described as the coded bits to be interleaved being located or "sandwiched" between other coded bits.

[0228] Some embodiments may involve multiple interleavers, or more generally, multiple interleaved subsets of coded bits. For example, the subsets described above may be one of multiple subsets of coded bits obtained by encoding the input bits. Each subset includes a unique subset of coded bits less than all coded bits, such that there is no overlap between subsets, or in other words, no common coded bits in multiple subsets. The coded bits in all subsets to be interleaved include fewer than all coded bits. There may be other subsets of coded bits that are not interleaved, but according to embodiments herein, there is partial interleaving of coded bits, meaning that the combination of all coded bits in one or more subsets used for interleaving does not include all coded bits. For example, Figure 10 The multiple subsets c1 and c2 to be interleaved are shown, but these subsets together do not include all the coded bits in codeword c.

[0229] For multiple subsets used for interleaving, interleaving can involve interleaving the coded bits in each subset separately. For example, performing rate matching at 1706 could include performing rate matching on the coded bits to reduce the number of coded bits in each subset. The number of coded bits reduced from each subset can be the same or different. Figure 10 Examples are shown where the number of coded bits reduced from each subset varies.

[0230] Any of the various types of interleaving can be used to change the order of coded bits within a subset. Examples are provided elsewhere in this paper, including block interleaving and bit-inverted interleaving, either of which can be used to interleave subsets.

[0231] In embodiments involving multiple subsets to be interleaved, interleaving can involve the same or different types of interleaving of different subsets.

[0232] The embodiment referred to in this paper as information bit reclamation can be implemented in combination with embodiments that also involve partial interleaving. For example, the first set of bit indices described above (for placing the values ​​of input bits) may include a first bit index where the values ​​of input bits are placed, rather than a second bit index where the values ​​of input bits are placed, and the second bit index is affected by the number of coded bits in the reduced subset. This may be in Figure 12 and Figure 13 This is best illustrated in the example above. In this context, referring to the example above, the first bit index is the supplementary information set I. R The bit index in the middle, the second bit index is the punch information set I P The bit index in I. The input bit value is placed in I. R It is placed at the first bit index in I, instead of being placed in I. P The second bit index in the array.

[0233] This reallocation or repositioning of bit values ​​to different bit indices can be considered as follows: moving an input bit from a second bit index to a first bit index, copying an input bit from a second bit index to a first bit index, or redirecting an input bit from a second bit index to a first bit index, etc.

[0234] From the perspective of bit indexing, information bit recycling can be considered in the following forms: moving a first bit index from the second bit index set (frozen set) to the first bit index set (information set) to place the input bit value, or re-marking or reassigning the first bit index as an information bit index instead of a frozen bit index, etc. Similarly, from the perspective of the second bit index in the punched information set, information bit recycling can be considered in the following forms: moving the second bit index from the first bit index set (information set) to the second bit index set (frozen set), or re-marking or reassigning the second bit index as a frozen bit index instead of an information bit index.

[0235] As disclosed herein, another way to interpret or represent information bit recycling is that the encoding involves placing the value of the input bit at a bit index in a first set of bit indices (the information set used to place the value of the input bit), rather than at a second bit index affected by the number of encoded bits in the reduced subset.

[0236] In the example above, the first bit index is described based on a first bit index set (an information set for placing the value of the input bit) that includes the first bit index. Supplementary bit indices (such as the first bit index in this example) can be considered as part of the information set for placing the value of the input bit or as part of the aforementioned first bit index set. In another embodiment, supplementary bit indices can be considered as part of a different set of bit indices, such as the supplementary information set I referenced herein. R Therefore, the bit index of a polar code can also include a third set of bit indices, which includes the first bit index, where the value of the input bit is placed at the first bit index, instead of the value of the input bit being placed at the second bit index, which is affected by the number of coded bits in the reduced subset.

[0237] For example, in communication standards or specifications, I R It can be defined as I T A subset of the first bit index can also be defined as a separate set of bit indices. The former is an example of the first bit index set of a polar code that includes the first bit index, and the latter is an example of the bit indices of a polar code that also includes the third bit index set (including the first bit index).

[0238] More generally, the bit indices of a polar code may include one or more bit indices that are described by way of example as a first bit index herein, and one or more bit indices that are described by way of example as a second bit index herein.

[0239] Information bit recycling can involve recycling only information bits or bit indices that have zero capacity due to the reduction in the number of encoded bits. In other words, the second bit index referenced in the example above can correspond to the bit index of the encoded bits reduced from the subset.

[0240] In an embodiment also referred to herein as more aggressive information bit reclamation, one or more information bits or bit indices are also reclaimed. These information bits or bit indices do not directly correspond to coded bits that have been punched or otherwise reduced, but rather to coded bits that are within the same subset or block as the reduced coded bits. This can be considered a form of subset-based or subset-level information bit reclamation because the determination of whether to reclaim information bits or bit indices is made at the subset or block level rather than at the level of a single bit or bit index. Figure 16 An example is shown where u8 is recycled, but its directly corresponding encoded bit c8 is not punched.

[0241] Using the preceding example to further illustrate this type of information bit reclamation, the second bit index can correspond to the bit index of the coded bits reduced from the subset. The first bit index set (or the third bit index set, or more generally, the bit indexes of the polar code) can also include the third bit index, where the value of another input bit is placed, instead of the value of another input bit being placed at the fourth bit index, which corresponds to the index of one of the coded bits in the subset that has been reduced in number. Figure 16 In the example, the third bit index used to place the input bit value is index 11 in the right grid, and the fourth bit index where no input bit value is placed is index 8 in the left grid. 8 is also the index of one of the reduced-number coded bits in the subset. In this example, coded bit c8 is one of the reduced-number coded bits because c8 remains in the subset even after the number of coded bits in the subset has been reduced.

[0242] Other embodiments may involve additional, fewer, and / or different features. For example, information bit recycling may be implemented in conjunction with partial interleaving or separately.

[0243] Methods related to information bit retrieval may involve encoding input bits using polar codes to obtain multiple encoded bits and outputting a reduced number of encoded bits, as described in detail elsewhere in this document, and... Figure 17 Points 1704 and 1708 are illustrated by example. As in other embodiments, the polar code includes bit indices for placing the values ​​of the input bits before encoding, and the bit indices include a first set of bit indices for the values ​​of the input bits and a second set of bit indices for the predetermined bit values. The encoded bits include a subset containing fewer encoded bits than all encoded bits and is used to reduce the number of encoded bits.

[0244] The bit index includes a corresponding first bit index, at which the value of the corresponding input bit is placed, rather than at a corresponding second bit index, which corresponds to the bit index of each coded bit in the subset. One or more corresponding first bit indices may exist (three are shown by way of example). Figure 13 (The supplementary information set in the text), the value of the corresponding input bit is placed at the corresponding first bit index instead of the corresponding second bit index (where the three are shown by example). Figure 13On the punctured information set), the corresponding second bit index corresponds to the bit index of each coded bit in the subset. One or more corresponding first bit indices and corresponding second bit indices corresponding to the bit index of each coded bit in the subset are intended to convey what is referred to herein as radical information bit reclamation, wherein each information bit in the subset of punctured (reduced) information bits in the punctured (reduced) information set is reclaimed, regardless of whether its corresponding coded bit is punctured or otherwise reduced from the subset of coded bits.

[0245] The features disclosed herein may also be embodied in other forms, or alternatively. For example, the ordered sequence of polar code bit indices may be embodied or modified to reflect features related to the partial interleaving and / or information bit reclamation disclosed herein.

[0246] For example, one approach may involve obtaining an ordered sequence indicating multiple bit indices of a polar code ordered by rank (e.g., according to reliability), the multiple bit indices being used to place the values ​​of input bits, which are then encoded by the polar code to obtain multiple encoded bits. The bit indices include: a first set of bit indices with the highest rank according to the ordered sequence, used to place the values ​​of the input bits before encoding; and a second set of bit indices with lower rank than the highest rank according to the ordered sequence, used to place predetermined bit values. This approach may also involve, for example, encoding the input bits by the polar code according to the ordered sequence at 1704 to obtain multiple encoded bits; and, for example, outputting a reduced number of encoded bits at 1708. Other features disclosed herein may also be provided or supported in this approach, or alternatively.

[0247] The rank order indicated by the ordered sequence is used to reduce the number of coded bits. Therefore, the rank order is determined based on how the reduction of coded bits affects the bit index rank, in order to prioritize the placement of input bit values. Depending on which coded bits are punctured or otherwise reduced, some bit indices may become less reliable or rank lower, while others may become more reliable or rank higher. The rank can consider one or both of information bit recycling and interleaving to enable or support various features, as disclosed herein, through the use of ordered sequences.

[0248] Obtaining an ordered sequence can involve selecting from multiple available ordered sequences. For example, ordered sequences with different mother code lengths, transmission code lengths, puncturing patterns, etc., can be pre-generated and specified in a communication standard or specification, and then selected for encoding based on coding parameters or conditions. Another possible option for obtaining an ordered sequence involves modifying the base sequence, which indicates the bit indices of the polar codes in a ranked base order. The bit indices are used to place the values ​​of the input bits, which are used to encode multiple coded bits using the polar codes, and the ranked base order is used to output multiple coded bits. In other words, a base sequence can be modified without considering bit reduction, information bit recycling, or interleaving to obtain a sequence where the ranking order of the bit indices is to reduce the number of coded bits. A communication standard or specification can specify one or more base sequences and possible instructions for modifying one or more base sequences according to coding parameters or conditions. The reliability sequence Q = [Q1, Q2…Q] is given above. N ] is an example of a base sequence that indicates a bit index, ordered in ascending order of reliability.

[0249] At 1750, Figure 17 Various decoding and / or receiving correspondences for the feature shown at 1700 are illustrated. From the perspective of the receiving device, receiving at 1752 indicates receiving a reduced number of coded bits that have been encoded using polar codes. For example, receiving at 1752 could involve receiving coded bits from a first communication device via a second communication device in a wireless communication network. The coded bits can be received through or via any of a variety of types of interfaces, and the embodiments are not in any way limited to any particular type of interface.

[0250] As in other embodiments herein, the polar code includes bit indices for placing the values ​​of the input bits, and the bit indices include a first set of bit indices for the values ​​of the input bits and a second set of bit indices for predetermined bit values. The received reduced number of coded bits includes the remaining coded bits after reducing the number of coded bits in a subset of the interleaved set of all coded bits.

[0251] The decoding at 1754 is intended to illustrate the decoding of a reduced number of received coded bits to obtain the decoded input bits. For example, a decoder or processor can implement or perform the decoding at 1754.

[0252] In some embodiments, the decoder may not be a discrete device, but rather part of a logic block in silicon or an on-chip system used to decode and use the decoded input bits. In other embodiments, for example, as shown at 1756, the decoded input bits are output for processing and / or storage.

[0253] For example, refer to Figure 17The operation at 1700 in the document, any or all of the features described in the context of the encoder-side or transmitter-side method can also be applied to or have corresponding features in the decoder-side or receiver-side method. For example, any one or more of the following features may be provided or supported individually or in any combination in the decoder-side or receiver-side method:

[0254] The encoded bits encoded by polar codes are in sequence;

[0255] The subset includes coded bits that are not consecutive in the sequence;

[0256] In this order, the subset is preceded and followed by other coded bits;

[0257] Reducing the number of coded bits in the interleaved subset involves rate matching;

[0258] A subset includes one of several subsets of encoded bits;

[0259] Each subset includes a unique subset of coded bits less than all coded bits, and multiple subsets together include coded bits less than all coded bits;

[0260] Before reducing the number of coded bits in each subset of the subset, the coded bits in each subset of the multiple subsets of the coded bits are interleaved separately;

[0261] Before performing rate matching to reduce the number of coded bits in each subset of the subset, the coded bits in each subset of the multiple subsets of the coded bits are interleaved separately.

[0262] The subset is interleaved using either block interleaving or bit-inverted interleaving;

[0263] There are multiple subsets, each of which is interleaved using either block interleaving or bit-inverted interleaving;

[0264] The coded bits in different subsets are interleaved using different types of interleaving;

[0265] The first bit index set includes, or more generally, the bit index includes the first bit index, where the value of the input bit is placed at the first bit index, instead of the value of the input bit being placed at the second bit index, which is affected by the reduction in the number of encoded bits;

[0266] The bit index also includes a third bit index set, which includes the first bit index. The value of the input bit is placed at the first bit index, instead of the value of the input bit being placed at the second bit index, which is affected by the reduction in the number of encoded bits.

[0267] The second bit index corresponds to the bit index of the encoded bits reduced from the subset;

[0268] The first bit index set also includes a third bit index, or more generally, the bit index also includes a third bit index, where the value of another input bit is placed at the third bit index, instead of the value of another input bit being placed at the fourth bit index, which corresponds to the index of one of the coded bits in the subset of reduced number of coded bits;

[0269] The third bit index set also includes a third bit index, where the value of another input bit is placed at the third bit index, instead of the value of another input bit being placed at the fourth bit index, which corresponds to the index of one of the coded bits in the subset with a reduced number of coded bits.

[0270] Information bit retrieval can be implemented or supported in conjunction with or independently of partial interleaving. For example, in a standalone embodiment, the method may involve receiving a reduced number of coded bits encoded by a polar code at 1752. The polar code includes a plurality of bit indices for placing the values ​​of input bits, and the bit indices include a first set of bit indices for the values ​​of the input bits and a second set of bit indices for predetermined bit values. The received reduced number of coded bits includes the remaining coded bits after reducing the number of coded bits in a subset of coded bits less than all coded bits. The bit indices include a corresponding first bit index, where the value of the corresponding input bit is placed, rather than where the value of the corresponding input bit is placed, and the corresponding second bit index corresponds to the bit index of each coded bit in the subset. The method may also involve decoding the reduced number of coded bits at 1754 to obtain the decoded input bits.

[0271] Sequence-based methods (described from an encoding perspective in the example above) can have corresponding reception, decoding, and other features. One method may involve receiving a reduced number of coded bits encoded using a polar code, wherein the polar code includes multiple bit indices for placing the values ​​of input bits, the input bits being encoded to obtain multiple coded bits, the bit indices including: a first set of bit indices with the highest rank according to an ordered sequence, used to place the values ​​of the input bits before encoding; and a second set of bit indices with lower rank according to an ordered sequence, used to place predetermined bit values. The ordered sequence indicates multiple bit indices in rank order, the multiple bit indices being used to place the values ​​of the input bits, and the rank order being used to reduce the number of coded bits to a reduced number of coded bits. The method may also involve decoding the reduced number of coded bits to obtain decoded input bits. This type of sequence-based method is also related to... Figure 17The method shown is consistent, including receiving at 1752 and decoding at 1754.

[0272] The ordered sequence in this example can be obtained by selecting from an available sequence or by modifying the base sequence. The base sequence can indicate multiple bit indices of a polar code in ranked base order, which are used to place the values ​​of the input bits. The input bits are used to encode multiple coded bits using the polar code, where the ranked base order is used to output multiple coded bits, rather than outputting a reduced number of coded bits.

[0273] The embodiments may also involve other features or operations. For example, some embodiments may involve transmitting signaling that indicates any of a variety of parameters, such as any one or more of the following: MCS index, code length, code rate, puncturing pattern, base sequence, etc. The transmission of signaling may involve an encoder / encoding device or a transmitter / transmitting device that wants to transmit coded bits sending signaling to a decoder / decoder or receiver / receiving device. Transmission may also, or alternatively, involve a decoder / decoder or receiver / receiving device receiving signaling from an encoder / encoding device or a transmitter / transmitter. Signaling does not necessarily have to be between the communication devices that are sending or receiving coded bits, or only between communication devices. For example, a network device such as a gNB or base station may send signaling to configure parameters at one or more communication devices. Therefore, the method may involve a network device sending signaling, and an encoder / encoding device or transmitter / transmitting device receiving signaling from the network device, and / or a decoder / decoder or receiver / receiving device receiving signaling from the network device.

[0274] This invention includes various embodiments, not only method embodiments but also other embodiments, such as apparatus embodiments and embodiments relating to non-transitory computer-readable storage media. Embodiments may be combined individually or in combination with the features disclosed herein.

[0275] The apparatus may include a processor for causing the apparatus to perform the methods or operations disclosed herein by means of, for example, executing a program, or providing or supporting the features disclosed herein. The apparatus may also include a non-transitory computer-readable storage medium coupled to the processor for storing a program for execution by the processor. Figure 3 For example, processors 210, 260, and 276 may be or include one or more processors, and each memory 208, 258, and 278 is an example of a non-transitory computer-readable storage medium in ED 110 and TRP 170 and 172. The non-transitory computer-readable storage medium need not be provided solely in conjunction with a processor, but may, for example, be provided separately in a computer program product.

[0276] As an illustrative example, a program stored in a non-transitory computer-readable storage medium may include instructions for, or for causing a processor to: encode input bits using a polar code to obtain a plurality of encoded bits, wherein the polar code includes a plurality of bit indices for placing the value of the input bits before encoding, the bit indices including a first set of bit indices for the value of the input bits and a second set of bit indices for the predetermined bit values. The program may also include instructions for, or for causing a processor to: interleave a subset of encoded bits. This subset includes fewer encoded bits than all encoded bits and is used to reduce the number of encoded bits. In some embodiments, the program may also include instructions for, or for causing a processor to: output a reduced number of encoded bits.

[0277] Other embodiments can be similarly implemented using a program including instructions for or to cause the processor to: encode input bits using polar codes to obtain a plurality of encoded bits, and output a reduced number of encoded bits. The polar codes include a plurality of bit indices for placing the values ​​of the input bits before encoding, and the bit indices include a first set of bit indices for the values ​​of the input bits and a second set of bit indices for predetermined bit values. The encoded bits include a subset containing fewer encoded bits than all encoded bits, the subset being used to reduce the number of encoded bits. The bit indices include a corresponding first bit index, where the value of a corresponding input bit is placed at the corresponding first bit index, instead of the value of the corresponding input bit being placed at a corresponding second bit index, the corresponding second bit index corresponding to the bit index of each encoded bit in the subset. This illustrates a procedural embodiment of information bit retrieval as disclosed herein.

[0278] According to another embodiment of the program, the program includes instructions for, or for causing, a processor to: acquire an ordered sequence indicating multiple bit indices of polar codes in rank order, the multiple bit indices being used to place values ​​of input bits, the input bits being encoded by polar codes to obtain multiple encoded bits; encode the input bits by polar codes according to the ordered sequence to obtain multiple encoded bits; and output a reduced number of encoded bits. The bit indices include: a first set of bit indices with the highest rank according to the ordered sequence, used to place values ​​of input bits before encoding; and a second set of bit indices with lower rank according to the ordered sequence, used to place predetermined bit values, the rank order being used to reduce the number of encoded bits.

[0279] The apparatus embodiments are not limited to the examples of the above-described program-based embodiments. For example, the apparatus may also or alternatively include: an encoder for encoding input bits using polar codes to obtain encoded bits; an interleaver coupled to the encoder for interleaving a subset of the encoded bits; and an interface coupled to the encoder for outputting a reduced number of encoded bits. As in other embodiments, the polar codes include bit indices for placing the values ​​of the input bits before encoding, and the bit indices include a first set of bit indices for the values ​​of the input bits and a second set of bit indices for predetermined bit values. The subset of encoded bits interleaved by the interleaver includes fewer encoded bits than all encoded bits and is used to reduce the number of encoded bits.

[0280] Figure 18 This is a block diagram of an apparatus that can implement or support such embodiments. Exemplary apparatus 1800 includes a polar encoder 1802, an interleaver 1804 coupled to the polar encoder, a rate matching module 1806 coupled to the interleaver, and a recycled bit index selector 1808 coupled to the rate matching module and the polar encoder. Input bits for encoding are shown as input TBs or payload bits, and rate-matched encoded bits are shown as the output of the rate matching module 1806. An interface for transmitting or otherwise outputting a reduced number of encoded bits may be provided, incorporated into, or coupled to any one or more of the polar encoder 1802, interleaver 1804, and rate matching module 1806.

[0281] The encoding or transmitting side features or functions, as well as other features or functions described herein, can be implemented in any of a variety of ways, such as in one or more components of hardware, firmware, or execution software. This invention is not limited to any particular type of implementation; for example, implementation details may differ between different devices.

[0282] In the exemplary device 1800, the polar encoder 1802 is used, for example, by executing software, to encode bits to obtain encoded bits. The interleaver 1804 is used, for example, by executing software, to interleave a subset of the encoded bits. Uninterleaved encoded bits may be output by the interleaver 1804 in the order in which the polar encoder 1802 provides the uninterleaved encoded bits, or they may be provided by the polar encoder to the rate matching module 1806. Not all embodiments involve interleaving, therefore the interleaver 1804 is optional.

[0283] The rate matching module 1806 is used, for example by executing software, to perform rate matching, and may include: a circular buffer for storing encoded bits from the interleaver 1804, and / or possibly a polar encoder 1802 (in the case that non-interleaved encoded bits bypass the interleaver or that interleaving is not performed or is not supported).

[0284] The recycled bit index selector 1808 is used, for example by executing software, to implement or support information bit recycling by selecting an alternative bit index to place the input bit value for encoding by the polar encoder 1802, rather than selecting other bit indices affected by rate matching. The recycled bit index selector 1808 is another optional component. For example, in a sequence-based embodiment, information bit recycling is actually incorporated into the ordered sequence used by the polar encoder 1802, and the recycled bit index selector 1808 is not required.

[0285] Device 1800 is intended to be an illustrative example only. Embodiments are not in any way limited to the implementations shown. Device embodiments may include fewer, additional, and / or different components.

[0286] More generally, the apparatus or its components (e.g., encoder 1802 or processor) may be used, or the program may include instructions for or to cause the processor to: encode input bits to obtain a plurality of encoded bits. In some embodiments, the apparatus or its components (e.g., interleaver 1804 or processor) may be used, or the program may include instructions for or to cause the processor to: interleave encoded bits in a subset of encoded bits, the subset comprising fewer encoded bits than all encoded bits, and to reduce the number of encoded bits.

[0287] Such devices or their components (e.g., interfaces) can be used, or programs may include instructions for or to cause a processor to: output a reduced number of coded bits, for example, to transmit a reduced number of coded bits to a second communication device, such as in a wireless communication network, via a first communication device.

[0288] Embodiments associated with such devices or non-transitory computer-readable storage media may include any one or more of the following features, which are also discussed elsewhere herein:

[0289] The encoded bits encoded by polar codes are in sequence;

[0290] The subset includes coded bits that are not consecutive in the sequence;

[0291] In this order, the subset is preceded and followed by other coded bits;

[0292] The apparatus or its components (e.g., rate matching module 1806) may be used, or the program may include instructions for or to cause the processor to: perform rate matching to reduce the number of coded bits in a subset;

[0293] A subset includes one of several subsets of encoded bits;

[0294] Each subset of the multiple subsets includes a unique subset with fewer coded bits than all coded bits, and the multiple subsets together include fewer coded bits than all coded bits;

[0295] The apparatus or its components (e.g., interleaver 1804) may be used, or the program may include instructions for or to cause the processor to: interleave the coded bits in each subset of a plurality of subsets of coded bits, respectively;

[0296] The apparatus or its components (e.g., rate matching module 1806) may be used, or the program may include instructions for or to cause the processor to: perform rate matching to reduce the number of coded bits in each subset of the subset;

[0297] The apparatus or its components (e.g., interleaver 1804) may be used, or the program may include instructions that are used to or cause the processor to: perform either block interleaving or bit inversion interleaving;

[0298] The apparatus or its components (e.g., interleaver 1804) may be used, or the program may include instructions for or to cause the processor to: perform different types of interleaving on different subsets of a plurality of subsets;

[0299] The first bit index set, or more generally, the bit index may include the first bit index, where the value of the input bit is placed at the first bit index, rather than the value of the input bit being placed at the second bit index, which is affected by the number of coded bits in the reduced subset;

[0300] Encoding may involve placing the value of the input bit at a bit index in a first set of bit indices, rather than at a second bit index affected by the number of encoded bits in the reduced subset;

[0301] The bit index also includes a third bit index set, which includes the first bit index. The value of the input bit is placed at the first bit index, instead of the value of the input bit being placed at the second bit index, which is affected by the number of coded bits in the reduced subset.

[0302] The second bit index corresponds to the bit index of the encoded bits reduced from the subset;

[0303] The first set of bit indices, or more generally, the bit indices may also include a third bit index, where the value of another input bit is placed at the third bit index, rather than at the fourth bit index, which corresponds to the index of one of the coded bits in a subset of reduced numbers of coded bits;

[0304] The third bit index set also includes a third bit index, where the value of another input bit is placed at the third bit index, instead of the value of another input bit being placed at the fourth bit index, which corresponds to the index of one of the coded bits in the subset with a reduced number of coded bits;

[0305] In another embodiment, the apparatus includes an encoder, such as an 1802, and an interface. The encoder is used to encode input bits using polar codes to obtain a plurality of encoded bits, wherein the polar codes include a plurality of bit indices for placing the values ​​of the input bits before encoding, the bit indices including a first set of bit indices for the values ​​of the input bits and a second set of bit indices for predetermined bit values. The encoded bits include a subset containing fewer encoded bits than all encoded bits. This subset is used to reduce the number of encoded bits. The bit indices include a corresponding first bit index where the value of a corresponding input bit is placed, rather than a corresponding second bit index where the value of the corresponding input bit is placed, the corresponding second bit index corresponding to the bit index of each encoded bit in the subset. The interface is coupled to the encoder for outputting the reduced number of encoded bits.

[0306] According to another embodiment of the apparatus, an encoder (e.g., 1802) is used to acquire an ordered sequence and encode input bits using polar codes according to the ordered sequence to obtain multiple encoded bits. The ordered sequence indicates multiple bit indices of polar codes in rank order, and these bit indices are used to place the values ​​of the input bits, which are then encoded using polar codes to obtain the multiple encoded bits. The bit indices include: a first set of bit indices with the highest rank according to the ordered sequence, used to place the values ​​of the input bits before encoding; and a second set of bit indices with lower rank according to the ordered sequence, used to place predetermined bit values. The rank order is used to reduce the number of encoded bits.

[0307] The device may also include an interface coupled to the encoder for outputting a reduced number of encoded bits.

[0308] In some embodiments, the apparatus or its components (e.g., encoder 1802) may be used, or the program may include instructions for or to cause the processor to: obtain an ordered sequence by modifying the base sequence. The base sequence indicates multiple bit indices of a polar code in ranked base order, the multiple bit indices being used to place the values ​​of input bits, the input bits being used to encode by the polar code to obtain multiple encoded bits, and the ranked base order being used to output multiple encoded bits.

[0309] For decoder-side or receiver-side devices or computer program products that include a non-transitory computer-readable storage medium to support decoder-side or receiver-side operation, the device may be used, or the program may include instructions for or to cause a processor to: receive a reduced number of coded bits encoded by polar codes, and decode the coded bits to obtain decoded input bits. In another embodiment, the device includes: an interface for receiving a reduced number of coded bits encoded by polar codes; and a decoder coupled to the interface for decoding the reduced number of coded bits to obtain decoded input bits. The polar code includes a plurality of bit indices for placing values ​​of the input bits, and the bit indices include a first set of bit indices for the values ​​of the input bits and a second set of bit indices for predetermined bit values. The received reduced number of coded bits includes the remaining coded bits after reducing the number of coded bits by less than the number of coded bits in an interleaved subset of all coded bits. The reduction in the number of coded bits should occur after the input bits are encoded and before the received reduced number of coded bits are transmitted.

[0310] Embodiments associated with such devices or non-transitory computer-readable storage media may include any one or more of the following features, which are also discussed elsewhere herein:

[0311] The device or its components (e.g., an interface) may be used, or the program may include instructions for or to cause the processor to: receive a reduced number of coded bits from the first communication device via a second communication device in a wireless communication network;

[0312] The encoded bits encoded by polar codes are in sequence;

[0313] The subset includes coded bits that are not consecutive in the sequence;

[0314] In this order, the subset is preceded and followed by other coded bits;

[0315] For example, reducing the number of coded bits in the interleaved subset includes: rate matching by a rate matching module 1806, etc., before transmitting coded bits with a reduced number of bits;

[0316] A subset includes one of several subsets of encoded bits;

[0317] Each subset of the multiple subsets includes a unique subset with fewer coded bits than all coded bits, and the multiple subsets together include fewer coded bits than all coded bits;

[0318] Before reducing the number of coded bits in each subset of the subset, the coded bits in each subset of the multiple subsets are interleaved separately;

[0319] Before performing rate matching to reduce the number of coded bits in each subset of the subset, the coded bits in each subset of the multiple subsets of the coded bits are interleaved separately.

[0320] The subset is interleaved using either block interleaving or bit-inverted interleaving;

[0321] In embodiments with multiple subsets, each subset is interleaved using either block interleaving or bit-inverted interleaving;

[0322] In another embodiment with multiple subsets, the coded bits in different subsets of the multiple subsets are interleaved by different types of interleaving;

[0323] The first bit index set, or more generally, the bit index of the polar code, includes the first bit index, where the value of the input bit is placed at the first bit index, rather than the value of the input bit being placed at the second bit index, which is affected by the reduction in the number of encoded bits;

[0324] The bit index also includes a third bit index set, which includes the first bit index. The value of the input bit is placed at the first bit index, instead of the value of the input bit being placed at the second bit index, which is affected by the reduction in the number of encoded bits.

[0325] The second bit index corresponds to the bit index of the encoded bits reduced from the subset;

[0326] The first set of bit indices, or more generally, the bit indices of the polar codes, also includes a third bit index, where the value of another input bit is placed at the third bit index, rather than at the fourth bit index, which corresponds to the index of one of the coded bits in a subset of reduced numbers of coded bits;

[0327] The third bit index set also includes a third bit index, where the value of another input bit is placed at the third bit index, instead of the value of another input bit being placed at the fourth bit index, which corresponds to the index of one of the coded bits in the subset with a reduced number of coded bits.

[0328] In another embodiment of the apparatus, the apparatus includes an interface and a decoder. The interface is used to receive a reduced number of coded bits encoded by a polar code, and the decoder is coupled to the interface for decoding the reduced number of coded bits to obtain decoded input bits. The program may include instructions for or to cause the processor to: receive the reduced number of coded bits encoded by the polar code, and decode the reduced number of coded bits to obtain decoded input bits. In both examples, the polar code may include a plurality of bit indices for placing the values ​​of the input bits, wherein the bit indices include a first set of bit indices for the values ​​of the input bits and a second set of bit indices for predetermined bit values. The received reduced number of coded bits includes the bits remaining after reducing the number of coded bits in a subset of coded bits by less than the total number of coded bits. The bit indices include a corresponding first bit index, where the value of the corresponding input bit is placed at the corresponding first bit index, instead of the value of the corresponding input bit being placed at a corresponding second bit index, the corresponding second bit index corresponding to the bit index of each coded bit in the subset.

[0329] An interface according to another apparatus embodiment is used to receive a reduced number of coded bits encoded by a polar code. The apparatus may further include a decoder coupled to the interface for decoding the reduced number of coded bits to obtain decoded input bits. In a program embodiment, the program may include instructions for or to cause a processor to: receive a reduced number of coded bits encoded by a polar code, and decode the reduced number of coded bits to obtain decoded input bits. In any of these embodiments, the polar code may include a plurality of bit indices for placing values ​​of input bits used for encoding to obtain a plurality of coded bits, wherein the bit indices include: a first set of bit indices having the highest rank according to an ordered sequence for placing the values ​​of the input bits before encoding; and a second set of bit indices having lower rank according to an ordered sequence for placing predetermined bit values. The ordered sequence indicates a plurality of bit indices in rank order for placing the values ​​of the input bits, the rank order being used to reduce the number of coded bits to a reduced number of coded bits.

[0330] An ordered sequence can be obtained by modifying the base sequence, which indicates multiple bit indices of the polar code in ranked base order. These bit indices are used to place the values ​​of the input bits, which are then encoded using the polar code to obtain multiple encoded bits. The ranked base order is used to output the multiple encoded bits.

[0331] The apparatus embodiments are not limited in any way to a single device. For example, the system may include a first communication device and a second communication device. The first communication device may be used to transmit a reduced number of coded bits encoded by polar codes, and the second communication device may be used to receive the reduced number of coded bits from the first communication device and decode the reduced number of coded bits to obtain decoded input bits. As in other embodiments, the polar code may include a plurality of bit indices for placing the values ​​of the input bits, wherein the bit indices include a first set of bit indices for the values ​​of the input bits and a second set of bit indices for predetermined bit values, and the reduced number of coded bits includes the bits remaining after reducing the number of coded bits by less than the number of coded bits in an interleaved subset of all coded bits.

[0332] The first communication device in the system may also, or alternatively, implement, provide, or support other encoding-side or transmitting-side features disclosed herein, and similarly, the second communication device in the system may also, or alternatively, implement, provide, or support other decoding-side or receiving-side features disclosed herein.

[0333] More generally, other features disclosed herein may also be provided in the method, apparatus and / or system embodiments, either by way of alternatives.

[0334] The embodiments disclosed herein include various aspects of polar coding, including encoding and decoding.

[0335] The disclosed embodiments can provide a fundamental upgrade to polar codes and make polar codes applicable to a wider range of scenarios.

[0336] For example, the disclosed embodiments can be implemented as part of a channel coding scheme and therefore can be applied wherever channel coding is used. This covers a very wide range of scenarios. The flexibility provided by the embodiments disclosed herein helps to make the associated channel coding schemes particularly suitable for wireless communications.

[0337] Possible product deployments that can be implemented or combined with embodiments include network devices (e.g., base stations), access devices (e.g., UEs), robots, sensors, automobiles, drones, and satellites. Examples of service deployments include enhanced mobile broadband (eMBB), ultra-reliable low latency communications (URLLC), massive machine-type communications (mMTC) / Internet of Things (IoT), and automotive and industrial scenarios. Examples of network deployments include 5G+, 6G, WiFi, non-terrestrial networks (NTN), optical networks, distributed networks, and self-organizing networks. These are illustrative and non-limiting examples, and other deployments, implementations, or applications are possible.

[0338] Potential advantages of the embodiments disclosed herein include providing low-complexity and rate-compatible polar codes.

[0339] For example, partially interleaved puncturing, as disclosed in this paper, can help avoid severe performance penalties and provides low-complexity puncturing-only rate matching. It eliminates the need for complex online computations (DE / GA) involved in some existing methods and also avoids complex hybrid puncturing and shortening.

[0340] The information bit recycling disclosed in this article also helps to avoid the severe performance loss caused by transmission on zero-capacity subchannels.

[0341] The disclosed embodiments also include parametric descriptions, which are advantageous, for example, in providing concise descriptions to efficiently define fine-grained partial interleaving.

[0342] Although this invention pertains to illustrative embodiments, it is not intended to be interpreted in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to those skilled in the art upon reference to this specification.

[0343] Features disclosed herein in the context of any particular embodiment may also be implemented, or alternatively, in other embodiments. For example, method embodiments may also be implemented, or alternatively, in apparatus, system, and / or computer program product embodiments. Furthermore, although embodiments are described primarily in the context of methods and apparatus, other implementations are contemplated, for example, as instructions stored in one or more non-transitory computer-readable media. These media may store programs or instructions to perform any of the various methods consistent with the present invention.

[0344] Although aspects of the invention have been described with reference to specific features and embodiments thereof, various modifications and combinations may be made without departing from the scope of the invention. Therefore, the specification and drawings are to be regarded only as illustrative of some embodiments of the invention as defined by the appended claims, and any and all modifications, variations, combinations, or equivalents within the scope of the invention are contemplated. Although embodiments and potential advantages have been described in detail, various changes, substitutions, and alterations may be made without departing from the invention as defined by the appended claims. Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machines, articles of manufacture, compositions of matter, components, methods, and steps described in the specification. Based on the disclosure of the invention, those skilled in the art will readily understand that processes, machines, articles of manufacture, compositions of matter, components, methods, or steps (including those currently existing or later developed) that perform substantially the same functions or achieve substantially the same results as the corresponding embodiments described herein can be used according to the invention. Therefore, the appended claims are intended to include such processes, machines, articles of manufacture, compositions of matter, components, methods, or steps within their scope.

[0345] Furthermore, any module, component, or device executing instructions illustrated herein may include or otherwise access one or more non-transitory computer-readable or processor-readable storage media to store information, such as computer-readable or processor-readable instructions, data structures, program modules, and / or other data. A non-exhaustive list of examples of non-transitory computer-readable or processor-readable storage media includes magnetic tape cassettes, magnetic tape, disk storage or other magnetic storage devices, compact disc read-only memory (CD-ROM), digital video disc or digital versatile disc (DVD), and Blu-ray. Optical discs or other optical storage devices, volatile and non-volatile, removable and non-removable media implemented in any method or technology, random-access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other storage technologies. Any of these non-transitory computer-readable or processor-readable storage media may be part of a device or may be accessed or connected to a device. Any application or module described herein may be implemented using computer-readable and executable instructions, or a processor may be stored or otherwise stored by such non-transitory computer-readable or processor-readable storage media.

Claims

1. A method, characterized in that, include: Input bits are encoded using polar codes to obtain multiple encoded bits. The polar codes include multiple bit indices for placing the value of the input bits before encoding. These bit indices include a first set of bit indices for the value of the input bits and a second set of bit indices for predetermined bit values. A subset of the encoded bits is interleaved, the subset containing fewer encoded bits than all encoded bits, the subset being used to reduce the number of encoded bits; The number of encoded bits is reduced.

2. The method according to claim 1, characterized in that, Also includes: In a wireless communication network, the reduced number of encoded bits are transmitted from a first communication device to a second communication device.

3. The method according to claim 1 or 2, characterized in that, The coded bits encoded by the polar code are arranged in order, and the subset includes coded bits that are not consecutive in the order.

4. The method according to claim 1 or 2, characterized in that, The coded bits encoded by the polar code are arranged in order, wherein the subset is preceded and followed by other coded bits.

5. The method according to any one of claims 1 to 4, characterized in that, Also includes: Rate matching is performed to reduce the number of coded bits in the subset.

6. The method according to any one of claims 1 to 4, characterized in that, The subset comprises one subset from a plurality of subsets of the coded bits, each subset comprising a unique subset containing fewer coded bits than all coded bits, and the plurality of subsets together comprising fewer coded bits than all coded bits. The interleaving includes interleaving the coded bits in each of the plurality of subsets of the coded bits, the plurality of subsets including the subsets.

7. The method according to claim 5, characterized in that, The subset comprises one subset from a plurality of subsets of the coded bits, each subset comprising a unique subset containing fewer coded bits than all coded bits, and the plurality of subsets together comprising fewer coded bits than all coded bits. The interleaving includes interleaving the coded bits in each of the plurality of subsets of the coded bits, wherein the plurality of subsets includes the subsets. The execution includes performing rate matching on the encoded bits to reduce the number of encoded bits in each subset of the subsets.

8. The method according to any one of claims 1 to 7, characterized in that, The interleaving includes either block interleaving or bit inversion interleaving.

9. The method according to claim 6 or 7, characterized in that, The interleaving includes different types of interleaving for different subsets of the plurality of subsets.

10. The method according to any one of claims 1 to 9, characterized in that, The first bit index set includes a first bit index, where the value of the input bit is placed at the first bit index, instead of the value of the input bit being placed at a second bit index, the second bit index being affected by reducing the number of coded bits in the subset.

11. The method according to any one of claims 1 to 9, characterized in that, The bit index further includes a third set of bit indices, which includes a first bit index, where the value of the input bit is placed at the first bit index, instead of the value of the input bit being placed at a second bit index, which is affected by reducing the number of encoded bits in the subset.

12. The method according to claim 10 or 11, characterized in that, The second bit index corresponds to the bit index of the encoded bits reduced from the subset.

13. The method according to claim 10, characterized in that, The second bit index corresponds to the bit index of the reduced number of encoded bits from the subset. The first set of bit indices also includes a third bit index, on which the value of another input bit is placed, instead of on which the value of the other input bit is placed, a fourth bit index, which corresponds to the index of one of the reduced number of encoded bits in the subset.

14. The method according to claim 11, characterized in that, The second bit index corresponds to the bit index of the reduced number of encoded bits from the subset. The third bit index set also includes a third bit index on which the value of another input bit is placed, instead of the value of the other input bit being placed on a fourth bit index, which corresponds to the index of one of the reduced number of encoded bits in the subset.

15. A method, characterized in that, include: Input bits are encoded using polar codes to obtain multiple encoded bits. The polar codes include multiple bit indices for placing the value of the input bits before encoding. These bit indices include a first set of bit indices for the value of the input bits and a second set of bit indices for predetermined bit values. The encoded bits include a subset, which contains fewer encoded bits than all encoded bits, and the subset is used to reduce the number of encoded bits. The bit index includes a corresponding first bit index, at which the value of the corresponding input bit is placed, instead of at which the value of the corresponding input bit is placed, at a corresponding second bit index, the second bit index corresponding to the bit index of each coded bit in the subset. The method further includes: The number of encoded bits is reduced.

16. A method, characterized in that, include: An ordered sequence is obtained, the ordered sequence indicating multiple bit indices of a polar code in rank order, the multiple bit indices being used to place the values ​​of input bits, the input bits being used to encode multiple encoded bits by the polar code, the bit indices comprising: a first set of bit indices having the highest rank according to the ordered sequence, used to place the values ​​of the input bits before encoding; and a second set of bit indices having lower rank according to the ordered sequence, below the highest rank, used to place predetermined bit values, the rank order being used to reduce the number of encoded bits; The input bits are encoded using the polar code according to the ordered sequence to obtain the plurality of encoded bits; The number of encoded bits is reduced.

17. The method according to claim 16, characterized in that, Obtaining the ordered sequence further includes modifying the base sequence, the base sequence indicating the plurality of bit indices of the polar code in a ranked base order, the plurality of bit indices being used to place the value of the input bit, the input bit being used to encode the plurality of encoded bits by the polar code, and the ranked base order being used to output the plurality of encoded bits.

18. A method, characterized in that, include: Receive a reduced number of encoded bits encoded using a polar code, the polar code comprising a plurality of bit indices for placing the value of an input bit, the bit indices comprising a first set of bit indices for the value of the input bit and a second set of bit indices for a predetermined bit value. The number of received reduced coded bits includes the remaining bits after the number of coded bits reduced is less than the number of coded bits in the interleaved subset of all coded bits. The method further includes: The reduced number of encoded bits are decoded to obtain the decoded input bits.

19. The method according to claim 18, characterized in that, The receiving includes: a second communication device in a wireless communication network receiving the reduced number of coded bits from a first communication device.

20. The method according to claim 18 or 19, characterized in that, The coded bits encoded by the polar code are arranged in order, and the subset includes coded bits that are not consecutive in the order.

21. The method according to claim 18 or 19, characterized in that, The coded bits encoded by the polar code are arranged in order, wherein the subset is preceded and followed by other coded bits.

22. The method according to any one of claims 18 to 21, characterized in that, Reducing the number of coded bits in the interleaved subset includes performing rate matching.

23. The method according to any one of claims 18 to 21, characterized in that, The subset comprises one subset from a plurality of subsets of the coded bits, each subset comprising a unique subset containing fewer coded bits than all coded bits, and the plurality of subsets together comprising fewer coded bits than all coded bits. Specifically, before reducing the number of coded bits in each subset of the subsets, the coded bits in each subset of the plurality of subsets of the coded bits are interleaved, and the plurality of subsets include the subsets.

24. The method according to claim 22, characterized in that, The subset comprises one subset from a plurality of subsets of the coded bits, each subset comprising a unique subset containing fewer coded bits than all coded bits, and the plurality of subsets together comprising fewer coded bits than all coded bits. Specifically, before performing rate matching to reduce the number of coded bits in each subset of the subsets, the coded bits in each subset of the plurality of subsets of the coded bits are interleaved, and the plurality of subsets include the subsets.

25. The method according to any one of claims 18 to 22, characterized in that, The subset is interleaved using either block interleaving or bit inversion interleaving.

26. The method according to claim 23 or 24, characterized in that, Each subset is interleaved using either block interleaving or bit-inverted interleaving.

27. The method according to claim 23 or 24, characterized in that, The encoded bits in different subsets of the plurality of subsets are interleaved using different types of interleaving.

28. The method according to any one of claims 18 to 27, characterized in that, The first bit index set includes a first bit index, where the value of the input bit is placed at the first bit index, instead of the value of the input bit being placed at a second bit index, which is affected by the reduction in the number of encoded bits.

29. The method according to any one of claims 18 to 27, characterized in that, The bit index further includes a third set of bit indices, which includes a first bit index, where the value of the input bit is placed at the first bit index, instead of the value of the input bit being placed at a second bit index, which is affected by the reduction in the number of encoded bits.

30. The method according to claim 28 or 29, characterized in that, The second bit index corresponds to the bit index of the encoded bits reduced from the subset.

31. The method according to claim 28, characterized in that, The second bit index corresponds to the bit index of the reduced number of encoded bits from the subset. The first set of bit indices also includes a third bit index, on which the value of another input bit is placed, instead of on which the value of the other input bit is placed, a fourth bit index, which corresponds to the index of one of the reduced number of encoded bits in the subset.

32. The method according to claim 29, characterized in that, The second bit index corresponds to the bit index of the reduced number of encoded bits from the subset. The third bit index set also includes a third bit index on which the value of another input bit is placed, instead of the value of the other input bit being placed on a fourth bit index, which corresponds to the index of one of the reduced number of encoded bits in the subset.

33. A method, characterized in that, include: Receive a reduced number of encoded bits encoded using a polar code, the polar code comprising a plurality of bit indices for placing the value of an input bit, the bit indices comprising a first set of bit indices for the value of the input bit and a second set of bit indices for a predetermined bit value. The number of received reduced coded bits includes the remaining bits after the reduction of the number of coded bits from the subset of the coded bits that is less than the total number of coded bits. The bit index includes a corresponding first bit index, at which the value of the corresponding input bit is placed, instead of at which the value of the corresponding input bit is placed, at a corresponding second bit index, the second bit index corresponding to the bit index of each coded bit in the subset. The method further includes: The reduced number of encoded bits are decoded to obtain the decoded input bits.

34. A method, characterized in that, include: The system receives a reduced number of encoded bits encoded using a polar code, the polar code comprising a plurality of bit indices for placing the values ​​of input bits used for encoding to obtain the plurality of encoded bits. The bit indices comprise: a first set of bit indices with the highest rank according to an ordered sequence, used to place the values ​​of the input bits before encoding; and a second set of bit indices with lower rank according to the ordered sequence than the highest rank, used to place predetermined bit values. The ordered sequence indicates the plurality of bit indices in rank order, the plurality of bit indices being used to place the value of the input bit, the rank order being used to reduce the number of encoded bits to the reduced number of encoded bits. The method further includes: The reduced number of encoded bits are decoded to obtain the decoded input bits.

35. The method according to claim 34, characterized in that, The ordered sequence is obtained by modifying the base sequence, which indicates the plurality of bit indices of the polar code in a ranked base order. The plurality of bit indices are used to place the value of the input bit, which is used to encode the plurality of encoded bits by the polar code. The ranked base order is used to output the plurality of encoded bits.

36. An apparatus, characterized in that, Includes a processor for causing the device to perform the method according to any one of claims 1 to 17.

37. An apparatus, characterized in that, include: An encoder is used to encode an input bit using a polar code to obtain a plurality of encoded bits, the polar code including a plurality of bit indices for placing the value of the input bit before encoding, the bit indices including a first set of bit indices for the value of the input bit and a second set of bit indices for a predetermined bit value; An interleaver, coupled to the encoder, is used to interleave a subset of the coded bits, the subset comprising fewer coded bits than all coded bits, the subset being used to reduce the number of coded bits; An interface, coupled to the encoder, is used to output a reduced number of encoded bits.

38. The apparatus according to claim 37, characterized in that, The interface is used for: The reduced number of encoded bits are transmitted from the first communication device to the second communication device in the wireless communication network.

39. The apparatus according to claim 37 or 38, characterized in that, The coded bits encoded by the polar code are arranged in order, and the subset includes coded bits that are not consecutive in the order.

40. The apparatus according to claim 37 or 38, characterized in that, The coded bits encoded by the polar code are arranged in order, in which the subset is preceded and followed by other coded bits.

41. The apparatus according to any one of claims 37 to 40, characterized in that, Also used for: Rate matching is performed to reduce the number of coded bits in the subset.

42. The apparatus according to any one of claims 37 to 40, characterized in that, The subset comprises one subset from a plurality of subsets of the coded bits, each subset comprising a unique subset containing fewer coded bits than all coded bits, and the plurality of subsets together comprising fewer coded bits than all coded bits. The interleaver is used to interleave the coded bits in each of the plurality of subsets of the coded bits, the plurality of subsets including the subsets.

43. The apparatus according to claim 41, characterized in that, The subset comprises one subset from a plurality of subsets of the coded bits, each subset comprising a unique subset containing fewer coded bits than all coded bits, and the plurality of subsets together comprising fewer coded bits than all coded bits. The interleaving includes interleaving the coded bits in each of the plurality of subsets of the coded bits, wherein the plurality of subsets includes the subsets. The execution includes performing rate matching on the encoded bits to reduce the number of encoded bits in each subset of the subsets.

44. The apparatus according to any one of claims 37 to 43, characterized in that, The interleaver is used to perform either block interleaving or bit inversion interleaving.

45. The apparatus according to claim 42 or 43, characterized in that, The interleaver is used to perform different types of interleaving on different subsets of the plurality of subsets.

46. ​​The apparatus according to any one of claims 37 to 45, characterized in that, The first bit index set includes a first bit index, where the value of the input bit is placed at the first bit index, instead of the value of the input bit being placed at a second bit index, the second bit index being affected by reducing the number of coded bits in the subset.

47. The apparatus according to any one of claims 37 to 45, characterized in that, The bit index further includes a third set of bit indices, which includes a first bit index, where the value of the input bit is placed at the first bit index, instead of the value of the input bit being placed at a second bit index, which is affected by reducing the number of encoded bits in the subset.

48. The apparatus according to claim 46 or 47, characterized in that, The second bit index corresponds to the bit index of the encoded bits reduced from the subset.

49. The apparatus according to claim 46, characterized in that, The second bit index corresponds to the bit index of the reduced number of encoded bits from the subset. The first set of bit indices also includes a third bit index, on which the value of another input bit is placed, instead of on which the value of the other input bit is placed, a fourth bit index, which corresponds to the index of one of the reduced number of encoded bits in the subset.

50. The apparatus according to claim 47, characterized in that, The second bit index corresponds to the bit index of the reduced number of encoded bits from the subset. The third bit index set also includes a third bit index on which the value of another input bit is placed, instead of the value of the other input bit being placed on a fourth bit index, which corresponds to the index of one of the reduced number of encoded bits in the subset.

51. An apparatus, characterized in that, include: An encoder is used to encode input bits using polar codes to obtain a plurality of encoded bits. The polar codes include a plurality of bit indices for placing the value of the input bits before encoding. The bit indices include a first set of bit indices for the value of the input bits and a second set of bit indices for predetermined bit values. The encoded bits include a subset, which contains fewer encoded bits than all encoded bits, and the subset is used to reduce the number of encoded bits. The bit index includes a corresponding first bit index, at which the value of the corresponding input bit is placed, instead of at which the value of the corresponding input bit is placed, at a corresponding second bit index, the second bit index corresponding to the bit index of each coded bit in the subset. The device further includes: An interface, coupled to the encoder, is used to output a reduced number of encoded bits.

52. An apparatus, characterized in that, include: An encoder is used to acquire an ordered sequence and encode input bits using polar codes based on the ordered sequence to obtain multiple encoded bits. The ordered sequence indicates multiple bit indices of the polar code in rank order, the multiple bit indices being used to place the value of the input bit, the input bit being used to encode the polar code to obtain multiple encoded bits, the bit indices comprising: a first set of bit indices having the highest rank according to the ordered sequence, used to place the value of the input bit before encoding; and a second set of bit indices having lower rank according to the ordered sequence, below the highest rank, used to place predetermined bit values, the rank order being used to reduce the number of encoded bits; The device further includes: An interface, coupled to the encoder, is used to output a reduced number of encoded bits.

53. The apparatus according to claim 52, characterized in that, The encoder is used to obtain the ordered sequence by modifying the base sequence, the base sequence indicating the plurality of bit indices of the polar code in a ranked base order, the plurality of bit indices being used to place the value of the input bit, the input bit being used to encode the plurality of encoded bits by the polar code, and the ranked base order being used to output the plurality of encoded bits.

54. An apparatus, characterized in that, Includes a processor for causing the device to perform the method according to any one of claims 18 to 35.

55. An apparatus, characterized in that, include: An interface for receiving a reduced number of encoded bits encoded using a polar code, the polar code comprising a plurality of bit indices for placing the value of an input bit, the bit indices comprising a first set of bit indices for the value of the input bit and a second set of bit indices for a predetermined bit value. The number of received reduced coded bits includes the remaining bits after the number of coded bits reduced is less than the number of coded bits in the interleaved subset of all coded bits. The device further includes: A decoder, coupled to the interface, is used to decode the reduced number of encoded bits to obtain decoded input bits.

56. The apparatus according to claim 55, characterized in that, The interface is used to receive the reduced number of coded bits from the first communication device via a second communication device in a wireless communication network.

57. The apparatus according to claim 55 or 56, characterized in that, The coded bits encoded by the polar code are arranged in order, and the subset includes coded bits that are not consecutive in the order.

58. The apparatus according to claim 55 or 56, characterized in that, The coded bits encoded by the polar code are arranged in order, wherein the subset is preceded and followed by other coded bits.

59. The apparatus according to any one of claims 55 to 58, characterized in that, Reducing the number of coded bits in the interleaved subset includes performing rate matching.

60. The apparatus according to any one of claims 55 to 58, characterized in that, The subset comprises one subset from a plurality of subsets of the coded bits, each subset comprising a unique subset containing fewer coded bits than all coded bits, and the plurality of subsets together comprising fewer coded bits than all coded bits. Specifically, before reducing the number of coded bits in each subset of the subsets, the coded bits in each subset of the plurality of subsets of the coded bits are interleaved, and the plurality of subsets include the subsets.

61. The apparatus according to claim 59, characterized in that, The subset comprises one subset from a plurality of subsets of the coded bits, each subset comprising a unique subset containing fewer coded bits than all coded bits, and the plurality of subsets together comprising fewer coded bits than all coded bits. Specifically, before performing rate matching to reduce the number of coded bits in each subset of the subsets, the coded bits in each subset of the plurality of subsets of the coded bits are interleaved, and the plurality of subsets include the subsets.

62. The apparatus according to any one of claims 53 to 59, characterized in that, The subset is interleaved using either block interleaving or bit inversion interleaving.

63. The apparatus according to claim 60 or 61, characterized in that, Each subset is interleaved using either block interleaving or bit-inverted interleaving.

64. The apparatus according to claim 60 or 61, characterized in that, The encoded bits in different subsets of the plurality of subsets are interleaved using different types of interleaving.

65. The apparatus according to any one of claims 55 to 64, characterized in that, The first set of bit indices includes a first bit index, where the value of the input bit is placed at the first bit index, instead of the value of the input bit being placed at a second bit index, which is affected by the reduction in the number of encoded bits.

66. The apparatus according to any one of claims 55 to 64, characterized in that, The bit index further includes a third set of bit indices, which includes a first bit index, where the value of the input bit is placed at the first bit index, instead of the value of the input bit being placed at a second bit index, which is affected by the reduction in the number of encoded bits.

67. The apparatus according to claim 65 or 66, characterized in that, The second bit index corresponds to the bit index of the encoded bits reduced from the subset.

68. The apparatus according to claim 65, characterized in that, The second bit index corresponds to the bit index of the reduced number of encoded bits from the subset. The first set of bit indices also includes a third bit index, on which the value of another input bit is placed, instead of on which the value of the other input bit is placed, a fourth bit index, which corresponds to the index of one of the reduced number of encoded bits in the subset.

69. The apparatus according to claim 66, characterized in that, The second bit index corresponds to the bit index of the reduced number of encoded bits from the subset. The third bit index set also includes a third bit index on which the value of another input bit is placed, instead of the value of the other input bit being placed on a fourth bit index, which corresponds to the index of one of the reduced number of encoded bits in the subset.

70. An apparatus, characterized in that, include: An interface for receiving a reduced number of encoded bits encoded using a polar code, the polar code comprising a plurality of bit indices for placing the value of an input bit, the bit indices comprising a first set of bit indices for the value of the input bit and a second set of bit indices for a predetermined bit value. The number of received reduced coded bits includes the remaining bits after the reduction of the number of coded bits from a subset of the total number of coded bits. The bit index includes a corresponding first bit index, at which the value of the corresponding input bit is placed, instead of at which the value of the corresponding input bit is placed, at a corresponding second bit index, the second bit index corresponding to the bit index of each coded bit in the subset. The device further includes: A decoder, coupled to the interface, is used to decode the reduced number of encoded bits to obtain decoded input bits.

71. An apparatus, characterized in that, include: An interface is provided for receiving a reduced number of encoded bits encoded using a polar code, the polar code comprising multiple bit indices for placing the values ​​of input bits used for encoding to obtain multiple encoded bits. The bit indices include: a first set of bit indices with the highest rank according to an ordered sequence, used to place the values ​​of the input bits before encoding; and a second set of bit indices with lower rank according to the ordered sequence than the highest rank, used to place predetermined bit values. The ordered sequence indicates the plurality of bit indices in rank order, the plurality of bit indices being used to place the value of the input bit, the rank order being used to reduce the number of encoded bits to the reduced number of encoded bits. The device further includes: A decoder, coupled to the interface, is used to decode the reduced number of encoded bits to obtain decoded input bits.

72. The apparatus according to claim 71, characterized in that, The ordered sequence is obtained by modifying the base sequence, which indicates the plurality of bit indices of the polar code in a ranked base order. The plurality of bit indices are used to place the value of the input bit, which is used to encode the plurality of encoded bits by the polar code. The ranked base order is used to output the plurality of encoded bits.

73. A computer program product, characterized in that, The invention includes a non-transitory computer-readable medium storing a program for execution by a processor, the program including instructions for performing the method according to any one of claims 1 to 35.

74. A system, characterized in that, include: A first communication device is configured to transmit a reduced number of coded bits encoded by a polar code, the polar code including a plurality of bit indices for placing the value of an input bit, the bit indices including a first set of bit indices for the value of the input bit and a second set of bit indices for a predetermined bit value, the reduced number of coded bits including bits remaining after reducing the number of coded bits in an interleaved subset of all coded bits; A second communication device is configured to receive the reduced number of encoded bits from the first communication device and decode the reduced number of encoded bits to obtain decoded input bits.

Images