Semiconductor device, electronic chip, and electronic apparatus
Patent Information
- Application Number
- CN202380096090.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-03-23
- Publication Date
- 2025-11-11
AI Technical Summary
SiC MOSFET has the problems of large reverse recovery loss and bipolar degradation when conducting reverse conduction, resulting in increased conduction loss and forward resistance.
A semiconductor device is designed, including a first MOSFET cell region and a second MOSFET cell region. The first gate electrode is in contact with the source electrode. The second gate electrode and the source electrode are isolated by a dielectric material. The first channel doped The impurity region and the second channel doping region realize the bidirectional conduction characteristics of the semiconductor device, reduce reverse recovery loss and avoid bipolar degradation.
It effectively reduces the reverse recovery loss of SiC MOSFET, avoids bipolar degradation, reduces conduction loss and power consumption, and avoids high-temperature process problems and increase in conduction resistance caused by integrated Schottky diodes.
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Abstract
Description
Semiconductor devices, electronic chips and electronic equipment Technical Field
[0001] The present application relates to the field of semiconductor technology, and more particularly, to a semiconductor device, an electronic chip, and an electronic device in the field of semiconductor technology. Background Art
[0002] With the rapid development of semiconductor technology, semiconductor devices such as metal-oxide-semiconductor field-effect transistors (MOSFETs) have been widely used. Silicon carbide (SiC) is a semiconductor material with advantages such as a wide bandgap, a high critical breakdown electric field, high thermal conductivity, and a high electron saturation drift velocity. MOSFETs made from SiC (referred to as SiC MOSFETs) can exhibit characteristics such as high breakdown voltage and low on-state voltage drop. Furthermore, due to the high switching speed characteristics of SiC MOSFETs, both conduction and switching losses are low.
[0003] However, when conducting in the reverse direction, SiC MOSFETs suffer from high reverse recovery losses and bipolar degradation. The high reverse recovery losses are manifested in the following: when current flows through the PN junction of the SiC MOSFET's body diode, the SiC MOSFET enters a bipolar conduction state, which takes a long time to transition from the on state to the off state, resulting in high reverse recovery losses. Bipolar degradation is manifested in the fact that the carrier recombination process easily excites defects such as dislocations in the SiC material's base crystal plane, increasing the SiC MOSFET's forward resistance and the voltage drop across the body diode, leading to increased conduction losses and body diode losses.
[0004] Therefore, there is an urgent need for a technical solution that can reduce the reverse recovery loss of SiC MOSFET and avoid bipolar degradation of SiC MOSFET.
[0005] Summary of the Invention
[0006] The embodiments of the present application provide a semiconductor device, an electronic chip, and an electronic device, which can not only reduce the reverse recovery loss of the semiconductor device, but also avoid bipolar degradation of the semiconductor device.
[0007] In a first aspect, an embodiment of the present application provides a semiconductor device, which may include a first MOSFET cell region and a second MOSFET cell region.
[0008] Optionally, the first MOSFET cell region and the second MOSFET cell region may share a substrate, epitaxial layer, and source. The substrate, epitaxial layer, and source may be stacked sequentially along a first direction. In other words, the first direction may be the direction in which the substrate, epitaxial layer, and source are stacked sequentially.
[0009] The first MOSFET cell region may further include a first gate. The first gate may be located inside the source, and the first gate may be in contact with the source.
[0010] Similarly, the second MOSFET cell region may further include a second gate. The second gate may also be located within the source, and a dielectric material such as SiC may be provided between the second gate and the source. In other words, the dielectric material may isolate the second gate from the source, ensuring that the second gate and the source are not in contact.
[0011] When the semiconductor device provided in the present application is reversely conducted, the first gate is in contact with the source, and a dielectric material can be provided between the second gate and the source. The semiconductor device can be easily turned on and enter a unipolar conduction state, thereby reducing the reverse recovery loss of the semiconductor device and avoiding bipolar degradation of the semiconductor device.
[0012] In a possible implementation, the first MOSFET cell region may further include a first channel doping region. The second MOSFET cell region may further include a second channel doping region.
[0013] The first channel doping region and the second channel doping region may both be located within the epitaxial layer, with the first channel doping region located below the first gate electrode and the second channel doping region located below the second gate electrode. Surfaces of the first channel doping region and the second channel doping region close to the source electrode may be flush with a surface of the epitaxial layer close to the source electrode.
[0014] It can be understood that when the semiconductor device is conducting in the forward direction, since the first gate is in contact with the source, the first channel doping region is not turned on and does not participate in the forward current. However, the second gate and the source are not in contact through the dielectric material, so the second channel doping region is turned on and participates in the forward current. It can be seen that the semiconductor device can achieve forward conduction through the second channel doping region, that is, the semiconductor device has a forward conduction characteristic. When the semiconductor device is conducting in the reverse direction, since the first gate is in contact with the source, the first channel doping region is turned on and participates in the forward current. However, the second gate and the source are not in contact through the dielectric material, so the second channel doping region is not turned on and does not participate in the reverse current. It can be seen that the semiconductor device can achieve reverse conduction through the first channel doping region, that is, the semiconductor device has a reverse conduction characteristic. Therefore, the present application can achieve forward conduction and reverse conduction of the semiconductor device through the first channel doping region and the second channel doping region, so that the semiconductor device has a bidirectional conduction characteristic.
[0015] In one example, the doping concentration of the first channel doping region can be lower than the doping concentration of the second channel doping region, which can make the threshold voltage of the first MOSFET cell region lower than the threshold voltage of the second MOSFET cell region, so that the first channel doping region is easily turned on, and the semiconductor device enters a unipolar conduction state, which can further reduce the reverse recovery loss of the semiconductor device and avoid bipolar degradation of the semiconductor device.
[0016] In another example, the size of the first channel doping region in the second direction may be larger than the size of the second channel doping region in the second direction. The first channel doping region having a relatively larger size in the second direction can reduce the influence of the depletion layer expansion on the first channel doping region during the reverse withstand voltage process, thereby reducing the reverse withstand voltage leakage current of the first MOSFET cell region, thereby reducing the power consumption of the semiconductor device. The second direction may be perpendicular to the first direction.
[0017] In another possible implementation, the first MOSFET cell region may further include a first P-type base region, and the second MOSFET cell region may further include a second P-type base region.
[0018] The first P-type base region and the second P-type base region may both be located within the epitaxial layer, with the first P-type base region located below the first channel doping region, and the second P-type base region located below the second channel doping region. It is conceivable that the first P-type base region may contact the first channel doping region and the epitaxial layer. Similarly, the second P-type base region may contact the second channel doping region and the epitaxial layer.
[0019] Furthermore, the junction depth of the first P-type base region can be greater than the junction depth of the second P-type base region. The first P-type base region with a relatively large junction depth can weaken the influence of the expansion of the depletion layer on the first channel doping region during the reverse withstand voltage process, and can also reduce the reverse withstand voltage leakage current of the first MOSFET cell region, thereby reducing the power consumption of the semiconductor device.
[0020] Optionally, the doping concentration of the first P-type base region can be greater than the doping concentration of the second P-type base region, the doping concentration of the first P-type base region can be greater than the doping concentration of the first channel doping region, and the doping concentration of the second P-type base region can be greater than the doping concentration of the second channel doping region. Compared with the second P-type base region, the first P-type base region with a relatively higher doping concentration can reduce the influence of the depletion layer expansion on the first channel doping region 6 during the reverse withstand voltage process, and can also reduce the reverse withstand voltage leakage current of the first MOSFET cell region 100, thereby reducing the power consumption of the semiconductor device 1000.
[0021] In yet another possible implementation, the first MOSFET cell region may further include a first JFET region. The second MOSFET cell region may further include a second JFET region.
[0022] Both the first JFET region and the second JFET region can be located within the epitaxial layer. The first JFET region can be located in the spacer region between the first P-type base region, and the second JFET region can be located in the spacer region between the second P-type base region. It is conceivable that the first JFET region can contact the first channel doping region and can also contact the first P-type base region. Similarly, the second JFET region can contact the second channel doping region and can also contact the second P-type base region.
[0023] Optionally, the size of the first JEFT region in the second direction can be smaller than the size of the second JEFT region in the second direction. The first JEFT region with a relatively small size in the second direction can weaken the influence of the depletion layer expansion on the first channel doping region during the reverse withstand voltage process, and can also reduce the reverse withstand voltage leakage current of the first MOSFET cell region, thereby reducing the power consumption of the semiconductor device.
[0024] In another possible implementation, the first MOSFET cell region may further include a first P+ doping region and a first N+ doping region. The first P+ doping region and the first N+ doping region may both be located within the first P-type base region, and the first N+ doping region may be located between the first channel doping region and the first P+ doping region. It is conceivable that the first N+ doping region may contact the first channel doping region, and may also contact the first P+ doping region, the first P-type base region, and the source.
[0025] Similarly, the second MOSFET cell region may further include a second P+ doping region and a second N+ doping region. The second P+ doping region and the second N+ doping region may both be located within the second P-type base region, and the second N+ doping region may be located between the second channel doping region and the second P+ doping region. It is conceivable that the second N+ doping region may contact the second channel doping region, and may also contact the second P+ doping region, the second P-type base region, and the source.
[0026] In another possible implementation, the first MOSFET cell region may further include a first gate dielectric layer and a first interlayer dielectric layer. Similarly, the second MOSFET cell region may further include a second gate dielectric layer and a second interlayer dielectric layer. Both the first interlayer dielectric layer and the second interlayer dielectric layer are made of a dielectric material such as silicon oxide.
[0027] The first gate dielectric layer may be stacked between the first gate electrode and the epitaxial layer, and the first interlayer dielectric layer may be disposed between the source electrode and the first gate electrode.
[0028] Similarly, the second gate dielectric layer may be stacked between the second gate electrode and the epitaxial layer, and the second interlayer dielectric layer may be disposed between the source electrode and the second gate electrode.
[0029] That is, the epitaxial layer, the first gate dielectric layer, the first gate electrode, the first interlayer dielectric layer, and the source electrode can be stacked, and the epitaxial layer, the second gate dielectric layer, the first gate electrode, the second interlayer dielectric layer, and the source electrode can be stacked. It is conceivable that the first interlayer dielectric layer may not completely wrap around the surface of the first gate electrode near the source electrode to achieve contact between the first gate electrode and the source electrode. The second interlayer dielectric layer may completely wrap around the surface of the second gate electrode near the source electrode to achieve non-contact between the second gate electrode and the source electrode.
[0030] In another possible implementation, both the substrate and the epitaxial layer may be made of semiconductor materials such as silicon carbide (SiC). Of course, the substrate and the epitaxial layer may also be made of other semiconductor materials besides SiC, which is not limited in this application.
[0031] In a second aspect, the present application provides an electronic chip, which may include a passive device and a semiconductor device provided by the first aspect and its possible implementations, wherein the passive device may be electrically connected to the semiconductor device.
[0032] Optionally, passive components may include resistors, capacitors, etc., which are not limited in this application.
[0033] In a third aspect, the present application provides an electronic device, which may include a circuit board and an electronic chip provided by the second aspect and its possible implementations, wherein the electronic chip may be provided on the circuit board.
[0034] Optionally, the electronic device may be a mobile phone, a computer, a wearable smart device, etc., which is not limited in this application.
[0035] It should be understood that the second and third aspects of this application are consistent with the technical solutions of the first aspect of this application, and the beneficial effects achieved by each aspect and the corresponding feasible implementation methods are similar and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS
[0036] In order to more clearly illustrate the technical solutions in the present application or the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.
[0037] FIG1 provides a schematic structural diagram of a semiconductor device 1000 according to an embodiment of the present application;
[0038] FIG2 provides another schematic structural diagram of a semiconductor device 1000 according to an embodiment of the present application;
[0039] FIG3 provides another schematic structural diagram of a semiconductor device 1000 according to an embodiment of the present application;
[0040] FIG4 provides another schematic structural diagram of a semiconductor device 1000 according to an embodiment of the present application;
[0041] FIG5 provides another schematic structural diagram of a semiconductor device 1000 according to an embodiment of the present application;
[0042] FIG6 provides another schematic structural diagram of a semiconductor device 1000 according to an embodiment of the present application;
[0043] FIG7 provides another schematic structural diagram of a semiconductor device 1000 according to an embodiment of the present application;
[0044] FIG8 provides another schematic structural diagram of a semiconductor device 1000 according to an embodiment of the present application;
[0045] FIG9 provides another schematic structural diagram of a semiconductor device 1000 according to an embodiment of the present application;
[0046] In the figure, 1-substrate, 2-epitaxial layer, 3-first gate, 4-second gate, 5-source, 6-first channel doping region, 7-second channel doping region, 8-first P-type base region, 9-second P-type base region, 10-first JFET region, 11-second JFET region, 12a-first P+ doping region, 12b-second P+ doping region, 13a-first N+ doping region, 13b-second N+ doping region, 14a-first gate dielectric layer, 14b-second gate dielectric layer, 15a-first interlayer dielectric layer, 15b-second interlayer dielectric layer, 13-drain, 100-first MOSFET cell region, 200-second MOSFET cell region. DETAILED DESCRIPTION
[0047] The technical solution in this application will be described below with reference to the accompanying drawings.
[0048] To make the objectives, technical solutions, and advantages of this application more clear, the technical solutions of this application will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments of this application, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of this application.
[0049] The terms "first," "second," and the like in the description, embodiments, claims, and drawings of this application are used solely for descriptive purposes and are not to be construed as indicating or implying relative importance or order. Furthermore, the terms "including," "having," and any variations thereof are intended to cover non-exclusive inclusions, such as, for example, inclusion of a series of steps or units. A method, system, product, or apparatus is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0050] It should be understood that in this application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.
[0051] With the rapid development of semiconductor technology, semiconductor devices such as metal-oxide-semiconductor field-effect transistors (MOSFETs) have been widely used. Silicon carbide (SiC) is a semiconductor material with advantages such as a wide bandgap, a high critical breakdown electric field, high thermal conductivity, and a high electron saturation drift velocity. MOSFETs made from SiC (referred to as SiC MOSFETs) can exhibit characteristics such as high breakdown voltage and low on-state voltage drop. Furthermore, due to the high switching speed characteristics of SiC MOSFETs, both conduction and switching losses are low.
[0052] However, when conducting in the reverse direction, SiC MOSFETs suffer from high reverse recovery losses and bipolar degradation. The high reverse recovery losses are manifested in that current flows through the PN junction of the SiC MOSFET's body diode, causing the SiC MOSFET to enter a bipolar conduction state. This results in a long time required to transition from the on state to the off state, resulting in high reverse recovery losses. Bipolar degradation is manifested in that the carrier recombination process easily excites defects such as dislocations in the SiC material's base crystal plane, increasing the SiC MOSFET's forward resistance and the voltage drop across the body diode. This results in high conduction losses and body diode losses, which in turn leads to high operating losses in the SiC MOSFET.
[0053] To address these shortcomings, related technologies offer semiconductor devices that integrate Schottky barrier diodes (SBDs). When the semiconductor device is reverse-conducting, current flows through the SBD rather than the PN junction of the body diode within the semiconductor device. Therefore, the unipolar conduction characteristics of the SBD can be utilized to reduce the reverse recovery loss of the semiconductor device and avoid bipolar degradation.
[0054] However, integrating SBDs requires additional high-temperature processes, which can easily lead to problems such as deterioration of the ohmic contact characteristics of semiconductor devices. Furthermore, integrating SBDs reduces the channel conduction area of semiconductor devices, increasing their on-resistance and, in turn, causing higher conduction losses.
[0055] To overcome the above shortcomings, an embodiment of the present application provides a semiconductor device. As shown in FIG1 , a semiconductor device 1000 may include a first MOSFET cell region 100 and a second MOSFET cell region 200 .
[0056] Optionally, the first MOSFET cell region 100 and the second MOSFET cell region 200 may share a substrate 1, epitaxial layer 2, and source 5. The substrate 1, epitaxial layer 2, and source 5 may be stacked sequentially along a first direction. In other words, the first direction may be the direction in which the substrate 1, epitaxial layer 2, and source 5 are stacked sequentially. With respect to FIG. 1 , the first direction may be a vertical direction.
[0057] The substrate 1 and epitaxial layer 2 can both be made of semiconductor materials such as silicon carbide (SiC). Of course, the substrate 1 and epitaxial layer 2 can also be made of other semiconductor materials besides SiC, which is not limited in this embodiment of the present application. The semiconductor device provided in this embodiment of the present application is described using a SiC MOSFET as an example.
[0058] 1 , the first MOSFET cell region 100 may further include a first gate 3 . The first gate 3 may be located inside the source, and the first gate 3 may be in contact with the source 5 .
[0059] Similarly, the second MOSFET cell region 200 may further include a second gate 4. The second gate 4 may also be located inside the source 5, and a dielectric material (i.e., the second interlayer dielectric layer 15b in FIG. 1 ) may be provided between the second gate 4 and the source 5. In other words, the dielectric material may isolate the second gate 4 from the source 5, thereby preventing the second gate 4 from contacting the source 5.
[0060] In the semiconductor device 1000 provided in the embodiment of the present application, the first gate 3 is in contact with the source 5, and the second gate 4 is not in contact with the source 5 through a dielectric material. Since the first gate 3 is short-circuited with the source 5, when the semiconductor device 1000 is reverse-conducted, the P-type base region of the semiconductor device 1000 causes the channel doping region in the semiconductor device 100 to be conductive through the liner bias effect, thereby causing the semiconductor device 1000 to enter a unipolar conduction state, thereby reducing the reverse recovery loss of the semiconductor device 1000 and avoiding bipolar degradation of the semiconductor device 1000.
[0061] In addition, compared with the integrated SBD of related technologies, the embodiments of the present application do not introduce additional high-temperature processes, and therefore will not cause problems such as poor ohmic contact characteristics of the semiconductor device, and will not reduce the channel conduction area of the semiconductor device, thereby avoiding an increase in the on-resistance of the semiconductor device, thereby reducing the conduction loss of the semiconductor device.
[0062] As shown in FIG1 , the first MOSFET cell region 100 and the second MOSFET cell region 200 may also share a drain 13. The drain 13 may be stacked with the substrate 1 and located on a surface of the substrate 1 away from the epitaxial layer 2. In other words, the drain 13 in FIG1 may be located on the lower surface of the substrate 1.
[0063] In some embodiments, referring to FIG1 , the first MOSFET cell region 100 may further include a first channel doping region 6 , and the second MOSFET cell region may further include a second channel doping region 7 .
[0064] The first channel doping region 6 and the second channel doping region 7 may both be located inside the epitaxial layer 2, with the first channel doping region 6 located below the first gate 3, and the second channel doping region 7 located below the second gate 4. Surfaces of the first channel doping region 6 and the second channel doping region 7 close to the source 5 (i.e., upper surfaces of the first channel doping region 6 and the second channel doping region 7 in FIG1 ) may be flush with the surface of the epitaxial layer 2 close to the source 5.
[0065] As can be understood, when the semiconductor device 1000 is forward conducting, since the first gate 3 is in contact with the source 5, the first channel doping region 6 is not turned on and does not participate in the forward current. However, since the second gate 4 and the source 5 are not in contact via the dielectric material, the second channel doping region 7 is turned on and participates in the forward current. It can be seen that the semiconductor device 1000 can achieve forward conduction through the second channel doping region 7, that is, current flows from the drain 13 to the source 5, as shown in Figure 2. In other words, the semiconductor device 1000 has a forward conducting characteristic.
[0066] It is also understandable that when the semiconductor device 1000 is conducting in the reverse direction, since the first gate 3 is in contact with the source 5, the first channel doping region 6 is turned on and participates in the reverse current flow. However, since the second gate 4 and the source 5 are not in contact via the dielectric material, the second channel doping region 7 is not turned on and does not participate in the reverse current flow. It can be seen that the semiconductor device 1000 can achieve reverse conduction through the first channel doping region 6, that is, current flows from the source 5 to the drain 13, as shown in Figure 3. In other words, the semiconductor device 1000 has a reverse conduction characteristic.
[0067] Therefore, in the embodiment of the present application, the first channel doping region 6 and the second channel doping region 7 can realize forward conduction and reverse conduction of the semiconductor device 1000 , so that the semiconductor device 1000 has a bidirectional conduction characteristic.
[0068] In one example, the doping concentration of the first channel doping region 6 can be lower than the doping concentration of the second channel doping region 7, which can make the threshold voltage of the first MOSFET cell region 100 lower than the threshold voltage of the second MOSFET cell region 200, so that the first channel doping region 6 is easily turned on, and the semiconductor device 1000 enters a unipolar conduction state, which can further reduce the reverse recovery loss of the semiconductor device 1000 and avoid bipolar degradation of the semiconductor device 1000.
[0069] In another example, a direction perpendicular to the first direction is defined as the second direction. Since the first direction is defined as the direction in which the substrate 1, epitaxial layer 2, and source 5 are stacked in sequence, that is, the vertical direction in FIG1 , the second direction can be the horizontal direction in FIG1 .
[0070] Optionally, as shown in FIG4 , the size of the first channel doping region 6 in the second direction may be greater than the size of the second channel doping region 7 in the second direction. In other words, the width of the first channel doping region 6 may be greater than the width of the second channel doping region 7. The relatively large width of the first channel doping region 6 can reduce the effect of the depletion layer expansion on the first channel doping region 6 during the reverse withstand voltage process, thereby reducing the reverse withstand voltage leakage current of the first MOSFET cell region 100, thereby reducing the power consumption of the semiconductor device 1000.
[0071] In other embodiments, the first MOSFET cell region 100 in the embodiment of the present application may further include a first P-type base region 8, and the second MOSFET cell region 200 may further include a second P-type base region 9, as shown in FIG. 1 to FIG. 4 .
[0072] The first P-type base region 8 and the second P-type base region 9 may both be located inside the epitaxial layer 2, with the first P-type base region 8 located below the first channel doping region 6, and the second P-type base region 9 located below the second channel doping region 7. It is conceivable that the first P-type base region 8 may be in contact with the first channel doping region 6 and the epitaxial layer 2. Similarly, the second P-type base region 9 may be in contact with the second channel doping region 7 and the epitaxial layer 2.
[0073] Furthermore, as shown in Figure 5, the junction depth of the first P-type base region 8 can be greater than the junction depth of the second P-type base region 9. The first P-type base region 8 with a relatively large junction depth can weaken the influence of the depletion layer expansion on the first channel doping region 6 during the reverse withstand voltage process, and can also reduce the reverse withstand voltage leakage current of the first MOSFET cell region 100, thereby reducing the power consumption of the semiconductor device 1000.
[0074] In some further embodiments, the first MOSFET cell region 100 in the present application may further include a first JFET region 10. The second MOSFET cell region 200 may further include a second JFET region 11, as shown in FIG. 1 to FIG. 5 .
[0075] The first JFET region 10 and the second JFET region 11 may both be located within the epitaxial layer 2. The first JFET region 10 may be located in the spacer region of the first P-type base region 8, and the second JFET region 11 may be located in the spacer region of the second P-type base region 9. It is conceivable that the first JFET region 10 may be in contact with the first channel doping region 6 and may also be in contact with the first P-type base region 8. Similarly, the second JFET region 11 may be in contact with the second channel doping region 7 and may also be in contact with the second P-type base region 9.
[0076] Optionally, as shown in Figure 6, the size of the first JEFT region 10 in the second direction can be smaller than the size of the second JEFT region 11 in the second direction, that is, the width of the first JEFT region 10 can be smaller than the width of the second JEFT region 11. The first JEFT region 10 with a relatively small width can weaken the influence of the depletion layer expansion on the first channel doping region 6 during the reverse withstand voltage process, and can also reduce the reverse withstand voltage leakage current of the first MOSFET cell region 100, thereby reducing the power consumption of the semiconductor device 1000.
[0077] In one example, in Figures 1 to 6 , the doping type of the first P-type base region 8, the second P-type base region 9, the first channel doping region 6, and the second channel doping region 7 can be the same. For example, the first P-type base region 8, the second P-type base region 9, the first channel doping region 6, and the second channel doping region 7 can all include P-type dopants such as aluminum and boron.
[0078] In another example, the doping concentration of the first P-type base region 8 can be greater than the doping concentration of the first channel doping region 6, the doping concentration of the second P-type base region 9 can be greater than the doping concentration of the second channel doping region 7, and the doping concentration of the first P-type base region 8 can be greater than the doping concentration of the second P-type base region 9. The first P-type base region 8 with a relatively large doping concentration can weaken the influence of the depletion layer expansion on the first channel doping region 6 during the reverse withstand voltage process, and can also reduce the reverse withstand voltage leakage current of the first MOSFET cell region 100, thereby reducing the power consumption of the semiconductor device 1000.
[0079] In some embodiments, as shown in FIG. 1 to FIG. 6 , the first MOSFET cell region 100 may further include a first P+ doping region 12 a and a first N+ doping region 13 a .
[0080] For example, the first P+ doping region 12a and the first N+ doping region 13a may both be located within the first P-type base region 8, and the first N+ doping region 13a may be located between the first channel doping region 6 and the first P+ doping region 12a. It is conceivable that the first N+ doping region 13a may be in contact with the first channel doping region 6, and may also be in contact with the first P+ doping region 12a, the first P-type base region 8, and the source 5.
[0081] Similarly, the second MOSFET cell region 200 may further include a second P+ doping region 12 b and a second N+ doping region 13 b.
[0082] For example, the second P+ doping region 12b and the second N+ doping region 13b may both be located within the second P-type base region 9, and the second N+ doping region 13b may be located between the second channel doping region 7 and the second P+ doping region 12b. It is conceivable that the second N+ doping region 13b may be in contact with the second channel doping region 7, and may also be in contact with the second P+ doping region 12b, the second P-type base region 9, and the source 5.
[0083] In some other embodiments, the first MOSFET cell region 100 may further include a first gate dielectric layer 14a and a first interlayer dielectric layer 15a. Similarly, the second MOSFET cell region 100 may further include a second gate dielectric layer 14b and a second interlayer dielectric layer 15b, as shown in FIG1 to FIG6.
[0084] Optionally, the first gate dielectric layer 14a may be stacked between the first gate 3 and the epitaxial layer 2, and the second gate dielectric layer 14b may be stacked between the second gate 4 and the epitaxial layer 2. The first interlayer dielectric layer 15a may be disposed between the source 5 and the first gate 3, and the second interlayer dielectric layer 15b may be disposed between the source 5 and the second gate 4.
[0085] That is, the epitaxial layer 2, the first gate dielectric layer 14a, the first gate electrode 3, the first interlayer dielectric layer 15a, and the source electrode 5 can be stacked, and the epitaxial layer 2, the second gate dielectric layer 14b, the first gate electrode 4, the second interlayer dielectric layer 15b, and the source electrode 5 can be stacked. It is conceivable that the first interlayer dielectric layer 15a may not completely wrap around the surface of the first gate electrode 3 near the source electrode 5 to achieve contact between the first gate electrode 3 and the source electrode 5. The second interlayer dielectric layer 15b may completely wrap around the surface of the second gate electrode 4 near the source electrode 5 to achieve non-contact between the second gate electrode 4 and the source electrode 5.
[0086] For example, the semiconductor device 1000 provided in the embodiment of the present application may include a plurality of first MOSFET cell regions 100 and a plurality of second MOSFET cell regions 200. All first MOSFET cell regions 100 and all second MOSFET cell regions 200 may share a substrate 1, an epitaxial layer 2, a source 5, and a drain 13.
[0087] Each first MOSFET cell region 100 may include a first electrode 3, a first channel doping region 6, a first P-type base region 8, a first JFET region 10, a first P+ doping region 12a, a first N+ doping region 13a, a first gate dielectric layer 14a and a first interlayer dielectric layer 15a.
[0088] Similarly, each second MOSFET cell region 200 may include a second electrode 4, a second channel doping region 7, a second P-type base region 9, a second JFET region 11, a second P+ doping region 12b, a second N+ doping region 13b, a second gate dielectric layer 14b and a second interlayer dielectric layer 15b.
[0089] In one example, the semiconductor device 1000 may include two first MOSFET cell regions 100 and two second MOSFET cell regions 200. The two first MOSFET cell regions 100 and the two second MOSFET cell regions 200 may be spaced apart, as shown in FIG7 .
[0090] In another example, the semiconductor device 1000 may include one first MOSFET cell region 100 and three second MOSFET cell regions 200 , as shown in FIG. 8 .
[0091] In yet another example, the semiconductor device 1000 may include three first MOSFET cell regions 100 and one second MOSFET cell region 200 , as shown in FIG. 9 .
[0092] The embodiment of the present application further provides an electronic chip, which may include a passive component and the semiconductor device 1000 , wherein the passive component may be electrically connected to the semiconductor device 1000 .
[0093] Optionally, passive components may include resistors, capacitors, etc., which are not limited in the embodiments of the present application.
[0094] The embodiment of the present application further provides an electronic device, which may include a circuit board and the above-mentioned electronic chip, wherein the electronic chip may be arranged on the circuit board.
[0095] Optionally, the electronic device may be a mobile phone, a computer, a wearable smart device, etc., which is not limited in the embodiments of the present application.
[0096] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.
Claims
1. A semiconductor device, characterized in that: including a first MOSFET cell region and a second MOSFET cell region; The first MOSFET cell region and the second MOSFET cell region share a substrate, an epitaxial layer and a source electrode, and the substrate, the epitaxial layer and the source electrode are stacked along a first direction; The first MOSFET cell region further includes a first gate, the first gate is located inside the source, and the first gate is in contact with the source; The second MOSFET cell region further includes a second gate, the second gate is located inside the source, and a dielectric material is provided between the second gate and the source.
2. The semiconductor device according to claim 1, wherein: The first MOSFET cell region further includes a first channel doping region, and the second MOSFET cell region further includes a second channel doping region; The first channel doping region and the second channel doping region are both located inside the epitaxial layer, and the first channel doping region is located below the first gate, and the second channel doping region is located below the second gate.
3. The semiconductor device according to claim 2, characterized in that The doping concentration of the first channel doping region is less than the doping concentration of the second channel doping region.
4. The semiconductor device according to claim 2 or 3, characterized in that: A size of the first channel doping region in a second direction is greater than a size of the second channel doping region in the second direction; wherein the second direction is perpendicular to the first direction.
5. The semiconductor device according to any one of claims 2 to 4, characterized in that The first MOSFET cell region further includes a first P-type base region, and the second MOSFET cell region further includes a second P-type base region; The first P-type base region and the second P-type base region are both located inside the epitaxial layer, and the first P-type base region is located below the first channel doping region, and the second P-type base region is located below the second channel doping region.
6. The semiconductor device according to claim 5, characterized in that The junction depth of the first P-type base region is greater than the junction depth of the second P-type base region.
7. The semiconductor device according to claim 5 or 6, characterized in that: The doping concentration of the first P-type base region is greater than the doping concentration of the second P-type base region.
8. The semiconductor device according to any one of claims 5 to 7, characterized in that The first MOSFET cell region further includes a first JFET region, and the second MOSFET cell region further includes a second JFET region; The first JFET region and the second JFET region are both located inside the epitaxial layer, and the first JFET region is located in a spacing region of the first P-type base region, and the second JFET region is located in a spacing region of the second P-type base region.
9. The semiconductor device according to claim 8, characterized in that A size of the first JEF region in a second direction is smaller than a size of the second JEF region in the second direction; wherein the second direction is perpendicular to the first direction.
10. The semiconductor device according to any one of claims 5 to 9, characterized in that The doping concentration of the first P-type base region is greater than the doping concentration of the first channel doping region; The doping concentration of the second P-type base region is greater than the doping concentration of the second channel doping region.
11. The semiconductor device according to any one of claims 5 to 10, characterized in that: The first MOSFET cell region further includes a first P+ doping region and a first N+ doping region; the first P+ doping region and the first N+ doping region are both located inside the first P-type base region, and the first N+ doping region is located between the first channel doping region and the first P+ doping region; The second MOSFET cell region also includes a second P+ doping region and a second N+ doping region; the second P+ doping region and the second N+ doping region are both located inside the second P-type base region, and the second N+ doping region is located between the second channel doping region and the second P+ doping region.
12. The semiconductor device according to any one of claims 5 to 10, characterized in that: The first MOSFET cell region further includes a first gate dielectric layer and a first interlayer dielectric layer; the first gate dielectric layer is disposed between the first gate and the epitaxial layer, and the first interlayer dielectric layer is disposed between the source and the first gate; The second MOSFET cell region further includes a second gate dielectric layer and a second interlayer dielectric layer; the second gate dielectric layer is arranged between the second gate and the epitaxial layer, and the second interlayer dielectric layer is arranged between the source and the second gate; The first interlayer dielectric layer and the second interlayer dielectric layer both use the dielectric material.
13. The semiconductor device according to any one of claims 1 to 12, characterized in that: The substrate and the epitaxial layer are both made of silicon carbide.
14. An electronic chip, characterized in that: The invention comprises a passive device and the semiconductor device according to any one of claims 1 to 13; the passive device is electrically connected to the semiconductor device.
15. An electronic device, characterized in that: It comprises a circuit board and the electronic chip as claimed in claim 14; the semiconductor device is arranged on the circuit board.