Imaging device

Abstract

An imaging device is provided with a plurality of pixels (24). Each of the plurality of pixels (24) has: a lower electrode (2); an upper electrode (5) disposed facing the lower electrode (2); and a photoelectric conversion layer (4) that is positioned between the lower electrode (2) and the upper electrode (5), contains a donor semiconductor material and an acceptor semiconductor material, and generates electrons and holes. Between the lower electrode (2) and the upper electrode (5), a first bias voltage is applied in a first period, which is an exposure period, and a second bias voltage different from the first bias voltage is applied in a second period, which is a non-exposure period. When C1 represents the capacitance between the lower electrode (2) and the upper electrode (5) when a first bias voltage is applied between the lower electrode (2) and the upper electrode (5), and C2 represents the capacitance between the lower electrode (2) and the upper electrode (5) when a second bias voltage is applied between the lower electrode (2) and the upper electrode (5), (C2-C1) / C1 < = 1 is satisfied.

Description

Technical Field

[0001] This disclosure relates to camera devices. Background Technology

[0002] As a MOS (Metal-Oxide Semiconductor) type imaging device, a stacked imaging device has been proposed. In a stacked imaging device, a photoelectric conversion element including a photoelectric conversion layer is stacked on top of a semiconductor substrate. The charge generated by photoelectric conversion within the photoelectric conversion layer is captured by electrodes and stored in a charge storage region. For example, Patent Document 1 discloses a stacked imaging device that uses a CCD (Charge Coupled Device) circuit or a CMOS (Complementary MOS) circuit within a semiconductor substrate to read out the charge stored in the charge storage region.

[0003] The photoelectric conversion element used in imaging devices typically has a structure with multiple functional layers stacked together, such as a photoelectric conversion layer that absorbs light and generates signal charge and a charge blocking layer that suppresses charge injection from the electrodes. For example, Patent Document 2 discloses an imaging device using a photoelectric conversion element with a structure having a photoelectric conversion layer and a charge blocking layer stacked together.

[0004] In addition, in CMOS image sensors with photodiodes, a so-called rolling shutter is typically used as the signal readout method, which sequentially exposes and reads out the signal charge of each row of the pixel array.

[0005] In rolling shutter photography, the start and end timings of the exposure vary for each row of the pixel array. Therefore, when photographing fast-moving objects, distorted images of the object may be obtained, or, when using a flash, differences in brightness may sometimes occur within the image. Due to these issues, the demand for a so-called global shutter function—where the start and end timings of the exposure are the same across all pixels in the pixel array—has been increasing in recent years.

[0006] For example, in Patent Document 3, as a method for realizing a global shutter function using a photoelectric conversion element utilizing an organic material thin film, the following method is disclosed: between the electrodes disposed at both ends of the photoelectric conversion element, in addition to a first bias voltage for moving the signal charge generated in the photoelectric conversion element toward the electrodes, a second bias voltage for suppressing the movement of the charge is applied at a timing when the signal charge after movement is read out by a signal detection circuit.

[0007] Existing technical documents

[0008] Patent documents

[0009] Patent Document 1: Japanese Patent Application Publication No. 2007-311647

[0010] Patent Document 2: Japanese Patent Application Publication No. 2012-94660

[0011] Patent Document 3: Japanese Patent Application Publication No. 2018-92990 Summary of the Invention

[0012] Camera devices are used in various environments. For example, camera devices used in shooting environments with large variations in brightness, such as surveillance or vehicle-mounted applications, require high-quality shooting regardless of the shooting environment. That is, wide dynamic range is important in the performance of camera devices. Dynamic range is determined by the saturation signal and noise of the camera device, and can be achieved by increasing the saturation signal and / or reducing noise. Furthermore, reducing noise is also important for improving the quality of the captured images.

[0013] Therefore, this disclosure provides a camera device with reduced noise.

[0014] An imaging device according to one aspect of the present invention includes a plurality of pixels, each of the plurality of pixels having: a first electrode; a second electrode disposed opposite to the first electrode; and a photoelectric conversion layer located between the first electrode and the second electrode, comprising a donor semiconductor material and an acceptor semiconductor material to generate electrons and holes. A first bias voltage is applied between the first electrode and the second electrode during a first period as an exposure period, and a second bias voltage different from the first bias voltage is applied during a second period as a non-exposure period. When the first bias voltage is applied between the first electrode and the second electrode, the electrostatic capacitance between the first electrode and the second electrode is set to C1, and when the second bias voltage is applied between the first electrode and the second electrode, the electrostatic capacitance between the first electrode and the second electrode is set to C2, wherein (C2-C1) / C1≤1 is satisfied.

[0015] Additionally, one aspect of the imaging device disclosed herein includes a plurality of pixels, each of which comprises: a first electrode; a second electrode disposed opposite to the first electrode; a photoelectric conversion layer located between the first electrode and the second electrode, comprising a donor semiconductor material and an acceptor semiconductor material to generate electrons and holes; a first charge blocking layer located between the first electrode and the photoelectric conversion layer; and a charge accumulation region electrically connected to the first electrode, accumulating a signal charge, which is one of the holes and the electrons, wherein a first bias voltage is applied between the first electrode and the second electrode during a first period, and a second bias voltage different from the first bias voltage is applied during a second period, wherein the thickness of the first charge blocking layer is at least 25% of the shortest distance between the first electrode and the second electrode.

[0016] According to this disclosure, a camera device with reduced noise can be provided. Attached Figure Description

[0017] Figure 1 This is a schematic cross-sectional view showing the configuration of the photoelectric conversion element in the embodiment.

[0018] Figure 2 This is an exemplary energy band diagram of the photoelectric conversion element of the embodiment.

[0019] Figure 3 This is a schematic cross-sectional view showing the configuration of another photoelectric conversion element in the embodiment.

[0020] Figure 4 This is a diagram illustrating an example of the circuit structure of a camera device according to an embodiment.

[0021] Figure 5 This is a schematic cross-sectional view showing the device structure of pixels in a camera device according to an embodiment.

[0022] Figure 6 This is an exemplary energy band diagram of a photoelectric conversion unit when a first bias voltage is applied between the lower electrode and the upper electrode.

[0023] Figure 7 This is an exemplary energy band diagram of a photoelectric conversion unit when a second bias voltage is applied between the lower electrode and the upper electrode.

[0024] Figure 8 This is a diagram illustrating an example of the electrostatic capacitance-voltage (CV) characteristics of a photoelectric conversion unit.

[0025] Figure 9 It is a diagram that conceptually illustrates the distribution of the amount of charge stored in the photoelectric conversion unit.

[0026] Figure 10This is a graph showing the relationship between (C2-C1) / C1 and random noise in the imaging device of the embodiments and comparative examples.

[0027] Figure 11 This is a graph showing the relationship between D2 / D1 and random noise in the imaging device of the embodiments and comparative examples. Detailed Implementation

[0028] (An insight into one way of implementing this disclosure)

[0029] In order to provide a camera device with reduced noise, the inventors of this application discovered the following problem.

[0030] As with the global shutter function disclosed in Patent Document 3 above, when two bias voltages are applied between the electrodes disposed at both ends of the photoelectric conversion element, the amount of charge accumulated in the photoelectric conversion element changes according to the two bias voltages. For example, during the application of the first bias voltage, a bias voltage for moving charge towards the electrode is applied, so the amount of charge accumulated in the photoelectric conversion element is small. On the other hand, during the application of the second bias voltage, a bias voltage for suppressing charge movement is applied, so the amount of charge accumulated in the photoelectric conversion element is large. In addition, when applying two bias voltages, if the amount of charge accumulated in the photoelectric conversion element increases significantly during the application of one bias voltage compared to the application of the other bias voltage, the deviation in the amount of charge accumulated in the photoelectric conversion element becomes large. Since one electrode of the photoelectric conversion element is electrically connected to a charge accumulation region that accumulates signal charge for reading as a signal, the deviation in the amount of charge accumulated in the photoelectric conversion element affects the charge accumulation region and becomes a cause of noise in the imaging device.

[0031] This invention was made based on the insight that it provides a camera device that reduces noise by reducing the variation in the amount of charge stored in the photoelectric conversion element.

[0032] (Summary of this disclosure)

[0033] As a summary of one aspect of the present invention, an example of the camera device of the present invention is shown below.

[0034] The imaging device of the first aspect of the present invention includes a plurality of pixels, each of the plurality of pixels having: a first electrode; a second electrode disposed opposite to the first electrode; and a photoelectric conversion layer located between the first electrode and the second electrode, comprising a donor semiconductor material and an acceptor semiconductor material, generating electrons and holes. Between the first electrode and the second electrode, a first bias voltage is applied during a first period which is an exposure period, and a second bias voltage different from the first bias voltage is applied during a second period which is a non-exposure period. When the first bias voltage is applied between the first electrode and the second electrode, the electrostatic capacitance between the first electrode and the second electrode is set to C1, and when the second bias voltage is applied between the first electrode and the second electrode, the electrostatic capacitance between the first electrode and the second electrode is set to C2, wherein (C2-C1) / C1≤1 is satisfied.

[0035] Based on the structure of this method, a camera device with reduced noise can be realized.

[0036] Specifically, noise can be reduced by decreasing the change in the amount of charge accumulated between the first and second electrodes. In functions such as global shutter, the change in charge accumulated between the first and second electrodes when two different bias voltages are applied is proportional to the change in electrostatic capacitance between them. Therefore, if the difference in electrostatic capacitance between the first and second electrodes when different first and second bias voltages are applied is less than or equal to the electrostatic capacitance under the first bias voltage, the change in the amount of charge between the first and second electrodes can be reduced. As a result, even during the application of the second bias voltage, the amount of charge accumulated between the first and second electrodes can be reduced, thus achieving sufficient noise reduction.

[0037] Furthermore, for example, in the camera device according to the second aspect of the present invention, the photoelectric conversion efficiency of the plurality of pixels in the first period is different from that of the plurality of pixels in the second period in the camera device according to the first aspect.

[0038] Therefore, even if a first bias voltage and a second bias voltage are applied between the first electrode and the second electrode during the first period and the second period, such that the amount of charge generated varies depending on the amount of light incident on the photoelectric conversion layer, the imaging device can achieve sufficient noise reduction as described above.

[0039] Furthermore, for example, in the imaging device according to the third aspect of the present invention, in the imaging device according to the first or second aspect, the imaging device operates with a global shutter mode that is uniform throughout all exposure periods of the plurality of pixels, and each of the plurality of pixels further has a charge accumulation region electrically connected to the first electrode, which accumulates a signal charge as one of the electrons and the holes, and the first period is a period for accumulating the signal charge in the charge accumulation region.

[0040] Therefore, exposure can be performed at the same timing in all pixels, thus suppressing image distortion and other phenomena unique to rolling shutters, and achieving sufficient noise reduction.

[0041] Furthermore, for example, in the imaging device according to the fourth aspect of the present invention, in the imaging device according to the third aspect, the electrons and holes in the photoelectric conversion layer recombine by applying the second bias voltage between the first electrode and the second electrode.

[0042] Thus, by applying a second bias voltage during the second period to recombine electrons and holes, the amount of light incident on the photoelectric conversion layer during the non-exposure period is less affected by the amount of charge generated in the photoelectric conversion layer during the non-exposure period, as the second period, which is the non-exposure period, is set as the signal readout period.

[0043] Furthermore, for example, in the camera device according to the fifth aspect of the present invention, the sensitivity of photoelectric conversion is generated in the photoelectric conversion layer by applying the first bias voltage between the first electrode and the second electrode, in the camera device according to the third or fourth aspect.

[0044] In this way, during the first period of the exposure period, by supplying a first bias voltage that makes the photoelectric conversion layer sensitive, it is possible to take pictures in a global shutter mode.

[0045] Furthermore, for example, the imaging device according to the sixth aspect of the present invention, and the imaging device according to any one of the first to fifth aspects, further include a voltage supply circuit that selectively applies a bias voltage to the first electrode and a bias voltage to the second electrode to make the potential of the second electrode relative to the first electrode positive and a bias voltage to make the potential of the second electrode relative to the first electrode negative.

[0046] Thus, even when a bias voltage is selectively applied between the first and second electrodes such that the potential of the second electrode relative to the first electrode is either positive or negative, the imaging device can achieve sufficient noise reduction.

[0047] Furthermore, the imaging device of the seventh aspect of the present invention includes a plurality of pixels, each of which has: a first electrode; a second electrode disposed opposite to the first electrode; a photoelectric conversion layer located between the first electrode and the second electrode, comprising a donor semiconductor material and an acceptor semiconductor material to generate electrons and holes; a first charge blocking layer located between the first electrode and the photoelectric conversion layer; and a charge accumulation region electrically connected to the first electrode, accumulating a signal charge as one of the holes and the electrons, wherein a first bias voltage is applied between the first electrode and the second electrode during a first period, and a second bias voltage different from the first bias voltage is applied during a second period, wherein the thickness of the first charge blocking layer is 25% or more of the shortest distance between the first electrode and the second electrode.

[0048] Based on the structure of this method, a camera device with reduced noise can be realized.

[0049] Specifically, noise can be reduced by decreasing the variation in the amount of charge accumulated between the first and second electrodes. When a charge-blocking layer is disposed between the first electrode and the photoelectric conversion layer, when a bias voltage for suppressing charge movement is applied between the first and second electrodes, charge accumulates near the interface between the photoelectric conversion layer and the first charge-blocking layer. That is, it can be considered as a capacitor where charge, with the first charge-blocking layer as the dielectric, accumulates near the interface between the first electrode and the photoelectric conversion layer, and also near the interface between the photoelectric conversion layer and the first charge-blocking layer. On the other hand, when a bias voltage that causes charge to move towards the electrodes is applied between the first and second electrodes, the amount of charge accumulated between them is small. That is, this state can be considered as a capacitor that accumulates charge between the first and second electrodes. Therefore, the variation in the amount of charge accumulated between the first and second electrodes when different bias voltages are applied depends on the ratio of the shortest distance between the first and second electrodes to the thickness of the first charge-blocking layer. Since the first electrode is electrically connected to the charge accumulation region, the variation in the amount of charge between the first and second electrodes can be reduced when the thickness of the first charge-blocking layer is 25% or more of the shortest distance between the first and second electrodes. As a result, even during the application of the second bias voltage, the amount of charge accumulated between the first and second electrodes can be reduced, thereby reducing the impact of the charge accumulated between the first and second electrodes on the charge accumulation area and achieving sufficient noise reduction.

[0050] Furthermore, for example, in the camera device according to the eighth aspect of the present invention, the thickness of the first charge blocking layer is 10 nm or more compared to the camera device according to the seventh aspect.

[0051] Therefore, even when a large potential difference is generated between the first electrode and the second electrode, leakage current from the first electrode to the photoelectric conversion layer can be suppressed, and sufficient noise reduction can be achieved.

[0052] Furthermore, for example, in the camera device according to the ninth aspect of the present invention, in the camera device according to the seventh or eighth aspect, the signal charge is the hole, the first charge blocking layer contains a first semiconductor material, and the difference between the ionization potential of the first semiconductor material contained in the first charge blocking layer and the ionization potential of the donor semiconductor material contained in the photoelectric conversion layer is less than 1 eV.

[0053] Furthermore, for example, in the imaging device according to the tenth aspect of the present invention, in the imaging device according to the seventh or eighth aspect, the signal charge is the electron, the first charge blocking layer contains a first semiconductor material, and the difference between the electron affinity of the first semiconductor material contained in the first charge blocking layer and the electron affinity of the acceptor semiconductor material contained in the photoelectric conversion layer is less than 1 eV.

[0054] This improves the efficiency of extracting signal charges generated in the photoelectric conversion layer to the first electrode and achieves significant noise reduction.

[0055] Furthermore, for example, in the camera device according to the eleventh aspect of the present invention, in the camera device according to any one of the eighth to tenth aspects, the plurality of pixels each further have a second charge blocking layer located between the second electrode and the photoelectric conversion layer.

[0056] This allows for the suppression of leakage current from the second electrode to the photoelectric conversion layer, and also achieves significant noise reduction.

[0057] Furthermore, for example, in the camera device according to the twelfth aspect of the present invention, the thickness of the second charge blocking layer is 5 nm or more in the camera device according to the eleventh aspect.

[0058] Therefore, even when a large potential difference is generated between the first electrode and the second electrode, leakage current from the second electrode to the photoelectric conversion layer can be suppressed, and sufficient noise reduction can be achieved.

[0059] Furthermore, for example, in the imaging device according to the thirteenth aspect of the present invention, in the imaging device according to the eleventh or twelfth aspect, the signal charge is the hole, the second charge blocking layer contains a second semiconductor material, and the difference between the electron affinity of the second semiconductor material contained in the second charge blocking layer and the electron affinity of the acceptor semiconductor material contained in the photoelectric conversion layer is less than 1 eV.

[0060] Furthermore, for example, in the imaging device according to the fourteenth aspect of the present invention, in the imaging device according to the eleventh or twelfth aspect, the signal charge is the electron, the second charge blocking layer contains a second semiconductor material, and the difference between the ionization potential of the second semiconductor material contained in the second charge blocking layer and the ionization potential of the donor semiconductor material contained in the photoelectric conversion layer is less than 1 eV.

[0061] This improves the efficiency of transporting charges of opposite polarity to the signal charges generated in the photoelectric conversion layer to the second electrode, suppresses the decrease in sensitivity caused by the recombination of charges of opposite polarity to the signal charges generated in the photoelectric conversion layer and the signal charges, and achieves sufficient noise reduction.

[0062] The embodiments will now be described with reference to the accompanying drawings.

[0063] Furthermore, the embodiments described below are general or specific examples. The numerical values, shapes, constituent elements, arrangement positions of constituent elements, connection methods, steps, and order of steps shown in the following embodiments are merely examples and are not intended to limit this disclosure. Additionally, constituent elements in the following embodiments not described in the independent claims are described as optional constituent elements. Furthermore, the figures are not necessarily strictly illustrative. In the figures, substantially identical structures are labeled with the same reference numerals, and sometimes repeated descriptions are omitted or simplified.

[0064] Furthermore, in this specification, terms such as vertical to indicate the relationship between elements, terms such as rectangle to indicate the shape of elements, and numerical ranges are not merely expressions of a strict meaning, but also include expressions of substantially equivalent ranges.

[0065] Furthermore, in this specification, the terms "above" and "below" do not refer to the absolute upward (vertical above) and downward (vertical below) directions in spatial identification, but are used as terms defined by relative positional relationships based on the stacking order in a stacked structure. Additionally, the terms "above" and "below" are merely used to specify the mutual arrangement between components and are not intended to limit the posture of the camera device during use. Moreover, the terms "above" and "below" apply not only to cases where two constituent elements are arranged with a gap between them and other constituent elements exist between them, but also to cases where two constituent elements are arranged close together and connected.

[0066] In addition, for convenience, all electromagnetic waves including visible light, infrared light, and ultraviolet light are referred to as "light" in this specification.

[0067] Implementation

[0068] The following describes this embodiment.

[0069] Photoelectric conversion element

[0070] First, use Figure 1 The photoelectric conversion element included in the imaging device of this embodiment will be described. The photoelectric conversion element of this embodiment is a charge readout type photoelectric conversion element. Figure 1 This is a schematic cross-sectional view showing the structure of the photoelectric conversion element 10 in this embodiment.

[0071] like Figure 1 As shown, the photoelectric conversion element 10 is supported by a support substrate 1 and includes an upper electrode 5 and a lower electrode 2 as a pair of electrodes, a photoelectric conversion layer 4 located between the upper electrode 5 and the lower electrode 2, and a charge blocking layer 3 located between the lower electrode 2 and the photoelectric conversion layer 4. In this embodiment, the lower electrode 2 is an example of a first electrode, and the upper electrode 5 is an example of a second electrode. The charge blocking layer 3 is an example of a first charge blocking layer.

[0072] The photoelectric conversion element 10 is used, for example, in a manner in which light passing through the upper electrode 5 is incident on the photoelectric conversion layer 4.

[0073] Hereinafter, the constituent elements of the photoelectric conversion element 10 of this embodiment will be described.

[0074] The support substrate 1 can be any substrate used to support general photoelectric conversion elements, such as a glass substrate, quartz substrate, semiconductor substrate or plastic substrate.

[0075] The lower electrode 2 and the upper electrode 5 are film-shaped electrodes arranged opposite to each other.

[0076] The lower electrode 2 collects the signal charge generated in the photoelectric conversion layer 4. The lower electrode 2 is formed of a metal, a metal nitride, a metal oxide, or conductive polycrystalline silicon. Examples of metals include aluminum, copper, titanium, and tungsten. Examples of methods for imparting conductivity to polycrystalline silicon include doping with impurities.

[0077] The upper electrode 5 is disposed opposite to the lower electrode 2 via the photoelectric conversion layer 4. The upper electrode 5 is, for example, a transparent electrode formed of a transparent conductive material. Examples of materials for the upper electrode 5 include transparent conductive oxide (TCO), indium tin oxide (ITO), indium zinc oxide (IZO), aluminum-doped zinc oxide (AZO), fluorine-doped tin oxide (FTO), SnO2, and TiO2. Furthermore, the upper electrode 5 may also be fabricated by using TCO and various metal materials such as aluminum (Al) and gold (Au), either individually or in combination, depending on the desired transmittance.

[0078] Furthermore, the materials for the lower electrode 2 and the upper electrode 5 are not limited to the aforementioned conductive materials, and other materials may also be used. For example, the lower electrode 2 may be a transparent electrode.

[0079] In the fabrication of the lower electrode 2 and the upper electrode 5, various methods are used depending on the materials used. For example, when using ITO, methods such as electron beam deposition, sputtering, resistance heating vapor deposition, chemical reaction methods such as sol-gel deposition, and coating of indium tin oxide dispersions can be used. In this case, to fabricate the lower electrode 2 and the upper electrode 5, further UV-ozone treatment, plasma treatment, etc., can be performed after the ITO film is formed.

[0080] The photoelectric conversion layer 4 generates electrons and holes by absorbing light. One of the electrons and holes serves as a signal charge. That is, the photoelectric conversion layer 4 converts light into signal charge.

[0081] The photoelectric conversion layer 4 may include, for example, a donor semiconductor material and an acceptor semiconductor material. The photoelectric conversion layer 4 may be fabricated using, for example, an organic semiconductor material. The fabrication method for the photoelectric conversion layer 4 may include, for example, a wet method such as spin coating, or a dry method such as vacuum evaporation. Vacuum evaporation refers to a method in which the material of the layer is vaporized and deposited onto a substrate by heating under vacuum. Furthermore, the charge blocking layer 3 may also be fabricated using the same method as the photoelectric conversion layer 4.

[0082] Furthermore, the photoelectric conversion layer 4 may be, for example, a hybrid film comprising a bulk heterostructure of a donor semiconductor material such as a donor organic semiconductor material and a acceptor semiconductor material such as an acceptor organic semiconductor material. Alternatively, the photoelectric conversion layer 4 may have a stacked structure consisting of layers of donor semiconductor material and layers of acceptor semiconductor material.

[0083] The photoelectric conversion layer 4 can be easily formed into a thin film by comprising a donor organic semiconductor material and an acceptor organic semiconductor material. Hereinafter, specific examples of the donor organic semiconductor material and the acceptor organic semiconductor material will be given.

[0084] Examples of donor organic semiconductor materials include triarylamine compounds, benzidine compounds, pyrazoline compounds, styrylamine compounds, hydrazone compounds, triphenylmethane compounds, carbazole compounds, polysilane compounds, thiophene compounds, phthalocyanine compounds, naphthylphthalocyanine compounds, phthalocyanine compounds, anthocyanin compounds, oxacyanine compounds, polyamine compounds, indole compounds, pyrrole compounds, pyrazole compounds, biphenyl compounds, terphenyl compounds, polyaryl compounds, fused aromatic carbocyclic compounds, and metal complexes with nitrogen-containing heterocyclic compounds as ligands.

[0085] Fused aromatic carbocyclic compounds include, for example, naphthalene derivatives, anthracene derivatives, phenanthrene derivatives, tetraphenyl derivatives, pyrene derivatives, perylene derivatives, and fluoranthene derivatives.

[0086] Examples of acceptor organic semiconductor materials include fullerenes, fullerene derivatives, fused aromatic carbocyclic compounds, 5- to 7-membered heterocyclic compounds containing nitrogen, oxygen, and sulfur atoms, polyarylene compounds, fluorene compounds, cyclopentadiene compounds, silyl compounds, and metal complexes with nitrogen-containing heterocyclic compounds as ligands.

[0087] Fullerenes include, for example, C60 fullerenes and C70 fullerenes.

[0088] Fullerene derivatives include, for example, PCBM (methyl phenyl C61 butyrate) and ICBA (indene C60 diadduct).

[0089] 5- to 7-membered heterocyclic compounds containing nitrogen, oxygen, and sulfur atoms include, for example, pyridine, pyrazine, pyrimidine, pyridazine, triazine, quinoline, quinoxaline, quinazoline, phthalazine, cinnamic acid, isoquinoline, pteridine, acridine, phenazine, phenanthrene, tetrazolium, pyrazole, imidazole, thiazole, oxazole, indazole, benzimidazole, benzoindole, benzoxazole, benzothiazole, carbazole, purine, triazolopyridazine, triazolopyrimidine, tetrazaindene, oxadiazole, imidazopyridine, pyrrolidine, pyrrolopyridine, thiadiazopyridine, and dibenzodiazepine. and tribenzodiazepines wait.

[0090] The donor and acceptor organic semiconductor materials are not limited to the examples mentioned above. Low-molecular-weight and high-molecular-weight compounds can be used as the donor and acceptor organic semiconductor materials constituting the photoelectric conversion layer 4, as long as the organic compounds can be formed into the photoelectric conversion layer by dry or wet methods.

[0091] In addition, the photoelectric conversion layer 4 may also contain semiconductor materials other than organic semiconductor materials as donor and acceptor semiconductor materials. The photoelectric conversion layer 4 may contain silicon semiconductors, compound semiconductors, quantum dots, perovskite materials, carbon nanotubes, or any two or more of them as semiconductor materials.

[0092] As described above, the photoelectric conversion element 10 according to this embodiment includes a charge blocking layer 3 disposed between the lower electrode 2 and the photoelectric conversion layer 4. The charge blocking layer 3 is, for example, in contact with the lower electrode 2 and the photoelectric conversion layer 4.

[0093] The charge-blocking layer 3 may contain, for example, a first semiconductor material. The first semiconductor material may be, for example, an organic semiconductor material. The organic semiconductor material may be, for example, the aforementioned donor organic semiconductor material or acceptor organic semiconductor material. The first semiconductor material forming the charge-blocking layer 3 is not limited to organic semiconductor materials, but may be an oxide semiconductor, a nitride semiconductor, or a composite material thereof. The material forming the charge-blocking layer 3 may be a metal oxide such as aluminum oxide.

[0094] Alternatively, the charge blocking layer 3 can also have a structure consisting of multiple stacked layers. In this case, the materials constituting the multiple layers can be the same or different from each other.

[0095] The thickness of the charge blocking layer 3 is set, for example, based on the shortest distance between the lower electrode 2 and the upper electrode 5, as described later. The thickness of the charge blocking layer 3 is, for example, 10 nm or more. From the viewpoint of effectively suppressing dark current and noise, the thickness of the charge blocking layer 3 can be 20 nm or more, 100 nm or more, 150 nm or more, or 200 nm or more. Furthermore, from the viewpoint of suppressing sensitivity reduction, the thickness of the charge blocking layer 3 can be 1000 nm or less, or 600 nm or less.

[0096] Figure 2 yes Figure 1 The illustrated energy band diagram of the photoelectric conversion element is shown. Figure 2 In the diagram, the energy bands of each layer are represented by rectangles.

[0097] The photoelectric conversion layer 4 generates excitons internally when irradiated with light. These excitons diffuse within the photoelectric conversion layer 4 and are separated into electrons and holes at the interface between the acceptor and donor semiconductor materials. When a voltage is applied between the upper electrode 5 and the lower electrode 2 such that the potential of the upper electrode 5 is higher than that of the lower electrode 2, electrons move towards the upper electrode 5, and holes move towards the lower electrode 2. When the photoelectric conversion element 10 is used in an imaging device, for example, holes are captured by the lower electrode 2 and stored as signal charge at a charge accumulation node electrically connected to the lower electrode 2. A charge accumulation node is an example of a charge accumulation region that stores the signal charge collected by the lower electrode 2. Thus, the photoelectric conversion layer 4 converts light into signal charge, and the lower electrode 2 captures the signal charge generated by the photoelectric conversion layer 4. Additionally, the upper electrode 5 collects charges with the opposite polarity to the signal charge. The following explanation describes the case where holes move towards the lower electrode 2 and are used as signal charge. Note that electrons can also be used as signal charge. In this case, a voltage is applied between the upper electrode 5 and the lower electrode 2 such that the potential of the upper electrode 5 is lower than that of the lower electrode 2. Holes move towards the upper electrode 5 and electrons move towards the lower electrode 2.

[0098] Here, the material that supplies electrons from the electron-hole pair generated by absorbing light to the other material is called the donor material, and the material that accepts electrons is called the acceptor material. In this embodiment, the donor semiconductor material is the donor material, and the acceptor semiconductor material is the acceptor material. When using two different organic semiconductor materials, which one becomes the donor material and which becomes the acceptor material is usually determined by the relative positions of the HOMO (Highest Occupied Molecular Orbital) and LUMO (Lowest Unoccupied Molecular Orbital) energy levels of the two organic semiconductor materials at the contact interface. Figure 2 In the rectangle representing energy bands, the upper end represents the LUMO level, and the lower end represents the HOMO level. The energy difference between the vacuum level and the LUMO level is called the electron affinity. The energy difference between the vacuum level and the HOMO level is called the ionization potential. Figure 2 In the band structure, the lower the band, the greater the electron affinity and ionization potential. This is also true in the band diagrams explained later.

[0099] like Figure 2As shown, among the two semiconductor materials included in the photoelectric conversion layer 4, the one with a shallower LUMO energy level, i.e., a lower electron affinity, becomes the donor semiconductor material 4A, serving as the donor material. Conversely, among the two semiconductor materials included in the photoelectric conversion layer 4, the one with a deeper LUMO energy level, i.e., a higher electron affinity, becomes the acceptor semiconductor material 4B, serving as the acceptor material. Furthermore, in... Figure 2 In the diagram, the energy bands of the donor semiconductor material 4A and the acceptor semiconductor material 4B are offset laterally for ease of observation and do not imply that the donor semiconductor material 4A and the acceptor semiconductor material 4B are separately distributed along the thickness direction of the photoelectric conversion layer 4. Furthermore, the energy band of the acceptor semiconductor material 4B is represented by a dashed rectangle, but this is also for ease of observation and is not intended to distinguish it from the solid rectangle. This is also true in the energy band diagrams described later.

[0100] The ionization potential of the donor semiconductor material 4A is, for example, less than the ionization potential of the acceptor semiconductor material 4B.

[0101] exist Figure 2 In this context, the electron affinity and ionization potential of the charge barrier layer 3 are, for example, the electron affinity and ionization potential of the first semiconductor material contained in the charge barrier layer 3.

[0102] The charge blocking layer 3 is configured to transmit signal charges and block charges of opposite polarity to the signal charges. In the case where holes are used as signal charges, such as... Figure 2 As shown, the electron affinity of the charge blocking layer 3 is, for example, equal to or less than the electron affinity of the acceptor semiconductor material 4B of the photoelectric conversion layer 4. The electron affinity of the charge blocking layer 3 is less than the work function of the lower electrode 2. Therefore, the charge blocking layer 3 suppresses the injection of charges (specifically electrons) with the opposite polarity to the signal charge flowing from the lower electrode 2 to the photoelectric conversion layer 4. As a result, noise caused by dark current, which adversely affects the signal-to-noise ratio (SN ratio), can be reduced. Furthermore, in the case where the charge blocking layer 3 has a structure with multiple layers stacked, the electron affinity of at least any one layer is below the electron affinity of the acceptor semiconductor material 4B of the photoelectric conversion layer 4 and less than the work function of the lower electrode 2.

[0103] Furthermore, for example, the difference between the ionization potential of the charge blocking layer 3 and the ionization potential of the donor semiconductor material 4A in the photoelectric conversion layer 4 is less than 1 eV. Therefore, signal charge can be easily transmitted through the charge blocking layer 3, and the efficiency of extracting the signal charge generated in the photoelectric conversion layer 4 through the lower electrode 2 is improved. Furthermore, when the charge blocking layer 3 has a structure with multiple layers stacked, for example, the difference between the ionization potential of any one layer and the ionization potential of the donor semiconductor material 4A is less than 1 eV.

[0104] Furthermore, when electrons are used as signal charges, in order to suppress the injection of holes from the lower electrode 2 into the photoelectric conversion layer 4, the ionization potential of the charge blocking layer 3 is, for example, greater than the ionization potential of the donor semiconductor material 4A of the photoelectric conversion layer 4. When electrons are used as signal charges, the ionization potential of the charge blocking layer 3 is greater than the work function of the lower electrode 2.

[0105] Furthermore, when using electrons as signal charges, the difference between the electron affinity of the charge blocking layer 3 and the electron affinity of the acceptor semiconductor material 4B is less than 1 eV. This improves the efficiency of the lower electrode 2 in extracting signal charges (specifically, electrons).

[0106] [Another example of a photoelectric conversion element]

[0107] Furthermore, the photoelectric conversion element of this embodiment may also have a charge blocking layer between the upper electrode 5 and the photoelectric conversion layer 4. Figure 3 This is a schematic cross-sectional view showing the structure of another photoelectric conversion element 11 in this embodiment. (See diagram below.) Figure 3 As shown, in addition to the structure of the photoelectric conversion element 10, the photoelectric conversion element 11 also includes a charge blocking layer 6 between the upper electrode 5 and the photoelectric conversion layer 4. The charge blocking layer 6 is, for example, in contact with the upper electrode 5 and the photoelectric conversion layer 4. The charge blocking layer 6 is an example of a second charge blocking layer.

[0108] The charge blocking layer 6 may contain a second semiconductor material, for example. This second semiconductor material may be composed of an organic semiconductor material, for example, the aforementioned donor or acceptor organic semiconductor material. The second semiconductor material forming the charge blocking layer 6 is not limited to organic semiconductor materials, but may be an oxide semiconductor, a nitride semiconductor, or a composite material thereof. The material forming the charge blocking layer 6 may be a metal oxide such as aluminum oxide. The charge blocking layer 6 may contain the same material as the charge blocking layer 3. Furthermore, the charge blocking layer 6 may contain the same material as the donor semiconductor material contained in the photoelectric conversion layer 4.

[0109] Alternatively, the charge blocking layer 6 can also have a structure consisting of multiple stacked layers. In this case, the materials constituting the multiple layers can be the same or different from each other.

[0110] The charge blocking layer 6 is configured to transmit charges with the opposite polarity to the signal charges and to block the signal charges. When holes are used as the signal charges, the ionization potential of the charge blocking layer 6 is, for example, equal to or higher than the ionization potential of the donor semiconductor material 4A of the photoelectric conversion layer 4. Furthermore, the ionization potential of the charge blocking layer 6 is greater than the work function of the upper electrode 5. Therefore, the charge blocking layer 6 suppresses the injection of signal charges (specifically, holes) from the upper electrode 5 into the photoelectric conversion layer 4. As a result, noise signals caused by dark currents that adversely affect the signal-to-signal ratio can be reduced. Additionally, when the charge blocking layer 6 has a structure with multiple layers stacked, the ionization potential of at least any one layer is greater than the ionization potential of the donor semiconductor material 4A of the photoelectric conversion layer 4 and greater than the work function of the upper electrode 5.

[0111] Furthermore, for example, the difference between the electron affinity of the charge blocking layer 6 and the electron affinity of the acceptor semiconductor material 4B in the photoelectric conversion layer 4 is less than 1 eV. This improves the efficiency of transporting charges (specifically electrons) with opposite polarity to the signal charge to the upper electrode 5. Furthermore, in the case where the charge blocking layer 6 has a structure consisting of multiple stacked layers, for example, the difference between the electron affinity of any one layer and the electron affinity of the acceptor semiconductor material 4B is less than 1 eV.

[0112] The electron affinity and ionization potential of the charge barrier layer 6 are, for example, the electron affinity and ionization potential of the second semiconductor material contained in the charge barrier layer 6.

[0113] The thickness of the charge blocking layer 6 is, for example, 5 nm or more. From the viewpoint of effectively suppressing dark current and noise, the thickness of the charge blocking layer 6 can be 10 nm or more, 20 nm or more, or 30 nm or more. Furthermore, from the viewpoint of suppressing sensitivity reduction, the thickness of the charge blocking layer 6 can be 500 nm or less, or 300 nm or less.

[0114] Note that when electrons are used as signal charges, in order to suppress the injection of electrons from the upper electrode 5 into the photoelectric conversion layer 4, the electron affinity of the charge barrier layer 6 is, for example, equal to or less than the electron affinity of the acceptor semiconductor material 4B of the photoelectric conversion layer 4. When electrons are used as signal charges, the electron affinity of the charge barrier layer 6 is less than the work function of the upper electrode 5.

[0115] Furthermore, when electrons are used as signal charges, the difference between the ionization potential of the charge blocking layer 6 and the ionization potential of the donor semiconductor material 4A is less than 1 eV. As a result, the efficiency of the upward movement of charges (specifically holes) with opposite polarity to the signal charges is improved.

[0116] [Camera device]

[0117] Next, use Figure 4 and Figure 5 The camera device of this embodiment will be described. Figure 4 It shows that it is installed and used. Figure 1 This diagram shows an example of the circuit structure of the imaging device 100, specifically the photoelectric conversion section 10A of the photoelectric conversion element 10. Additionally, Figure 5 This is a schematic cross-sectional view showing an example of the device structure of pixel 24 in the camera device 100 of this embodiment.

[0118] like Figure 4 as well as Figure 5 As shown, the imaging device 100 of this embodiment includes: a semiconductor substrate 40; and a plurality of pixels 24, each having a charge detection circuit 35 disposed on the semiconductor substrate 40, a photoelectric conversion unit 10A disposed on the semiconductor substrate 40, and a charge accumulation node 34 electrically connected to the charge detection circuit 35 and the photoelectric conversion unit 10A. The photoelectric conversion unit 10A of the plurality of pixels 24 is constituted by the aforementioned photoelectric conversion element 10. That is, the plurality of pixels 24 each have a lower electrode 2, an upper electrode 5, a photoelectric conversion layer 4, and a charge blocking layer 3. In this embodiment, the charge accumulation node 34 is an example of a charge accumulation region. Alternatively, the photoelectric conversion unit 10A may also be constituted by a photoelectric conversion element 11. That is, the plurality of pixels 24 may also each have a charge blocking layer 6 in addition to the above structure.

[0119] In the photoelectric conversion unit 10A, the upper electrode 5, the photoelectric conversion layer 4, the charge blocking layer 3, and the lower electrode 2 are arranged sequentially from the light incident side of the imaging device 100. In this embodiment, light passing through the upper electrode 5 is incident on the photoelectric conversion layer 4. Furthermore, in this embodiment, the light incident side relative to the imaging device 100 is the side of the photoelectric conversion unit 10A opposite to the semiconductor substrate 40 side. Additionally, in this embodiment, the light incident side is set to the upper side.

[0120] The charge accumulation node 34 accumulates the signal charge generated by the photoelectric conversion unit 10A, and the charge detection circuit 35 detects the signal charge accumulated in the charge accumulation node 34. In addition, the charge detection circuit 35 disposed on the semiconductor substrate 40 can be disposed on the semiconductor substrate 40 or directly disposed in the semiconductor substrate 40.

[0121] like Figure 4 As shown, the camera device 100 includes a plurality of pixels 24 and peripheral circuitry. The camera device 100 is, for example, an image sensor implemented by a single-chip integrated circuit, having a pixel array PA comprising a plurality of pixels 24 arranged in a two-dimensional manner.

[0122] Multiple pixels 24 are arranged two-dimensionally on a semiconductor substrate 40, i.e., along both row and column directions, to form a photosensitive area that serves as a pixel region. Figure 4The image shows an example of pixels 24 arranged in a two-row, two-column matrix. The arrangement of pixels 24 is not limited to two rows and two columns; there is no particular limitation on the number of rows and columns. Furthermore, in... Figure 4 For ease of illustration, the circuitry (e.g., pixel electrode control circuitry) used to individually set the sensitivity of pixel 24 is omitted. Additionally, the imaging device 100 can also be a line sensor. In this case, the multiple pixels 24 can also be arranged in one dimension. Furthermore, in this specification, row direction and column direction refer to the directions in which rows and columns extend, respectively. That is, in Figure 4 In the diagram, the vertical axis on the paper represents the column direction, and the horizontal axis represents the row direction.

[0123] like Figure 4 and Figure 5 As shown, each pixel 24 has a photoelectric conversion unit 10A, a charge detection circuit 35, and a charge accumulation node 34 electrically connected to the photoelectric conversion unit 10A and the charge detection circuit 35. The charge detection circuit 35 includes an amplification transistor 21, a reset transistor 22, and an address transistor 23.

[0124] The photoelectric conversion unit 10A includes a lower electrode 2, which serves as a pixel electrode, and an upper electrode 5, which serves as a counter electrode opposite to the pixel electrode. The photoelectric conversion unit 10A does not need to be a separate component for each pixel 24; a portion of the photoelectric conversion unit 10A may span multiple pixels 24. A voltage for applying a predetermined bias voltage is supplied to the upper electrode 5 via the counter electrode signal line 26.

[0125] The lower electrode 2 is connected to the gate electrode 21G of the amplifying transistor 21, and the signal charge collected by the lower electrode 2 is stored in the charge storage node 34 located between the lower electrode 2 and the gate electrode 21G of the amplifying transistor 21. For example, when the signal charge is a hole, the charge storage node 34 is electrically connected to the lower electrode 2 and stores the holes in the excitons generated by the photoelectric conversion layer 4.

[0126] A voltage corresponding to the amount of signal charge accumulated in charge accumulation node 34 is applied to the gate electrode 21G of amplifying transistor 21. Amplifying transistor 21 amplifies this voltage, which is selectively read out as a signal voltage by address transistor 23. The source / drain electrodes of reset transistor 22 are connected to lower electrode 2 via charge accumulation node 34, and reset the signal charge accumulated in charge accumulation node 34. In other words, reset transistor 22 resets the potential of gate electrode 21G and lower electrode 2 of amplifying transistor 21.

[0127] To selectively perform the aforementioned operations on multiple pixels 24, the imaging device 100 includes a power supply line 31, a vertical signal line 27, an address signal line 36, and a reset signal line 37, which are respectively connected to each pixel 24. Specifically, the power supply line 31 is connected to the source / drain electrodes of the amplifying transistor 21, and the vertical signal line 27 is connected to the source / drain electrodes of the address transistor 23. The address signal line 36 is connected to the gate electrode 23G of the address transistor 23. Additionally, the reset signal line 37 is connected to the gate electrode 22G of the reset transistor 22.

[0128] The peripheral circuitry includes a voltage supply circuit 19, a vertical scanning circuit 25, a horizontal signal readout circuit 20, multiple column signal processing circuits 29, multiple load circuits 28, and multiple differential amplifiers 32.

[0129] The voltage supply circuit 19 is electrically connected to the upper electrode 5 via the counter electrode signal line 26. The voltage supply circuit 19 applies a voltage between the upper electrode 5 and the lower electrode 2 by supplying a voltage to the upper electrode 5, thus creating a potential difference between them. When the lower electrode 2 collects holes as signal charges, the voltage supply circuit 19 supplies a voltage to the upper electrode 5 such that the potential of the upper electrode 5 is higher than that of the lower electrode 2. Furthermore, when the lower electrode 2 collects electrons as signal charges, the voltage supply circuit 19 supplies a voltage to the upper electrode 5 such that the potential of the upper electrode 5 is lower than that of the lower electrode 2.

[0130] As will be explained in detail later, the sensitivity of the photoelectric conversion unit 10A is controlled by switching the voltage supplied from the voltage supply circuit 19 to the upper electrode 5 between multiple different voltages.

[0131] The voltage supply circuit 19 selectively applies a bias voltage between the lower electrode 2 and the upper electrode 5 such that the potential of the upper electrode 5 relative to the lower electrode 2 is positive and the potential of the upper electrode 5 relative to the lower electrode 2 is negative.

[0132] The voltage supply circuit 19 is not limited to a specific power supply circuit; it can be a circuit that generates a specified voltage or a circuit that converts a voltage supplied from another power source into a specified voltage. Furthermore, the camera device 100 may not include the voltage supply circuit 19. For example, voltage may be supplied to the upper electrode 5 from an external power source.

[0133] The vertical scanning circuit 25 is connected to the address signal line 36 and the reset signal line 37, selecting multiple pixels 24 arranged in each row on a row-by-row basis to read out signal voltages and reset the potential of the lower electrode 2. The power supply wiring 31, serving as the source follower power supply, supplies a predetermined power voltage to each pixel 24. The horizontal signal readout circuit 20 is electrically connected to multiple column signal processing circuits 29. The column signal processing circuits 29 are electrically connected to the pixels 24 arranged in each column via vertical signal lines 27 corresponding to each column. The load circuit 28 is electrically connected to each vertical signal line 27. The load circuit 28 and the amplifying transistor 21 form a source follower circuit.

[0134] Multiple differential amplifiers 32 are arranged corresponding to each column. The inverting input terminal of the differential amplifier 32 is connected to the corresponding vertical signal line 27. In addition, the output terminal of the differential amplifier 32 is connected to the pixel 24 via the feedback line 33 corresponding to each column.

[0135] The vertical scan circuit 25 applies a row selection signal, controlling the on / off state of the address transistor 23, to the gate electrode 23G of the address transistor 23 via the address signal line 36. This scans and selects the row to be read. A signal voltage is read from the pixel 24 of the selected row to the vertical signal line 27. Additionally, the vertical scan circuit 25 applies a reset signal, controlling the on / off state of the reset transistor 22, to the gate electrode 22G of the reset transistor 22 via the reset signal line 37. This selects the row of pixels 24 to be reset. The signal voltage read from the pixel 24 selected by the vertical scan circuit 25 is transmitted to the column signal processing circuit 29 via the vertical signal line 27.

[0136] The signal processing circuit 29 performs noise suppression signal processing, such as correlated double sampling, and analog-to-digital conversion (AD conversion).

[0137] The horizontal signal readout circuit 20 reads signals sequentially from multiple column signal processing circuits 29 to the horizontal common signal line.

[0138] Differential amplifier 32 is connected to the drain electrode of reset transistor 22 via feedback line 33. Therefore, differential amplifier 32 receives the output value of address transistor 23 at its inverting input terminal. Differential amplifier 32 performs feedback operation to make the gate potential of amplifying transistor 21 a predetermined feedback voltage. At this time, the output voltage value of differential amplifier 32 is, for example, 0V or a positive voltage near 0V. The feedback voltage refers to the output voltage of differential amplifier 32.

[0139] like Figure 5 As shown, pixel 24 has a semiconductor substrate 40, a charge detection circuit 35, a photoelectric conversion unit 10A, and a charge accumulation node 34 (see reference). Figure 4 ).

[0140] The semiconductor substrate 40 may also be an insulating substrate, such as a p-type silicon substrate, on the surface of which a semiconductor layer is provided on the side where the photosensitive area is formed. The semiconductor substrate 40 has impurity regions 21D, 21S, 22D, 22S, and 23S and a component separation region 41 for electrical separation between pixels 24. The impurity regions 21D, 21S, 22D, 22S, and 23S are, for example, n-type regions. Here, the component separation region 41 is provided between impurity regions 21D and 22D. This suppresses leakage of signal charge accumulated at the charge accumulation node 34. Furthermore, the component separation region 41 is formed, for example, by ion implantation of a acceptor under specified implantation conditions.

[0141] Impurity regions 21D, 21S, 22D, 22S, and 23S are, for example, diffusion regions formed within the semiconductor substrate 40. Figure 5 As shown, the amplifying transistor 21 includes an impurity region 21S, an impurity region 21D, and a gate electrode 21G. The impurity regions 21S and 21D function as, for example, the source and drain regions of the amplifying transistor 21, respectively. A channel region of the amplifying transistor 21 is formed between the impurity regions 21S and 21D.

[0142] Similarly, address transistor 23 includes impurity regions 23S and 21S, and a gate electrode 23G connected to address signal line 36. In this example, amplifying transistor 21 and address transistor 23 are electrically connected to each other by sharing the impurity region 21S. The impurity region 23S functions as, for example, the source region of address transistor 23. The impurity region 23S has a similar characteristic to... Figure 4 The connection of the vertical signal line 27 is shown.

[0143] An interlayer insulating layer 50 is stacked on the semiconductor substrate 40 in such a manner that it covers the amplification transistor 21, the address transistor 23, and the reset transistor 22. Furthermore, Figure 5 In the diagram, for ease of observation, the shading representing the cross-section of the interlayer insulation layer 50 is omitted.

[0144] Furthermore, a wiring layer (not shown) can be disposed in the interlayer insulating layer 50. The wiring layer is formed of a metal such as copper, and may include wiring such as the vertical signal line 27 described above in a portion thereof. The number of insulating layers in the interlayer insulating layer 50 and the number of layers included in the wiring layer disposed in the interlayer insulating layer 50 can be arbitrarily set.

[0145] A contact plug 53 connected to the gate electrode 21G of the amplifying transistor 21, a contact plug 54 connected to the impurity region 22D of the reset transistor 22, a contact plug 51 connected to the lower electrode 2, and wiring 52 connecting the contact plugs 51, 54, and 53 are disposed in the interlayer insulating layer 50. Thus, the impurity region 22D of the reset transistor 22 is electrically connected to the gate electrode 21G of the amplifying transistor 21. Figure 5 In the illustrated structure, the contact plugs 51, 53 and 54, the wiring 52, the gate electrode 21G of the amplifying transistor 21 and the impurity region 22D of the reset transistor 22 constitute at least a portion of the charge accumulation node 34.

[0146] The charge detection circuit 35 detects the signal charge collected by the lower electrode 2 and outputs a signal voltage. The charge detection circuit 35 includes an amplifying transistor 21, a reset transistor 22, and an address transistor 23, and is formed on the semiconductor substrate 40.

[0147] The amplifying transistor 21 is formed in the semiconductor substrate 40, including impurity regions 21D and 21S that function as drain and source electrodes, respectively, a gate insulating layer 21X formed on the semiconductor substrate 40, and a gate electrode 21G formed on the gate insulating layer 21X.

[0148] The reset transistor 22 is formed in the semiconductor substrate 40, including impurity regions 22D and 22S that function as drain and source electrodes respectively, a gate insulating layer 22X formed on the semiconductor substrate 40, and a gate electrode 22G formed on the gate insulating layer 22X.

[0149] Address transistor 23 includes: impurity regions 21S and 23S formed within semiconductor substrate 40, functioning as drain and source electrodes, respectively; gate insulating layer 23X formed on semiconductor substrate 40; and gate electrode 23G formed on gate insulating layer 23X. In impurity region 21S, amplification transistor 21 and address transistor 23 are connected in series.

[0150] The aforementioned photoelectric conversion unit 10A is disposed on the interlayer insulating layer 50. In other words, in this embodiment, a plurality of pixels 24 constituting the pixel array PA are formed on the semiconductor substrate 40. Furthermore, the plurality of pixels 24 arranged in two dimensions on the semiconductor substrate 40 form a photosensitive area. The distance between two connected pixels 24 (i.e., pixel pitch) can be, for example, about 2 μm.

[0151] The charge blocking layer 3, photoelectric conversion layer 4, and upper electrode 5 are formed, for example, spanning multiple pixels 24. On the other hand, the lower electrode 2 is provided for each pixel 24, and is electrically separated from the lower electrodes 2 of other pixels 24 by being spatially separated from them. As described above, the upper electrode 5 has a connection to the counter electrode signal line 26 connected to the voltage supply circuit 19. Therefore, a desired voltage can be applied simultaneously from the voltage supply circuit 19 to multiple pixels 24 via the counter electrode signal line 26. Furthermore, the upper electrode 5 can also be provided separately for each pixel 24, provided that a desired voltage can be applied from the voltage supply circuit 19. Similarly, the photoelectric conversion layer 4 and the charge blocking layer 3 can also be provided separately for each pixel 24.

[0152] The shortest distance D1 between the lower electrode 2 and the upper electrode 5 in the photoelectric conversion unit 10A and the thickness D2 of the charge blocking layer 3 will be described later. Figure 5 As shown, the shortest distance D1 between the lower electrode 2 and the upper electrode 5 is also the total thickness of the layer disposed between the lower electrode 2 and the upper electrode 5 (in Figure 5 The example shown represents the combined thickness of the charge blocking layer 3 and the photoelectric conversion layer 4. Furthermore, the thickness D2 of the charge blocking layer 3 is also the shortest distance between the lower electrode 2 and the photoelectric conversion layer 4.

[0153] A color filter 60 is formed above the photoelectric conversion unit 10A, and a microlens 61 is formed above the color filter 60. The color filter 60 is, for example, formed as a patterned on-chip color filter, using a photosensitive resin in which dyes or pigments are dispersed. The microlens 61 is, for example, formed as an on-chip microlens, using an ultraviolet photosensitive material.

[0154] In the manufacture of the camera device 100, conventional semiconductor manufacturing processes can be used. In particular, when a silicon substrate is used as the semiconductor substrate 40, it can be manufactured using various silicon semiconductor processes.

[0155] [Operation of the camera device]

[0156] The imaging device 100 operates, for example, using a global shutter mode where the exposure period of the multiple pixels 24 is uniform. In this specification, "exposure period" refers to the period during which one of the electrons and holes generated by photoelectric conversion is stored as a signal charge in the charge accumulation node 34. Furthermore, in this specification, the period during the operation of the imaging device 100 that is other than the exposure period is referred to as the "non-exposure period." The "non-exposure period" can be a period during which the incident light to the photoelectric conversion unit 10A is blocked, or a period during which light is irradiated to the photoelectric conversion unit 10A but the charge does not substantially accumulate in the charge accumulation node 34. Furthermore, the readout operation of the imaging device 100 is not limited to a global shutter mode; known imaging device readout operations can be used. For example, the imaging device 100 can also operate using a rolling shutter mode where the multiple pixels 24 are exposed sequentially for each pixel row and the signal is read out.

[0157] The voltage supply circuit 19 supplies a voltage to the upper electrode 5 during exposure for imaging with the desired sensitivity, and supplies a voltage to the upper electrode 5 during non-exposure periods that does not cause the photoelectric conversion unit 10A to generate sensitivity. Therefore, the photoelectric conversion efficiency of the plurality of pixels 24 during exposure is different from that during non-exposure periods; specifically, it is higher than that during non-exposure periods. During exposure, signal charge is accumulated at the charge accumulation node 34, and during non-exposure periods, the signal charge accumulated at the charge accumulation node 34 during exposure is read out sequentially for each pixel row. Furthermore, causing the photoelectric conversion unit 10A to generate no sensitivity means causing the photoelectric conversion unit 10A to generate no substantial sensitivity; for example, the sensitivity of the photoelectric conversion unit 10A during non-exposure periods is less than 5% of the sensitivity of the photoelectric conversion unit 10A during exposure periods. The sensitivity of the photoelectric conversion unit 10A during non-exposure periods can be equal to or less than 1% of the sensitivity of the photoelectric conversion unit 10A during exposure periods.

[0158] For example, during a first period, which is an exposure period, the voltage supply circuit 19 supplies the upper electrode 5 with a voltage that applies a first bias voltage between the lower electrode 2 and the upper electrode 5. Additionally, during a second period, which is a non-exposure period, the voltage supply circuit 19 supplies the upper electrode 5 with a voltage that applies a second bias voltage between the lower electrode 2 and the upper electrode 5. By applying the first bias voltage between the lower electrode 2 and the upper electrode 5, the photoelectric conversion layer 4 in the photoelectric conversion unit 10A generates photoelectric conversion sensitivity. Furthermore, by applying the second bias voltage between the lower electrode 2 and the upper electrode 5, electrons and holes in the photoelectric conversion layer 4 recombine. The absolute value of the second bias voltage is, for example, less than the absolute value of the first bias voltage. Furthermore, the magnitude of the bias voltage applied between the lower electrode 2 and the upper electrode 5 varies depending on the potential of the charge accumulation node 34, i.e., the amount of signal charge accumulated. However, the voltage supply circuit 19 selectively supplies voltages to the upper electrode 5 such that the potential difference between the upper electrode 5 and the lower electrode 2 when the pixel 24 is reset becomes a first bias voltage and a second bias voltage. That is, in this specification, applying a first bias voltage or a second bias voltage between the lower electrode 2 and the upper electrode 5 means supplying the upper electrode 5 with a voltage such that the potential difference between the upper electrode 5 and the lower electrode 2 when the pixel 24 is reset becomes a first bias voltage or a second bias voltage.

[0159] Figure 6 This is an exemplary energy band diagram of the photoelectric conversion unit 10A when a first bias voltage is applied between the lower electrode 2 and the upper electrode 5. Additionally, Figure 7 This is an exemplary energy band diagram of the photoelectric conversion unit 10A when a second bias voltage is applied between the lower electrode 2 and the upper electrode 5. Figure 6 and Figure 7 The energy band structure is shown when the photoelectric conversion unit 10A is composed of a photoelectric conversion element 10. Additionally, in Figure 6 and Figure 7 In the diagram, black circles represent electrons and white circles represent holes, schematically illustrating a portion of the movement of electrons and holes.

[0160] For example, in the case where the camera device 100 stores holes as signal charges at the charge storage node 34 during exposure, such as Figure 6 As shown, a first bias voltage is applied between the lower electrode 2 and the upper electrode 5, making the potential of the upper electrode 5 relative to the lower electrode 2 a positive potential. Furthermore, in... Figure 6In the state shown, electron-hole pairs are generated in the photoelectric conversion layer 4. Then, a voltage higher than the potential of the lower electrode 2 is applied to the upper electrode 5, causing holes to move to the lower electrode 2 and electrons to move to the upper electrode 5, with holes accumulating at the charge accumulation node 34. That is, during exposure, an amount of signal charge corresponding to the amount of light irradiation of the photoelectric conversion unit 10A is accumulated in the charge accumulation node 34.

[0161] In addition, Figure 6 In the state shown, holes pass through the charge blocking layer 3 and move from the photoelectric conversion layer 4 to the lower electrode 2, while electrons move from the photoelectric conversion layer 4 to the upper electrode 5. Therefore, less charge is accumulated in the photoelectric conversion section 10A.

[0162] Furthermore, for example, when the camera device 100 reads the signal charge during the non-exposure period following the aforementioned exposure period, such as Figure 7 As shown, a second bias voltage is applied between the lower electrode 2 and the upper electrode 5. Under this second bias voltage, the potential of the upper electrode 5 relative to the lower electrode 2 becomes negative. Then, in Figure 7 In the shown state, holes accumulated in charge accumulation node 34 are read out via lower electrode 2. During non-exposure periods, a second bias voltage is applied between lower electrode 2 and upper electrode 5 to suppress charge movement in photoelectric conversion unit 10A. Therefore, with the second bias voltage applied, holes accumulated in charge accumulation node 34 are difficult to discharge to lower electrode 2, and charges supplied from voltage supply circuit 19 via lower electrode 2 are difficult to flow into charge accumulation node 34. Therefore, even when readout is performed row by row during non-exposure periods, the amount of charge accumulated in charge accumulation node 34 during these readout periods is not easily changed.

[0163] In addition, Figure 7 In the illustrated state, because a voltage lower than the potential of the lower electrode 2 is applied to the upper electrode 5, electrons generated and remaining in the photoelectric conversion layer 4, or electrons injected from the upper electrode 5, accumulate near the interface between the photoelectric conversion layer 4 and the charge blocking layer 3. Furthermore, during non-exposure periods, a second bias voltage for suppressing charge movement is applied between the lower electrode 2 and the upper electrode 5; therefore, the charge accumulated in the photoelectric conversion section 10A increases compared to the exposure period.

[0164] During the non-exposure period, the amount of electrons accumulated depends on the thickness D2 of the charge-blocking layer 3. Specifically, as Figure 7As shown, as electron accumulation proceeds, the energy band of the photoelectric conversion layer 4 bends near the interface between the photoelectric conversion layer 4 and the charge blocking layer 3. Since the electric field applied near the interface between the photoelectric conversion layer 4 and the charge blocking layer 3 decreases, the electron accumulation in the photoelectric conversion layer 4 becomes constant. This state can be considered as a capacitor with the charge blocking layer 3 acting as a dielectric, where the amount of electron accumulation is equal to the amount of charge accumulated in the aforementioned capacitor. Therefore, by increasing the thickness D2 of the charge blocking layer 3, which corresponds to the dielectric, the amount of electron accumulation decreases. Furthermore, when the first bias voltage is applied and the second bias voltage is applied, the change in the amount of charge accumulation in the photoelectric conversion section 10A depends on the ratio of the shortest distance D1 between the upper electrode 5 and the lower electrode 2 to the thickness D2 of the charge blocking layer 3.

[0165] [Electrostatic Capacitance-Voltage Characteristics of the Photoelectric Conversion Unit]

[0166] Next, the electrostatic capacitance-voltage characteristics of the photoelectric conversion unit 10A will be described.

[0167] Figure 8 This is a diagram illustrating an example of the electrostatic capacitance-voltage characteristic (CV characteristic) of the photoelectric conversion unit 10A. Figure 8 In the diagram, the vertical axis represents the electrostatic capacitance output between the lower electrode 2 and the upper electrode 5, while the horizontal axis represents the voltage applied between the upper electrode 5 and the lower electrode 2. Figure 8 An example of the schematic electrostatic capacitance-voltage characteristics of a photoelectric conversion unit according to a reference example is also shown.

[0168] exist Figure 8 In the diagram, solid lines illustrate an example of the schematic CV characteristics of the photoelectric conversion unit 10A according to this embodiment. Dashed lines illustrate an example of the schematic CV characteristics of the photoelectric conversion unit according to a reference example. For example, Figure 8 The CV characteristics shown were measured when the photoelectric conversion unit 10A was not exposed to light. Additionally, in... Figure 8 In this context, electrostatic capacitance is expressed in standardized arbitrary units.

[0169] exist Figure 8 In this diagram, the voltage at which the signal charge moves downward to the lower electrode 2 is defined as a "positive" value, illustrating the CV characteristic. That is, in Figure 8 In the diagram, the voltage at which the signal charge is captured by the lower electrode 2 is on the right side of the horizontal axis, and the voltage at which the signal charge is inhibited from moving to the lower electrode 2 is on the left side of the horizontal axis. Therefore, when the signal charge is a hole, the voltage at which the potential of the upper electrode 5 is higher than that of the lower electrode 2 is a "positive" value; when the signal charge is an electron, the voltage at which the potential of the upper electrode 5 is lower than that of the lower electrode 2 is a "positive" value. Furthermore, as... Figure 8As shown, the first bias voltage V1 used to trap signal charge on the lower electrode 2 is higher than the second bias voltage V2 used to suppress the movement of signal charge to the lower electrode 2 and promote the recombination of holes and electrons.

[0170] like Figure 8 As shown, in the CV characteristics of the photoelectric conversion unit according to the reference example and the photoelectric conversion unit 10A according to this embodiment, generally, when the voltage applied between the lower electrode 2 and the upper electrode 5 decreases, the electrostatic capacitance increases. More specifically, in the CV characteristics of the photoelectric conversion unit 10A, when the voltage applied between the lower electrode 2 and the upper electrode 5 decreases from a large positive voltage, the electrostatic capacitance remains constant until a predetermined voltage is reached, and the electrostatic capacitance increases at the predetermined voltage. This is because, as described above, charge tends to accumulate in the photoelectric conversion unit 10A. Furthermore, when the voltage further decreases below the predetermined voltage, the electrostatic capacitance again becomes constant below the predetermined negative voltage. Note that the electrostatic capacitance specifically refers to the electrostatic capacitance that changes by less than 1% when the voltage changes by 1V, provided that the voltage is decreased or increased within a range that does not damage the photoelectric conversion unit 10A. Furthermore, in the CV characteristics of the photoelectric conversion unit 10A, if the voltage is made further lower than the specified negative voltage, the potential difference between the lower electrode 2 and the upper electrode 5 will increase, and the charge accumulated in the photoelectric conversion unit 10A will easily move back to the electrode, so the temporarily increased electrostatic capacitance may also decrease.

[0171] When the electrostatic capacitance is set to C1 when a first bias voltage V1 is applied between the lower electrode 2 and the upper electrode 5, and to C2 when a second bias voltage V2 is applied between the lower electrode 2 and the upper electrode 5, the electrostatic capacitance C1 is smaller than the electrostatic capacitance C2. This is because, as mentioned above... Figure 6 and Figure 7 The charge accumulated in the photoelectric conversion unit 10A is small when the first bias voltage V1 is applied, and large when the second bias voltage V2 is applied. Furthermore, the electrostatic capacitances C1 and C2 are averaged values ​​obtained by measuring the impedance at frequencies from 10Hz to 10kHz using an impedance meter such as an LCR meter connected to the lower electrode 2 and the upper electrode 5, without irradiating the photoelectric conversion unit 10A with light. Additionally, the electrostatic capacitances C1 and C2 can be measured together for multiple pixels 24 and calculated as the value in the photoelectric conversion unit 10A of a single pixel 24. The electrostatic capacitances C1 and C2 can also be used to divide the imaging device 100 and measure pixel blocks composed of one or more pixels 24.

[0172] Figure 9This is a diagram conceptually illustrating the distribution of the amount of charge accumulated in the photoelectric conversion unit 10A. Figure 9 In the diagram, the horizontal axis represents the amount of charge stored in the photoelectric conversion unit 10A. Additionally, in... Figure 9 In the figure, the vertical axis represents the number of photoelectric conversion units 10A that have accumulated charge when multiple photoelectric conversion units 10A are charged under the same conditions, or the number of times the charge has accumulated in the photoelectric conversion units 10A when the photoelectric conversion units 10A are charged multiple times under the same conditions at certain intervals.

[0173] In addition, Figure 9 In the graph, the solid line schematically illustrates the distribution of charge when the amount of charge accumulated in the photoelectric conversion unit 10A is large. Furthermore, in Figure 9 In the diagram, the dashed curve schematically illustrates the distribution of charge when the amount of charge accumulated in the photoelectric conversion unit 10A is small. For example... Figure 9 As shown, the deviation in the amount of charge accumulated in the photoelectric conversion unit 10A varies depending on this charge amount. Therefore, since the variation in the amount of charge accumulated in the photoelectric conversion unit 10A is small during exposure and non-exposure periods, even during non-exposure periods when charge easily accumulates in the photoelectric conversion unit 10A, the amount of charge accumulated in the photoelectric conversion unit 10A is small, and the deviation in the amount of charge accumulated in the photoelectric conversion unit 10A is small. Therefore, the influence of the deviation in the amount of charge accumulated in the photoelectric conversion unit 10A on the charge accumulation node 34 electrically connected to the photoelectric conversion unit 10A can be reduced, and the noise in the imaging device 100 can be reduced.

[0174] The amount of charge in the photoelectric conversion unit 10A depends on its electrostatic capacitance. Therefore, by ensuring that the electrostatic capacitance C1 when the first bias voltage V1 is applied and the electrostatic capacitance C2 when the second bias voltage V2 is applied in the photoelectric conversion unit 10A meet predetermined conditions, a camera device 100 with reduced noise can be achieved. Specifically, in the camera device 100 of this embodiment, by satisfying (C2-C1) / C1≤1, the amount of charge accumulated in the photoelectric conversion unit 10A can be reduced, thereby reducing noise. Furthermore, from the viewpoint of further reducing noise, in the camera device 100, (C2-C1) / C1≤0.5 or (C2-C1) / C1≤0.3 can be satisfied. From the viewpoint of maintaining the sensitivity of the photoelectric conversion unit 10A, (C2-C1) / C1≥0.1 can be satisfied.

[0175] The first bias voltage V1 is, for example, greater than 0V, and the absolute value of the first bias voltage V1 is greater than the absolute value of the second bias voltage V2. The first bias voltage V1 can be, for example, 2V or more, or 5V or more. Alternatively, the first bias voltage V1 can be, for example, 15V or less. Furthermore, the first bias voltage V1 is, for example, within the CV characteristics of the photoelectric conversion unit 10A, such that the electrostatic capacitor becomes a voltage within a certain voltage range when the voltage is increased.

[0176] The second bias voltage V2 is, for example, a negative voltage less than 0V. The second bias voltage V2 can be less than -0.5V or less than -1V. Alternatively, the second bias voltage V2 can be greater than -5V or greater than -3V. Furthermore, the second bias voltage V2 is a voltage below the inflection point after the value of the electrostatic capacitance begins to rise in the CV characteristic of the photoelectric conversion unit 10A when the voltage is reduced.

[0177] Furthermore, the values ​​of these first bias voltages V1 and second bias voltages V2, as described above, are values ​​where the voltage that moves the signal charge to the lower electrode 2 is defined as a "positive" value.

[0178] Furthermore, as described above, the change in the amount of charge accumulated in the photoelectric conversion unit 10A when the first bias voltage V1 and the second bias voltage V2 are applied depends on the ratio of the shortest distance D1 between the upper electrode 5 and the lower electrode 2 to the thickness D2 of the charge blocking layer 3. In the imaging device 100 according to this embodiment, since the thickness D2 of the charge blocking layer 3 is equal to or greater than 25% of the shortest distance D1 between the lower electrode 2 and the upper electrode 5, the amount of charge accumulated in the photoelectric conversion unit 10A can be reduced, and noise can be reduced. From the viewpoint of further reducing noise, the thickness D2 of the charge blocking layer 3 can be 40% or more, or 50% or more, of the shortest distance D1 between the lower electrode 2 and the upper electrode 5.

[0179] Furthermore, from the viewpoint of maintaining the sensitivity of the photoelectric conversion unit 10A by suppressing the decrease in the electric field strength applied to the photoelectric conversion unit 10A, the thickness D2 of the charge blocking layer 3 can be less than 80% of the shortest distance between the lower electrode 2 and the upper electrode 5, or less than 60%.

[0180] Next, refer to Figure 4 This section will explain the saturation signal quantity and the ratio of saturation signal quantity to noise, i.e., the dynamic range, of the imaging device 100. Here, the case where holes are used as signal charges will be described.

[0181] exist Figure 4As described above, holes generated by the photoelectric conversion unit 10A are stored in the charge storage node 34. When holes are stored, the potential of the charge storage node 34 rises. That is, in this case, the maximum potential corresponding to the amount of charge that the charge storage node 34 can retain becomes the saturation signal quantity in the imaging device 100. Typically, a voltage amplitude of approximately 3V in the charge storage node 34, equivalent to the gate voltage of the amplifying transistor 21, is permissible. In this case, for example, when the conversion gain is 50μV / e... - 6e was generated in the camera device - When noise levels are low, a dynamic range of 80 dB, comparable to that of the human eye, can be ensured. In the imaging device 100 of this embodiment, the amount of charge accumulated in the photoelectric conversion unit 10A changes little during exposure and non-exposure periods. Therefore, even during non-exposure periods when charge easily accumulates in the photoelectric conversion unit 10A, the amount of charge accumulated in the photoelectric conversion unit 10A is reduced, noise is lowered, and a wide dynamic range can be achieved.

[0182] Example

[0183] The imaging device of the present invention will be specifically described below through embodiments, but the present invention is not limited to the following embodiments. In detail, the photoelectric conversion element and the photoelectric conversion element for characteristic comparison of the imaging device of the present invention are manufactured, and the electrostatic capacitance is measured. In addition, the imaging device and the imaging device for characteristic comparison according to the present disclosure are manufactured, and the noise is measured.

[0184] (Fabrication of photoelectric conversion elements)

[0185] The photoelectric conversion element in the embodiments and comparative examples is fabricated.

[0186] [Example 1]

[0187] Using TiN as the lower electrode 2, a 9,9'-[1,1'-biphenyl]-4,4'-dimethylbis[3,6-bis(1,1-dimethylethyl]]-9H-carbazole film was deposited on the lower electrode 2 by vacuum evaporation, thereby forming a charge blocking layer 3. The thickness D2 of the charge blocking layer 3 obtained at this time is 150 nm.

[0188] Next, on the charge blocking layer 3, a photoelectric conversion layer 4 is formed by co-deposition using subphthalocyanine as the donor semiconductor material and fullerene C60 as the acceptor semiconductor material, via vacuum evaporation. The weight ratio of the donor semiconductor material to the acceptor semiconductor material is 1:3. Furthermore, the thickness of the photoelectric conversion layer 4 obtained at this time is 400 nm. Additionally, the subphthalocyanine used has boron (B) as the central metal and chloride ions coordinated on B as ligands.

[0189] Next, an ITO film is formed on the photoelectric conversion layer 4 as the upper electrode 5 by sputtering, and then an Al2O3 film is formed on the upper electrode 5 as a sealing film by atomic layer deposition, thereby obtaining the photoelectric conversion element in Example 1. In the photoelectric conversion element of Example 1, the shortest distance D1 between the lower electrode 2 and the upper electrode 5 is 550 nm, and D2 / D1 = 0.27 (27%).

[0190] [Example 2]

[0191] Except for forming a charge blocking layer 3 with a thickness D2 of 300 nm, the photoelectric conversion element in Example 2 is obtained by performing the same steps as in Example 1. In the photoelectric conversion element of Example 2, the shortest distance D1 between the lower electrode 2 and the upper electrode 5 is 700 nm, and D2 / D1 = 0.43 (43%).

[0192] [Example 3]

[0193] Except for forming a charge blocking layer 3 with a thickness D2 of 450 nm, the photoelectric conversion element in Example 3 is obtained by performing the same steps as in Example 1. In the photoelectric conversion element of Example 3, the shortest distance D1 between the lower electrode 2 and the upper electrode 5 is 850 nm, and D2 / D1 = 0.53 (53%).

[0194] [Comparative Example 1]

[0195] Except for forming the charge blocking layer 3 with a thickness D2 of 50 nm, the same process as in Example 1 was performed to obtain the photoelectric conversion element in Comparative Example 1. In the photoelectric conversion element of Comparative Example 1, the shortest distance D1 between the lower electrode 2 and the upper electrode 5 is 450 nm, and D2 / D1 = 0.11 (11%).

[0196] (Measurement of electrostatic capacitance)

[0197] The electrostatic capacitance of the photoelectric conversion element in the examples and comparative examples was measured.

[0198] In measuring the electrostatic capacitance of a photoelectric conversion element, for the obtained photoelectric conversion element, without allowing light to be incident on the element, the impedance at AC frequencies from 10 Hz to 10 kHz is measured using an LCR meter (E4980A, KeySite Technologie) connected to the lower electrode 2 and the upper electrode 5, and the average value of the electrostatic capacitance at each frequency is calculated. Furthermore, the electrostatic capacitance when a first bias voltage of 10V is applied between the lower electrode 2 and the upper electrode 5 is designated as C1, and the electrostatic capacitance when a second bias voltage of -1V is applied between the lower electrode 2 and the upper electrode 5 is designated as C2. Additionally, the bias voltage applied when the potential of the upper electrode 5 is higher than that of the lower electrode 2 is designated as a "positive" value.

[0199] In the photoelectric conversion elements of Examples 1 to 3, (C2-C1) / C1 is less than 1, while in the photoelectric conversion element of Comparative Example 1, (C2-C1) / C1 is greater than 1.

[0200] (The construction of the camera device)

[0201] Using the photoelectric conversion element from Embodiment 1 as the photoelectric conversion unit of each pixel 24, a charge detection circuit 35 connected to the lower electrode 2 via the charge accumulation node 34 is formed, and the imaging device of Embodiment 1 is manufactured. In the same manner as Embodiment 1, the photoelectric conversion elements from Embodiments 2 and 3 and Comparative Example 1 are used as the photoelectric conversion units of each pixel 24, and the imaging devices of Embodiments 2 and 3 and Comparative Example 1 are manufactured respectively.

[0202] (Measurement of random noise)

[0203] Regarding the imaging apparatus in the embodiments and comparative examples, in order to evaluate noise, the output detected by the charge detection circuit 35 of each pixel 24 is obtained. Specifically, without light incident on the imaging apparatus, the output detected by the charge detection circuit 35 is obtained based on the amount of charge accumulated in the charge accumulation node 34 after a predetermined period has elapsed since the potential of the charge accumulation node 34 of each pixel 24 was reset. Furthermore, at this time, a voltage of -1V is applied between the lower electrode 2 and the upper electrode 5, with the potential of the lower electrode 2 as a reference. That is, a voltage lower than the potential of the upper electrode 5 is applied between the lower electrode 2 and the upper electrode 5. Then, as random noise, the standard deviation of the output from each pixel 24 is calculated.

[0204] Figure 10 This is a graph showing the relationship between (C2-C1) / C1 and random noise in the camera device of the embodiments and comparative examples. Figure 11 This is a graph showing the relationship between D2 / D1 and random noise in the imaging devices of the embodiments and comparative examples. Figure 10 and Figure 11In the diagram, the vertical axis represents random noise. The value of the random noise on the vertical axis is obtained by normalizing the random noise value to 1 relative to the saturation signal of the imaging device in the embodiments and comparative examples, under the condition of a dynamic range equivalent to 80 dB of the human eye. Furthermore, the dynamic range at this time is 20log. 10 (Saturated semaphore / random noise). Additionally, in Figure 10 The horizontal axis is (C2-C1) / C1, in Figure 11 The horizontal axis is D2 / D1. Figure 10 and Figure 11 The black dots in the table correspond to the random noise measurement results of the camera devices in Example 3, Example 2, Example 1 and Comparative Example 1, in ascending order of random noise.

[0205] like Figure 10 and Figure 11 As shown, it can be seen that in the camera device that satisfies (C2-C1) / C1≤1 and the camera device that satisfies D2 / D1≥0.25 (25%), the random noise of the camera device is reduced, and a wide dynamic range of more than 80dB equivalent to the human eye can be achieved.

[0206] As described above, in the imaging apparatus according to this disclosure, such as the imaging apparatus according to the first to third embodiments, a noise-reduced imaging apparatus can be achieved by satisfying (C2-C1) / C1≤1 and D2 / D1≥0.25 (25%). This is because, as described above, the variation in the amount of charge stored in the photoelectric conversion unit is small, thereby reducing the influence of deviations in the amount of charge stored in the photoelectric conversion unit on the charge storage node 34 electrically connected to the photoelectric conversion unit.

[0207] Although a camera device according to this disclosure has been described based on embodiments and examples, this disclosure is not limited to these embodiments and examples. Various modifications to the embodiments and embodiments that would occur to those skilled in the art, as well as other ways of constructing embodiments and embodiments by combining some of their constituent elements, are also included within the scope of this disclosure, without departing from its spirit.

[0208] Industrial applicability

[0209] The camera devices disclosed herein can be applied to various camera systems and sensor systems, such as medical cameras, surveillance cameras, vehicle-mounted cameras, rangefinder cameras, microscope cameras, drone cameras, and robot cameras.

[0210] Explanation of reference numerals in the attached figures

[0211] 1 Support base plate

[0212] 2 Lower electrode

[0213] 3, 6 charge blocking layers

[0214] 4 Photoelectric conversion layer

[0215] 4A donor semiconductor materials

[0216] 4B receptor semiconductor materials

[0217] 5. Upper electrode

[0218] 10, 11 Photoelectric conversion elements

[0219] 10A Photoelectric Conversion Unit

[0220] 19. Voltage supply circuit

[0221] 20 Horizontal Signal Readout Circuit

[0222] 21 Amplifying Transistors

[0223] 22 Reset transistor

[0224] 23 Address Transistors

[0225] 21D, 21S, 22D, 22S, 23S impurity regions

[0226] 21G, 22G, 23G gate electrodes

[0227] 21X, 22X, 23X gate insulating layers

[0228] 24 pixels

[0229] 25 Vertical Scanning Circuit

[0230] 26 Opposite electrode signal lines

[0231] 27 Vertical signal lines

[0232] 28 Load Circuit

[0233] 29 signal processing circuits

[0234] 31 Power Wiring

[0235] 32 Differential Amplifier

[0236] 33 Feedback Line

[0237] 34 Charge accumulation nodes

[0238] 35 Charge Detection Circuit

[0239] 36 address signal lines

[0240] 37 Reset signal line

[0241] 40 Semiconductor substrate

[0242] 41 Component Separation Area

[0243] 50 interlayer insulation layers

[0244] 51, 53, 54 contact plugs

[0245] 52 Wiring

[0246] 60 color filter

[0247] 61 Microlenses

[0248] 100 camera devices

Claims

1. A camera device having multiple pixels, The plurality of pixels each have: First electrode; A second electrode, configured opposite to the first electrode; and A photoelectric conversion layer, located between the first electrode and the second electrode, comprises donor semiconductor material and acceptor semiconductor material to generate electrons and holes. Between the first electrode and the second electrode, a first bias voltage is applied during a first period, which is an exposure period, and a second bias voltage, different from the first bias voltage, is applied during a second period, which is a non-exposure period. When the electrostatic capacitance between the first and second electrodes is set to C1 when the first bias voltage is applied between the first and second electrodes, and the electrostatic capacitance between the first and second electrodes is set to C2 when the second bias voltage is applied between the first and second electrodes, the following conditions are met: (C2-C1) / C1≤1.

2. The camera device according to claim 1, wherein, The photoelectric conversion efficiency of the plurality of pixels in the first period is different from that of the plurality of pixels in the second period.

3. The camera device according to claim 1, wherein, The camera device operates using a uniform global shutter speed across all exposure periods of the multiple pixels. Each of the plurality of pixels also has a charge accumulation region, which is electrically connected to the first electrode, and accumulates signal charge as one of the electrons and holes. The first period is a period for accumulating the signal charge in the charge accumulation region.

4. The camera device according to claim 3, wherein, By applying the second bias voltage between the first electrode and the second electrode, the electrons and holes in the photoelectric conversion layer recombine.

5. The camera device according to claim 3, wherein, The photoelectric conversion sensitivity is generated in the photoelectric conversion layer by applying the first bias voltage between the first electrode and the second electrode.

6. The camera device according to any one of claims 1 to 5, wherein, The camera device also includes a voltage supply circuit that selectively applies a bias voltage between the first electrode and the second electrode to make the potential of the second electrode positive relative to the first electrode and a bias voltage to make the potential of the second electrode negative relative to the first electrode.

7. A camera device having multiple pixels, The plurality of pixels each have: First electrode; The second electrode is configured opposite to the first electrode; A photoelectric conversion layer, located between the first electrode and the second electrode, comprises donor semiconductor material and acceptor semiconductor material to generate electrons and holes; A first charge-blocking layer is located between the first electrode and the photoelectric conversion layer; as well as The charge accumulation region is electrically connected to the first electrode, and accumulates signal charge as either the hole or the electron. A first bias voltage is applied between the first electrode and the second electrode during a first period, and a second bias voltage different from the first bias voltage is applied during a second period. The thickness of the first charge barrier layer is more than 25% of the shortest distance between the first electrode and the second electrode.

8. The camera device according to claim 7, wherein, The thickness of the first charge-blocking layer is 10 nm or more.

9. The camera device according to claim 7 or 8, wherein, The signal charge is the hole. The first charge-blocking layer comprises a first semiconductor material. The difference between the ionization potential of the first semiconductor material contained in the first charge blocking layer and the ionization potential of the donor semiconductor material contained in the photoelectric conversion layer is less than 1 eV.

10. The camera device according to claim 7 or 8, wherein, The signal charge is the electron. The first charge-blocking layer comprises a first semiconductor material. The difference between the electron affinity of the first semiconductor material contained in the first charge blocking layer and the electron affinity of the acceptor semiconductor material contained in the photoelectric conversion layer is less than 1 eV.

11. The camera device according to claim 7, wherein, Each of the plurality of pixels also has a second charge blocking layer located between the second electrode and the photoelectric conversion layer.

12. The camera device according to claim 11, wherein, The thickness of the second charge barrier layer is 5 nm or more.

13. The camera device according to claim 11 or 12, wherein, The signal charge is the hole. The second charge-blocking layer comprises a second semiconductor material. The difference between the electron affinity of the second semiconductor material contained in the second charge blocking layer and the electron affinity of the acceptor semiconductor material contained in the photoelectric conversion layer is less than 1 eV.

14. The camera device according to claim 11 or 12, wherein, The signal charge is the electron. The second charge-blocking layer comprises a second semiconductor material. The difference between the ionization potential of the second semiconductor material contained in the second charge blocking layer and the ionization potential of the donor semiconductor material contained in the photoelectric conversion layer is less than 1 eV.

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