Voltage step scanning method and device of Josephson junction array

Abstract

The invention relates to a Josephson junction array voltage step scanning method and device, computer equipment, a computer readable storage medium and a computer program product. The method comprises the following steps: determining a critical current of a junction array section of a Josephson junction array in a superconducting state; according to the critical current, under preset microwave frequency and power, voltage steps of a junction array section of the Josephson junction array in the positive direction and the negative direction are obtained; determining step widths and center point data of voltage steps in the positive direction, the negative direction and the zero direction by adopting a variable step size strategy; respectively determining voltage step boundaries in the positive direction and the negative direction by using a successive comparison method; and in an interval defined by the voltage step boundary, correcting the central point data and the step width of the voltage step by adopting a local outlier factor anomaly detection algorithm. By adopting the method, the voltage step boundary can be positioned, and the accuracy of voltage step scanning of the Josephson junction array is improved.

Description

Technical Field

[0001] This application relates to the field of current monitoring technology, and in particular to a method, apparatus, computer device, computer-readable storage medium, and computer program product for scanning voltage steps using a Josephson array. Background Technology

[0002] With the development of quantum metrology, the Josephson effect has been widely applied to the establishment of quantum references for AC voltage. Josephson arrays, under microwave irradiation, can generate quantized voltage steps, known as Shapiro steps. By differentially measuring the step wave quantum voltage with the measured sinusoidal voltage, extremely high-precision AC voltage references can be achieved. However, the stability of this process is highly dependent on the smoothness of the voltage steps generated by the Josephson array.

[0003] Currently, researchers generally employ software-based random scanning methods to test the stability of quantum voltage steps. This method pre-sets multiple scan points, applies a preset scan current to the array, and detects voltage changes to determine its disturbance rejection capability. The selection of scan points depends on the minimum step width and scanning accuracy of the array, typically using equal division, with the point closest to the step center and not exceeding a threshold value serving as the current boundary. However, traditional techniques have the following drawbacks: this method can only obtain a rough boundary of the critical current, failing to accurately pinpoint its true value; it is highly dependent on the accuracy of the step width data, and errors in the data may lead to missed boundary points; when the step center data is offset or has significant noise, the scanning range is limited, resulting in unreliable results; multiple random scans are required, which is time-consuming and difficult to automate and implement in real-time correction.

[0004] Therefore, there is an urgent need for a method, apparatus, computer equipment, computer-readable storage medium, and computer program product for scanning voltage steps using a Josephson array, which can locate voltage step boundaries and improve the accuracy of voltage step scanning using a Josephson array. Summary of the Invention

[0005] Therefore, it is necessary to provide a method, apparatus, computer device, computer-readable storage medium, and computer program product for scanning voltage steps of a Josephson array that can locate voltage step boundaries and improve the accuracy of voltage step scanning of the Josephson array, in order to address the above-mentioned technical problems.

[0006] In a first aspect, this application provides a voltage step scanning method for a Josephson array, including:

[0007] Determine the critical current for maintaining superconductivity in the junction section of the Josephson array;

[0008] Based on the critical current, at a preset microwave frequency and power, the voltage steps of the array segment of the Josephson array in the positive and negative directions are obtained.

[0009] Based on the voltage steps in the positive and negative directions, a variable step size strategy is adopted to determine the step width and center point data of the voltage steps in the positive, negative and zero directions.

[0010] Based on the step width and center point data of the voltage steps in the positive, negative and zero directions, the voltage step boundaries in the positive and negative directions are determined by the successive comparison method.

[0011] Within the interval defined by the voltage step boundary, a local outlier anomaly detection algorithm is used to correct the center point data and step width of the voltage step.

[0012] In one embodiment, determining the voltage step boundaries in the positive and negative directions using a successive comparison method based on the step width and center point data of the voltage steps in the positive, negative, and zero directions includes:

[0013] Based on the step width and center point data of the voltage steps in the positive, negative and zero directions, the last two scan currents are used as the interval endpoints.

[0014] Based on the relationship between the previous comparison result and the preset threshold, a new average boundary current is calculated within the interval;

[0015] Return to the step of determining the critical current of the Josephson array segment in maintaining the superconducting state until the cumulative number of comparisons reaches the preset comparison threshold or the preset convergence condition, and then determine the voltage step boundaries in the positive and negative directions respectively.

[0016] In one embodiment, the step of employing a local outlier anomaly detection algorithm to correct the center point data and step width of the voltage step includes:

[0017] Within the interval defined by the voltage step boundary, a local outlier anomaly detection algorithm is used to filter voltage and current data within the positive and negative voltage step boundaries to determine the flat sections of the voltage step.

[0018] Based on the leftmost and rightmost boundary current values ​​corresponding to the flat segment, the voltage step boundaries in the positive and negative directions are redefined, and the center point data and step width of the voltage step are corrected.

[0019] In one embodiment, the use of a local outlier anomaly detection algorithm to filter voltage and current data within the positive and negative voltage step boundaries to determine the flat segments of the voltage step includes:

[0020] Based on the voltage and current data within the voltage step boundaries in the positive and negative directions, calculate the k-th reachable distance between any two current data or any two voltage data, and sort the multiple k-th reachable distances.

[0021] Based on the k-th reachable distance after sorting, a local outlier anomaly detection algorithm is used to determine the unstable points at the voltage step boundary and the abnormal noise points in the middle of the step.

[0022] Based on the unstable points at the voltage step boundary and the abnormal noise points in the middle of the step, abnormal data are filtered out from the voltage and current data within the voltage step boundary in the positive and negative directions.

[0023] Based on the voltage and current data within the positive and negative voltage step boundaries after filtering out abnormal data, the flat section of the voltage step is determined.

[0024] In one embodiment, determining the step width and center point data of the voltage steps in the positive, negative, and zero directions using a variable step size strategy based on the voltage steps in the positive and negative directions includes:

[0025] The required output voltage of the digital-to-analog converter is calculated based on the voltage steps in the positive and negative directions and the preset scanning current.

[0026] A variable step size strategy is adopted to alternately apply preset scanning currents in the positive and negative directions to the voltage steps in the array section, and the output voltage of the Josephson array is collected after each application of the preset scanning current.

[0027] The number of times the difference between the output voltage and the theoretical voltage exceeds a set threshold is obtained. As the number of accumulated times gradually increases, the step size of the preset scanning current is gradually reduced until the preset range of the critical current is reached. Then, the step width and center point data of the voltage step in the positive direction, negative direction and zero direction are determined.

[0028] The variable step size strategy includes: scanning with a first-level preset step size; after exceeding a preset threshold for the first time, reducing the step size to a second-level preset step size; after exceeding the preset threshold again, reducing the step size to a third-level preset step size; and when exceeding the preset threshold for the third time, terminating the current level approximation and outputting the current values ​​of the last two scans.

[0029] In one embodiment, determining the critical current for maintaining the superconducting state in the junction section of the Josephson array includes:

[0030] Obtain the current bias state information of the Josephson array, which is used to apply a preset scanning current;

[0031] When the bias state information indicates a superconducting state, the critical current for maintaining the superconducting state in the array segment of the Josephson array is determined.

[0032] Secondly, this application also provides a voltage step scanning device for a Josephson array, comprising:

[0033] The critical current determination module is used to determine the critical current of the Josephson array segment in maintaining superconductivity.

[0034] The voltage step scanning module is used to obtain the voltage steps of the array segment of the Josephson array in the positive and negative directions according to the critical current and at a preset microwave frequency and power.

[0035] The voltage step scanning module is also used to determine the step width and center point data of the voltage steps in the positive, negative and zero directions by adopting a variable step size strategy based on the voltage steps in the positive and negative directions.

[0036] The voltage step scanning module is also used to determine the voltage step boundaries in the positive and negative directions respectively by using the successive comparison method based on the step width and center point data of the voltage steps in the positive, negative and zero directions.

[0037] The voltage step scanning module is also used to correct the center point data and step width of the voltage step within the interval defined by the voltage step boundary by employing a local outlier anomaly detection algorithm.

[0038] Thirdly, this application also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to perform the following steps:

[0039] Determine the critical current for maintaining superconductivity in the junction section of the Josephson array;

[0040] Based on the critical current, at a preset microwave frequency and power, the voltage steps of the array segment of the Josephson array in the positive and negative directions are obtained.

[0041] Based on the voltage steps in the positive and negative directions, a variable step size strategy is adopted to determine the step width and center point data of the voltage steps in the positive, negative and zero directions.

[0042] Based on the step width and center point data of the voltage steps in the positive, negative and zero directions, the voltage step boundaries in the positive and negative directions are determined by the successive comparison method.

[0043] Within the interval defined by the voltage step boundary, a local outlier anomaly detection algorithm is used to correct the center point data and step width of the voltage step.

[0044] Fourthly, this application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, performs the following steps:

[0045] Determine the critical current for maintaining superconductivity in the junction section of the Josephson array;

[0046] Based on the critical current, at a preset microwave frequency and power, the voltage steps of the array segment of the Josephson array in the positive and negative directions are obtained.

[0047] Based on the voltage steps in the positive and negative directions, a variable step size strategy is adopted to determine the step width and center point data of the voltage steps in the positive, negative and zero directions.

[0048] Based on the step width and center point data of the voltage steps in the positive, negative and zero directions, the voltage step boundaries in the positive and negative directions are determined by the successive comparison method.

[0049] Within the interval defined by the voltage step boundary, a local outlier anomaly detection algorithm is used to correct the center point data and step width of the voltage step.

[0050] Fifthly, this application also provides a computer program product, including a computer program that, when executed by a processor, performs the following steps:

[0051] Determine the critical current for maintaining superconductivity in the junction section of the Josephson array;

[0052] Based on the critical current, at a preset microwave frequency and power, the voltage steps of the array segment of the Josephson array in the positive and negative directions are obtained.

[0053] Based on the voltage steps in the positive and negative directions, a variable step size strategy is adopted to determine the step width and center point data of the voltage steps in the positive, negative and zero directions.

[0054] Based on the step width and center point data of the voltage steps in the positive, negative and zero directions, the voltage step boundaries in the positive and negative directions are determined by the successive comparison method.

[0055] Within the interval defined by the voltage step boundary, a local outlier anomaly detection algorithm is used to correct the center point data and step width of the voltage step.

[0056] The aforementioned Josephson array voltage step scanning method, apparatus, computer equipment, computer-readable storage medium, and computer program product, firstly, utilize the critical current maintaining the superconducting state as a global anchor point in the first stage to quickly delineate the approximate range of potential steps, avoiding blindly scanning the entire range; the second stage introduces a variable step size strategy, first using a larger step size for coarse scanning to quickly cover the area, and then using an exponentially shrinking fine step size to approximate the actual transition region, significantly reducing redundant sampling, allowing the number of scan points to be compressed further, and reducing the test time from minutes to seconds; the third stage independently executes the successive comparison method in both positive and negative directions, through iterative binary division... Alternatively, the golden ratio method can be used to converge the boundary positioning error to the level of single-step resolution, completely eliminating the risk of missing boundary points due to inaccurate step width estimation. In the fourth stage, within the locked boundary interval, the Local Outlier Factor (LOF) algorithm is used to perform statistical outlier detection on the center point data, dynamically removing abnormal samples caused by temperature drift, microwave power fluctuations, or electromagnetic interference. Then, the center point and step width are recalculated using weighted average or spline interpolation to ensure that stable and repeatable physical quantities can be output even in strong noise environments, thereby improving the accuracy of voltage step scanning of Josephson arrays. Attached Figure Description

[0057] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0058] Figure 1 This is a standard step curve diagram for voltage step scanning of Josephson arrays in traditional techniques.

[0059] Figure 2 This is a diagram showing the excessively wide step curve of voltage step scanning for Josephson arrays in traditional techniques.

[0060] Figure 3 A diagram of the narrow step curve for voltage step scanning of Josephson array in traditional technology;

[0061] Figure 4 This is a flowchart illustrating a voltage step scanning method for a Josephson array in one embodiment.

[0062] Figure 5 This is a set of valid points and a step curve diagram after removing outliers in one embodiment;

[0063] Figure 6 This is a flowchart illustrating the voltage step scanning method for a Josephson array in another embodiment;

[0064] Figure 7 This is a schematic diagram illustrating the calculation of the relative neighborhood radius of each scan point in the k-th reachable distance in one embodiment;

[0065] Figure 8 This is a structural block diagram of a voltage step scanning device for a Josephson array in one embodiment;

[0066] Figure 9 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0067] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0068] It should be noted that the terms "first," "second," etc., used in this application can be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from the second element. The terms "comprising" and "having," and any variations thereof, used in this application, are intended to cover non-exclusive inclusion. The term "multiple" used in this application refers to two or more. The term "and / or" used in this application refers to one of the embodiments, or any combination of multiple embodiments.

[0069] Traditional techniques have achieved scanning of the critical current and steps of Josephson arrays, but the scanning still has the following drawbacks: some Josephson arrays in a liquid helium-free environment exhibit narrow steps and high noise; existing step scanning methods do not provide accurate step widths and boundaries, resulting in large scanning errors and susceptibility to noise. Ideally, a Josephson array should have smooth steps, with step edges rising or falling in a straight line, such as... Figure 1 As shown. In a liquid helium-free environment, the steps produced by some Josephson arrays are not necessarily ideal curves and exhibit significant noise. Figure 2 ) or the step width is too narrow ( Figure 3 The phenomenon of these steps. Existing methods cannot achieve good results for these steps.

[0070] like Figure 4 As shown, a voltage step scanning method for a Josephson array is provided, including the following steps S402 to S410. Wherein:

[0071] Step S402: Determine the critical current of the Josephson array segment in maintaining the superconducting state.

[0072] The Josephson array is a micro / nano structure composed of several superconducting-insulating-superconducting layers. It can generate quantized voltage steps at zero resistance, serving as a quantum voltage reference. In this embodiment, the array is divided into N segments, each of which can be independently subjected to current.

[0073] The superconducting state refers to a state obtained from the current bias state information of the Josephson array, in which the array segment is always in a superconducting coherent state at zero voltage (or quantum voltage plateau) without any dissipation voltage. The current bias state information refers to the step center point data I_center[i] (the current setting value of the DAC, which determines the operating point) of the i-th segment of the array at any time t; and the voltage across it V_bias[i] (the measured value of the nanovoltmeter, used to determine the stability of the step).

[0074] The critical current refers to the additional, controllable, small DC bias current I_bias injected into the junction array to "perturb" its superconducting state. As I_bias gradually increases from zero, there exists a threshold I_c; exceeding I_c will destroy the superconducting state, causing a voltage jump. This I_c is the "critical current." The preset range of the critical current is a software variable [I_left, I_right], with an initial value of [0,0].

[0075] Step S404: Based on the critical current, determine the voltage steps in the positive and negative directions of the array segment of the Josephson array at a preset microwave frequency and power.

[0076] Specifically, based on the "critical current I_c" measured in step S402, which is the current magnitude that just allows the Josephson array segment to escape the zero-voltage superconducting state, a pre-set microwave frequency f and microwave power P are applied to the array (this is the necessary external excitation for generating the Shapiro step). At this time, the array is in a microwave irradiation environment. Based on I_c, a DC bias current I_bias, which can be positive or negative, is superimposed on the array using a controllable current source. When I_bias slowly increases from 0 in the positive direction, the quantized voltage plateaus (Shapiro steps) appearing at both ends of the array are recorded; this is the "voltage step in the positive direction". When I_bias slowly decreases from 0 in the negative direction (reverse current), a series of quantized voltage plateaus appearing are also recorded; this is the "voltage step in the negative direction".

[0077] Step S406: Based on the voltage steps in the positive and negative directions, a variable step size strategy is adopted to determine the step width and center point data of the voltage steps in the positive, negative and zero directions.

[0078] The "variable step size strategy" refers to the dynamic decreasing of the scan current increment according to a preset rule, rather than a fixed step size. A voltage threshold can be set to determine an initial step size, which is then reduced to a suitable value, and then further reduced to the minimum step size. This reduces the number of scan points and lowers the testing time while maintaining approximation accuracy.

[0079] Specifically, for each step, a variable step size strategy is adopted, which will be given in three offset directions:

[0080] Positive direction: The difference between the left and right boundary currents obtained by positive scanning is the "positive step width", and the midpoint is the "positive center point";

[0081] Negative direction: Similarly, we can obtain the "negative step width" and "negative center point";

[0082] Zero direction: Averaging the results from the positive and negative directions or performing a symmetrical fitting yields the "equivalent step width and center point under zero bias".

[0083] Step S408: Based on the step width and center point data of the voltage steps in the positive, negative and zero directions, the voltage step boundaries in the positive and negative directions are determined by successive comparisons.

[0084] Specifically, the voltage positions corresponding to the last two scanned currents in the positive and negative directions of each segment of the array in step two are used as the voltage step boundaries in the positive and negative directions. Successive comparisons are performed to first determine the number of successive comparisons, and then the voltage step boundaries in the positive and negative directions are determined according to the direction.

[0085] Compared to the variable step size method, the successive comparison method is not limited by the minimum step size accuracy; each comparison increases the accuracy by one bit. However, the successive comparison method runs slower than the variable step size method. Therefore, the variable step size method is suitable for finding step edges, while the successive comparison method is suitable for determining the precise value of step edges. Within the limits of hardware accuracy, setting the appropriate number of successive comparisons can maximize the accuracy of step boundaries.

[0086] Step S410: Within the interval defined by the voltage step boundary, a local outlier anomaly detection algorithm is used to correct the center point data and step width of the voltage step.

[0087] Specifically, within the current range defined by the voltage step boundaries determined by the aforementioned successive comparison method, local outlier factor (LOF) anomaly detection is performed on the set of discrete sampling points contained in the range.

[0088] First, the ratio of the local reachability density of each sampling point to its k nearest neighbors is calculated to obtain the LOF score, which characterizes the degree of anomaly at that point. Then, a statistical threshold is set, and sampling points with LOF scores higher than this threshold are identified as outliers and removed, thus forming a cleaned set of valid points. Subsequently, the center point coordinates of the voltage step are recalculated based on this set of valid points. Specifically, the weighted average of the valid point current values ​​is used as the updated center point current value, and the minimum and maximum valid point current values ​​are used as the updated left and right boundary current values, respectively, to derive the corrected step width. This eliminates center point offset and width distortion caused by measurement noise, temperature drift, or systematic errors, ensuring higher accuracy and repeatability of the voltage step center point data and step width. Figure 5 As shown, Figure 5 The right side shows the set of valid points after outlier removal. Figure 5 The left side shows the voltage step curve formed by the effective point set.

[0089] In the aforementioned Josephson array voltage step scanning method, firstly, the critical current maintaining the superconducting state is used as a global anchor point in the first stage to quickly delineate the approximate range of potential steps, avoiding blindly scanning the entire range; the second stage introduces a variable step size strategy, first using a larger step size for coarse scanning to quickly cover the area, and then using an exponentially shrinking fine step size to approximate the actual transition region, significantly reducing redundant sampling, making the number of scan points compressible and reducing the test time from minutes to seconds; the third stage independently executes the successive comparison method in both positive and negative directions, using iterative binary search or golden section methods to locate the boundary. The error converges to the level of single-step resolution, completely eliminating the risk of missing boundary points due to inaccurate step width estimation. In the fourth stage, within the locked boundary interval, the Local Outlier Factor (LOF) algorithm is used to perform statistical outlier detection on the center point data, dynamically eliminating abnormal samples caused by temperature drift, microwave power fluctuations, or electromagnetic interference. Subsequently, the center point and step width are recalculated using weighted average or spline interpolation, ensuring that stable and repeatable physical quantities can be output even in strong noise environments, thereby improving the accuracy of voltage step scanning of Josephson arrays.

[0090] In one exemplary embodiment, such as Figure 6 As shown, based on the step width and center point data of the voltage steps in the positive, negative, and zero directions, the voltage step boundaries in the positive and negative directions are determined using a successive comparison method, including:

[0091] Step S602: Based on the step width and center point data of the voltage steps in the positive, negative and zero directions, the last two scan currents are used as the interval endpoints.

[0092] Step S604: Based on the relationship between the previous comparison result and the preset threshold, calculate the new average boundary current within the interval; return to the step of determining the critical current of the Josephson array segment in maintaining the superconducting state until the cumulative number of comparisons reaches the preset comparison number threshold or the preset convergence condition, and then determine the voltage step boundaries in the positive and negative directions respectively.

[0093] Specifically, after the variable step size strategy compresses the scanning current to the "preset range of the critical current", it is necessary to further pinpoint two limit values ​​within this range, namely the maximum forward-tolerant scanning current I. + _crit and the maximum reverse scan current I - _crit. This step uses the "successive comparison method" to achieve this precise positioning.

[0094] The interval endpoints refer to the two endpoints of the initial interval, using the last two scan current values ​​as the starting points. Their function is to provide a starting range for the successive comparison method, ensuring that the search interval includes the critical value. The last two scan currents, I_left and I_right, constitute a closed interval [I_left, I_right], with an interval width ≤ 0.1mA. Let the positive pointer p... + and reverse pointer p - The initial values ​​are I_left and I_right, respectively. Convergence is considered to have occurred when the interval width is less than or equal to the minimum resolution of 0.01mA or when two consecutive comparisons yield the same result.

[0095] The preset threshold refers to the set voltage difference threshold ΔV_th, used to determine whether the disturbance exceeds the allowable range. Its function is to serve as a criterion for deciding whether the search interval needs to be further refined. The average boundary current refers to the new boundary current value calculated within the current interval, usually the average of the interval endpoints. Its function is to gradually narrow the search interval, approaching the boundary current.

[0096] The preset number of comparisons or convergence criteria refers to the maximum number of comparisons or the minimum value of the interval width. Its purpose is to ensure that the algorithm completes within a finite number of steps, avoiding infinite loops.

[0097] Specifically, within the interval [I_left, I_right], calculate the new scanning current I_mid = (I_left + I_right) / 2; calculate the corresponding DAC output voltage based on I_mid and apply the preset scanning current; acquire the array output voltage V_out and calculate the difference ΔV = |V_out - V_theory| with the theoretical voltage V_theory; if ΔV < ΔV_th, it means the current scanning current is within the allowable range, and update I_left to I_mid; if ΔV ≥ ΔV_th, it means the current scanning current exceeds the allowable range, and update I_right to I_mid; repeat these steps until the preset number of comparisons is reached or the interval width is less than the preset convergence condition; when the termination condition is met, take I_left as the positive voltage step boundary I. + _crit; Repeat the above process for the negative direction, taking I_left as the voltage step boundary I-_crit in the negative direction.

[0098] In this embodiment, the voltage step boundaries in the positive and negative directions are precisely determined by progressively refining the search interval. Boundary localization is completed within a finite number of steps, avoiding unnecessary minor perturbations and improving testing efficiency. The stability and reliability of the algorithm are ensured by pre-setting the number of comparisons and convergence conditions. The positive and negative directions are executed independently to ensure boundary symmetry and reliability, providing an accurate basis for the subsequent establishment of a quantum voltage benchmark.

[0099] In an exemplary embodiment, a local outlier anomaly detection algorithm is used to correct the center point data and step width of the voltage step, including:

[0100] Within the interval defined by the voltage step boundary, a local outlier anomaly detection algorithm is used to filter voltage and current data within the positive and negative voltage step boundaries to determine the flat section of the voltage step.

[0101] Based on the leftmost and rightmost boundary current values ​​corresponding to the flat segment, the voltage step boundaries in the positive and negative directions are redefined, and the center point data and step width of the voltage step are corrected.

[0102] The Local Outlier Factor (LOF) anomaly detection algorithm is a density-based anomaly detection algorithm used to identify outliers in data. Its function is to filter out flat segments of voltage steps within the voltage step boundaries, eliminating noise and outliers to ensure data reliability.

[0103] The flat section refers to the interval within the voltage step boundary where voltage data is relatively stable and changes are minimal. Its purpose is to serve as a basis for correcting critical boundaries and voltage step parameters, ensuring that the corrected parameters are more accurate.

[0104] The leftmost and rightmost boundary current values ​​refer to the leftmost and rightmost current values ​​corresponding to the flat segment. Their function is to redefine the positive and negative voltage step boundaries and correct the center point data and step width of the voltage steps.

[0105] In this embodiment, the LOF algorithm is used to filter out flat segments, eliminating noise and outliers to ensure data reliability. The redefined voltage step boundaries are more accurate, reducing errors caused by noise. The corrected voltage step center point data and step width better match actual physical characteristics, improving measurement accuracy and reliability. The corrected parameters provide a more accurate foundation for the subsequent establishment of a quantum voltage reference, enhancing the overall system performance.

[0106] In an exemplary embodiment, a local outlier anomaly detection algorithm is used to filter voltage and current data within the boundaries of voltage steps in both positive and negative directions to determine the flat sections of the voltage steps, including:

[0107] Based on the voltage and current data within the voltage step boundaries in the positive and negative directions, calculate the k-th reachable distance between any two current data or any two voltage data, and sort the multiple k-th reachable distances.

[0108] Based on the k-th reachable distance after sorting, a local outlier anomaly detection algorithm is used to determine the unstable points at the voltage step boundary and the abnormal noise points in the middle of the step.

[0109] Based on the unstable points at the voltage step boundary and the abnormal noise points in the middle of the step, abnormal data are filtered out from the voltage and current data within the voltage step boundary in both positive and negative directions.

[0110] Based on the voltage and current data within the positive and negative voltage step boundaries after filtering out abnormal data, the flat section of the voltage step is determined.

[0111] Specifically, within the interval defined by the voltage step boundary, all recorded voltage and current data are collected; a Local Outlier Factor (LOF) anomaly detection algorithm is applied to calculate the LOF value for each data point; based on the LOF value, data points with LOF values ​​less than a preset threshold (e.g., 1.5) are selected, and these data points constitute a flat segment; the leftmost boundary current value I_left_flat and the rightmost boundary current value I_right_flat corresponding to the flat segment are found; and the voltage step boundary I_left_flat is used as the positive direction. +_crit, with I_right_flat as the negative direction voltage step boundary I-_crit; based on the voltage data of the flat segment, recalculate the center point data I_center and the step width ΔI of the voltage step; center point data I_center=(I_left_flat+I_right_flat) / 2; step width ΔI=I_right_flat-I_left_flat.

[0112] It should be noted that a local outlier anomaly detection algorithm is used for current and voltage data within the interval defined by the voltage step boundary. The implementation steps of the algorithm are as follows:

[0113] 1. Determine the k-th reachable distance for each point. First, calculate the pairwise distances between each data point. The formula for calculating the distance from scan point a to scan point b is as follows:

[0114]

[0115] Sort the distance data and find the k nearest points (excluding itself) to each point. This is called the k-th neighborhood, and its radius is the distance to the k-th point, denoted as r. k (a) The relative neighborhood radius of each scan point is as follows: Figure 7 As shown, the k-th reachable distance from a to b can be expressed as:

[0116] r k (a, b) = max{r k (a), r(a, b)};;

[0117] 2. Calculate the local reachability density l(a), where the local reachability density of point a is the sum of the local reachability of all points p in the k-th neighborhood of point a. i (i = 1, 2, ..., N) k The reciprocal of the average of the k-th reachable distances from (a) to a is expressed by the formula:

[0118]

[0119] The higher the local reachability density, the more likely this point is to form the same cluster with the k-th neighborhood.

[0120] 3. Calculate the local outlier factor. The local outlier factor of point a is the sum of the outliers of all points p in the k-th neighborhood of point a. i (i = 1, 2, ..., N) k The average ratio of the local reachability density of point (a) to the local reachability density of point a is expressed by the formula:

[0121]

[0122] The local outlier factor reflects the degree of deviation of data from the data set. When the local outlier factor of a data point is 1, it means that the data distribution around this point is completely uniform; when it is greater than 1, it means that the data distribution around this point is relatively sparse; when it is much greater than 1, it indicates that this point is an outlier; when it is less than 1, it means that the data distribution around this point is relatively dense.

[0123] Generally, setting k=10, after executing the local outlier anomaly detection algorithm, unstable points near the critical current and points with high noise in the middle of the step have large local outlier factors. For example... Figure 5 As shown. Stable points within the step have small local outliers. K-means clustering is used to divide these points into two classes, retaining the class with the smaller local outlier. The currents at the two endpoints of the retained data are then identified; these endpoints encompass the truly stable portion of the step. The average of the two currents is used to correct the step center current, and the difference is used to correct the step width data.

[0124] In this embodiment, local outlier (LOF) anomaly detection is performed within the range bounded by the positive and negative voltage step boundaries. First, the k-th reachable distance between any two current or voltage data points is calculated and sorted to quantify local density differences. Then, based on the sorting results, unstable transition points at the boundaries and anomalous noise points in the middle section are identified and removed, completing data cleaning. Finally, the flat section of the step is accurately defined based on the selected effective dataset. This technical solution significantly improves the signal-to-noise ratio and boundary consistency of the flat section of the step, eliminates pseudo-jumps introduced by measurement drift, environmental disturbances, and system white noise, reduces center point positioning error, improves step width reproducibility, and thus enhances the long-term stability and metrological accuracy of the Josephson quantum voltage reference.

[0125] In an exemplary embodiment, based on the voltage steps in the positive and negative directions, a variable step-size strategy is used to determine the step width and center point data of the voltage steps in the positive, negative, and zero directions, including:

[0126] The required output voltage of the digital-to-analog converter is calculated based on the voltage steps in the positive and negative directions and the preset scanning current.

[0127] A variable step size strategy is adopted to alternately apply preset scanning currents in the positive and negative directions to the voltage steps in the array section, and the output voltage of the Josephson array is collected after each application of the preset scanning current.

[0128] The system acquires the number of times the difference between the output voltage and the theoretical voltage exceeds a set threshold. As the number of accumulated times gradually increases, the step size of the preset scanning current is gradually reduced until the preset range of the critical current is reached. Then, the step width and center point data of the voltage steps in the positive, negative and zero directions are determined.

[0129] The variable step size strategy includes: scanning with a first-level preset step size; after exceeding the preset threshold for the first time, reducing the step size to a second-level preset step size; after exceeding the preset threshold again, reducing the step size to a third-level preset step size; and when exceeding the preset threshold for the third time, terminating the current level approximation and outputting the current values ​​of the last two scans.

[0130] Specifically, alternating the application of preset scanning currents in positive and negative directions refers to first applying a positive scan to the same segment, then performing an equal amount of reverse scan, and repeating this cycle. This eliminates the effects of system drift and thermal drift, ensuring that the positive and reverse critical boundaries are independent and symmetrical. After each DAC voltage write is completed, a current injection is immediately performed, converting the calculated current value into the actual current within the array in real time.

[0131] The acquisition of the output voltage of the Josephson array refers to the reading of the quantum voltage at both ends of the array using a nanovoltmeter. This is used to evaluate the step stability after perturbation and to provide a measured value that is compared with the theoretical voltage, serving as a basis for determining whether the step size continues to decrease.

[0132] The difference between the output voltage and the theoretical voltage refers to the absolute difference between the measured output voltage V_out of the nanovoltmeter and the theoretical voltage V_theory calculated by the system based on the Josephson relation. The threshold ΔV_th is set by the quantum voltage reference calibration experiment, for example, 1μV. The counter C is an 8-bit hardware counter with an initial value of 0. The hardware register stores three step sizes (0.5mA, 0.25mA, 0.1mA). The preset range of the critical current is a software variable [I_left, I_right] with an initial value of [0,0].

[0133] Specifically, after each perturbation, ΔV = |V_out – V_theory| is calculated; if ΔV ≥ ΔV_th, then the counter C ← C + 1; when C reaches 1 for the first time, the step size decreases from 0.5mA to 0.25mA, and C is reset to 0; when C reaches 1 again, the step size decreases from 0.25mA to 0.1mA, and C is reset to 0; when C reaches 1 for the third time, the last scan current I_last is recorded, and the interval [I_last – 0.1mA, I_last + 0.1mA] is set as the "preset interval for the critical current"; the system stops decreasing the step size and enters the successive comparison stage. Through the "three-trigger" rule, the step size is adaptively reduced from coarse to fine, avoiding oversampling while ensuring approximation accuracy, ultimately compressing the scan current to an interval with a width of only 0.1mA.

[0134] In this embodiment, through a closed-loop strategy of "calculating DAC output → alternating positive and negative scans → real-time comparison of output voltage with theoretical voltage → approximating step by step with a three-stage variable step size," the step boundary positioning error can be compressed to the resolution corresponding to the final step size within a single test cycle. The dynamic reduction of the step size reduces the number of sampling points compared to the fixed step size scheme, shortening the test time from minutes to seconds. The cumulative threshold discrimination mechanism ensures that high-resolution scanning is only activated when approaching the instability region, avoiding the additional power consumption and thermal disturbance caused by oversampling and significantly improving the repeatability of center point current and step width. Ultimately, the system can obtain consistent and highly reliable step parameters in the positive, negative, and zero directions without relying on the prior step width.

[0135] In an exemplary embodiment, determining the critical current for maintaining the superconducting state in the junction section of the Josephson array includes:

[0136] Obtain the current bias state information of the Josephson array, which is used to apply a preset scanning current;

[0137] Given that the bias state information represents the superconducting state, determine the critical current for maintaining the superconducting state in the array segment of the Josephson array.

[0138] The acquisition methods can be: Hardware: 16-bit DAC board (±10mA, 1μA step) + nanovoltmeter (1nV resolution). Communication: SPI bus polling, period ≤1ms. Software: MCU firmware functions dac.read_register() and nv.read_voltage().

[0139] Specifically, the MCU reads each segment of the DAC register sequentially via SPI to obtain I_center[i]; the FPGA synchronously triggers the nanovoltmeter to obtain V_bias[i]; (I_center[i], V_bias[i]) is stored in the SRAM buffer; if V_bias[i] exceeds the preset voltage window, the segment is marked as "skipped", and the remaining segments are reserved as "segments to be perturbed"; this array is the input basis for all subsequent critical current calculations and boundary scans.

[0140] In this embodiment, by acquiring and determining the "current bias state information" in real time, the critical current scan is only initiated after confirming that the array segment is in a zero-voltage superconducting coherent state, which fundamentally eliminates the risk of misjudgment caused by initial bias drift or historical state residue; the critical current obtained in this way has higher physical authenticity and repeatability.

[0141] In one embodiment, the array segment to which a preset scanning current is to be applied is determined based on bias state information.

[0142] Among them, the bias state information refers to the current step center point data and the voltage at both ends of each segment array.

[0143] The array segment to which the preset scanning current is to be applied refers to the segment that meets the criteria of "minimum absolute value of total voltage" or "step width greater than minimum measurable value" among all segments; unselected segments are kept at zero bias and no current is injected.

[0144] Specifically, the bias state information is obtained by filtering the N segments S_target from the array D = {(I_center[i], V_bias[i]) | i = 1…N}, where the "allowed injection current" is selected. For each i, if |V_bias[i]| > V_window (example: ±5μV), skip[i] = 1; otherwise, skip[i] = 0.

[0145] Read the minimum step width w_min from the database; if the measured step width of this segment is less than w_min, set skip[i] = 1. Sort the segments with skip[i] = 0 in ascending order by I_center[i], and take the first K segments (K is preset by the user or automatically calculated = ceil(N / 4)). Return S_target = {i | skip[i] = 0 and sort number ≤ K} as the array segment to be applied with the preset scanning current.

[0146] In this process, based on the required scanning current (initial scanning current is 0), the center point data of the array steps is added to it to obtain the array bias current I_bias[k] for each segment. The corresponding voltage is then output by the DAC. The calculation method is as follows:

[0147] The total number of segments in the array is N. To calculate the DAC output voltage V_DAC[k] when the k-th segment is at the corresponding step center point data I_bias[k], we can first calculate the voltages V_JJS[k] and V_JJS[k+1] across the k-th segment. Let the voltage generated by the k-th segment be V_PJVS[k]. The formula for calculating V_JJS[k] is as follows:

[0148]

[0149] The formula for calculating V_DAC[k] is:

[0150]

[0151] In other embodiments, if the array is a redundant parallel structure, S103-1 to S103-4 can be executed in parallel, and the results can be combined according to the minimum total voltage criterion.

[0152] In one embodiment, the required output voltage of the digital-to-analog converter is calculated based on the step center point data of the array segment and a preset scanning current.

[0153] Specifically, the step center point data I_center of the array segment refers to data read from the database or real-time register, in milliamperes. The preset scan current I_perturb is given by a variable step size strategy and changes dynamically with the approximation stage. The digital-to-analog converter (DAC) parameters are 16-bit, ±10mA full range, with a linear mapping relationship of 1LSB≈0.3μA. The array equivalent resistance Rcell is given by the chip design parameters, with a typical value of 2Ω.

[0154] Furthermore, the total injected current I_total = I_center + I_perturb. According to Ohm's law, the required output voltage of the digital-to-analog converter (DAC) is V_DAC = I_total × R_cell. V_DAC is converted into a DAC code value and written to the register. The board then outputs the corresponding voltage, causing the array to flow through I_total. Through this three-step closed-loop process of "current superposition → voltage conversion → DAC output," the scanning current is ensured to be precisely controllable, avoiding errors from manual calculations and providing a repeatable and quantifiable current injection reference for subsequent successive approximations.

[0155] In one exemplary embodiment, the method further includes:

[0156] Before each application of the preset scan current, the initial voltage reading of the digital-to-analog converter is set to zero;

[0157] Determine the current voltage of the Josephson array based on the required output voltage of the digital-to-analog converter;

[0158] Obtain the theoretical voltage of the Josephson array under the current bias state;

[0159] If the voltage deviation between the current voltage and the theoretical voltage of the Josephson array exceeds the preset deviation range, adjust the magnitude and direction of the scanning current for the next scan.

[0160] Setting the initial voltage reading of the digital-to-analog converter (DAC) to zero means setting the DAC's output voltage to zero before each application of a preset scan current. This ensures that the starting point of each scan current is consistent, eliminating the residual effects of previous disturbances.

[0161] The current voltage of the Josephson array refers to the actual voltage of the array calculated based on the output voltage of the DAC. Its function is to provide a real-time voltage reference for comparison with the theoretical voltage.

[0162] The theoretical voltage refers to the expected voltage calculated based on the physical model of the Josephson array and the current bias state. Its purpose is to serve as a standard for assessing whether the current voltage is within acceptable limits.

[0163] The preset voltage deviation range refers to the set allowable voltage deviation range, such as ±1μV. Its function is to serve as a criterion to determine whether the scanning current needs to be adjusted.

[0164] Adjusting the magnitude and direction of the scanning current refers to dynamically adjusting the magnitude and direction of the scanning current for the next scan based on the voltage deviation. Its purpose is to ensure that the applied scanning current remains within the control range, avoiding overshoot or undershoot.

[0165] Specifically, before each application of the preset scan current, the DAC's output voltage is set to zero to ensure a consistent starting point. Based on the required output voltage of the DAC, the current actual voltage V_current of the array is calculated. Based on the array's physical model and the current bias state, the theoretical voltage V_theory is calculated. The voltage deviation ΔV = |V_current - V_theory| is calculated. If ΔV exceeds the preset deviation range (e.g., ±1μV), the magnitude and direction of the next scan current are adjusted according to the deviation direction.

[0166] If V_current > V_theory, decrease the scanning current or change the direction to negative.

[0167] If V_current < V_theory, increase the scanning current or maintain the positive direction.

[0168] In this embodiment, real-time monitoring and adjustment ensure that the applied scanning current remains within the control range, improving measurement accuracy. This avoids system instability caused by excessive voltage deviation, ensuring the reliability of the testing process. The scanning current is dynamically adjusted based on real-time voltage deviation to adapt to different array states and environmental changes. Initial voltage zeroing and real-time adjustment reduce measurement errors and improve the overall system performance.

[0169] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0170] Based on the same inventive concept, this application also provides a voltage step scanning device for Josephson arrays for implementing the voltage step scanning method for Josephson arrays described above. The solution provided by this device is similar to the solution described in the above method. Therefore, the specific limitations of one or more embodiments of the voltage step scanning device for Josephson arrays provided below can be found in the limitations of the voltage step scanning method for Josephson arrays described above, and will not be repeated here.

[0171] In one exemplary embodiment, such as Figure 8 As shown, a voltage step scanning device for a Josephson array is provided, comprising:

[0172] Critical current determination module 802 is used to determine the critical current of the array segment of the Josephson array in maintaining the superconducting state.

[0173] The voltage step scanning module 804 is used to obtain the voltage steps of the array segment of the Josephson array in the positive and negative directions based on the critical current and at a preset microwave frequency and power.

[0174] The voltage step scanning module 804 is also used to determine the step width and center point data of the voltage steps in the positive, negative and zero directions by adopting a variable step size strategy based on the voltage steps in the positive and negative directions.

[0175] The voltage step scanning module 804 is also used to determine the voltage step boundaries in the positive and negative directions respectively by using the successive comparison method based on the step width and center point data of the voltage steps in the positive, negative and zero directions.

[0176] The voltage step scanning module 804 is also used to correct the center point data and step width of the voltage step within the interval defined by the voltage step boundary by employing a local outlier anomaly detection algorithm.

[0177] In an exemplary embodiment, the voltage step scanning module 804 is further configured to: use the step width and center point data of the voltage steps in the positive, negative and zero directions as the interval endpoints, and use the last two scanning currents as the interval endpoints; calculate a new average boundary current within the interval based on the relationship between the previous comparison result and a preset threshold; return to the step of determining the critical current of the Josephson array segment in maintaining the superconducting state, until the cumulative number of comparisons reaches a preset comparison number threshold or a preset convergence condition, and then determine the voltage step boundaries in the positive and negative directions respectively.

[0178] In an exemplary embodiment, the voltage step scanning module 804 is further configured to, within the interval defined by the voltage step boundary, use a local outlier anomaly detection algorithm to filter voltage data and current data within the positive and negative voltage step boundaries to determine the flat segment of the voltage step; based on the leftmost and rightmost boundary current values ​​corresponding to the flat segment, redetermine the positive and negative voltage step boundaries, and correct the center point data and step width of the voltage step.

[0179] In an exemplary embodiment, the voltage step scanning module 804 is further configured to: calculate the k-th reachable distance between any two current data points or any two voltage data points based on the voltage and current data within the voltage step boundaries in the positive and negative directions; sort the multiple k-th reachable distances; determine the unstable points at the voltage step boundaries and the abnormal noise points in the middle section of the step based on the sorted k-th reachable distances; filter the voltage and current data within the voltage step boundaries in the positive and negative directions based on the unstable points at the voltage step boundaries and the abnormal noise points in the middle section of the step; and determine the flat sections of the voltage step based on the voltage and current data within the voltage step boundaries in the positive and negative directions after filtering the abnormal data.

[0180] In an exemplary embodiment, the voltage step scanning module 804 is further configured to calculate the required output voltage of the digital-to-analog converter based on the voltage steps in the positive and negative directions and the preset scanning current; employ a variable step size strategy to alternately apply the preset scanning current in the positive and negative directions to the voltage steps in the array segment, and acquire the output voltage of the Josephson array after each application of the preset scanning current; obtain the cumulative number of times the difference between the output voltage and the theoretical voltage exceeds a set threshold, and gradually reduce the step size of the preset scanning current as the cumulative number increases until a preset range of the critical current is reached, thereby determining the step width and center point data of the voltage steps in the positive, negative, and zero directions; wherein, the variable step size strategy includes: scanning with a first-level preset step size; after exceeding the preset threshold for the first time, reducing the step size to a second-level preset step size; after exceeding the preset threshold again, reducing the step size to a third-level preset step size; when exceeding the preset threshold for the third time, terminating the current level of approximation and outputting the current values ​​of the last two scanning currents.

[0181] In an exemplary embodiment, the critical current determination module 802 is further configured to acquire the current bias state information of the Josephson array, the Josephson array being used to apply a preset scanning current; and, if the bias state information indicates a superconducting state, determine the critical current of the array segment of the Josephson array in maintaining the superconducting state.

[0182] Each module in the aforementioned Josephson array voltage step scanning device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in hardware within or independently of the processor in a computer device, or stored in software within the memory of a computer device, so that the processor can call and execute the operations corresponding to each module.

[0183] In one exemplary embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be as follows: Figure 9 As shown, this computer device includes a processor, memory, input / output (I / O) interfaces, and a communication interface. The processor, memory, and I / O interfaces are connected via a system bus, and the communication interface is also connected to the system bus via the I / O interfaces. The processor provides computational and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and a database. The internal memory provides the environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The database stores the current bias state information of the Josephson array. The I / O interfaces are used for exchanging information between the processor and external devices. The communication interface is used for communication with external terminals via a network connection. When executed by the processor, the computer program implements a voltage step scanning method for a Josephson array.

[0184] Those skilled in the art will understand that Figure 9 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0185] In one exemplary embodiment, a computer device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the method described above.

[0186] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the steps of the above-described method.

[0187] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps of the method described above.

[0188] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of the relevant data must comply with relevant regulations.

[0189] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0190] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0191] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A voltage step scanning method for a Josephson array, characterized in that, The method includes: Determine the critical current for maintaining superconductivity in the junction section of the Josephson array; Based on the critical current, at a preset microwave frequency and power, the voltage steps of the array segment of the Josephson array in the positive and negative directions are obtained. Based on the voltage steps in the positive and negative directions, a variable step size strategy is adopted to determine the step width and center point data of the voltage steps in the positive, negative and zero directions. Based on the step width and center point data of the voltage steps in the positive, negative and zero directions, the voltage step boundaries in the positive and negative directions are determined by the successive comparison method. Within the interval defined by the voltage step boundary, a local outlier anomaly detection algorithm is used to correct the center point data and step width of the voltage step.

2. The method according to claim 1, characterized in that, The step of determining the voltage step boundaries in the positive and negative directions based on the step width and center point data of the voltage steps in the positive, negative, and zero directions, using a successive comparison method, includes: Based on the step width and center point data of the voltage steps in the positive, negative and zero directions, the last two scan currents are used as the interval endpoints. Based on the relationship between the previous comparison result and the preset threshold, a new average boundary current is calculated within the interval; Return to the step of determining the critical current of the Josephson array segment in maintaining the superconducting state until the cumulative number of comparisons reaches the preset comparison threshold or the preset convergence condition, and then determine the voltage step boundaries in the positive and negative directions respectively.

3. The method according to claim 1, characterized in that, The method employs a local outlier anomaly detection algorithm to correct the center point data and step width of the voltage step, including: Within the interval defined by the voltage step boundary, a local outlier anomaly detection algorithm is used to filter voltage and current data within the positive and negative voltage step boundaries to determine the flat sections of the voltage step. Based on the leftmost and rightmost boundary current values ​​corresponding to the flat segment, the voltage step boundaries in the positive and negative directions are redefined, and the center point data and step width of the voltage step are corrected.

4. The method according to claim 3, characterized in that, The method employs a local outlier anomaly detection algorithm to filter voltage and current data within the positive and negative voltage step boundaries to determine the flat segments of the voltage step, including: Based on the voltage and current data within the voltage step boundaries in the positive and negative directions, calculate the k-th reachable distance between any two current data or any two voltage data, and sort the multiple k-th reachable distances. Based on the k-th reachable distance after sorting, a local outlier anomaly detection algorithm is used to determine the unstable points at the voltage step boundary and the abnormal noise points in the middle of the step. Based on the unstable points at the voltage step boundary and the abnormal noise points in the middle of the step, abnormal data are filtered out from the voltage and current data within the voltage step boundary in the positive and negative directions. Based on the voltage and current data within the positive and negative voltage step boundaries after filtering out abnormal data, the flat section of the voltage step is determined.

5. The method according to claim 1, characterized in that, The step width and center point data of the voltage steps in the positive, negative, and zero directions are determined using a variable step size strategy based on the voltage steps in the positive and negative directions, including: The required output voltage of the digital-to-analog converter is calculated based on the voltage steps in the positive and negative directions and the preset scanning current. A variable step size strategy is adopted to alternately apply preset scanning currents in the positive and negative directions to the voltage steps in the array section, and the output voltage of the Josephson array is collected after each application of the preset scanning current. The number of times the difference between the output voltage and the theoretical voltage exceeds a set threshold is obtained. As the number of accumulated times gradually increases, the step size of the preset scanning current is gradually reduced until the preset range of the critical current is reached. Then, the step width and center point data of the voltage step in the positive direction, negative direction and zero direction are determined. The variable step size strategy includes: scanning with a first-level preset step size; after exceeding a preset threshold for the first time, reducing the step size to a second-level preset step size; after exceeding the preset threshold again, reducing the step size to a third-level preset step size; and when exceeding the preset threshold for the third time, terminating the current level approximation and outputting the current values ​​of the last two scans.

6. The method according to claim 1, characterized in that, Determining the critical current for maintaining superconductivity in the junction section of the Josephson array includes: Obtain the current bias state information of the Josephson array, which is used to apply a preset scanning current; When the bias state information indicates a superconducting state, the critical current for maintaining the superconducting state in the array segment of the Josephson array is determined.

7. A voltage step scanning device for a Josephson array, characterized in that, The device includes: The critical current determination module is used to determine the critical current of the Josephson array segment in maintaining superconductivity. The voltage step scanning module is used to obtain the voltage steps of the array segment of the Josephson array in the positive and negative directions according to the critical current and at a preset microwave frequency and power. The voltage step scanning module is also used to determine the step width and center point data of the voltage steps in the positive, negative and zero directions by adopting a variable step size strategy based on the voltage steps in the positive and negative directions. The voltage step scanning module is also used to determine the voltage step boundaries in the positive and negative directions respectively by using the successive comparison method based on the step width and center point data of the voltage steps in the positive, negative and zero directions. The voltage step scanning module is also used to correct the center point data and step width of the voltage step within the interval defined by the voltage step boundary by employing a local outlier anomaly detection algorithm.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 6.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 6.

10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 6.

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