De-embedding structure and de-embedding method for 1-100GHz radio frequency chip on-chip test

Abstract

The invention belongs to the technical field of radio frequency microwaves, provides a de-embedding structure and a de-embedding method for on-chip testing of a 1-100GHz radio frequency chip, and is used for solving the problems of low precision and narrow frequency band of a de-embedding method in the prior art. The de-embedding structure comprises a to-be-tested piece test structure and a first microstrip line test structure, a second microstrip line test structure and a third microstrip line test structure which are arranged on the same substrate of the to-be-tested piece test structure, firstly, ABCD parameters of a test fixture are obtained based on ABCD parameters of the first microstrip line test structure; secondly, optimizing and correcting ABCD parameters of the test fixture based on the second microstrip line test structure and the third microstrip line test structure; and finally, solving an intrinsic ABCD parameter of the to-be-tested piece based on the ABCD parameter of the test structure of the to-be-tested piece and the ABCD parameter of the test fixture, and converting the intrinsic ABCD parameter into an intrinsic S parameter of the to-be-tested piece to complete de-embedding. According to the invention, the broadband of 1GHz-100GHz is covered, the method has the advantages of high precision and strong robustness, and the accuracy and reliability of on-chip testing can be improved.

Description

Technical Field

[0001] This invention belongs to the field of radio frequency and microwave technology, and specifically provides a de-embedding structure and de-embedding method for on-chip testing of 1-100GHz radio frequency chips. Background Technology

[0002] With the rapid development of millimeter-wave integrated circuits in high-frequency applications such as 5G communication, radar systems, and satellite communication, chip testing accuracy and parameter extraction accuracy have become key factors restricting performance verification and model building. During on-chip testing, the intrinsic parameters of the device under test (DUT) cannot be directly obtained due to the presence of test probes, pads, and electrical connections. De-embedding techniques are needed to effectively remove parasitic effects from the measurement results. In recent years, to meet the compactness and high-frequency requirements of on-chip testing of millimeter-wave chips, L-2L de-embedding and through-de-embedding techniques have been widely researched and applied. These two methods, with their high structural integration, small area footprint, and suitability for on-chip testing environments, have certain practical value in engineering.

[0003] L-2L de-embedding technology constructs two transmission line structures with lengths L and 2L respectively. Using the difference between their measurements, it calculates the impact of parasitic structures such as transmission lines and pads, and then corrects the target device. This method is relatively simple to design and implement, and can operate effectively within a specific frequency range. However, the L-2L de-embedding method inherently relies on a stable ratio between transmission line length and wavelength, resulting in a periodic frequency response, making it difficult to maintain consistent de-embedding accuracy across a wide frequency range. Furthermore, this method does not consider the distributed parameter characteristics of pads and interconnect structures in the millimeter-wave band, causing the de-embedding error to increase significantly with increasing frequency, making it difficult to meet current wideband high-precision testing requirements.

[0004] The pass-through de-embedding technique uses a symmetrical "pad-interconnect-pad" structure with the transmission line as a reference. Based on ABCD matrix theory, it performs mathematical modeling to remove non-target structural effects from the overall measurement. This method is highly integrated structurally, making it particularly suitable for area-constrained on-chip testing environments, and it possesses strong algorithmic scalability. However, in practical applications, the pass-through structure is highly dependent on symmetricalness. If the structure is not perfectly symmetrical or has geometric / process deviations, the ABCD matrix cannot achieve ideal cancellation, leading to systematic biases in the de-embedding results. Furthermore, traditional pass-through methods typically use lumped parameter models to approximate high-frequency transmission structures, neglecting distributed capacitance, inductance, reflection, and coupling effects. Especially at W-band and higher frequencies, parasitic errors cannot be effectively suppressed.

[0005] Furthermore, existing L-2L de-embedding and direct-through de-embedding technologies are typically designed for relatively narrow-band applications, and their applicability in ultra-wideband testing such as 1GHz–100GHz is limited. This manifests as a significant increase in de-embedding error at high frequencies, drastic fluctuations in frequency domain response, and unstable result reconstruction. In the current engineering application context of high-precision modeling of chip intrinsic parameters and wide-frequency range characterization, these shortcomings make it difficult for existing technologies to meet practical needs. Summary of the Invention

[0006] The purpose of this invention is to provide a de-embedding structure and method for on-chip testing of 1-100GHz radio frequency chips, in order to solve the problems of low accuracy and narrow bandwidth in existing de-embedding methods.

[0007] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0008] A de-embedding structure for on-chip testing of 1-100GHz radio frequency chips, characterized in that it includes: a test structure 1 for the device under test and a first microstrip line test structure 2, a second microstrip line test structure 3 and a third microstrip line test structure 4 on the same substrate;

[0009] The test structure 1 for the device under test includes: the device under test 1-1 and a first test fixture and a second test fixture symmetrically connected at both ends; the first test fixture and the second test fixture adopt the same structure, including: microstrip connection line 1-2 and GSG pad structure;

[0010] The first microstrip line test structure 2 includes: a first microstrip line 2-1 and a GSG pad structure symmetrically connected at both ends, wherein the length of the first microstrip line 2-1 is the total length of the microstrip connecting lines 1-2 at both ends of the test device 1-1, marked as L; the width of the first microstrip line 2-1 is the same as that of the microstrip connecting lines 1-2.

[0011] The second microstrip line test structure 3 includes: a second microstrip line 3-1 and a GSG pad structure symmetrically connected at both ends, wherein the length of the second microstrip line 3-1 is 3L / 2 and the width is the same as that of the first microstrip line 2-1;

[0012] The third microstrip line test structure 4 includes: a third microstrip line 4-1 and a GSG pad structure symmetrically connected at both ends, wherein the length of the third microstrip line 4-1 is L / 2 and the width is the same as that of the first microstrip line 2-1.

[0013] Furthermore, the GSG pad structure consists of a first pad 1-3, a second pad 1-4, and a third pad 1-5 arranged in sequence. The first and third pads serve as grounding pads and are grounded through vias, while the second pad serves as a signal pad and is connected to the next-top metal layer through a via.

[0014] Furthermore, in the first microstrip line test structure, the second microstrip line test structure, and the third microstrip line test structure, the GSG pad structure is the same as that in the first test fixture and the second test fixture.

[0015] Furthermore, the first, second, and third microstrip lines are all linear microstrip lines.

[0016] Furthermore, the lengths of the microstrip lines in the test structure for the device under test and the first, second, and third microstrip line test structures must meet the following requirements:

[0017] Using the first microstrip line in the first microstrip line test structure as a reference, the S-parameters of the GSG pad structure on one side of the first microstrip line test structure are transformed into an ABCD parameter matrix. A The pad on this side is used to construct a test fixture with half the length of the microstrip line. The S-parameters of the test fixture are then transformed into an ABCD parameter matrix. L1 The parameter matrix ABCD is calculated. AL1 ABCD AL1 =ABCD A ×ABCD L1 Then the parameter matrix ABCD AL1 The absolute value of the difference between the elements in the first row and first column and the elements in the second row and second column is less than 0.001.

[0018] The de-intercalation method for the de-intercalation structure of the above-mentioned 1-100GHz RF chip on-chip testing is characterized by comprising the following steps:

[0019] Step S1: Obtain the ABCD parameter matrix of the first microstrip line test structure. ALLB Solving for the ABCD parameter matrix of the first test fixture yields the ABCD parameter matrix. AL The ABCD parameter matrix of the second test fixture LB :

[0020]

[0021] Where a, b, c, and d are the matrix coefficients in the ABCD parameter matrix of the test fixture, representing the A11, A12, A21, and A22 parameters of the test fixture, respectively;

[0022] Step S2: Obtain the ABCD parameter matrix of the second microstrip line test structure. ALLLB Combining the ABCD parameter matrix of the first test fixture and the second test fixture AL ABCD LB The parameter matrix ABCD is calculated.L :

[0023] ABCD L =ABCD AL -1 ×ABCD ALLLB ×ABCD LB -1

[0024] Step S3: Obtain the ABCD parameter matrix of the third microstrip line test structure. ALB ;

[0025] Step S4: Calculate the ABCD parameter matrix of the first test fixture. AL The ABCD parameter matrix of the second test fixture LB The matrix coefficients a, b, c, and d in the matrix are iterated and optimized. Based on the optimization results, the corrected ABCD parameter matrix of the first test fixture is constructed. ALO The calibrated ABCD parameter matrix with the second test fixture. LBO ;

[0026] Step S5: Obtain the S-parameters S of the test structure of the test piece. MEAS And use matrix transformation to change the S-parameters S MEAS Convert to ABCD parameter matrix ABCD MEAS ;

[0027] Step S6: Based on the ABCD parameter matrix of the test structure of the device under test (DUT) MEAS The calibrated ABCD parameter matrix of the first test fixture. ALO The calibrated ABCD parameter matrix with the second test fixture. LBO The intrinsic ABCD parameter matrix of the test part is obtained by solving the problem. DUT ;

[0028] Step S7: Based on the intrinsic ABCD parameter matrix of the test piece ABCD DUT The intrinsic S-parameters S of the test piece are obtained by solving the equation. DUT .

[0029] Furthermore, in step S1, the solution process is as follows:

[0030]

[0031] DETA = e 2 -f×g

[0032]

[0033] Where e, f, g, and h are the matrix coefficients in the ABCD parameter matrix of the first microstrip line test structure, representing the A11, A12, A21, and A22 parameters of the first microstrip line test structure, respectively.

[0034] Furthermore, the specific process of step S4 is as follows:

[0035] For any frequency point freq in the frequency range of 1GHz-100GHz, the real part of the matrix coefficient a at that frequency point is labeled as reala, and the imaginary part is labeled as imaga;

[0036] For the real part `reala`, set the lower bound of the traversal interval to `reala-freq`. 3 ×10 -27 The upper limit of the traversal interval is real, and the gradient of the traversal interval is 10. -5 For the imaginary part *imaga*, set the lower bound of the traversal interval to *imaga-0.0002*, the upper bound of the traversal interval to *imaga+0.0002*, and the traversal gradient to 10. -5 ;

[0037] During the traversal, the traversal result of matrix coefficient 'a' is marked as 'a', and the traversal result of matrix coefficient 'b' is calculated as 'b'. The result of traversing the matrix coefficients c is c′: The traversal result of the matrix coefficients d is d′:

[0038] The obtained matrix coefficients are combined to form the corrected ABCD parameter matrix for the first and second test fixtures. ALO With ABCD LBO :

[0039]

[0040] Combining the ABCD parameter matrix ABCD ALO ABCD LBO With ABCD L The parameter matrix ABCD is calculated. ALBO :

[0041] ABCD ALBO =ABCD ALO ×ABCD L -1 ×ABCD LBO

[0042] Set optimization conditions: ABCD parameter matrix ABCD ALB With ABCD ALBOIf the norm difference is less than 0.001, the traversal result that satisfies the optimization condition and has the smallest norm difference is selected as the optimal value, thus obtaining the corrected ABCD parameter matrix ABCD of the first test fixture. ALO The calibrated ABCD parameter matrix with the second test fixture. LBO .

[0043] Based on the above technical solution, the beneficial effects of the present invention are as follows:

[0044] This invention proposes a de-intercalation structure and method for on-chip testing of radio frequency (RF) chips. The de-intercalation structure includes: a test structure 1 for a device under test (DUT) and a first microstrip line test structure, a second microstrip line test structure, and a third microstrip line test structure on the same substrate. First, the ABCD parameters of the test fixture are obtained based on the ABCD parameters of the first microstrip line test structure. Then, the ABCD parameters of the test fixture are optimized and corrected based on the second and third microstrip line test structures. Finally, the intrinsic ABCD parameters of the DUT are solved based on the ABCD parameters of the DUT test structure and the ABCD parameters of the test fixture, and converted into the intrinsic S-parameters of the DUT to complete the de-intercalation.

[0045] In summary, this invention is applicable to the millimeter-wave frequency band, covering a wide frequency range of 1GHz–100GHz, and has the advantages of high precision and strong robustness. It can improve the accuracy and reliability of on-chip testing, and further support the performance verification, model extraction and long-term stable operation design of high-frequency integrated circuits. Attached Figure Description

[0046] Figure 1 This is a schematic diagram of the de-embedding principle for on-chip testing of radio frequency chips in this invention.

[0047] Figure 2 This is a schematic diagram of the test structure of the device under test in this invention, wherein 1 is the test structure of the device under test, 1-1 is the device under test, 1-2 is the microstrip connection line, 1-3 is the first pad, 1-4 is the second pad, and 1-5 is the third pad.

[0048] Figure 3 This is a schematic diagram of the first microstrip line test structure in this invention, wherein 2 is the first microstrip line test structure and 2-1 is the first microstrip line.

[0049] Figure 4 This is a schematic diagram of the second microstrip line test structure in this invention, wherein 3 is the second microstrip line test structure and 3-1 is the second microstrip line.

[0050] Figure 5 This is a schematic diagram of the third microstrip line test structure in this invention, wherein 4 is the third microstrip line test structure and 4-1 is the third microstrip line.

[0051] Figure 6 This is a schematic diagram of the equivalent network of the test structure of the device under test in this invention.

[0052] Figure 7 This is a flowchart illustrating the de-embedding method for on-chip testing of radio frequency chips in this invention.

[0053] Figure 8 This is a graph showing the amplitude error between the electromagnetic simulation results and the de-embedding results of the spiral inductor in this embodiment of the invention.

[0054] Figure 9 This is a phase error diagram showing the electromagnetic simulation results and de-embedding results of the spiral inductor in an embodiment of the present invention.

[0055] Figure 10 This is a comparison chart of the amplitude error between the spiral inductor de-embedding result in the embodiment of the present invention and the spiral inductor de-embedding result in the comparative example.

[0056] Figure 11 This is a comparison diagram of the phase error between the de-embedding results of the spiral inductor in the embodiment of the present invention and the de-embedding results of the spiral inductor in the comparative example. Detailed Implementation

[0057] To make the objectives, technical solutions, and beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0058] This embodiment provides a de-intercalation structure and method for on-chip testing of 1GHz-100GHz RF chips. It innovatively improves upon traditional through-pass de-intercalation technology, and its basic principle is as follows: Figure 1 As shown.

[0059] Specifically, the de-intercalation structure of the 1GHz-100GHz RF chip during on-chip testing is as follows: Figures 2-5 As shown, it includes: test structure 1 of the device under test and the first microstrip line test structure 2, the second microstrip line test structure 3 and the third microstrip line test structure 4 on the same substrate;

[0060] like Figure 2 As shown, the test structure 1 for the device under test (DUT) includes: a DUT 1-1 and a first test fixture and a second test fixture symmetrically connected at both ends; the first test fixture and the second test fixture adopt the same structure, including: a microstrip connection line 1-2 and a GSG pad structure; the GSG pad structure is composed of a first pad 1-3, a second pad 1-4 and a third pad 1-5 arranged sequentially, the first pad 1-3 and the third pad 1-5 serve as ground pads and are grounded through vias respectively, the second pad 1-4 serves as a signal pad and is connected to the second-to-top metal layer through a via; in this embodiment, the DUT 1-1 adopts a spiral inductor, and in actual use, any device under test is applicable to this invention;

[0061] like Figure 3 As shown, the first microstrip line test structure 2 includes: a first microstrip line 2-1 and a GSG pad structure symmetrically connected at both ends. The length of the first microstrip line 2-1 is the total length of the microstrip connecting lines 1-2 at both ends of the device under test 1-1, marked as L. That is, the lengths of the microstrip connecting lines 1-2 in the first test fixture and the second test fixture are L / 2 respectively. The width of the first microstrip line 2-1 is the same as that of the microstrip connecting lines 1-2. The GSG pad structure is the same as that in the first test fixture and the second test fixture, that is, the structure and dimensions are the same.

[0062] like Figure 4 As shown, the second microstrip line test structure 3 includes: a second microstrip line 3-1 and a GSG pad structure symmetrically connected at both ends. The length of the second microstrip line 3-1 is 3L / 2, and the width is the same as that of the first microstrip line 2-1. The GSG pad structure is the same as that in the first test fixture and the second test fixture, that is, the structure and size are the same.

[0063] like Figure 5 As shown, the third microstrip line test structure 4 includes: a third microstrip line 4-1 and a GSG pad structure symmetrically connected at both ends. The length of the third microstrip line 4-1 is L / 2, and the width is the same as that of the first microstrip line 2-1. The GSG pad structure is the same as that in the first test fixture and the second test fixture, that is, the structure and size are the same.

[0064] Furthermore, the first microstrip line 2-1, the second microstrip line 3-1, and the third microstrip line 4-1 are all straight microstrip lines.

[0065] Furthermore, the lengths of the microstrip lines in the test structure for the device under test and the first, second, and third microstrip line test structures must meet the following requirements:

[0066] Using the first microstrip line in the first microstrip line test structure as a reference, the S-parameters of the GSG pad structure on any side of the first microstrip line test structure are transformed into an ABCD parameter matrix. A The S-parameters of the microstrip line connecting half the length of the pad on that side are transformed into an ABCD parameter matrix. L1 The test fixture on one side, consisting of the aforementioned pads and half the length of the microstrip line, is used to calculate the ABCD parameter matrix of this test fixture. AL1 ABCD AL1 =ABCD A ×ABCD L1 Then the parameter matrix ABCD AL1The absolute value of the difference between the elements in the first row and first column and the elements in the second row and second column is less than 0.001. It should be noted that the length of the microstrip line in the test structure of the device under test and the first microstrip line test structure, the second microstrip line test structure and the third microstrip line test structure can be simulated and calculated by the electromagnetic field simulation software HFSS.

[0067] like Figure 6 As shown, in this invention, the first test fixture, the device under test (DUT), and the second test fixture are each equivalent to a two-port network. Therefore, the DUT test structure is equivalent to three two-port networks, and de-embedding is achieved through matrix operations. Based on the aforementioned de-embedding structure for on-chip testing of 1GHz-100GHz RF chips, this embodiment provides a corresponding de-embedding method, such as... Figure 7 As shown, the specific steps include:

[0068] Step S1: Obtain the ABCD parameter matrix of the first microstrip line test structure. ALLB Solving for the ABCD parameter matrix of the first and second test fixtures yields the ABCD parameter matrix. AL With ABCD LB Specifically, it means:

[0069] Where a, b, c, and d are the matrix coefficients in the ABCD parameter matrix of the test fixture, representing parameters A11, A12, A21, and A22 of the test fixture, respectively; specifically:

[0070]

[0071] DETA = e 2 -f×g

[0072]

[0073] Where e, f, g, and h are the matrix coefficients in the ABCD parameter matrix of the first microstrip line test structure, representing the A11, A12, A21, and A22 parameters of the first microstrip line test structure, respectively.

[0074] Step S2: Obtain the ABCD parameter matrix of the second microstrip line test structure. ALLLB Combining the ABCD parameter matrix of the first test fixture and the second test fixture AL ABCD LB The parameter matrix ABCD is calculated. L :

[0075] ABCD L＝ ABCD AL -1 ×ABCD ALLLB×ABCD LB -1

[0076] Step S3: Obtain the ABCD parameter matrix of the third microstrip line test structure. ALB ;

[0077] Step S4: Calculate the ABCD parameter matrix of the first and second test fixtures using the mathematical simulation software MATLAB. AL With ABCD LB The matrix coefficients a, b, and c are traversed to complete the matrix coefficient correction; the specific process is as follows:

[0078] The ABCD parameter matrix of the first test fixture and the second test fixture. AL With ABCD LB The matrix coefficients a, b, and c are all complex numbers, and the values ​​of a, b, and c are different at each frequency point;

[0079] For any frequency point freq in the frequency range of 1GHz-100GHz, the real part of the matrix coefficient a at that frequency point is labeled as reala, and the imaginary part is labeled as imaga;

[0080] For the real part `reala`, set the lower bound of the traversal interval to `reala-freq`. 3 ×10 -27 The upper limit of the traversal interval is real, and the gradient of the traversal interval is 10. -5 For the imaginary part *imaga*, set the lower bound of the traversal interval to *imaga-0.0002*, the upper bound of the traversal interval to *imaga+0.0002*, and the traversal gradient to 10. -5 After traversing the matrix using the mathematical simulation software MATLAB, the traversal result of matrix coefficient 'a' is marked as 'a', and the traversal result of matrix coefficient 'b' is calculated as 'b'. The result of traversing the matrix coefficients c is c′: The traversal result of the matrix coefficients d is d′:

[0081] The obtained matrix coefficients are combined to form a new ABCD parameter matrix for the first and second test fixtures. ALO With ABCD LBO :

[0082]

[0083] Combined with the ABCD parameter matrix of the two clamps after iterative optimization ALO ABCD LBO With ABCD parameter matrix ABCD LThe new ABCD parameter matrix is ​​calculated. ALBO :

[0084] ABCD ALBO =ABCD ALO ×ABCD L -1 ×ABCD LBO

[0085] To obtain the optimal ABCD parameter matrix for the two clamps. ALO With ABCD LBO It must satisfy the ABCD parameter matrix ABCD ALB With ABCD parameter matrix ABCD ALBO The norm difference is less than 0.001; therefore, in all ABCD cases that satisfy this condition... ALO and ABCD LBO The matrix with the smallest norm is selected as the optimal value to complete the correction. It should be noted that the optimization method for matrix coefficients a, b, and c at any frequency point in the 1-100GHz frequency range is the same as the above process.

[0086] Step S5: Obtain the S-parameters S of the test structure of the test piece. MEAS And use matrix transformation to change the S-parameters S MEAS Convert to ABCD parameter matrix ABCD MEAS The matrix transformation process is existing technology in this field and will not be described in detail here;

[0087] Step S6: Based on the ABCD parameter matrix of the test structure of the device under test (DUT) MEAS The ABCD parameter matrix after calibration of the first and second test fixtures. ALO With ABCD LBO The intrinsic ABCD parameter matrix of the test part is obtained by solving the problem. DUT The solution process is existing technology in this field and will not be described in detail here;

[0088] Step S7: Based on the intrinsic ABCD parameter matrix of the test piece ABCD DUT The intrinsic S-parameters S of the test piece are obtained by solving the equation. DUT The solution process is also a prior art in this field, and will not be described in detail here.

[0089] The beneficial effects of the present invention will be explained in detail below with reference to simulation tests.

[0090] like Figure 8 The figure shows the amplitude error between the electromagnetic simulation results and the de-embedding results of the spiral inductor in this embodiment. Figure 9The figure shows the phase error between the electromagnetic simulation result and the de-embedding result of the spiral inductor in this embodiment, including parameters S11, S21, S12 and S22. As can be seen from the figure, the RF parameters after de-embedding using the de-embedding method proposed in this invention have a very good fit with the amplitude and phase of the intrinsic structure simulation result, thus proving that the de-embedding method proposed in this invention has high de-embedding accuracy.

[0091] Furthermore, using the traditional direct-through de-embedding method as a comparative example, such as... Figure 10 The figure shows the amplitude error between the spiral inductor de-embedding result in this embodiment and the spiral inductor de-embedding result in the comparative example. Figure 11 The figure shows the phase error between the de-embedding result of the spiral inductor in this embodiment and the de-embedding result of the spiral inductor in the comparative example, including parameters S11, S21, S12 and S22. As can be seen from the figure, the error of the de-embedding method of the present invention is much smaller than that of the traditional through-hole de-embedding method.

[0092] The above description is merely a specific embodiment of the present invention. Any feature disclosed in this specification may be replaced by other equivalent or similar features unless otherwise specified. All disclosed features, or steps in all methods or processes, may be combined in any way except for mutually exclusive features and / or steps.

Claims

1. A de-intercalation structure for on-chip testing of 1-100GHz radio frequency chips, characterized in that, include: Test structure (1) of the device under test and its first microstrip line test structure (2), second microstrip line test structure (3) and third microstrip line test structure (4) on the same substrate; The test structure (1) of the device under test includes: the device under test (1-1) and a first test fixture and a second test fixture symmetrically connected at both ends; the first test fixture and the second test fixture adopt the same structure, including: microstrip connection line (1-2) and GSG pad structure; The first microstrip line test structure (2) includes: a first microstrip line (2-1) and a GSG pad structure symmetrically connected at both ends, wherein the length of the first microstrip line (2-1) is the total length of the microstrip connecting lines (1-2) at both ends of the device under test (1-1), marked as L; the width of the first microstrip line is the same as that of the microstrip connecting lines; The second microstrip line test structure (3) includes: a second microstrip line (3-1) and a GSG pad structure symmetrically connected at both ends, wherein the length of the second microstrip line is 3L / 2 and the width is the same as that of the first microstrip line; The third microstrip line test structure (4) includes: a third microstrip line (4-1) and a GSG pad structure symmetrically connected at both ends, wherein the length of the third microstrip line is L / 2 and the width is the same as that of the first microstrip line.

2. The de-intercalation structure for on-chip testing of 1-100GHz RF chips according to claim 1, characterized in that, The GSG pad structure consists of a first pad (1-3), a second pad (1-4), and a third pad (1-5) arranged in sequence. The first and third pads serve as grounding pads and are grounded through vias, while the second pad serves as a signal pad and is connected to the next-top metal layer through a via.

3. The de-intercalation structure for on-chip testing of 1-100GHz RF chips according to claim 1, characterized in that, In the first microstrip line test structure, the second microstrip line test structure, and the third microstrip line test structure, the GSG pad structure is the same as that in the first test fixture and the second test fixture.

4. The de-intercalation structure for on-chip testing of 1-100GHz RF chips according to claim 1, characterized in that, The first, second, and third microstrip lines are all linear microstrip lines.

5. The de-intercalation structure for on-chip testing of 1-100GHz RF chips according to claim 1, characterized in that, The length of the microstrip line in the test structure of the device under test and the first, second, and third microstrip line test structures must meet the following requirements: Using the first microstrip line in the first microstrip line test structure as a reference, the S-parameters of the GSG pad structure on one side of the first microstrip line test structure are transformed into an ABCD parameter matrix. A The pad on this side is used to construct a test fixture with half the length of the microstrip line. The S-parameters of the test fixture are then transformed into an ABCD parameter matrix. L1 The parameter matrix ABCD is calculated. AL1 ABCD AL1 =ABCD A ×ABCD L1 Then the parameter matrix ABCD AL1 The absolute value of the difference between the elements in the first row and first column and the elements in the second row and second column is less than 0.

001.

6. A de-embedding method for on-chip testing of 1-100GHz radio frequency chips, characterized in that, This method is implemented based on the de-intercalation structure for on-chip testing of the 1-100GHz RF chip as described in claim 1, and specifically includes the following steps: Step S1: Obtain the ABCD parameter matrix of the first microstrip line test structure. ALLB Solving for the ABCD parameter matrix of the first test fixture yields the ABCD parameter matrix. AL The ABCD parameter matrix of the second test fixture LB : Where a, b, c, and d are the matrix coefficients in the ABCD parameter matrix of the test fixture, representing the A11, A12, A21, and A22 parameters of the test fixture, respectively; Step S2: Obtain the ABCD parameter matrix of the second microstrip line test structure. ALLLB Combining the ABCD parameter matrix of the first test fixture and the second test fixture AL ABCD LB The parameter matrix ABCD is calculated. L : ABCD L＝ ABCD AL -1 ×ABCD ALLLB ×ABCD LB -1 Step S3: Obtain the ABCD parameter matrix of the third microstrip line test structure. ALB ; Step S4: Calculate the ABCD parameter matrix of the first test fixture. AL The ABCD parameter matrix of the second test fixture LB The matrix coefficients a, b, c, and d in the matrix are iterated and optimized. Based on the optimization results, the corrected ABCD parameter matrix of the first test fixture is constructed. ALO The calibrated ABCD parameter matrix with the second test fixture. LBO ; Step S5: Obtain the S-parameters S of the test structure of the test piece. MEAS And use matrix transformation to change the S-parameters S MEAS Convert to ABCD parameter matrix ABCD MEAS ; Step S6: Based on the ABCD parameter matrix of the test structure of the device under test (DUT) MEAS The calibrated ABCD parameter matrix of the first test fixture. ALO The calibrated ABCD parameter matrix with the second test fixture. LBO The intrinsic ABCD parameter matrix of the test part is obtained by solving the problem. DUT ; Step S7: Based on the intrinsic ABCD parameter matrix of the test piece ABCD DUT The intrinsic S-parameters S of the test piece are obtained by solving the equation. DUT .

7. The de-embedding method for on-chip testing of 1-100GHz RF chips according to claim 6, characterized in that, In step S1, the solution process is as follows: DETA=e 2 -f×g Where e, f, g, and h are the matrix coefficients in the ABCD parameter matrix of the first microstrip line test structure, representing the A11, A12, A21, and A22 parameters of the first microstrip line test structure, respectively.

8. The de-embedding method for on-chip testing of 1-100GHz RF chips according to claim 6, characterized in that, The specific process of step S4 is as follows: For any frequency point freq in the frequency range of 1GHz-100GHz, the real part of the matrix coefficient a at that frequency point is labeled as reala, and the imaginary part is labeled as imaga; For the real part `reala`, set the lower bound of the traversal interval to `reala-freq`. 3 ×10 -27 The upper limit of the traversal interval is real, and the gradient of the traversal interval is 10. -5 ; For the imaginary part *imaga*, we set the lower bound of the traversal interval to *imaga-0.0002*, the upper bound of the traversal interval to *imaga+0.0002*, and the traversal gradient to 10. -5 ; During the traversal, the traversal result of matrix coefficient 'a' is marked as 'a', and the traversal result of matrix coefficient 'b' is calculated as 'b'. The result of traversing the matrix coefficients c is c′: The traversal result of the matrix coefficients d is d′: The obtained matrix coefficients are combined to form the corrected ABCD parameter matrix for the first and second test fixtures. ALO With ABCD LBO : Combining the ABCD parameter matrix ABCD ALO ABCD LBO With ABCD L The parameter matrix ABCD is calculated. ALBO : ABCD ALBO =ABCD ALO ×ABCD L -1 ×ABCD LBO Set optimization conditions: ABCD parameter matrix ABCD ALB With ABCD ALBO If the norm difference is less than 0.001, the traversal result that satisfies the optimization condition and has the smallest norm difference is selected as the optimal value, thus obtaining the corrected ABCD parameter matrix ABCD of the first test fixture. ALO The calibrated ABCD parameter matrix with the second test fixture. LBO .

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