Chip test method and device, test machine and storage medium

Abstract

The invention provides a chip testing method and device, a testing machine and a storage medium, and is suitable for the technical field of chip testing. The method comprises the steps of determining test information for a to-be-tested device and a test result range corresponding to the test information based on an acquired test program; based on the test information, controlling the first test module to output a first electric signal to a first pin of the to-be-tested chip, controlling the second test module to output a second electric signal to a second pin of the to-be-tested chip, and obtaining a test result signal; wherein in the first electric signal and the second electric signal, one electric signal is a negative value, and the other electric signal is a positive value; and determining a test result of the to-be-tested chip based on the test result signal and the test result range. According to the embodiment of the invention, the test time of the chip can be shortened, and the test efficiency is improved.

Description

Technical Field

[0001] This application relates to the field of chip testing technology, and in particular to a chip testing method, apparatus, testing machine and storage medium. Background Technology

[0002] With the rapid development of the semiconductor industry, chips are widely used in various industries. To meet the market demand for chips, the use of probe stations or sorters capable of multi-station testing in conjunction with test machines with sufficient resource channels has become the mainstream testing method to improve chip testing efficiency.

[0003] Currently, in the process of multi-station testing using a probe station, the high voltage board channel in the test machine is generally used to provide high voltage to the chip. Some test machines usually need to insert other board modules to achieve functional testing, but the board slots are limited and a single high voltage board has only one resource channel.

[0004] Especially when performing high-voltage related tests on the device under test (DUT) of a chip, it is only possible to complete the first station before testing the next station. For example, when testing the clamping diode of a chip, each chip needs to be tested in sequence, which results in a long testing time and low testing efficiency. Summary of the Invention

[0005] In view of this, embodiments of this application provide a chip testing method, apparatus, testing machine, and storage medium to solve the problems of long testing time and low testing efficiency of chips in the prior art.

[0006] The first aspect of this application provides a chip testing method applied to a testing machine. The testing machine includes a first testing module and a second testing module, both of which are electrically connected to a chip under test (DUT). The DUT includes a device under test (DUT), with its two ends electrically connected to a first pin and a second pin of the DUT, respectively. A third pin of the DUT is grounded. The method includes:

[0007] Based on the acquired test program, determine the test information for the device under test and the range of test results corresponding to the test information;

[0008] Based on the test information, the first test module is controlled to output a first electrical signal to the first pin of the chip under test, and the second test module is controlled to output a second electrical signal to the second pin of the chip under test, so as to obtain the test result signal; wherein, of the first electrical signal and the second electrical signal, one electrical signal is negative and the other electrical signal is positive.

[0009] Based on the test result signal and the test result range, the test result of the chip under test is determined.

[0010] In one possible implementation, the first electrical signal is a first preset negative voltage, and the second electrical signal is a preset positive current;

[0011] Controlling the first test module to output a first electrical signal to the first pin of the chip under test, and controlling the second test module to output a second electrical signal to the second pin of the chip under test, including:

[0012] The first test module is controlled to output a first preset negative voltage to the first pin of the chip under test, and the second test module is controlled to output a preset positive current to the second pin of the chip under test, so as to superimpose the channel resources of the first test module and the second test module.

[0013] In one possible implementation, the test result signal includes a test voltage, which is the voltage of the second pin to ground, and the test result range includes a preset voltage difference range.

[0014] Based on the test result signal and the test result range, the test results of the chip under test are determined, including:

[0015] The voltage difference between the second pin and the first pin is obtained by summing the absolute values ​​of the test voltage and the first preset negative voltage.

[0016] The test results of the chip under test are determined based on the voltage difference and the preset voltage difference range.

[0017] In one possible implementation, the first electrical signal is a second preset negative voltage, and the second electrical signal is a preset positive voltage;

[0018] Controlling the first test module to output a first electrical signal to the first pin of the chip under test, and controlling the second test module to output a second electrical signal to the second pin of the chip under test, including:

[0019] The first test module is controlled to output a second preset negative voltage to the first pin of the chip under test, and the second test module is controlled to output a preset positive voltage to the second pin of the chip under test, so as to form a preset voltage difference between the second pin and the first pin.

[0020] In one possible implementation, the test result signal includes a test current, which is the current from the second pin to ground, and the test result range includes a preset current range.

[0021] Based on the test result signal and the test result range, the test results of the chip under test are determined, including:

[0022] The test results of the chip under test are determined based on the test current and the preset current range.

[0023] In one possible implementation, the device under test includes a clamping diode.

[0024] In one possible implementation, the test machine also includes a switch control module, at least two chips under test are mounted on the test board, and the test board also includes a switch module;

[0025] Based on the test information, the first test module is controlled to output a first electrical signal to the first pin of the chip under test, and the second test module is controlled to output a second electrical signal to the second pin of the chip under test, including:

[0026] Based on the test information, the control switch module sends control information to the switch module, so that the switch module controls the first channel of the first test module to be electrically connected to the first pin of the chip under test, and the first channel of the second test module to be electrically connected to the second pin of the chip under test.

[0027] The first channel of the first test module is controlled to output a first electrical signal to the first pin of the chip under test, and the first channel of the second test module is controlled to output a second electrical signal to the second pin of the chip under test.

[0028] A second aspect of this application provides a chip testing apparatus applied to a testing machine. The testing machine includes a first testing module and a second testing module, both of which are electrically connected to a chip under test (DUT). The DUT includes a device under test (DUT), with its two ends electrically connected to a first pin and a second pin of the DUT, respectively. The third pin of the DUT is grounded. The apparatus includes:

[0029] The determination module is used to determine the test information for the device under test and the range of test results corresponding to the test information based on the acquired test program.

[0030] The control module is used to control the first test module to output a first electrical signal to the first pin of the chip under test, and to control the second test module to output a second electrical signal to the second pin of the chip under test, based on test information, so as to obtain a test result signal; wherein, of the first electrical signal and the second electrical signal, one electrical signal is negative and the other electrical signal is positive.

[0031] The processing module is used to determine the test results of the chip under test based on the test result signal and the test result range.

[0032] A third aspect of this application provides a test machine, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the steps of the method of the first aspect of this application.

[0033] A fourth aspect of this application provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the method as described in the first aspect of this application.

[0034] The beneficial effects of the embodiments in this application compared with the prior art are:

[0035] The chip testing method of the first aspect of this application can determine the test information for the device under test (DUT) and the corresponding test result range based on the acquired test program. Based on the test information, it can control a first test module to output a first electrical signal to a first pin of the DUT and control a second test module to output a second electrical signal to a second pin of the DUT, acquiring a test result signal. Then, based on the test result signal and the test result range, it can determine the test result of the DUT. Since the third pin of the DUT is grounded, one of the first and second electrical signals is negative and the other is positive. Therefore, the channel resources of the first and second test modules can be superimposed, providing a high voltage to the DUT for testing. Simultaneously, since both the first and second test modules can include at least two channels, the other channel resources of the first and second test modules can be used to test other DUTs. This avoids the problem of having to use only one high-voltage test module to test individual chips sequentially when the DUT requires a high voltage, reducing waiting time and thus shortening the chip testing time and improving testing efficiency.

[0036] It is understood that the beneficial effects of the second to fourth aspects mentioned above can be found in the relevant descriptions in the first aspect mentioned above, and will not be repeated here. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 This is a schematic diagram of the framework of a chip testing system provided in an embodiment of this application;

[0039] Figure 2 This is a flowchart of a chip testing method provided in an embodiment of this application;

[0040] Figure 3 This is a schematic diagram of the framework of another chip testing system provided in an embodiment of this application;

[0041] Figure 4 This is a schematic diagram of the structure of a chip testing device provided in an embodiment of this application;

[0042] Figure 5 This is a schematic diagram of the structure of a testing machine provided in an embodiment of this application. Detailed Implementation

[0043] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0044] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0045] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0046] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if detected [the described condition or event]" may be interpreted, depending on the context, as meaning "once determined," "in response to determination," "once detected [the described condition or event]," or "in response to detection [the described condition or event]."

[0047] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0048] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0049] The technical solution of this application and how it solves the above-mentioned technical problems are described in detail below with specific embodiments. It should be noted that the following embodiments can be referenced, borrowed, or combined with each other, and the same terms, similar features, and similar implementation steps in different embodiments will not be described again.

[0050] See Figure 1 As shown, this application provides a schematic diagram of the framework of a chip testing system. Figure 1 As shown, the chip testing system includes a tester 10 and a test board 20. The test board 20 can hold multiple chips for testing and includes at least one chip under test 210. The figure illustrates a test board 20 including at least two chips under test 210 as an example. The tester 10 includes a first test module 110 and a second test module 120.

[0051] Optionally, the chip testing system may also include a testing machine software system that is communicatively connected to the testing machine 10. The testing machine 10 can send the test results to the testing machine software system for display, and the testing machine software system can send the test program to the testing machine 10.

[0052] In some embodiments, the chip testing system may include a terminal device with a display screen, which may be a laptop, an ultra-mobile personal computer (UMPC), a netbook, a personal digital assistant (PDA), a host computer, or other similar devices.

[0053] Optionally, the chip testing system may also include a probe station, on which the test board 20 is mounted.

[0054] See Figure 2 As shown, this application provides a flowchart of a chip testing method. The chip testing method of this application is applied to a testing machine 10, which includes a first testing module 110 and a second testing module 120. Both the first testing module 110 and the second testing module 120 are electrically connected to a chip under test (DUT) 210. The DUT 210 includes a device under test (DUT), and its two ends are electrically connected to the first pin and the second pin of the DUT 210, respectively. The third pin of the DUT 210 is grounded. Figure 2 As shown, the chip testing method of this application embodiment includes steps S201 to S203.

[0055] S201. Based on the acquired test program, determine the test information for the device under test and the range of test results corresponding to the test information.

[0056] In some embodiments, the device under test includes a clamping diode.

[0057] Optionally, the testing of clamping diodes is related to high voltage.

[0058] Alternatively, in actual multi-station testing, the test machine 10 can be an STS8200 test machine.

[0059] The STS8200 tester is a tester suitable for testing chips with large-module, small-scale characteristics. It mainly consists of modules such as FOVI100, FPVI10, FPVI10_PLUS, DIO, QTMU, and CBIT128. The FPVI10 and FPVI10_PLUS modules differ in accuracy and measurement range; the appropriate module can be selected based on the product's testing requirements and characteristics.

[0060] Optionally, the first test module 110 and the second test module 120 in this application embodiment can be selected from the FPVI10 module and FPVI10_PLUS module of the STS8200 test machine, respectively. The FPVI10 module is also the FPVI10 board, and the FPVI10_PLUS module is also the FPVI10_PLUS board.

[0061] S202. Based on the test information, control the first test module 110 to output a first electrical signal to the first pin of the chip under test 210, and control the second test module 120 to output a second electrical signal to the second pin of the chip under test 210, and obtain the test result signal; wherein, of the first electrical signal and the second electrical signal, one electrical signal is negative and the other electrical signal is positive.

[0062] Alternatively, the electrical signal may include either voltage or current.

[0063] Specifically, the first test module 110 may have at least two channels, and the second test module 120 may also have at least two channels. Based on the test information, one channel of the first test module 110 and one channel of the second test module 120 can be controlled to output the required electrical signals to the first pin and the second pin, respectively.

[0064] S203. Based on the test result signal and the test result range, determine the test result of the chip under test.

[0065] Specifically, the test results of the chip under test are the test results of the device under test for the chip under test 210.

[0066] Optionally, the test result of the chip under test is determined based on the test result signal and the test result range, including: if the test result signal is within the test result range, the test result of the chip under test is determined to be qualified; if the test result signal is not within the test result range, the test result of the chip under test is determined to be unqualified.

[0067] Optionally, after determining the test result of the chip under test, the method further includes: sending the test result to the test machine software system so that the test machine software system can display the test result.

[0068] Specifically, testers can determine whether the chip under test is qualified by using the test results displayed by the test machine software system.

[0069] The chip testing method of this application embodiment can determine the test information for the device under test and the test result range corresponding to the test information based on the acquired test program. Thus, based on the test information, the first test module 110 can be controlled to output a first electrical signal to the first pin of the chip under test 210, and the second test module 120 can be controlled to output a second electrical signal to the second pin of the chip under test 210, thereby acquiring the test result signal. Then, based on the test result signal and the test result range, the test result of the chip under test can be determined.

[0070] Since the third pin of the chip under test 210 is grounded, one of the first electrical signals and the other of the second electrical signal is negative and positive, the channel resources of the first test module 110 and the second test module 120 can be superimposed between the second pin and the first pin, which can provide a large voltage to the device under test for testing.

[0071] Meanwhile, since both the first test module 110 and the second test module 120 can include at least two channels, the other channel resources of the first test module 110 can be used to test other chips under test 210, and the other channel resources of the second test module 120 can also be used to test other chips under test 210. This avoids the problem that when the chip under test 210 requires a large voltage, only one test module that provides a large voltage can be used to test a single chip sequentially, reducing the waiting time and thus shortening the overall test time of the chip and improving the test efficiency.

[0072] As an example, a single FOVI100 module has 8 channels, and an FPVI10_PLUS module has 2 channels. The FOVI100 module's resource channels are FOVI channels, and the FPVI10_PLUS module's resource channels are FPVI channels. Each channel of the FOVI100 and FPVI10_PLUS modules floats independently. The board channel resources are led out from the STS8200 tester's DUT board via wires and connected to the horn-shaped connector on test board 20. The maximum voltage of the FOVI channel can reach 40V, and the maximum voltage of the FPVI channel can reach 100V.

[0073] In practical applications, due to the characteristics of the FOVI100 module and the FPVI10_PLUS module, the FOVI channel and FPVI channel resources can only provide or test voltages below 140V when they are superimposed.

[0074] In some embodiments, the first electrical signal is a first preset negative voltage, and the second electrical signal is a preset positive current;

[0075] Controlling the first test module 110 to output a first electrical signal to the first pin of the chip under test 210, and controlling the second test module 120 to output a second electrical signal to the second pin of the chip under test 210, includes:

[0076] The first test module 110 is controlled to output a first preset negative voltage to the first pin of the chip under test 210, and the second test module 120 is controlled to output a preset positive current to the second pin of the chip under test 210, so as to superimpose the channel resources of the first test module 110 and the second test module 120.

[0077] As an example, the first test module 110 is an FPVI10 module, and the second test module 120 is an FPVI10_PLUS module. The FPVI channel of the FPVI10 module outputs a first preset negative voltage to the first pin, and the FPVI channel of the FPVI10_PLUS module outputs a preset positive current to the second pin.

[0078] Among them, the first pin of the chip under test 210 is the CN pin, the second pin of the chip under test 210 is the COM pin, the third pin of the chip under test 210 is the EN pin, and the fourth pin of the chip under test 210 is the BN pin. The BN pin is mainly used for other functions of the chip under test 210.

[0079] In some embodiments, the test result signal includes a test voltage, which is the voltage of the second pin to ground, and the test result range includes a preset voltage difference range.

[0080] Based on the test result signal and the test result range, the test results of the chip under test are determined, including:

[0081] The voltage difference between the second pin and the first pin is obtained by summing the absolute values ​​of the test voltage and the first preset negative voltage.

[0082] The test results of the chip under test are determined based on the voltage difference and the preset voltage difference range.

[0083] As an example, taking a clamping diode as the device under test, the breakdown voltage test of the clamping diode is performed. The first preset negative voltage is -90V, and the preset positive current is 10uA. The breakdown voltage of the clamping diode is the voltage difference between the CN pin and the COM pin, which is approximately in the range of 90V-110V. When testing this voltage, the FOVI channel and FPVI channel resources need to be used together. In the test program, the FPVI channel connected to the CN pin is supplied with -90V. At this time, the voltage difference between ground and CN pin is 90V, and the ground potential is higher than the CN pin potential. The FOVI channel connected to the COM pin is supplied with 10uA current, and the voltage between the COM pin and ground is tested simultaneously to obtain the test voltage. At this time, the current supplied by the FOVI channel flows from the COM pin to ground, and the COM pin potential is higher than the ground potential. Taking 0V ground as the voltage reference point, the COM pin potential is higher than the CN pin potential, and the voltage difference between the COM pin and CN pin is the sum of the voltage between the COM pin and ground and the voltage between ground and CN pin.

[0084] In some embodiments, the first electrical signal is a second preset negative voltage, and the second electrical signal is a preset positive voltage;

[0085] Controlling the first test module 110 to output a first electrical signal to the first pin of the chip under test 210, and controlling the second test module 120 to output a second electrical signal to the second pin of the chip under test 210, includes:

[0086] The first test module 110 is controlled to output a second preset negative voltage to the first pin of the chip under test 210, and the second test module 120 is controlled to output a preset positive voltage to the second pin of the chip under test 210, so as to form a preset voltage difference between the second pin and the first pin.

[0087] As an example, the first test module 110 is an FPVI10 module, and the second test module 120 is an FPVI10_PLUS module. The FPVI channel of the FPVI10 module outputs a second preset negative voltage to the first pin, and the FPVI channel of the FPVI10_PLUS module outputs a preset positive voltage to the second pin.

[0088] Optionally, the second preset negative voltage can be the same as or different from the first preset positive voltage.

[0089] In some embodiments, the test result signal includes a test current, which is the current from the second pin to ground, and the test result range includes a preset current range.

[0090] Based on the test result signal and the test result range, the test results of the chip under test are determined, including:

[0091] The test results of the chip under test are determined based on the test current and the preset current range.

[0092] For example, if the device under test (DUT) is a clamping diode, when the voltage difference between the COM and CN pins is 115V, the current flowing from the COM pin to the CN pin is measured. This current is the reverse current of the clamping diode, and a large voltage is provided by superimposing the FOVI and FPVI channel resources. By measuring the current flowing from the COM pin to the CN pin, the test current is obtained. Then, based on the test current and a preset current range, the test result of the DUT is determined.

[0093] As an example, a diode reverse current test is performed on a clamped diode, with a second preset negative voltage of -90V and a preset positive voltage of 25V.

[0094] In the test procedure, the FPVI channel connected to the CN pin is supplied with -90V. At this time, the voltage difference between ground and the CN pin is 90V, and the ground potential is higher than the CN pin potential. The FOVI channel connected to the COM pin is supplied with 25V, and the current to ground of the COM pin is measured to obtain the test current. At this time, the voltage difference between the COM pin and the CN pin is 115V. The COM pin, ground, and CN pin are on the same circuit, and the current to ground of the COM pin is the current flowing from the COM pin to the CN pin.

[0095] See Figure 3 As shown in the diagram, this application provides a schematic diagram of the framework of another chip testing system. Figure 3 As shown. The test machine 10 also includes a switch control module 130. At least two chips under test 210 are mounted on the test board 20, which also includes a switch module 220. The switch module 220 is electrically connected to the chips under test 210.

[0096] Optionally, the switch control module 130 is electrically connected to the switch module 220, and the first test module 110, the second test module 120, and the chip under test 210 are all electrically connected to the switch module 220.

[0097] In some embodiments, based on test information, controlling the first test module 110 to output a first electrical signal to the first pin of the chip under test 210, and controlling the second test module 120 to output a second electrical signal to the second pin of the chip under test 210, includes:

[0098] Based on the test information, the control switch control module 130 sends control information to the switch module 220, so that the switch module 220 controls the first channel of the first test module 110 to be electrically connected to the first pin of the chip under test 210, and the first channel of the second test module 120 to be electrically connected to the second pin of the chip under test 210.

[0099] The first channel of the first test module 110 is controlled to output a first electrical signal to the first pin of the chip under test 210, and the first channel of the second test module 120 is controlled to output a second electrical signal to the second pin of the chip under test 210.

[0100] Optionally, the control information can be a relay control signal, and the switch module 220 includes a relay.

[0101] Optionally, the first channel of the first test module 110 is an FOVI channel, and the first channel of the second test module 120 is an FPVI channel.

[0102] In some embodiments, the STS8200 tester also includes a CBIT128 module. The switch control module 130 uses the CBIT128 module and implements current-voltage measurement and voltage-current measurement on the chip through the FOVI100 module and the FPVI10_PLUS module. The CBIT128 module provides relay control signals.

[0103] The chip testing in this embodiment can combine the resources in the FOVI100 module and the FPVI10_PLUS module to provide a high voltage for current testing and a high voltage for current testing to the chip. Therefore, a 64-pin connector for connecting the chip pins and resource channels, as well as a relay for switching resource channels, needs to be soldered onto the test board 20. The H terminal of the FOVI channel is connected to the COM pin of the chip, the H terminal of the FPVI channel is connected to the CN pin of the chip, and the L terminals of both the FOVI channel and the FPVI channel are grounded to 0V.

[0104] Based on the above technical solution, this application embodiment relates to a scheme for multi-station chip testing by superimposing a large voltage through a floating source. Therefore, this application embodiment can test or provide large voltages, enabling concurrent testing at multiple stations and reducing the single-test time during multi-station product testing. Simultaneously, during chip testing, the FOVI and FPVI channels in this application embodiment are in an independent state and can be used independently and normally in other parameter tests, improving resource utilization.

[0105] See Figure 4As shown in the diagram, this application provides a schematic diagram of the structure of a chip testing device 40. The chip testing device 40 is applied to a testing machine 10, which includes a first testing module 110 and a second testing module 120. Both the first testing module 110 and the second testing module 120 are electrically connected to a chip under test (DUT) 210. The DUT 210 includes a device under test (DUT), with its two ends electrically connected to the first pin and the second pin of the DUT 210, respectively. The third pin of the DUT 210 is grounded. The chip testing device 40 includes a determination module 401, a control module 402, and a processing module 403.

[0106] The determination module 401 is used to determine the test information for the device under test and the range of test results corresponding to the test information based on the acquired test program;

[0107] The control module 402 is used to control the first test module 110 to output a first electrical signal to the first pin of the chip under test 210 based on the test information, and to control the second test module 120 to output a second electrical signal to the second pin of the chip under test 210, so as to obtain the test result signal; wherein, of the first electrical signal and the second electrical signal, one electrical signal is negative and the other electrical signal is positive.

[0108] The processing module 403 is used to determine the test results of the chip under test based on the test result signal and the test result range.

[0109] Optionally, the control module 402 is used to control the first test module 110 to output a first preset negative voltage to the first pin of the chip under test 210, and to control the second test module 120 to output a preset positive current to the second pin of the chip under test 210, so as to superimpose the channel resources of the first test module 110 and the second test module 120.

[0110] Optionally, the processing module 403 is used to determine the test result of the chip under test based on the test result signal and the test result range, including: summing the absolute values ​​of the test voltage and the first preset negative voltage to obtain the voltage difference between the second pin and the first pin; and determining the test result of the chip under test based on the voltage difference and the preset voltage difference range.

[0111] Optionally, the control module 402 is used to control the first test module 110 to output a second preset negative voltage to the first pin of the chip under test 210, and to control the second test module 120 to output a preset positive voltage to the second pin of the chip under test 210, so as to form a preset voltage difference between the second pin and the first pin.

[0112] Optionally, the processing module 403 is used to determine the test result of the chip under test based on the test current and a preset current range.

[0113] Optionally, the control module 402 is used to control the switch control module 130 to send control information to the switch module 220 based on the test information, so that the switch module 220 controls the first channel of the first test module 110 to be electrically connected to the first pin of the chip under test 210, and the first channel of the second test module 120 to be electrically connected to the second pin of the chip under test 210; controls the first channel of the first test module 110 to output a first electrical signal to the first pin of the chip under test 210, and controls the first channel of the second test module 120 to output a second electrical signal to the second pin of the chip under test 210.

[0114] The apparatus in this application embodiment can execute the method provided in this application embodiment, and the implementation principle is similar. The actions performed by each module in the apparatus of each embodiment of this application correspond to the steps in the method of each embodiment of this application. For detailed functional descriptions of each module of the apparatus, please refer to the descriptions in the corresponding methods shown above, which will not be repeated here.

[0115] See Figure 5 As shown, this application provides a schematic diagram of the structure of a testing machine 10. Figure 5 As shown, the test machine 10 of this embodiment includes: a memory 61, a processor 60, and a computer program 62 stored in the memory 61 and executable on the processor 60. When the processor 60 executes the computer program, it implements the steps of the methods of the various embodiments of this application.

[0116] The test machine 10 may include, but is not limited to, a processor 60 and a memory 61. Those skilled in the art will understand that... Figure 5 This is merely an example of test machine 10 and does not constitute a limitation on test machine 10. It may include more or fewer components than shown, or combine certain components, or different components, such as input / output devices, network access devices, etc.

[0117] The processor 60 can be a Central Processing Unit (CPU), but it can also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor.

[0118] In some embodiments, memory 61 may be an internal storage unit, such as a hard disk or RAM. Memory 61 may be a removable / non-removable, volatile / non-volatile computer system storage medium; for example, memory 61 may be a non-volatile memory used for reading and writing non-volatile magnetic media. In other embodiments, memory 61 may also be an external storage device, such as a pluggable hard disk, Smart Media Card (SMC), Secure Digital (SD) card, or Flash Card equipped on the test machine 10. Memory 61 is used to store operating systems, applications, bootloaders, data, and other programs, such as program code for computer programs. Memory 61 may also be used to temporarily store data that has been output or will be output.

[0119] It should be noted that the information interaction and execution process between the above-mentioned devices / units are based on the same concept as the method embodiments of this application. For details on their specific functions and technical effects, please refer to the method embodiments section, and they will not be repeated here.

[0120] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0121] This application also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in the above-described method embodiments.

[0122] If the integrated units described above are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include at least: any entity or device capable of carrying computer program code to a device / terminal equipment, a recording medium, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electrical carrier signal, a telecommunication signal, and a software distribution medium. Examples include USB flash drives, portable hard drives, magnetic disks, or optical disks.

[0123] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium. When the program is executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), random access memory (RAM), flash memory, hard disk drive (HDD), or solid-state drive (SSD), etc. The storage medium can also include combinations of the above types of memory.

[0124] This application provides a computer program product that, when run on a test machine 10, enables the test machine 10 to execute the steps described in the above-described method embodiments.

[0125] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0126] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0127] In the embodiments provided in this application, it should be understood that the disclosed apparatus / network devices and methods can be implemented in other ways. For example, the apparatus / network device embodiments described above are merely illustrative. For instance, the division of modules or units described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0128] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0129] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A chip testing method, characterized in that, The method is applied to a testing machine, which includes a first testing module and a second testing module. Both the first testing module and the second testing module are electrically connected to a chip under test (DUT). The DUT includes a device under test (DUT), and its two ends are electrically connected to a first pin and a second pin of the DUT, respectively. The third pin of the DUT is grounded. Based on the acquired test program, the test information for the device under test and the range of test results corresponding to the test information are determined. Based on the test information, the first test module is controlled to output a first electrical signal to the first pin of the chip under test, and the second test module is controlled to output a second electrical signal to the second pin of the chip under test, so as to obtain a test result signal; wherein, of the first electrical signal and the second electrical signal, one electrical signal is negative and the other electrical signal is positive. Based on the test result signal and the test result range, the test result of the chip under test is determined.

2. The chip testing method according to claim 1, characterized in that, The first electrical signal is a first preset negative voltage, and the second electrical signal is a preset positive current; Controlling the first test module to output a first electrical signal to the first pin of the chip under test, and controlling the second test module to output a second electrical signal to the second pin of the chip under test, includes: The first test module is controlled to output a first preset negative voltage to the first pin of the chip under test, and the second test module is controlled to output a preset positive current to the second pin of the chip under test, so as to superimpose the channel resources of the first test module and the second test module.

3. The chip testing method according to claim 2, characterized in that, The test result signal includes a test voltage, which is the voltage of the second pin to ground, and the test result range includes a preset voltage difference range; Based on the test result signal and the test result range, the test result of the chip under test is determined, including: The voltage difference between the second pin and the first pin is obtained by summing the absolute values ​​of the test voltage and the first preset negative voltage. The test result of the chip under test is determined based on the voltage difference and the preset voltage difference range.

4. The chip testing method according to claim 1, characterized in that, The first electrical signal is a second preset negative voltage, and the second electrical signal is a preset positive voltage; Controlling the first test module to output a first electrical signal to the first pin of the chip under test, and controlling the second test module to output a second electrical signal to the second pin of the chip under test, includes: The first test module is controlled to output a second preset negative voltage to the first pin of the chip under test, and the second test module is controlled to output a preset positive voltage to the second pin of the chip under test, so as to form a preset voltage difference between the second pin and the first pin.

5. The chip testing method according to claim 4, characterized in that, The test result signal includes a test current, which is the current from the second pin to ground, and the test result range includes a preset current range. Based on the test result signal and the test result range, the test result of the chip under test is determined, including: Based on the test current and the preset current range, the test result of the chip under test is determined.

6. The chip testing method according to any one of claims 1-5, characterized in that, The device under test includes a clamping diode.

7. The chip testing method according to any one of claims 1-5, characterized in that, The testing machine also includes a switch control module, and at least two of the chips under test are mounted on a test board, which also includes a switch module. Based on the test information, the first test module is controlled to output a first electrical signal to the first pin of the chip under test, and the second test module is controlled to output a second electrical signal to the second pin of the chip under test, including: Based on the test information, the switch control module sends control information to the switch module, so that the switch module controls the first channel of the first test module to be electrically connected to the first pin of the chip under test, and the first channel of the second test module to be electrically connected to the second pin of the chip under test. The first channel of the first test module is controlled to output a first electrical signal to the first pin of the chip under test, and the first channel of the second test module is controlled to output a second electrical signal to the second pin of the chip under test.

8. A chip testing device, characterized in that, An application is made in a testing machine, the testing machine including a first testing module and a second testing module, both the first testing module and the second testing module being electrically connected to a chip under test (DUT). The DUT includes a device under test (DUT), the two ends of which are electrically connected to a first pin and a second pin of the DUT, respectively, and the third pin of the DUT is grounded. The device includes: The determination module is used to determine, based on the acquired test program, the test information for the device under test and the range of test results corresponding to the test information; The control module is used to control the first test module to output a first electrical signal to the first pin of the chip under test, and to control the second test module to output a second electrical signal to the second pin of the chip under test, based on the test information, to obtain a test result signal; wherein, of the first electrical signal and the second electrical signal, one electrical signal is negative and the other electrical signal is positive. The processing module is used to determine the test result of the chip under test based on the test result signal and the test result range.

9. A testing machine, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method as described in any one of claims 1 to 7.

10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method as described in any one of claims 1 to 7.

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