Application verification system

Abstract

The invention provides an application verification system. The system comprises a DSP test system and an FPGA test system. The DSP test system comprises at least one peripheral interface; the FPGA test system comprises an FPGA mother board and an FPGA daughter board. The DSP test system is used for testing the function of the DSP chip; the at least one peripheral interface is used for testing a function corresponding to the peripheral interface in the DSP chip; the FPGA test system is used for testing the function of the FPGA chip; and the FPGA mother board is in communication connection with the FPGA daughter board and is used for controlling the FPGA daughter board to test the function of the FPGA chip. According to the embodiment of the invention, through collaborative design of the DSP test system and the FPGA test system, comprehensive verification of functions of the DSP chip and the FPGA chip is realized, and the test efficiency, the coverage rate and the system suitability are improved.

Description

Technical Field

[0001] This application relates to the field of application verification technology, and in particular to an application verification system. Background Technology

[0002] In the field of electronic testing, with the continuous development of large-scale integrated circuits, integration and complexity have significantly increased, with the number of pins on chips typically reaching hundreds or even thousands. Traditional test machines are usually configured with 256 or 512 channels. When dealing with large-scale chips with more than 1,000 channels, the hardware cost of the test machine increases dramatically, making it difficult to comprehensively cover the electrical parameters of all pins. Furthermore, modern integrated circuits widely use peripheral circuits, such as Double Data Rate (DDR), Synchronous Dynamic Random Access Memory (SDRAM), and Flash Memory, which play important roles in chip functional testing. However, traditional test machines struggle to simulate these complex peripheral circuits in actual testing, resulting in insufficient test coverage. Simultaneously, program downloading for Field Programmable Gate Array (FPGA) or Digital Signal Processor (DSP) chips requires specific timing or dedicated download software. Traditional test machines are complex and inefficient when simulating download timing or switching test programs. Taking the 93K test machine as an example, its Linux-based operating system further increases the difficulty of operation and is not suitable for flexible and diverse program switching needs.

[0003] Existing technologies have significant shortcomings in terms of cost, functional coverage, and ease of operation. First, for chips with high pin density, traditional test equipment cannot maintain a reasonable cost while increasing the number of channels, limiting its application. Second, in terms of functional testing, test equipment struggles to simulate complex peripheral circuits and cannot fully verify the interaction performance between the chip and peripherals, resulting in incomplete test results. Furthermore, existing test equipment lacks support for specific experimental requirements, such as single-particle experiments, a verification process that relies on special testing environments. Traditional test equipment cannot assist in completing such experiments, increasing additional development costs and experimental complexity. Summary of the Invention

[0004] In view of this, the purpose of this application is to propose an application verification system.

[0005] To achieve the above objectives, this application provides an application verification system, comprising:

[0006] A DSP testing system and an FPGA testing system; the DSP testing system includes at least one peripheral interface; the FPGA testing system includes an FPGA motherboard and an FPGA daughterboard;

[0007] The DSP testing system is used to test the functionality of the DSP chip; at least one of the peripheral interfaces is used to test the corresponding functions in the DSP chip.

[0008] The FPGA testing system is used to test the functionality of the FPGA chip; the FPGA master board is communicatively connected to the FPGA daughter board and is used to control the FPGA daughter board to test the functionality of the FPGA chip.

[0009] In one possible implementation, the DSP testing system further includes a UART module; the system also includes a host computer.

[0010] The DSP testing system communicates with the host computer through the UART module.

[0011] In one possible implementation, the peripheral interface further includes: a DDR test module, an I2C interface, an SPI interface, and an EMIF interface;

[0012] The system also includes an EEPROM module, a NOR FLASH module, and a NAND FLASH chip;

[0013] The DDR test module is used to test the communication function with the DDR chip; the communication function includes communication data integrity, communication read / write speed and communication stability.

[0014] The I2C interface is connected to the EEPORM module, which is used to implement read and write operations of the EEPORM module and test the I2C bus function of the DSP chip; the I2C bus function includes the correctness of data transmission and protocol compliance.

[0015] The SPI interface is connected to the NOR FLASH module and is used to test the data integrity during the read and write process of the DSP chip.

[0016] The EMIF interface is connected to the NAND FLASH chip and is used to perform read and write tests on the NAND FLASH chip.

[0017] In one possible implementation, the peripheral interface further includes a clock generation module;

[0018] The clock generation module is used to provide a reference clock for the DSP test system;

[0019] The DSP test system is used to synchronize the reference clock to all the peripheral interfaces.

[0020] In one possible implementation, the peripheral interface further includes: an SRIO interface, a HyperLink interface, and an SGMII interface;

[0021] The SRIO interface is used to perform SRIO read / write tests on the DSP chip;

[0022] The HyperLink interface is used to perform read / write tests and interrupt tests on the DSP chip.

[0023] The SGMII interface is used to send network packets, perform tests based on the number of errors received, and conduct interruption tests.

[0024] In one possible implementation, the FPGA motherboard includes: a host computer communication module; the system further includes a host computer;

[0025] The FPGA motherboard receives test commands from the host computer through the host computer communication module and returns the test results to the host computer through the host computer communication module.

[0026] In one possible implementation, the FPGA motherboard includes: a daughterboard power supply module, a current sampling module, a relay control module, and an FPGA control core module; the daughterboard power supply module includes multiple power supply modules.

[0027] The subboard power supply module is used to provide multiple power supplies to the FPGA subboard, control the power-on sequence of the FPGA subboard, and / or collect the power supply current through the current sampling module to monitor the power consumption of the FPGA subboard.

[0028] The current sampling module is used to adjust the amplification factor according to the magnitude of the measured current;

[0029] The relay control module is used to control the output voltage and on / off state of the power supply module;

[0030] The FPGA control core module is used for the logical control of the test process and to store the test program, and loads the test program into the FPGA chip under test on the FPGA daughterboard.

[0031] In one possible implementation, the FPGA master also includes a clock generation module;

[0032] The clock generation module is used to generate a global system clock, providing a reference clock for the FPGA chip under test and the FPGA daughterboard.

[0033] In one possible implementation, the FPGA motherboard and the FPGA daughterboard communicate via a high-speed connector.

[0034] In one possible implementation, the FPGA daughterboard includes a DDR memory module, a download mode selection module, and a power supply module for the FPGA under test.

[0035] The FPGA chip under test is mounted on the FPGA sub-board;

[0036] The DDR memory module is used to verify the DDR controller function of the FPGA chip under test;

[0037] The download mode selection module is used to support multiple FPGA program download methods;

[0038] The FPGA power module under test is used to receive various power supplies provided by the FPGA motherboard and to power the FPGA chip under test.

[0039] As can be seen from the above, the application verification system provided in this application includes: a DSP testing system and an FPGA testing system; the DSP testing system includes at least one peripheral interface; the FPGA testing system includes an FPGA motherboard and an FPGA daughterboard; the DSP testing system is used to test the functionality of the DSP chip; at least one peripheral interface is used to test the corresponding function of the DSP chip corresponding to the peripheral interface; the FPGA testing system is used to test the functionality of the FPGA chip; the FPGA motherboard is communicatively connected to the FPGA daughterboard and is used to control the FPGA daughterboard to test the functionality of the FPGA chip. This application embodiment, by designing dedicated DSP testing systems and FPGA testing systems, comprehensively tests the functionality, performance, and electrical parameters of the DSP chip and FPGA chip respectively, solving the problems of insufficient functional coverage, poor flexibility, and high cost of traditional testing equipment in complex chip verification. The DSP testing system efficiently verifies the multi-core architecture, high-speed interfaces, memory read / write performance, and signal processing capabilities of DSP chips. The FPGA testing system, based on a modular motherboard and daughterboard design, focuses on testing logic unit functionality, input / output characteristics (IO characteristics), dynamic power consumption, and peripheral interface performance, supporting multiple download methods and operating modes. The separate design of the two systems not only optimizes the testing process and improves test coverage and efficiency but also reduces overall testing and development / maintenance costs. By combining automated testing procedures with host computer software, this application significantly improves the accuracy of test results and the convenience of data processing, providing reliable and efficient technical support for the functional verification and performance evaluation of complex chips. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in this application or related technologies, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 This is a schematic diagram of the application verification system structure according to an embodiment of this application;

[0042] Figure 2 This is a schematic diagram of the DSP testing system structure according to an embodiment of this application;

[0043] Figure 3 This is a schematic diagram of the FPGA test system structure according to an embodiment of this application. Detailed Implementation

[0044] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0045] It should be noted that, unless otherwise defined, the technical or scientific terms used in the embodiments of this application should have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms "first," "second," and similar terms used in the embodiments of this application do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are only used to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0046] It is understood that before using the technical solutions of the various embodiments in this disclosure, users will be informed of the type, scope of use, and usage scenarios of the personal information involved in an appropriate manner, and user authorization will be obtained.

[0047] For example, upon receiving a user's active request, a prompt message is sent to the user to explicitly inform them that the requested operation will require the acquisition and use of the user's personal information. This allows the user to independently choose, based on the prompt message, whether to provide personal information to the software or hardware such as electronic devices, applications, servers, or storage media performing the operations of this disclosed technical solution.

[0048] As an optional but not limited implementation, in response to a user's active request, sending a prompt message to the user can be done via a pop-up window, where the prompt message can be presented in text format. Furthermore, the pop-up window can also include a selection control allowing the user to choose "agree" or "disagree" to provide personal information to the electronic device.

[0049] It is understood that the above notification and user authorization process are merely illustrative and do not constitute a limitation on the implementation of this disclosure. Other methods that comply with relevant laws and regulations may also be applied to the implementation of this disclosure.

[0050] As described in the background section, with the continuous advancement of large-scale integrated circuit technology, the integration and complexity of chips have significantly increased, often reaching hundreds or even thousands of pins. However, traditional test machines are typically configured with 256 or 512 channels. When dealing with chips with more than 1000 pins, the hardware cost increases dramatically, making it difficult to comprehensively cover all electrical parameters. Furthermore, peripheral circuits widely used in modern integrated circuits (such as DDR, SDRAM, and flash memory) play a crucial role in chip functional testing, but traditional test machines struggle to simulate these complex peripherals, resulting in insufficient test function coverage. Simultaneously, downloading programs for FPGA or DSP chips requires specific timing sequences or dedicated software, and traditional test machines are complex and inefficient in simulating download timing and switching test programs. Taking the 93K test machine as an example, its Linux-based operating system environment further increases the operational difficulty, making it unsuitable for flexible and diverse program switching requirements. Therefore, existing technologies have significant shortcomings in terms of cost, functional coverage, and ease of operation, limiting their application scope and failing to comprehensively verify the interaction performance between chips and peripherals. In addition, traditional test machines lack support for specific experimental needs, such as single-particle experiments, which increases development costs and experimental complexity.

[0051] Based on the above considerations, this application proposes an application verification system, including a DSP testing system and an FPGA testing system. The DSP testing system includes at least one peripheral interface; the FPGA testing system includes an FPGA motherboard and an FPGA daughterboard. The DSP testing system is used to test the functionality of a DSP chip; at least one peripheral interface is used to test the corresponding function of the DSP chip corresponding to the peripheral interface; the FPGA testing system is used to test the functionality of an FPGA chip; the FPGA motherboard is communicatively connected to the FPGA daughterboard and is used to control the FPGA daughterboard to test the functionality of the FPGA chip. This application, by designing dedicated DSP and FPGA testing systems, achieves comprehensive testing of the functionality, performance, and electrical parameters of DSP and FPGA chips, solving the problems of insufficient functional coverage, poor flexibility, and high cost of traditional testing equipment in complex chip verification. The DSP testing system efficiently verifies multi-core architecture, high-speed interfaces, and memory performance, while the FPGA testing system, based on modular design, focuses on testing logic unit functionality, input / output characteristics, dynamic power consumption, and peripheral interface performance, and supports multiple download methods and operating modes. This separate design optimizes the testing process, improves test coverage and efficiency, and reduces overall testing and maintenance costs. Combined with automated testing procedures and host computer software, this application significantly improves the accuracy of test results and the convenience of data processing, providing reliable technical support for the functional verification and performance evaluation of complex chips.

[0052] The technical solutions of the embodiments of this application will be described in detail below through specific examples.

[0053] refer to Figure 1 The application verification system of this application embodiment includes:

[0054] The system includes a DSP testing system and an FPGA testing system. The DSP testing system includes at least one peripheral interface. The FPGA testing system includes an FPGA motherboard and an FPGA daughterboard. The DSP testing system is used to test the functionality of a DSP chip. At least one peripheral interface is used to test the corresponding function of the DSP chip. The FPGA testing system is used to test the functionality of an FPGA chip. The FPGA motherboard is communicatively connected to the FPGA daughterboard and is used to control the FPGA daughterboard to test the functionality of the FPGA chip.

[0055] In this embodiment, the main function of the DSP test system is to perform functional verification of the DSP chip. It includes at least one peripheral interface for testing the functions corresponding to these peripheral interfaces within the DSP chip. The DSP test system is designed with multiple peripheral interfaces, including a Double Data Rate Interface (DDR interface), an Inter-Integrated Circuit (I2C interface), a Serial Peripheral Interface (SPI interface), an External Memory Interface (EMIF interface), a Universal Asynchronous Receiver-Transmitter (UART interface), a Serial RapidIO (SRIO interface), a HyperLink Interface, and a Serial Gigabit Media Independent Interface (SGMII interface), etc. Each peripheral interface is meticulously designed. For example, the DDR interface is primarily used to test the communication capabilities between the DSP and the DDR chip, specifically including data integrity, read / write speed, and communication stability. The I2C interface is used to test the read / write capabilities of the Electrically Erasable Programmable Read-Only Memory Module (EEPROM) and the correctness and protocol compliance of the I2C bus. The SPI interface is used to test the read / write processes of Flash Memory (NORFLASH). The EMIF interface is used to test the read / write operations of Flash Memory Chips (NAND FLASH chips). Furthermore, the DSP test system communicates with the host computer via a UART module, providing the entire test system with the ability to interact with external devices.

[0056] Secondly, the FPGA test system consists of an FPGA motherboard and an FPGA daughterboard, which work together via a communication connection. The main function of the FPGA motherboard is to control the FPGA daughterboard to perform functional tests on the FPGA chip. The FPGA motherboard is responsible for providing multiple power supplies to the daughterboard, controlling the power-on sequence, and monitoring the power consumption of the FPGA chip through a current sampling module. Furthermore, the FPGA motherboard integrates a control logic module to manage the logical control of the test process and stores the test program through a built-in storage module. After the test program is loaded onto the FPGA daughterboard, its functionality is verified through actual operation of the FPGA chip.

[0057] The FPGA daughterboard design focuses more on the functional verification of the FPGA chip under test. The daughterboard houses the FPGA chip under test and includes a DDR memory module, a download mode selection module, and a power supply module. The DDR memory module is used to test the DDR controller function of the FPGA chip; the download mode selection module supports various FPGA program download methods, such as master-slave serial mode and slave serial mode; and the power supply module receives various power supplies from the motherboard to power the FPGA chip. The entire FPGA test system comprehensively verifies all functions of the FPGA chip through the coordinated operation of the motherboard and daughterboard.

[0058] Overall, this application, through the combination of a DSP testing system and an FPGA testing system, comprehensively covers the functional verification requirements of large-scale integrated circuit chips. Compared with traditional testing equipment, this system has advantages such as a higher number of channels, a wider testing range, more convenient program switching, and lower cost, and can also assist in completing special testing tasks such as single-event experiments. Every module and function in the system design has been carefully considered to ensure the accuracy, comprehensiveness, and efficiency of the testing.

[0059] refer to Figure 2 This is a schematic diagram of the DSP test system structure according to an embodiment of this application.

[0060] like Figure 2 As shown, a Gigabit Ethernet interface is illustrated. Gigabit Ethernet is a term describing various Ethernet frame transmission technologies at gigabit per second, defined by the IEEE 802.3-2005 standard. This standard allows half-duplex gigabit connections via hubs, but the speeds truly compliant with the standard are achieved in the market using full-duplex connections via switches.

[0061] Peripheral Component Interconnect Express Interface (PCIe) is a high-speed serial computer expansion bus standard. Originally named "3GIO," it was proposed by Intel in 2001 to replace the older Peripheral Component Interconnect (PCI), Extended Peripheral Component Interconnect (PCI-X), and Accelerated Graphics Port Bus Standard (AGP).

[0062] SRIO Interface. SRIO stands for Serial RapidIO Interface, a serial fast input / output interface for serial backplane, DSP, and related serial data plane connection applications. Serial RapidIO comprises a three-layer protocol: physical layer, transport layer, and logic layer. The physical layer defines electrical characteristics, link control, low-level error management, and low-level flow control data; the transport layer defines packet switching, routing, and addressing mechanisms; and the logic layer defines the overall protocol and packet format. It can achieve a minimum number of pins, uses Direct Memory Access Transfer (DMA), supports complex scalable topologies, and multi-point transmission; and offers four selectable speeds of 1.25Gbps, 2.5Gbps, 3.125Gbps, and 5Gbps to meet different application requirements, making it the best choice for embedded system interconnects for the next decade or so.

[0063] The HyperLink interface comprises digital signals and sideband control signals. The digital signals are based on a serializer / deserializer (SerDes), while the sideband signals are based on Low Voltage Complementary Metal-Oxide-Semiconductor (LVCMOS). Current HyperLink interfaces offer point-to-point connectivity.

[0064] UART interface. Universal Asynchronous Receiver / Transmitter, commonly known as UART, converts data between serial and parallel communication. As a chip that converts parallel input signals to serial output signals, UART is typically integrated into the connection of other communication interfaces.

[0065] SPI interface. SPI is an abbreviation for Serial Peripheral Interface. It is a high-speed, full-duplex, synchronous communication bus that only occupies four pins on the chip, saving chip pins and PCB layout space. Due to its simplicity and ease of use, more and more chips are integrating this communication protocol.

[0066] The I2C interface requires only two wires to transfer information between devices connected to the bus. The master device initiates data transmission and generates a clock signal to enable transmission. At this point, any addressed device is considered a slave. The master-slave and send-receive relationships on the bus are not constant but depend on the direction of data transmission. If the master wants to send data to a slave device, it first addresses the slave device, then actively sends data, and finally terminates the transmission. If the master wants to receive data from a slave device, it first addresses the slave device, then receives the data sent by the slave, and finally terminates the reception process. In this case, the master is responsible for generating the timing clock and terminating the data transmission.

[0067] EMIF Interface. The EMIF interface is an interface on TMS Digital Signal Processing Devices (TMSDSPs), specifically divided into EMIFA and EMIFB. Generally, EMIF enables the connection between the DSP and different types of memory (SRAM, Flash RAM, DDR-RAM, etc.). Typically, EMIF is connected to an FPGA, allowing the FPGA platform to act as a coprocessor, high-speed data processor, or high-speed data transmission interface.

[0068] In addition, external instrument interfaces are reserved on the control board and test board, such as standard miniature RF interface (SubMiniature version A, SMA), coaxial cable connector (Bayonet Neill-Concelman, BNC), test points, etc. The host computer software integrates drivers for commonly used instruments, such as Agilent oscilloscopes, signal generators, power supplies, etc. If it is necessary to control external instruments, automatic control can be easily performed, saving the trouble of manual adjustment and greatly improving debugging and testing efficiency.

[0069] In some embodiments, the DSP testing system further includes a UART module; the system also includes a host computer; the DSP testing system communicates with the host computer through the UART module.

[0070] In this embodiment, the DSP testing system includes a UART module, which communicates with the host computer. The UART module enables bidirectional data interaction between the DSP testing system and the host computer. Its function is to transmit test commands sent by the host computer to the DSP testing system, and simultaneously return the test results generated during the DSP testing process to the host computer for recording and display. The design of the UART module gives the testing system efficient communication capabilities, supports the implementation of test automation, and improves the convenience and efficiency of test operations.

[0071] Throughout the testing system, the UART module works closely with the peripheral interfaces of the DSP chip, forming the transmission channel for test commands and the path for result feedback. The host computer software sends test commands to the DSP testing system via the UART module. Upon receiving the commands, the DSP chip executes the test tasks according to the command content. For example, when a user needs to perform functional tests on the DSP chip's peripheral interfaces such as I2C, SPI, and EMIF, the test commands are transmitted to the DSP testing system via the UART module. The DSP chip performs read and write operations on the corresponding peripheral interfaces and returns the test results to the host computer via the UART module. The test results are presented on the host computer interface as data records and displayed in real time, and are also saved to a log file for subsequent analysis and traceability.

[0072] The UART module also supports hardware connection status detection. Before the test begins, the host computer sends a hardware connection detection command to the DSP test system via the UART module. If there is a problem with the hardware connection, the system will return an error message, prompting the user to check the connection status. Throughout the entire test process, the UART module continuously plays its role in bidirectional communication, both sending the user-configured test parameters to the test system and obtaining test progress and results in real time, ensuring the integrity and accuracy of the test.

[0073] Furthermore, the implementation of the UART module also incorporates the interface requirements of practical applications. The system design uses the FT2232HL chip to perform signal conversion between USB and UART, allowing the host computer to connect to the DSP test system via a common USB interface. This simplifies the use of the test equipment and enhances the system's applicability. The entire design not only meets the chip testing's need for efficient communication but also improves the system's flexibility through modular design, facilitating expansion in different application scenarios.

[0074] Through the collaboration between the UART module and the host computer, the entire system enables functional testing and data exchange of the DSP chip. Users can easily complete testing operations through the host computer's graphical interface, and test results can be returned and saved in real time, greatly facilitating test analysis. This design significantly improves testing efficiency and automation, making the testing of complex chips more efficient, controllable, and easy to operate. The addition of the UART module not only improves the functional structure of the testing system but also provides reliable communication assurance for the system's practical applications.

[0075] In some embodiments, the peripheral interface further includes: a DDR test module, an I2C interface, an SPI interface, and an EMIF interface; the system further includes an EEPOR module, a NOR FLASH module, and a NAND FLASH chip; the DDR test module is used to test the communication function with the DDR chip; the communication function includes communication data integrity, communication read / write speed, and communication stability; the I2C interface is externally connected to the EEPOR module, used to implement the read / write operation of the EEPOR module and test the I2C bus function of the DSP chip; the I2C bus function includes the correctness of data transmission and protocol compliance; the SPI interface is externally connected to the NOR FLASH module, used to test the data integrity during the read / write process of the DSP chip; the EMIF interface is connected to the NAND FLASH chip, used to perform read / write tests on the NAND FLASH chip.

[0076] In some embodiments, the peripheral interface further includes a clock generation module; the clock generation module is used to provide a reference clock for the DSP test system; the DSP test system is used to synchronize the reference clock to all the peripheral interfaces.

[0077] The DDR test module is used to test the communication functionality between the DSP chip and the DDR chip, including the integrity of communication data, read / write speed, and communication stability. During the test, the DSP sends data to the DDR chip through the DDR interface and reads the returned data, thereby verifying the correctness of data transmission and evaluating the chip's performance in a high-speed data transmission environment. This test ensures the DSP chip's ability to work seamlessly with the DDR memory in practical applications.

[0078] The I2C interface works in conjunction with an external EEPROM module to perform read and write operations on the EEPROM module and to test the I2C bus functionality of the DSP chip. During testing, the DSP chip sends data write commands to the EEPROM module via the I2C protocol and subsequently reads the data to verify successful writing, thus ensuring the correctness of data transmission and protocol compliance. The I2C interface testing also includes evaluations of data transfer rate and reliability to verify the chip's performance in a multi-device I2C bus environment.

[0079] The SPI interface connects to an external NOR FLASH module to test the DSP chip's read and write operations under the SPI protocol. During testing, the DSP chip sends write commands to the NOR FLASH module via the SPI interface and then reads the stored data for verification to check data integrity and transmission correctness. Testing the SPI interface can also verify the DSP chip's efficiency in accessing external memory and its stability under high-frequency communication conditions.

[0080] The EMIF interface connects to an external NAND flash chip for read / write testing. In this test, the DSP chip sends data write commands to the NAND flash chip via the EMIF interface and reads data from a specified memory address to verify the success of the write operation. This method allows for a comprehensive evaluation of the DSP chip's external memory expansion capabilities and its performance in large-scale data processing scenarios.

[0081] In addition, the DSP test system includes a clock generation module, which provides a reference clock signal for the entire system and ensures clock synchronization across all peripheral interfaces. Clock stability and accuracy are crucial for DSP chip functional testing, and the inclusion of the clock generation module provides a reliable timing foundation for the testing process.

[0082] DSP chips rely on a clock signal for operation, and the quality and stability of this clock signal directly affect the chip's performance. The clock generation module generates a high-precision reference clock, providing a reliable timing reference for the DSP chip and its peripheral modules. During testing, various peripheral interfaces (such as DDR, I2C, and SPI interfaces) need to exchange data with the DSP chip, and the timing of these data exchanges must be strictly synchronized with the reference clock. The clock generation module not only ensures the stability of the clock signal but also ensures highly coordinated communication timing between modules, guaranteeing the smooth progress of the testing process.

[0083] In implementation, the clock generation module typically consists of a crystal oscillator or a clock generation chip. The clock signal generated by these devices serves as a reference clock source for the DSP chip. The DSP chip uses internal frequency multiplication or division mechanisms to convert the reference clock into a suitable operating clock for each module, thereby supporting the normal operation of the chip and the functional testing of peripheral interfaces. For example, in DDR testing, the clock generation module provides a reference clock for the DDR interface, enabling the DSP chip to transmit data with external memory according to a preset timing protocol, thus verifying data integrity and transmission rate. Similarly, in I2C and SPI interface testing, the clock generation module provides a stable clock signal, ensuring the chip can correctly handle the timing requirements of the protocol.

[0084] Furthermore, the clock generation module is designed with flexibility and scalability in mind. During testing, if the clock frequency needs to be adjusted to suit different testing requirements, the clock generation module can dynamically change the frequency through configuration. This flexible clock control capability enables the DSP test system to meet the testing requirements of different types of chips and peripherals, while enhancing the system's applicability and versatility.

[0085] The clock generation module ensures the timing coordination and accuracy of the test process by providing a reference clock for the DSP test system and peripheral interfaces. It plays a crucial foundational role in the entire system, providing reliable support for the functional verification of the DSP chip. With the addition of the clock generation module, the entire system can complete comprehensive testing of the DSP chip, ensuring the accuracy of the test results and providing a scientific basis for the chip's subsequent applications.

[0086] The combination of these peripheral interfaces and modules enables the DSP testing system to cover the main functions and performance indicators of the DSP chip. By testing the read and write operations of the interfaces, the system can verify the compatibility of the DSP chip with various external devices and its reliability in different communication environments. This comprehensive testing capability provides crucial support for the functional verification of the DSP chip, while also ensuring the stability and efficiency of the chip in practical applications.

[0087] In some embodiments, the peripheral interface further includes: an SRIO interface, a HyperLink interface, and an SGMII interface; the SRIO interface is used to perform SRIO read / write tests on the DSP chip; the HyperLink interface is used to perform read / write tests and interrupt tests on the DSP chip; the SGMII interface is used to send network packets, perform tests based on the number of received errors, and perform interrupt tests.

[0088] In this embodiment, the SRIO interface is a high-performance serial communication interface widely used in embedded systems and high-bandwidth data transmission scenarios. During testing, the DSP chip communicates with external devices through the SRIO interface, performing read and write operations to verify the integrity of data transmission and the correctness of the protocol. For example, the test can configure the SRIO in multi-channel mode, transmitting data through different channels to ensure the normal functioning of each channel and to check for data loss or errors. This test can also evaluate the performance of the SRIO interface at different transmission rates, providing reliable support for the chip's application in high-bandwidth environments.

[0089] The HyperLink interface is designed for high-speed point-to-point connections and is commonly used for direct communication between DSP chips. In testing, the HyperLink interface verifies the communication capabilities and data integrity of the DSP chips by performing data read and write operations. The test also includes verification of interrupt functionality; by triggering and capturing interrupt signals, it ensures that the HyperLink interface can correctly respond to external events. This testing method not only evaluates the interface's basic functions but also verifies its stability in complex communication scenarios.

[0090] The SGMII interface provides Gigabit Ethernet communication capabilities and is a crucial interface for network data transmission in DSP testing systems. During testing, the DSP chip sends and receives network packets through the SGMII interface, and error counts are recorded to verify the accuracy of data transmission. This test comprehensively evaluates the DSP chip's performance in network communication, ensuring its data exchange capabilities in practical applications. Furthermore, the SGMII interface supports interrupt function testing, verifying the DSP chip's interrupt response capabilities by simulating network events to trigger interrupt signals.

[0091] The addition of these peripheral interfaces enables the DSP test system to cover a wider range of functions, meeting the testing requirements for high-performance communication and complex data processing. The high-speed serial communication function of the SRIO interface, the point-to-point connection capability of the HyperLink interface, and the network communication performance of the SGMII interface are used to comprehensively verify the DSP chip for different application scenarios. Through these interfaces, the test system can evaluate the performance of the DSP chip in various complex environments, providing strong technical support for the chip's practical application. This design not only expands the functionality of the test system but also enhances its flexibility and practicality, providing an efficient solution for testing different types of DSP chips.

[0092] In some embodiments, the power supply of the DSP under test is provided independently, including separate supply of different voltages such as core voltage and I / O voltage. The power consumption of the device can be tested by reading current data.

[0093] DSP Boot Method: The TMS320C6678 offers a highly flexible two-level boot method. This application employs this boot method. First, the DSP itself is set to I2C boot mode. Upon power-up, the device automatically loads the first-level boot program from the external I2C EEPROM memory. After this first-level boot program starts, it loads the test program from the SPI Flash memory into the DSP and resets to boot according to the new program.

[0094] SRIO Loopback: The TMS320C6678 provides a configurable 4-channel SRIO interface. In this application, it is configured as two sets of 2-channel interfaces, connected together to form a loopback circuit. The SRIO clock uses 312.5MHz and can be internally configured to achieve a maximum 5G transmission speed.

[0095] UART Interface: In this design, the DSP's UART interface is connected to the interface circuit via an external level conversion circuit, enabling communication with the motherboard. An option to connect to the FT2232 to convert the serial port to a USB interface is also provided, which can be switched using a jumper.

[0096] SGMII Loopback: SGMII interfaces can be used to provide Ethernet interfaces up to Gigabit speeds. In this design, the transmit and receive ports of two SGMII interfaces are interconnected to form a loopback circuit.

[0097] In one feasible embodiment, the DSP test items include:

[0098] Memory read / write test:

[0099] RAM test: Perform data filling and address tests on unused RAM (part of Local L2 SRAM and part of Multicore shared memory). The filling test value is 0xff55aa00.

[0100] DDR3 testing: Data filling and address testing are performed on the first 1M address of DDR3.

[0101] Data filling test: Write fixed data to a certain address, and then read back to verify whether the data is correct.

[0102] Address test: Start writing data continuously from a certain address. The writing length can be defined by yourself. The written data is the corresponding address value. After writing all the data, read back to verify whether it is correct.

[0103] I2C read / write EEPROM test: After the chip is powered on, the I2C protocol is initialized and the I2C self-loopback test is completed.

[0104] Data filling and address testing are performed on the last 1K address in the EEPROM via the I2C protocol, with the filling test value being 0xff55aa00.

[0105] SPI read / write NOR FLASH test: After the chip is powered on, the SPI protocol is initialized and an SPI self-loop test is performed.

[0106] The last 1K address of the NOR FLASH was tested for data filling and addressing using the SPI protocol. The filling test value was 0xff55aa00.

[0107] UART host computer communication test: After the chip is powered on, the UART initialization is completed.

[0108] Throughout the entire testing process, the host computer needs to send instructions to the TMS320C6678 via UART to complete the test; otherwise, the test cannot be performed. Therefore, this test does not need to be performed separately.

[0109] EMIF NAND FLASH test: The EMIF interface is initialized after the chip is powered on.

[0110] The last block of the NAND flash is tested for data filling and addressing via the EMIF interface. The filling test value is 0xff55aa00.

[0111] PCIe self-loopback test: After the chip powers on, the PCIe interface is initialized to RC mode.

[0112] The data filling and address testing of a portion of memory was performed via the PCIe interface. The test data for filling the memory was 0x00000000 and 0xFFFFFFFF.

[0113] After the test is completed, manually trigger the PCIe interrupt and check if the interrupt has been triggered.

[0114] SRIO self-loopback test: The chip completes SRIO initialization after power-on.

[0115] After the test begins, configure SRIO as 1xLaneA, 1xLaneB, 1xLaneC, and 1xLaneD, and perform SRIO read and write tests through the SRIO interface.

[0116] HyperLink self-loopback test: The HyperLink interface is initialized after the chip is powered on.

[0117] The test begins with read / write tests via the HyperLink interface, followed by HyperLink interruption tests.

[0118] SGMII self-loopback test: The chip initializes the SGMII interface upon power-up.

[0119] At the start of the test, network packets are sent through the SGMII interface. After receiving the packets, the number of errors is checked to complete the module test. Then, an interrupt is manually triggered to check the interrupt function of this module.

[0120] Parameter testing: The functional test covers the measurement of the following parameters by setting limiting parameters: high-level output voltage (VOH), low-level output voltage (VOL), high input current (IIH), low input current (IIL), high output current (IOH), low output current (IOL), high-impedance output current (IOZ), static current (IDD), and short-circuit output current (IOS).

[0121] refer to Figure 3 This is a schematic diagram of the FPGA test system structure according to an embodiment of this application.

[0122] like Figure 3 As shown in the figure, this is a block diagram of the structure between the motherboard and daughterboard in the FPGA testing system. It includes the FPGA motherboard, the FPGA daughterboard, and high-speed connectors. The high-speed connectors use a pogo pin configuration. Pogo pin connectors are characterized by their high signal frequency capability and crimping method, eliminating the need for soldering connectors on the daughterboard, thus simplifying use. Since the FPGA requires multiple power supplies, this application designs multiple power supplies onto the control motherboard. The control core on the motherboard controls the power-on sequence, enabling power-on sequence testing. Simultaneously, the control motherboard is responsible for the entire board testing process and test sequence, and uploads the measured results to the host computer for display.

[0123] The FPGA public board mainly performs functions such as communication with the host computer, controlling the power-on sequence of the daughter board, power supply to the daughter board, current sampling, and communication with the FPGA under test. To accomplish the above functions, the circuit module is designed as follows.

[0124] Host computer communication module: The host computer communication module consists of two parts: a gigabit Ethernet communication module and a serial communication module. The two serve as backups for each other. When one communication method has a problem, it switches to the second communication method. This application temporarily uses the serial communication method.

[0125] Daughterboard Power Supply Module: Since FPGAs require various voltage types, multiple power supply modules are used. Each power supply module can use a relay to switch its output voltage, with the relay logic controlled by the motherboard. Each power supply module has up to four voltage outputs, which can power different power supply modules on the daughterboard. Each output is connected in series with a sampling resistor to the sampling circuit for current sampling.

[0126] The current sampling module includes a multiplexer module, an instrumentation amplifier module, and an ADC sampling module. This sampling circuit can adjust the amplification factor according to the magnitude of the measured current to ensure the accuracy of the measurement or sampling.

[0127] Clock generation module: Used to provide a clock for the entire board system, and can also lead the clock to the pogo pin connector to provide a clock for the daughter board.

[0128] Relay control module: This module is used to control the resistor pairs of each power supply module. This reference board has a total of 7 relays.

[0129] FPGA control core module: This module uses Xilinx's K7160T as the control core, and is supplemented by a reset module, a clock generation module, and 10 SPI flash memory modules to store daughterboard test programs.

[0130] FPGA (325T) Test Daughterboard Design: The daughterboard mainly houses the chip under test and related peripheral test circuits. Since most FPGA testing is concentrated in the internal logic units, the number of peripheral test circuits is relatively small, mainly including a DDR memory module, a download mode selection module, and a power supply control module.

[0131] In some embodiments, the FPGA motherboard includes a host computer communication module; the system further includes a host computer; the FPGA motherboard receives test commands from the host computer through the host computer communication module, and returns the test results to the host computer through the host computer communication module.

[0132] In this embodiment, the FPGA motherboard serves as the core control unit of the entire FPGA testing system, integrating a host computer communication module to support communication with external devices. Through this module, the host computer can send test-related instructions to the FPGA testing system, such as starting specific test tasks, configuring test parameters, or loading test programs. During testing, the FPGA motherboard parses the instructions sent by the host computer and controls the FPGA daughterboard and the FPGA chip under test to perform corresponding test operations. After the test is completed, the FPGA motherboard summarizes the test results and sends them to the host computer for display and recording via the host computer communication module, thereby achieving real-time transmission and analysis of test data.

[0133] The host computer communication module supports multiple communication methods during implementation to ensure system flexibility and reliability. For example, the system design includes both Gigabit Ethernet and serial communication modules for communication between the host computer and the FPGA motherboard. These two methods can serve as backups for each other; if one communication method fails, it can switch to the other to continue communication, ensuring system stability and reliability. In practical applications, users can select the appropriate communication method based on their testing requirements, thereby improving testing efficiency and adaptability.

[0134] Furthermore, the host computer communication module collaborates with other functional modules of the FPGA motherboard to complete testing tasks. During the testing process, after receiving test commands from the host computer, the FPGA motherboard calls relevant modules to execute test operations based on the commands. For example, it provides the necessary power to the FPGA chip under test via the daughterboard power supply module, or loads the test program and starts the test via the FPGA control core module. After the test is completed, the test results are uploaded to the host computer via the host computer communication module. Users can view the results on the host computer interface and save the data for subsequent analysis. This process demonstrates the crucial role of the host computer communication module in the system's functional implementation.

[0135] Through the host computer communication module, the FPGA testing system achieves efficient command transmission and data interaction, providing users with a convenient operating method. Users do not need to directly operate the hardware devices; they only need to send commands and view test results through the host computer's software interface, thus greatly reducing the barrier to entry and improving testing efficiency. The design of the host computer communication module allows the FPGA testing system to flexibly adapt to different testing needs and meet the requirements of complex testing scenarios, while also providing technical support for system expansion and upgrades. This design not only enhances the system's practicality and reliability but also provides users with a user-friendly operating experience.

[0136] In some embodiments, the FPGA motherboard includes: a daughterboard power supply module, a current sampling module, a relay control module, and an FPGA control core module; the daughterboard power supply module includes multiple power modules; the daughterboard power supply module is used to provide multiple power supplies to the FPGA daughterboard, control the power-on sequence of the FPGA daughterboard, and / or collect the power supply current through the current sampling module to monitor the power consumption of the FPGA daughterboard; the current sampling module is used to adjust the amplification factor according to the magnitude of the measured current; the relay control module is used to control the output voltage and on / off state of the power supply module; the FPGA control core module is used for the logical control of the test process and storing the test program, and loading the test program into the FPGA chip under test on the FPGA daughterboard.

[0137] In this embodiment, it is explicitly stated that the FPGA motherboard includes a daughterboard power supply module, a current sampling module, a relay control module, and an FPGA control core module. These modules together constitute the key functional units of the FPGA motherboard. The daughterboard power supply module is responsible for providing multiple power supplies to the FPGA daughterboard, supporting control of the daughterboard's power-on sequence, and collecting the supply current through the current sampling module to monitor the FPGA daughterboard's power consumption. The relay control module is responsible for controlling the output voltage and on / off state of the power supply module, while the FPGA control core module is used for the logic control of the test process and the storage and loading of test programs. Through their collaborative work, they achieve comprehensive testing of the FPGA chip.

[0138] The daughterboard power supply module is designed to fully consider the complex power supply requirements of the FPGA chip. Since FPGA chips typically require multiple voltage supports, such as core voltage and input / output voltages, the daughterboard power supply module provides multiple power outputs and can dynamically adjust the output values ​​of each voltage according to test requirements. Furthermore, the daughterboard power supply module supports precise control of the power-on sequence, ensuring that each voltage starts up sequentially according to the specified timing, thus providing a reliable power guarantee for the normal operation of the FPGA chip. This design not only meets the basic requirements for chip operation but also supports power consumption measurements and power performance evaluations involved in the test project.

[0139] The current sampling module monitors the power supply current to the daughterboard to measure the power consumption of the FPGA chip. The measurement process involves connecting a sampling resistor in series in the power supply line, amplifying and processing the voltage drop across the sampling resistor using an instrumentation amplifier, and finally acquiring the current data via an ADC (analog-to-digital converter). The current sampling module is also designed to dynamically adjust the amplification factor based on the actual power supply current, ensuring sampling accuracy. By monitoring power consumption data in real time, the system can evaluate the power consumption characteristics of the FPGA chip under test under different operating conditions, providing a reference for optimizing the chip's energy efficiency.

[0140] The relay control module manages the on / off state of the power supply in the daughterboard power supply module and controls the output voltage of the power supply module. This module flexibly switches the power output by controlling the switching operation of relays, supporting various testing requirements. For example, in the power-on sequence testing of FPGA chips, the relay control module can sequentially start each power supply module to verify whether the chip's power timing requirements meet design standards. Simultaneously, this module also facilitates dynamic power supply adjustment and fault protection during testing.

[0141] The FPGA control core module is the core logic unit of the motherboard. Using the FPGA chip as the control core, it is responsible for the logical control of the test process and the management of the test program. This module parses the test commands sent by the host computer and coordinates various functional modules to complete the specified test tasks. In addition, the control core module integrates a storage unit for storing test programs and configuration data, and can load the test program into the FPGA chip under test on the daughterboard to initiate functional testing. After the test is completed, the control core module summarizes the results and feeds them back to the host computer, completing the entire test process.

[0142] These modules work closely together, enabling the FPGA motherboard to meet the demands of complex testing scenarios. The combination of the daughterboard power supply module and current sampling module ensures power stability and accurate power consumption measurement; the addition of the relay control module makes power management more flexible; and the FPGA control core module manages the entire testing process, achieving efficient system operation. Through the collaborative work of these modules, the FPGA motherboard can support testing of various types of FPGA chips and ensure the reliability and comprehensiveness of test results. This design not only enhances the functionality and adaptability of the testing system but also provides users with an efficient and reliable testing solution.

[0143] In some embodiments, the FPGA master board further includes a clock generation module; the clock generation module is used to generate a global system clock to provide a reference clock for the FPGA chip under test and the FPGA daughter board.

[0144] In this embodiment, the FPGA master board also includes a clock generation module, which is responsible for generating a global system clock and providing a reference clock for the FPGA chip under test and the FPGA daughterboard. In the test system, the clock signal is a core element ensuring the coordinated operation of all modules. The clock generation module is designed to provide a high-precision, stable clock signal, thereby meeting the stringent timing requirements of the FPGA chip under test and related test modules.

[0145] The clock generation module generates a clock signal via a crystal oscillator or clock generation chip. This signal can be directly provided to the FPGA chip under test as its operating clock, or it can be distributed to other modules on the daughter board for synchronous operation. During testing, the reference clock signal output by the clock generation module on the FPGA motherboard becomes the timing reference for the entire system operation, ensuring the stability and accuracy of the test process. For example, in the testing of DDR memory modules, the reference clock provided by the clock generation module ensures that data transmission between the FPGA and DDR follows a predetermined timing protocol, thereby verifying the integrity and smoothness of data transmission.

[0146] Furthermore, the clock generation module possesses flexible frequency adjustment capabilities, enabling it to generate clock signals of different frequencies to meet diverse testing requirements. This flexibility allows the system to adapt to the testing needs of various types of FPGA chips; for example, high-frequency applications require faster clock signals, while low-frequency applications require more stable clock support. Through dynamic adjustment of the clock frequency, the clock generation module provides technical support for the diversification of testing projects, thereby expanding the system's applicability.

[0147] The clock generation module is designed with a focus on signal integrity and interference immunity, ensuring that the clock signal is not distorted by external environmental interference during transmission. This high-quality clock signal is crucial for the accuracy of test results, especially in scenarios requiring precise measurement of the performance of the FPGA chip under test, where the stability of the clock signal directly determines the success or failure of the test.

[0148] By providing a unified reference clock for both the FPGA motherboard and daughterboard, the clock generation module enables efficient collaboration among modules within the system, ensuring timing consistency during testing. It not only supports the normal operation of the FPGA chip under test but also plays a fundamental role in guaranteeing the performance of the entire test system. The addition of the clock generation module allows the FPGA test system to maintain efficient operation in various application scenarios, providing reliable technical support for chip functional verification and performance evaluation. This design enhances the system's stability and flexibility while providing convenience for users operating under different testing requirements.

[0149] In some embodiments, the FPGA motherboard and the FPGA daughterboard communicate via a high-speed connector.

[0150] In this embodiment, the communication method between the FPGA motherboard and the FPGA daughterboard is further defined, explicitly stating that they communicate via a high-speed connector. The high-speed connector is designed to meet the requirements of high-frequency signal and large data volume transmission in the FPGA test system, while ensuring signal integrity and stability. Specifically, the high-speed connector between the FPGA motherboard and the daughterboard adopts the Pogo Pin Connection Method, which features high reliability and high-frequency signal transmission capabilities, effectively reducing signal loss and interference during transmission.

[0151] In FPGA testing systems, the motherboard and daughterboard frequently exchange data and control signals. High-speed connectors not only ensure signal transmission speed and quality but also offer simpler and more stable connections through their mechanical structure. Pogopin connectors feature a spring-loaded contact design, which not only accommodates high-frequency signal transmission requirements but also enables quick connection and disconnection via crimping. This solderless connection method reduces soldering steps on the daughterboard connectors, improving the daughterboard's maintainability and reusability.

[0152] The high-speed connector also considers the parallelism and isolation of multiple signal channels during transmission, ensuring that no interference occurs between different signal channels. Through this connection method, the FPGA motherboard can accurately transmit test commands and data to the FPGA chip under test on the daughter board, while the daughter board can also quickly return test results and acquired data to the motherboard for processing via the connector. This efficient data exchange method ensures the rapid operation of the test system.

[0153] Furthermore, the application of high-speed connectors enhances the system's modular design capabilities. The motherboard and daughterboards are physically connected via connectors. This separate design allows users to replace different daughterboards to accommodate different FPGA chip models or testing tasks, without requiring modifications to the motherboard's hardware structure. This flexibility not only reduces the cost of using the test system but also significantly improves its adaptability and scalability.

[0154] By using high-speed connectors to enable communication between the motherboard and daughterboard, the FPGA test system has been optimized in terms of data transmission rate, signal integrity, and modular design. This connection method provides a reliable hardware foundation for the test system, enabling it to meet the stringent requirements of signal transmission and data processing in high-performance FPGA chip testing, while also providing users with a convenient operating experience and maintenance solutions. The high-speed connector design reflects a balance between performance and practicality, allowing the FPGA test system to maintain efficient and stable operation in complex and ever-changing testing environments.

[0155] In some embodiments, the FPGA daughterboard includes a DDR memory module, a download mode selection module, and a power supply module for the FPGA under test; the FPGA chip under test is mounted on the FPGA daughterboard; the DDR memory module is used to verify the DDR controller function of the FPGA chip under test; the download mode selection module is used to support multiple FPGA program download methods; the power supply module for the FPGA under test is used to receive multiple power supplies provided by the FPGA motherboard and to power the FPGA chip under test.

[0156] In this embodiment, the constituent modules and functions of the FPGA daughterboard are further defined. In the test system, the FPGA daughterboard mainly includes a DDR memory module, a download mode selection module, and a power supply module for the FPGA under test. It is also specified that the FPGA chip under test is mounted on the daughterboard. The FPGA daughterboard is designed to provide the necessary functional support and peripheral circuit environment for the FPGA chip under test, enabling it to operate normally during the test and verifying the chip's various performance characteristics and functions.

[0157] The DDR memory module is a crucial component of the daughterboard, used to verify the DDR controller functionality of the FPGA chip under test (FPGA). DDR memory is a high-speed storage device widely used in modern FPGA chips, and its performance directly impacts the chip's performance in data processing and multi-tasking parallel operations. During testing, the DDR memory module performs data read and write operations with the FPGA chip under test to verify whether the chip's DDR controller can correctly control the memory, ensuring that the integrity, stability, and speed of data transmission meet design requirements. Specific tests include writing fixed data to the DDR module and reading it to verify the consistency of write and read operations, while simultaneously testing the stability of the chip processing data at high frequencies.

[0158] The download mode selection module supports multiple FPGA program loading methods, providing an effective means for flexibly configuring test tasks. The FPGA chip under test typically supports multiple program download modes, such as master-serial, slave-serial, master-parallel, and slave-parallel modes. Through hardware circuit design and jumper configuration, the download mode selection module allows users to select the appropriate download mode according to their test requirements. During testing, the FPGA control core module on the motherboard sends the test program to the daughterboard, and the download mode selection module loads the program into the FPGA chip under test according to the set mode, ensuring that the test program can accurately start and complete the test task. This module's design not only expands the adaptability of the test system but also makes it possible to evaluate the impact of different loading modes on chip performance.

[0159] The power supply module for the FPGA under test (DUT) is responsible for providing a stable operating voltage to the FPGA chip mounted on the daughterboard. FPGA chips typically require multiple different voltages, such as core voltage and input / output voltages. The power supply module works in conjunction with the daughterboard power supply module of the motherboard, receiving multiple power supplies from the motherboard to provide the required operating voltages to the DUT. To ensure the normal operation of the chip, the power supply module also supports precise voltage adjustment and monitoring, ensuring that the chip's power requirements are fully met under different testing scenarios.

[0160] The FPGA daughterboard, through its modular design, provides a complete testing environment for the functional verification of the chip under test (DUT). The DUT communicates with the motherboard through the daughterboard and executes specified test tasks under the control of the motherboard.

[0161] In some embodiments, FPGA test items include:

[0162] The FPGA under test is powered off; the continuity characteristics of the I / O pins are tested.

[0163] Test method: Set the power supply of each FPGA I / O to zero, apply a current of 200uA, and measure the voltage to obtain the continuity characteristics. The continuity characteristics of FPGA dedicated I / O pins (such as I / O pins connected to DDR) are not tested.

[0164] The FPGA under test is powered on according to the specified procedure, and the power-on sequence test is performed.

[0165] Test method: The main control board can control the enabling or disabling of various voltages of the FPGA under test. Enable the FPGA in the order specified in the detailed specification. After enabling, the program will automatically load the flash into the FPGA. After waiting for the instruction time, check whether the done signal is pulled high to determine whether the power-on sequence is normal.

[0166] The FPGA under test was successfully powered on, and the program was loaded into the FPGA using the main string method to test parameters such as IIL, IIH, VOL, and VOH.

[0167] Test method: When the FPGA is programmed, all IOs are configured as inputs to measure IIL and IIH, respectively, and the corresponding current values ​​are measured to obtain the corresponding IIL and IIH. When measuring VOL and VOH, all IOs are configured as outputs, and the corresponding positive and negative currents are supplied by the PPMU to measure the corresponding voltage values. During program configuration, the FPGA's three IOs (IO[2:0]) are selected. When IO[2:0] = 000, it is in input mode; when IO[2:0] = 100, it is configured as output mode.

[0168] The test download methods include: master string method, slave string method, master selectmap mode, and slave selectmap mode;

[0169] Test Method: This test item is mainly used to test various download methods of the FPGA, including master-serial download, slave-serial download, master-parallel download, and slave-parallel download. The main control board has test logic for various download methods. Different download methods are selected through software, and the done signal is monitored to verify and test different download methods.

[0170] Test resource utilization: 60%, 70%, 80%;

[0171] Test Method: The system motherboard contains five SPI flash memory chips, capable of storing different versions of the program. Before testing, different compiled versions of the program, including programs with resource utilization rates of 60%, 70%, and 80%, are downloaded to three different flash memory chips via a host computer. During the actual test, the system motherboard reads the different versions of the program from the flash memory and downloads them to the FPGA under test via serial communication, monitoring the status of the output pins to ensure they are functioning correctly.

[0172] In addition, different download and startup methods were tested using the control FPGA.

[0173] The test measures the dynamic power consumption of each module during operation. The chip under test controls the power-on sequence and provides the operating voltage through the main control board. The main control board obtains the output current value by measuring the voltage drop across the detection resistor on the power supply line, thereby measuring the power of different power supply modules.

[0174] The measurement uses the AD7686 chip. When the FPGA is running all its functions, the main FPGA switches the measurement channels one by one and selects an appropriate amplification factor. The AD chip samples the data, and the main FPGA reads the sampled data back to the host computer, which then calculates and displays the power consumption.

[0175] DDR peripheral interface testing. The DDR peripheral uses DDR3 chips, with a maximum speed of 1600Mbps. The DDR read and write control is converted by the IP provided by the manufacturer into a user-side I / O interface. The FPGA reads and writes DDR3 according to the timing of the user-side interface, and checks whether the read and write results are consistent with expectations, thus verifying the FPGA's DDR controller.

[0176] In this embodiment, the test system is developed based on the Microsoft .NET framework, written in VB.net, and developed in Visual Studio 2013. The user graphical interface is designed using the WinForm library under the .NET platform.

[0177] The .NET Framework is a software development platform developed by Microsoft that is dedicated to agile software development, rapid application development, platform independence, and network transparency.

[0178] Visual Basic .NET is an object-oriented programming language built on the Microsoft .NET Framework. It operates as an interpreted language during debugging and as a compiled language when outputting as an EXE program. Visual Basic .NET can be seen as an upgraded version of Visual Basic on the .NET Framework platform, enhancing its support for object-oriented programming. Most VB.NET programmers use Visual Studio .NET as their IDE (Integrated Development Environment). SharpDevelop is another available open-source IDE. Furthermore, VB.NET requires the .NET Framework platform to run.

[0179] The software's graphical interface is designed using the WinForms library on the .NET platform. WinForms provides a rich set of controls that developers can flexibly combine to design form interfaces that meet diverse project requirements. WinForms also facilitates data display and manipulation; displaying data on a form is one of the most common scenarios in application development. WinForms provides comprehensive support for database processing, allowing access to data in the database and displaying and manipulating that data on the form.

[0180] As can be seen from the above embodiments, the application verification system described in this application includes: a DSP testing system and an FPGA testing system; the DSP testing system includes at least one peripheral interface; the FPGA testing system includes an FPGA motherboard and an FPGA daughterboard; the DSP testing system is used to test the functionality of the DSP chip; at least one peripheral interface is used to test the corresponding function of the DSP chip corresponding to the peripheral interface; the FPGA testing system is used to test the functionality of the FPGA chip; the FPGA motherboard is communicatively connected to the FPGA daughterboard and is used to control the FPGA daughterboard to test the functionality of the FPGA chip. This application embodiment, through the combination of the DSP testing system and the FPGA testing system, and the reasonable design and collaborative work of each functional module, significantly improves the coverage, testing efficiency, and system flexibility of chip testing.

[0181] First, this application achieves comprehensive verification of the DSP chip's functionality through a DSP testing system. The system integrates various peripheral interfaces, such as a DDR test module, I2C interface, SPI interface, EMIF interface, SRIO interface, HyperLink interface, and SGMII interface, enabling comprehensive testing of the DSP chip's communication capabilities, data integrity, protocol compliance, and read / write performance. This multi-interface design overcomes the shortcomings of traditional testing equipment in terms of functional coverage and peripheral simulation capabilities, allowing the testing system to more accurately reflect the DSP chip's performance in real-world application scenarios.

[0182] Secondly, the FPGA testing system achieves efficient testing of FPGA chips through a distributed design comprising an FPGA motherboard and FPGA daughterboards. The motherboard integrates a daughterboard power supply module, a current sampling module, a relay control module, and an FPGA control core module, enabling precise control of the daughterboard power supply and real-time monitoring of the supply current to assess the power consumption of the chip under test. The daughterboard integrates a DDR memory module, a download mode selection module, and the FPGA power supply module, providing the necessary peripheral support and operating environment for the chip under test. This modular design not only improves the system's adaptability and scalability but also makes the testing process more flexible and controllable, meeting the testing needs of different types and specifications of FPGA chips.

[0183] Furthermore, the test system of this application ensures precise timing coordination during testing through a clock generation module. The clock generation module provides a high-precision reference clock for both the DSP and FPGA test systems, ensuring synchronized operation of each module during testing. This design solves the problem of test result deviations caused by unstable clock signals in traditional test equipment, further improving the accuracy and reliability of the test.

[0184] The host computer communication module enables efficient data interaction between the test system and the user. Users can configure test parameters and view test results in real time through the host computer interface, greatly simplifying chip testing operations. Through UART, Ethernet, and serial port modules, test commands and results are transmitted rapidly, ensuring a smooth testing process.

[0185] The application of high-speed connectors significantly improves data transmission efficiency and signal integrity between the motherboard and daughterboard. High-speed connectors using pogo pin connections support high-frequency signal transmission, reducing signal loss and interference, while enabling rapid hardware connection and disconnection. This design not only improves system maintenance convenience but also allows users to flexibly replace daughterboards according to testing needs, thereby reducing overall testing costs.

[0186] In summary, this application, through the collaborative design of a DSP test system and an FPGA test system, combined with multiple interfaces, modular circuits, flexible clock and communication schemes, and the application of high-speed connectors, successfully achieved comprehensive functional verification, performance evaluation, and cost optimization of large-scale integrated circuit chips. The test system boasts advantages such as high coverage, high adaptability, high precision, and high efficiency, providing reliable technical support for chip research and development, production, and quality control.

[0187] It should be noted that the above description describes some embodiments of this application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in a different order than that shown in the above embodiments and still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0188] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of this application (including the claims) is limited to these examples; within the framework of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of the embodiments of this application as described above, which are not provided in the details for the sake of brevity.

[0189] The embodiments of this application are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the embodiments of this application should be included within the protection scope of this application.

Claims

1. An application verification system, characterized in that, include: A DSP testing system and an FPGA testing system; the DSP testing system includes at least one peripheral interface; the FPGA testing system includes an FPGA motherboard and an FPGA daughterboard; The DSP testing system is used to test the functionality of the DSP chip; at least one of the peripheral interfaces is used to test the corresponding functions in the DSP chip. The FPGA testing system is used to test the functionality of the FPGA chip; the FPGA master board is communicatively connected to the FPGA daughter board and is used to control the FPGA daughter board to test the functionality of the FPGA chip.

2. The system according to claim 1, characterized in that, The DSP testing system also includes a UART module; the system also includes a host computer; The DSP testing system communicates with the host computer through the UART module.

3. The system according to claim 2, characterized in that, The peripheral interfaces also include: a DDR test module, an I2C interface, an SPI interface, and an EMIF interface; The system also includes an EEPROM module, a NOR FLASH module, and a NAND FLASH chip; The DDR test module is used to test the communication function with the DDR chip; the communication function includes communication data integrity, communication read / write speed and communication stability. The I2C interface is connected to the EEPORM module, which is used to implement read and write operations of the EEPORM module and test the I2C bus function of the DSP chip; the I2C bus function includes the correctness of data transmission and protocol compliance. The SPI interface is connected to the NOR FLASH module and is used to test the data integrity during the read and write process of the DSP chip. The EMIF interface is connected to the NAND FLASH chip and is used to perform read and write tests on the NAND FLASH chip.

4. The system according to claim 3, characterized in that, The peripheral interface also includes a clock generation module; The clock generation module is used to provide a reference clock for the DSP test system; The DSP test system is used to synchronize the reference clock to all the peripheral interfaces.

5. The system according to claim 4, characterized in that, The peripheral interfaces also include: SRIO interface, HyperLink interface and SGMII interface; The SRIO interface is used to perform SRIO read / write tests on the DSP chip; The HyperLink interface is used to perform read / write tests and interrupt tests on the DSP chip. The SGMII interface is used to send network packets, perform tests based on the number of errors received, and conduct interruption tests.

6. The system according to claim 1, characterized in that, The FPGA motherboard includes: a host computer communication module; the system also includes a host computer. The FPGA motherboard receives test commands from the host computer through the host computer communication module and returns the test results to the host computer through the host computer communication module.

7. The system according to claim 6, characterized in that, The FPGA motherboard includes: a daughterboard power supply module, a current sampling module, a relay control module, and an FPGA control core module; the daughterboard power supply module includes multiple power supply modules. The subboard power supply module is used to provide multiple power supplies to the FPGA subboard, control the power-on sequence of the FPGA subboard, and / or collect the power supply current through the current sampling module to monitor the power consumption of the FPGA subboard. The current sampling module is used to adjust the amplification factor according to the magnitude of the measured current; The relay control module is used to control the output voltage and on / off state of the power supply module; The FPGA control core module is used for the logical control of the test process and to store the test program, and loads the test program into the FPGA chip under test on the FPGA daughterboard.

8. The system according to claim 7, characterized in that, The FPGA master also includes a clock generation module; The clock generation module is used to generate a global system clock, providing a reference clock for the FPGA chip under test and the FPGA daughterboard.

9. The system according to claim 8, characterized in that, The FPGA motherboard and the FPGA daughterboard communicate via a high-speed connector.

10. The system according to claim 9, characterized in that, The FPGA daughterboard includes a DDR memory module, a download mode selection module, and a power supply module for the FPGA under test. The FPGA chip under test is mounted on the FPGA sub-board; The DDR memory module is used to verify the DDR controller function of the FPGA chip under test; The download mode selection module is used to support multiple FPGA program download methods; The FPGA power module under test is used to receive various power supplies provided by the FPGA motherboard and to power the FPGA chip under test.

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