High-speed triggering device

Abstract

A high-speed trigger device disclosed by the present invention comprises an ARM module and an FPGA module, the FPGA module comprises an encoder signal input interface, a high-speed input interface and a high-speed output interface, the ARM module is in communication connection with an upper computer, the ARM module is in communication connection with the FPGA module, and the ARM module is used for receiving parameter instruction information provided by the upper computer and transmitting the parameter instruction information to the FPGA module. The parameter instruction information comprises operation mode configuration information. According to the high-speed triggering device, the architecture that ARM and FPGA are processed separately is adopted, setting of parameter instruction information and the like are processed by the ARM module, counting of triggering signals, output of control signals of the high-speed output interface and the like are processed by the FPGA module, parallel processing is achieved through the FPGA module, the processing logic can be completely achieved by a hardware circuit of the FPGA module, and low-delay triggering is achieved.

Description

Technical Field

[0001] This invention relates to the field of industrial equipment technology, and in particular to a high-speed triggering device. Background Technology

[0002] In industrial automation, especially in applications requiring high precision and speed, such as dispensing machines and inkjet printers, programmable logic controllers (PLCs) are typically used to process signals from various sensors and execute corresponding operations based on these signals. For applications requiring precise position control, high-speed incremental encoders are widely used to provide position feedback information.

[0003] Existing solutions rely on a PLC receiving pulse signals from a high-speed incremental encoder, performing counting processing via software algorithms, and triggering an output action after reaching a predetermined number of pulses. For example, during dispensing or inkjet printing, the PLC receives pulse signals from a high-speed incremental encoder and begins counting. After counting to N pulses, it triggers an output to control the dispensing valve or inkjet head.

[0004] However, PLCs operate using a cyclic scanning method, requiring the processing of multiple tasks within each scanning cycle. Due to the complexity of PLC tasks and the long scanning cycle, the response speed is relatively slow, which can easily lead to problems such as inaccurate spraying during processes like dispensing or inkjet printing. Therefore, PLCs are not suitable for high-speed applications such as high-speed trigger dispensing or high-speed trigger inkjet printing. Summary of the Invention

[0005] This invention provides a high-speed triggering device to reduce triggering delay.

[0006] This invention provides a high-speed triggering device, including an ARM module and an FPGA module;

[0007] The FPGA module includes an encoder signal input interface, a high-speed input interface, and a high-speed output interface;

[0008] The ARM module is communicatively connected to the host computer and the FPGA module. The ARM module is used to receive parameter instruction information provided by the host computer and transmit the parameter instruction information to the FPGA module.

[0009] The parameter instruction information includes operating mode configuration information;

[0010] When the operating mode configuration information is the first preset operating mode configuration information, the FPGA module outputs a control signal through the high-speed output interface according to the trigger signal received by the high-speed input interface;

[0011] When the operating mode configuration information is the second preset operating mode configuration information, the FPGA module outputs the control signal through the high-speed output interface according to the trigger signal provided by the ARM module;

[0012] When the operating mode configuration information is the third preset operating mode configuration information, the FPGA module outputs the control signal through the high-speed output interface according to the trigger signal received by the encoder signal input interface.

[0013] Optionally, the ARM module includes an RS485 interface;

[0014] The ARM module and the host computer are connected via the RS485 interface;

[0015] The host computer transmits the parameter instruction information to the ARM module via the Modbus protocol.

[0016] Optionally, the FPGA module further includes a parallel bus processing module, which includes a FIFO buffer;

[0017] The parallel bus processing module is connected to the ARM module via a parallel bus.

[0018] Optionally, the FPGA module further includes an encoder counting and alarm module, which includes a signal conversion unit, a filtering unit, and an encoder counting and alarm unit.

[0019] The filtering unit is connected to the encoder through the encoder signal input interface. The encoder is used to output the trigger signal, and the trigger signal output by the encoder is a differential signal. The filtering unit is used to filter the differential signal.

[0020] The signal conversion unit is electrically connected to the filtering unit and is used to convert the filtered differential signal into a single-ended signal.

[0021] The encoder counting and alarm unit is electrically connected to the signal conversion unit and is used to output the control signal through the high-speed output interface according to the single-ended signal.

[0022] Optionally, the signal conversion unit is also used to provide an alarm signal to the encoder counting and alarm unit;

[0023] The encoder counting and alarm unit is also used to output the control signal through the high-speed output interface according to the alarm signal.

[0024] Optionally, the encoder counting and alarm unit is also used to provide conversion parameter information to the signal conversion unit;

[0025] The signal conversion unit outputs the single-ended signal corresponding to the level standard according to the conversion parameter information;

[0026] The level standard includes at least one of the TTL level standard and the RS422 level standard.

[0027] Optionally, the FPGA module further includes a high-speed I / O receiving module and a data storage module, wherein the high-speed I / O receiving module includes a first isolation optocoupler unit;

[0028] The first isolation optocoupler unit is electrically connected to the high-speed input interface, and the data storage module is electrically connected to the first isolation optocoupler unit;

[0029] The data storage module is used to output the control signal through the high-speed output interface based on the trigger signal received by the high-speed input interface.

[0030] Optionally, the FPGA module further includes a high-speed I / O output module and a data storage module, wherein the high-speed I / O output module includes a second isolation optocoupler unit;

[0031] The data storage module is electrically connected to the second isolation optocoupler unit, and the second isolation optocoupler unit is electrically connected to the high-speed output interface.

[0032] The data storage module is used to output the control signal through the high-speed output interface.

[0033] Optionally, the FPGA module further includes a clock management module, which includes a phase-locked loop.

[0034] Optionally, the parameter instruction information may also include at least one of the following: encoder type information, encoder filter coefficient configuration information, high-speed input interface function and logic level selection configuration information, filter coefficient configuration information, trigger output pulse comparison value configuration information, trigger output pulse width information, high-speed output interface function setting information, start trigger pulse count, and stop trigger pulse count.

[0035] The high-speed triggering device of this invention adopts an ARM+FPGA separate processing architecture. The setting of parameter instruction information is handled by the ARM module, while the counting of trigger signals and the output control signals of the high-speed output interface are handled by the FPGA module. Parallel processing is achieved through the FPGA module, allowing counting to begin immediately upon receiving the trigger signal. Once the count reaches the preset trigger output pulse comparison value N, the control signal is output immediately. The processing logic can be entirely implemented by the hardware circuitry of the FPGA module, resulting in extremely fast response speeds (nanosecond level). This avoids the delay problems caused by the scanning cycle in traditional PLCs, thus achieving low-latency triggering. It is suitable for applications with extremely time-sensitive requirements, such as high-speed dispensing, inkjet printing, and laser marking. Furthermore, the high-speed triggering device provides three independent triggering operation modes, each of which can be independently configured with parameter instruction information through the ARM module. Users can freely switch between modes according to actual working conditions, offering high flexibility and configurability.

[0036] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 This is a schematic diagram of the structure of a high-speed triggering device provided in an embodiment of the present invention;

[0039] Figure 2 This is a schematic diagram of the structure of an FPGA module provided in an embodiment of the present invention;

[0040] Figures 3-5 This is a schematic diagram of the structure of an ARM module provided in an embodiment of the present invention;

[0041] Figure 6 This is a schematic diagram of the structure of a bus processing module provided in an embodiment of the present invention;

[0042] Figures 7-11 This is a schematic diagram of the structure of an encoder counting and alarm module provided in an embodiment of the present invention;

[0043] Figures 12-18 This is a schematic diagram of the structure of a high-speed I / O receiving module provided in an embodiment of the present invention;

[0044] Figures 19-25 This is a schematic diagram of a high-speed I / O output module provided in an embodiment of the present invention. Detailed Implementation

[0045] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0046] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0047] Figure 1 This is a schematic diagram of a high-speed triggering device provided in an embodiment of the present invention, as shown below. Figure 1 As shown, the high-speed triggering device provided in this embodiment of the invention includes an ARM module 10 and an FPGA module 20. The FPGA module 20 includes an encoder signal input interface 31, a high-speed input interface 32, and a high-speed output interface 33. The ARM module 10 is communicatively connected to a host computer 40 and to the FPGA module 20. The ARM module 10 receives parameter instruction information provided by the host computer 40 and transmits the parameter instruction information to the FPGA module 20. The parameter instruction information includes operating mode configuration information. When the operating mode configuration information is a first preset operating mode configuration information, the FPGA module 20 outputs a control signal through the high-speed output interface 33 according to the trigger signal received by the high-speed input interface 32. When the operating mode configuration information is a second preset operating mode configuration information, the FPGA module 20 outputs a control signal through the high-speed output interface 33 according to the trigger signal provided by the ARM module 10. When the operating mode configuration information is a third preset operating mode configuration information, the FPGA module 20 outputs a control signal through the high-speed output interface 33 according to the trigger signal received by the encoder signal input interface 31.

[0048] Specifically, such as Figure 1 As shown, the ARM (Advanced RISC Machine) module 10 is a communication processing chip based on a Reduced Instruction Set Computing (RISC) architecture.

[0049] FPGA (Field-Programmable Gate Array) module 20 is an integrated circuit that can be programmed by the user to implement specific logic functions. FPGA module 20 can respond to external input trigger signals in real time and output control signals quickly according to preset logic. Compared with traditional microprocessors or PLCs, FPGA module 20 has parallel processing capabilities and extremely low latency.

[0050] The encoder signal input interface 31 of the FPGA module 20 is used to connect to an external encoder 50 to receive trigger signals (e.g., position feedback signals) from the encoder 50.

[0051] The high-speed input interface 32 of the FPGA module 20 is used to receive trigger signals provided by external devices, wherein the trigger signals may include sensor signals, start / trigger stop commands, etc.

[0052] The high-speed output interface 33 of the FPGA module 20 is used to output control signals to the actuator 60 to control the actuator 60 to perform corresponding actions. The actuator 60 may include industrial equipment such as a dispensing valve 61 and an inkjet printhead 62, but is not limited to these.

[0053] The number of high-speed input interfaces 32 and high-speed output interfaces 33 can be multiple (e.g., 5 high-speed input interfaces 32 and 5 high-speed output interfaces 33) to simultaneously control multiple actuators 60 (e.g., control 5 actuators 60) to perform corresponding actions. The number of high-speed input interfaces 32 and high-speed output interfaces 33 can be the same, but is not limited to this.

[0054] In this embodiment, the ARM module 10 receives parameter instruction information provided by the host computer 40 and forwards the parameter instruction information to the FPGA module 20 for execution.

[0055] The host computer 40 can be a computer system or smart terminal that can provide an operating interface to the user and interact with the ARM module 10 through various communication protocols.

[0056] The parameter command information includes the operation mode configuration information, which is used to control the trigger operation mode of the FPGA module 20. Users can input parameter command information through the host computer 40 to modify the trigger operation mode of the FPGA module 20.

[0057] Specifically, when the FPGA module 20 receives the first preset operating mode configuration information (e.g., the first preset operating mode configuration information is 0), the FPGA module 20 listens to changes in the trigger signal received by the high-speed input interface 32 and responds accordingly. For example, when a specific trigger signal is detected through the high-speed input interface 32 (e.g., a trigger signal output by a sensor when it detects an object reaching a certain position), the FPGA immediately sends a control signal to the actuator 60 through the high-speed output interface 33 (e.g., sending a control signal to the dispensing valve 61 or the inkjet printhead 62 to start dispensing or inkjet printing). This trigger-based operating mode is suitable for situations requiring a rapid response to external events, such as immediately starting dispensing or inkjet printing after a sensor detects an object reaching a certain position. This trigger-based operating mode has strong real-time performance and low latency, making it suitable for high-speed response requirements. Furthermore, the signal source input to the high-speed input interface 32 can be independent of other signal sources, ensuring high reliability.

[0058] When the FPGA module 20 receives the second preset operating mode configuration information (e.g., the second preset operating mode configuration information is 1), the ARM module 10 sends trigger information to the FPGA module 20 to inform the FPGA module 20 when it should output a control signal. The FPGA module 20 receives the trigger information sent by the ARM module 10 and determines when to output a control signal through the high-speed output interface 33 based on the trigger information. This trigger operating mode is suitable for trigger operations that require unified scheduling by the host computer 40 or complex judgment, such as when a PLC or PC sends a dispensing start signal through the ARM module 10; or when multiple devices work together, all actions need to be triggered and executed in a predetermined order. This trigger operating mode is flexible and controllable, suitable for multi-task collaboration, can support remote control and centralized scheduling, and can be combined with other system logic (such as visual recognition results) to determine whether to trigger.

[0059] When the FPGA module 20 receives the third preset operating mode configuration information (e.g., the third preset operating mode configuration information is 2), the FPGA module 20 continuously monitors the trigger signal generated by the encoder 50 through the encoder signal input interface 31. Upon receiving the trigger signal generated by the encoder 50, it can immediately start counting. When the accumulated number of pulses reaches the preset trigger output pulse comparison value N, the FPGA module 20 can immediately output a control signal through the high-speed output interface 33. This trigger operating mode is suitable for motion control systems that require precise control based on position feedback, such as when a conveyor belt moves a certain distance or a moving platform reaches a preset position and then begins dispensing or inkjet printing, achieving high-precision positioning control.

[0060] In this embodiment, the high-speed triggering device adopts an ARM+FPGA separate processing architecture. Parameter instruction settings are handled by the ARM module 10, while the counting of trigger signals and the output of control signals from the high-speed output interface 33 are handled by the FPGA module 20. Parallel processing is achieved through the FPGA module 20, which can start counting immediately upon receiving a trigger signal and output a control signal immediately after the count reaches the preset trigger output pulse comparison value N. The processing logic can be completely implemented by the hardware circuit of the FPGA module 20, resulting in extremely fast response speed (nanosecond level). This avoids the delay problem caused by the scanning cycle in traditional PLCs, thus achieving low-latency triggering, suitable for applications with extremely time-sensitive requirements such as high-speed dispensing, inkjet printing, and laser marking. Simultaneously, the high-speed triggering device provides three independent trigger operation modes, each of which can be independently configured with parameter instruction information through the ARM module 10. Users can freely switch between modes according to actual working conditions, offering high flexibility and configurability.

[0061] Optional, such as Figure 1 As shown, the ARM module 10 includes an RS485 interface 101. The ARM module 10 and the host computer 40 are connected through the RS485 interface 101. The host computer 40 transmits parameter instruction information to the ARM module 10 through the Modbus protocol.

[0062] RS485 is a differential signaling standard used for serial communication, which can support half-duplex asynchronous serial communication.

[0063] In this embodiment, the RS485 interface 101 serves as a physical interface of the ARM module 10, responsible for establishing a communication link with external devices (such as the host computer 40). The RS485 interface 101 may include a pair of differential signal lines (A / B lines) for sending and receiving data. The RS485 interface 101 provides good electrical isolation and anti-interference performance, ensuring the accuracy of data transmission.

[0064] Furthermore, Modbus is an open serial communication protocol that defines the communication rules between the ARM module 10 and the host computer 40, and supports multiple transmission media (such as RS485).

[0065] In this embodiment, the RS485 communication format adopts the standard MODBUS protocol, supporting functions such as reading and writing parameter command information, reading the status of the high-speed trigger device, and sending parameter command information. When the high-speed trigger device is working, the host computer 40 can transmit parameter command information to the ARM module 10, read the status of the high-speed trigger device, and control the FPGA module 20 via the Modbus protocol. The aforementioned parameter command information can be encapsulated into Modbus request frames and sent to the ARM module 10. The ARM module 10 parses these frames and forwards the corresponding parameter command information to the FPGA module 20. The FPGA module 20 can execute the corresponding trigger operation mode according to the received parameter command information.

[0066] The Modbus protocol has a mature error detection mechanism (such as CRC check), which can further enhance the reliability of high-speed triggering devices.

[0067] Figure 2 This is a schematic diagram of the structure of an FPGA module provided in an embodiment of the present invention, as shown below. Figure 1 and Figure 2 As shown, optionally, the FPGA module 20 also includes a parallel bus processing module 201, which includes a FIFO buffer and is connected to the ARM module 10 via a parallel bus 41.

[0068] Specifically, the parallel bus processing module 201 is a dedicated module within the FPGA module 20, responsible for managing data interaction with the ARM module 10. The parallel bus processing module 201 is connected to the ARM module 10 via a parallel bus 41, which can transmit multiple bits of data in a single clock cycle, significantly improving the data transmission rate.

[0069] Meanwhile, the parallel bus processing module 201 can use a FIFO (First-In-First-Out) buffer to optimize data flow control.

[0070] The FIFO buffer is a special type of memory that performs data read and write operations according to the first-in, first-out (FIFO) principle. When the data processing speeds of the ARM module 10 and the FPGA module 20 are inconsistent, the FIFO buffer can temporarily store data to prevent data loss or blockage. The FIFO buffer provides a simple and effective synchronization mechanism, enabling smooth data transfer between devices with different speeds (such as the high-speed FPGA module 20 and the relatively low-speed ARM module 10).

[0071] In this embodiment, the parallel bus processing module 201 can provide a high-bandwidth data channel, support fast data read and write operations, and can also use a FIFO buffer to solve the data rate mismatch problem, ensuring the continuity and reliability of data transmission.

[0072] Figures 3-5 A schematic diagram of the structure of an ARM module provided in an embodiment of the present invention is shown below. Figure 4 and Figure 5 As shown, exemplarily, the ARM module 10 includes a power supply section 102, which connects multiple 0.1μF capacitors (C35-C42, C43-C49) to the VDD_3V3 power line for decoupling and filtering to ensure power stability. Simultaneously, a 3V3 regulator FB1 provides 3.3V to the high-speed trigger device.

[0073] For example, such as Figure 3 As shown, the ARM module 10 also includes a microcontroller section 103, whose pin functions may include, but are not limited to:

[0074] NE1, NOE, and NWE pins: These represent the memory enable, read enable, and write enable signals, respectively, used to control access operations to external memory.

[0075] ADDR0-ADDR10 pins: used to provide 11-bit parallel address lines, which can be connected to the parallel bus processing module 201 for accessing the address bus of external memory.

[0076] DATA0-DATA15 pins: used to provide parallel 16-bit data lines, which can be connected to the parallel bus processing module 201 and support high-speed data exchange with external memory.

[0077] MCLK, CSSPIN, SISPI, SOSPI pins: These are the master clock, chip select, data input, and data output pins used for SPI communication.

[0078] NBL0 and NBL1 pins: enable byte function.

[0079] 485_USART1_TX and 485_USART1_RX pins: Spare serial communication interfaces that can be connected to a host computer. The 485_USART1_TX pin is used to send data, and the 485_USART1_RX pin is used to receive data.

[0080] 485_DRE pin: Used to receive the 485_DRE signal. The 485_DRE signal is used to control the working state of the 485 transceiver, determining whether it is in transmit mode or receive mode.

[0081] UART3_TX and UART3_RX are two UART (Universal Asynchronous Receiver / Transmitter) interfaces used for serial communication. UART3_TX is the transmit data pin, and UART3_RX is the receive data pin. T1 and T3 represent the test points on these two pins, respectively.

[0082] I2C_SDA and I2C_SCL are I2C (Inter-Integrated Circuit) bus interfaces used for simple two-wire communication. I2C_SDA is the data line, and I2C_SCL is the clock line.

[0083] Other functional pins, such as PHO-OSC_IN and PHI-OSC_OUT pins (external crystal oscillator input and output pins, used to provide a stable clock signal for ARM module 10), Vcap_1 and Vcap_2 pins (connected with 2.2μF / 6.3V capacitors (C52 and C53) for stabilizing the internal oscillator), PDR_ON pin (power detection pin, used to detect power status), BOOT0 pin (boot mode selection pin, used to select the boot mode), NRST pin (reset pin), RSTFPGA (external reset signal input), and VDD, VSS, VSSA, VREF+, VBAT, and VDDA (power and reference voltage pins), can be configured according to actual needs, and will not be elaborated here.

[0084] Other components, such as resistors R31 (33Ω±1%), R35 (4.7kΩ±1%), R36 (4.7kΩ±1%), R25-R28 (0Ω±1%), capacitor C43 (1μF), diodes (indicator lights), etc., can be set according to actual needs, and will not be elaborated here.

[0085] Figure 6 This is a schematic diagram of the structure of a bus processing module provided in an embodiment of the present invention, as shown below. Figure 6 As shown, for example, the pin functions of the bus processing module 201 may include, but are not limited to:

[0086] DATA0-DATA15 pins: Connect to the DATA0-DATA15 pins in ARM module 10 via resistors of 33Ω±1% (e.g., R49-R53, R55, R58, R60, R62, R66, R68, R70, R72, R75 and R76).

[0087] ADDR0-ADDR10 pins: Connect to the ADDR0-ADDR10 pins in ARM module 10 via resistors of 33Ω±1% (e.g., R54, R56, R59, R61, R63, R65, R67, R71, R73 and R77).

[0088] Other function pins can be configured according to actual needs, and will not be described in detail here.

[0089] Optionally, the parallel bus communication of the 16-bit data lines and 11-bit address lines of the ARM module 10 can use the FSMC (Flexible Static Memory Controller) bus interface of the STM32, and the FSMC bus interface is connected to the bus processing module 201 of the FPGA module 20.

[0090] The FSMC bus interface can handle data widths of up to 16 bits and support up to 26 address lines, which can match the communication needs of ARM module 10 and FPGA module 20.

[0091] Figures 7-11 This is a schematic diagram of the structure of an encoder counting and alarm module provided in an embodiment of the present invention, as shown below. Figures 1-2 , Figures 7-11 As shown, optionally, the FPGA module 20 also includes an encoder counting and alarm module 202. The encoder counting and alarm module 202 includes a signal conversion unit 2021, a filtering unit 2022, and an encoder counting and alarm unit 2023. The filtering unit 2022 is connected to the encoder 50 via the encoder signal input interface 31. The encoder 50 outputs a trigger signal, and the trigger signal output by the encoder 50 is a differential signal. The filtering unit 2022 is used to filter the differential signal. The signal conversion unit 2021 is electrically connected to the filtering unit 2022 and is used to convert the filtered differential signal into a single-ended signal. The encoder counting and alarm unit 2023 is electrically connected to the signal conversion unit 2021 and is used to output a control signal via the high-speed output interface 33 based on the single-ended signal.

[0092] Specifically, encoder 50 can be a high-speed incremental encoder, a sensor used to measure rotational or linear motion by outputting pulse signals to reflect changes in the position of the measured object. The incremental encoder outputs a series of pulse signals (i.e., trigger signals) during rotation or movement, with each pulse representing a fixed unit of angle or displacement. The pulse signals typically contain two orthogonal signals (phase A and phase B) and a reference point signal (phase Z). The phase A and phase B signals are 90° out of phase and can be used to determine direction; the phase Z signal generates one pulse per revolution and can be used to locate the reference point.

[0093] like Figures 1-2 , Figures 7-11 As shown, encoder 50 is connected to FPGA module 20 through encoder signal input interface 31.

[0094] The trigger signal output by encoder 50 is a differential signal. For example... Figure 10 As shown, in the encoder signal input interface 31, the EEA+ pin and the EEA- pin form a differential pair for the A-phase signal. The EEA+ pin transmits the positive signal of the A-phase, and the EEA- pin transmits the negative signal of the A-phase. The EEB+ pin and the EEB- pin form a differential pair for the B-phase signal. The EEB+ pin transmits the positive signal of the B-phase, and the EEB- pin transmits the negative signal of the B-phase.

[0095] The GND pin is the signal ground, used to provide a stable reference level for differential signals. All differential signal pairs can return through this common ground.

[0096] The PE pin is for protective ground, used to connect to protective ground to prevent electrical interference.

[0097] like Figures 1-2 , Figures 7-11 As shown, the filtering unit 2022 is connected to the encoder signal input interface 31 to receive the differential signal and perform filtering to remove high-frequency interference and mechanical jitter in the signal, improve signal stability, and prevent false counting or false triggering.

[0098] For example, such as Figure 8 As shown, the filtering unit 2022 includes a first filtering unit 2022A. In the first filtering unit 2022A, EEA+ and EEA- are a pair of differential signal input ports, which are connected to the EEA+ pin and EEA- pin in the encoder signal input interface 31, respectively, to receive the positive and negative signals of phase A. The positive and negative signals of phase A are filtered by a common-mode inductor L4 to remove common-mode noise.

[0099] Among them, the common-mode inductor L4 can be model ACM2012. Its main function is to suppress common-mode noise, that is, the same noise signal that exists on two signal lines at the same time. It allows the differential signal to pass normally, but has a high impedance to common-mode noise, thus playing a filtering role, but it is not limited to this.

[0100] When an overcurrent occurs in the circuit, fuses F10 and F12 will blow, cutting off the power supply and protecting downstream circuits from damage. The model number of fuses F10 and F12 can be 0603L, but they are not limited to this.

[0101] When a circuit is subjected to electrostatic discharge (ESD) or transient voltage surges, the discharge tube ZD2 can quickly conduct, discharging excessive voltage to ground and protecting sensitive electronic components. The ZD2 model can be PESD2CANFD27L, but is not limited to this.

[0102] Resistors R105 and R108 (33Ω) are used as terminating matching resistors to match the characteristic impedance of transmission lines (typically 50Ω or 100Ω), reduce signal reflection, and improve signal integrity.

[0103] Resistors R107 (120Ω) and R111 (1KΩ) can be used for further filtering and current limiting to prevent excessive current from flowing into subsequent circuits.

[0104] Capacitors C86, C88, and C90 (10pF / 50V) can be used for high-frequency filtering to remove high-frequency noise and ensure signal purity.

[0105] The 24V_P power input provides the DC power required by the circuit.

[0106] Resistor R103 (1KΩ) is a current-limiting resistor to prevent the power supply from being directly short-circuited.

[0107] EA+ and EA- are the filtered and protected differential signal output ports, which can be connected to subsequent receiving circuits (such as signal conversion unit 2021).

[0108] The main function of the first filtering unit 2022A is to filter, protect and match the received differential signals (EEA+ and EEA-), and then output optimized differential signals (EA+ and EA-) to improve the quality and integrity of the differential signals.

[0109] For example, such as Figure 9 As shown, the filtering unit 2022 also includes a second filtering unit 2022B. In the second filtering unit 2022B, EEB+ and EEB- are a pair of differential signal input ports, which are connected to the EEB+ pin and EEB- pin in the encoder signal input interface 31, respectively, to receive the positive and negative signals of phase B. The positive and negative signals of phase B are filtered by a common-mode inductor L5 to remove common-mode noise.

[0110] Among them, the common mode inductor L5 can be model ACM2012. Its main function is to suppress common mode noise, that is, the same noise signal that exists on two signal lines at the same time. It allows the differential signal to pass normally, but has a high impedance to common mode noise, thus playing a filtering role, but it is not limited to this.

[0111] When an overcurrent occurs in the circuit, fuses F11 and F13 will blow, cutting off the power supply and protecting downstream circuits from damage. The model number of fuses F11 and F13 can be 0603L, but it is not limited to this.

[0112] When a circuit is subjected to electrostatic discharge (ESD) or transient voltage surges, the discharge tube ZD3 can quickly conduct, discharging excessive voltage to ground and protecting sensitive electronic components. The ZD3 discharge tube can be of the model PESD2CANFD27L, but is not limited to this.

[0113] Resistors R106 and R110 (33Ω) are used as terminating matching resistors to match the characteristic impedance of transmission lines (typically 50Ω or 100Ω), reducing signal reflection and improving signal integrity.

[0114] Resistors R109 (120Ω) and R112 (1KΩ) can be used for further filtering and current limiting to prevent excessive current from flowing into subsequent circuits.

[0115] Capacitors C87, C89, and C91 (10pF / 50V) can be used for high-frequency filtering to remove high-frequency noise and ensure signal purity.

[0116] The 24V_P power input provides the DC power required by the circuit.

[0117] Resistor R104 (1KΩ) is a current-limiting resistor to prevent the power supply from being directly short-circuited.

[0118] EB+ and EB- are the filtered and protected differential signal output ports, which can be connected to subsequent receiving circuits (such as signal conversion unit 2021).

[0119] The main function of the second filtering unit 2022B is to filter, protect and match the received differential signals (EEB+ and EEB-) and then output optimized differential signals (EB+ and EB-) to improve the quality and integrity of the differential signals.

[0120] like Figures 1-2 , Figures 7-11 As shown, the signal conversion unit 2021 is connected to the filtering unit 2022 to convert the filtered differential signal into a single-ended signal, which is compatible with the internal logic level standard of the FPGA module 20 (such as TTL or RS422) to prevent signal distortion or level incompatibility.

[0121] For example, such as Figure 7 As shown, in the signal conversion unit 2021, VCC_3.3V provides a 3.3V DC power supply and VCC_5V provides a 5V DC power supply for the operation of the signal conversion unit 2021.

[0122] Capacitors C83 (10μF), C84 (0.1μF), and C85 (0.1μF) are used as power supply filter capacitors to remove high-frequency noise and ripple in the power supply and provide a stable power supply voltage.

[0123] The EA+ and EA- pins receive the differential pair of the A-phase signal, where EA+ is the positive signal and EA- is the negative signal.

[0124] The EB+ and EB- pins receive the differential pair of the B-phase signal, where EB+ is the positive signal and EB- is the negative signal.

[0125] The EAO and EBO pins output the processed single-ended signals of phase A and phase B.

[0126] The DI_TTLY, DI_TTL2, and DI_TTL3 pins can receive external TTL level digital input signals for other control or status monitoring. The DI_TTLY, DI_TTL2, and DI_TTL3 pins can be connected to the VCC_3.3V power supply via resistors R91, R94, and R97 (10KΩ), respectively, but are not limited to this connection.

[0127] Other functional pins of the signal conversion unit 2021, such as VL, VCC, GND and EP pins (power and ground pins), can be configured according to actual needs, and will not be described in detail here.

[0128] like Figures 1-2 , Figures 7-11 As shown, the encoder counting and alarm unit 2023 is connected to the signal conversion unit 2021. It receives the converted single-ended signal and uses its internal logic to perform quadrature decoding on the single-ended signal, thereby identifying the rotation direction and speed. When the single-ended signal reaches a specific condition (for example, the accumulated number of pulses reaches a preset trigger output pulse comparison value N), the encoder counting and alarm unit 2023 generates a corresponding control signal. The control signal is transmitted to the external actuator 60 through the high-speed output interface 33 to realize the operation control of the actuator 60.

[0129] For example, such as Figure 7 and Figure 11 As shown, in the encoder counting and alarm unit 2023, the EAO pin and EBO pin are respectively connected to the EAO pin and EBO pin of the signal conversion unit 2021 to receive the single-ended signal converted by the signal conversion unit 2021.

[0130] Other functional pins of the encoder counting and alarm unit 2023, such as the CSSPIN pin (clock synchronization signal input, used to synchronize with the external clock signal), the MCLK pin and the SPISO pin (main clock signal input and SPI serial data output, respectively, used to provide the clock source and transmit data), and the SISPI pin (a specific signal for SPI communication, used to communicate with other devices via SPI), can be configured according to actual needs, and will not be elaborated here.

[0131] Optional, such as Figures 7-11 As shown, the signal conversion unit 2021 is also used to provide an alarm signal to the encoder counting and alarm unit 2023, and the encoder counting and alarm unit 2023 is also used to output a control signal through the high-speed output interface 33 according to the alarm signal.

[0132] The signal conversion unit 2021 not only converts differential signals into single-ended signals, but can also monitor the encoder status in certain situations. For example, it can detect abnormal conditions such as encoder short circuits and open circuits.

[0133] When an anomaly is detected, the signal conversion unit 2021 transmits an alarm signal to the encoder counting and alarm unit 2023. The alarm signal can be a simple high-low level change or a more complex digital signal. This embodiment of the invention does not specifically limit this.

[0134] After receiving an alarm signal, the encoder counting and alarm unit 2023 can decide how to respond according to preset logic rules, including but not limited to stopping the current operation, recording error information, or adjusting operating parameters to try to restore normal operation.

[0135] In some designs, the encoder counting and alarm unit 2023 may include dedicated hardware or software logic to analyze the nature of alarm signals in order to make a more accurate response.

[0136] For example, depending on the nature and severity of the alarm signal, the encoder counting and alarm unit 2023 can send control signals to the external actuator 60 through the high-speed output interface 33. These control signals can be used to trigger an emergency stop, activate the backup system, notify the user to check, etc.

[0137] The alarm signal processing logic can be fully implemented by the hardware circuit of the FPGA module 20, which has a fast response speed and avoids the delay problem caused by the scanning cycle of traditional PLC, thereby achieving low-latency triggering. This ensures that control signals can be quickly transmitted in case of emergency, reducing potential risks and losses.

[0138] For example, such as Figure 7 and Figure 11 As shown, in the signal conversion unit 2021, the AFLT# pin and the BFLT# pin provide alarm signals for phase A and phase B. When an abnormal signal is detected, the AFLT# pin and the BFLT# pin will output an alarm signal.

[0139] Optionally, when the AFLT# and BFLT# pins output alarm signals, the EAO signal (single-ended signal) and EBO signal (single-ended signal) can be pulled high to 5V through resistors R100 (33Ω) and R102 (33Ω), and the fault status can be indicated by indicator lights GD6 / GD7.

[0140] In the encoder counting and alarm unit 2023, the AFLT# pin and the BFLT# pin are respectively connected to the AFLT# pin and the BFLT# pin of the signal conversion unit 2021 to receive the alarm signal output by the signal conversion unit 2021.

[0141] Optional, such as Figure 7 and Figure 11 As shown, the encoder counting and alarm unit 2023 is also used to provide conversion parameter information to the signal conversion unit 2021. The signal conversion unit 2021 outputs a single-ended signal with a corresponding level standard according to the conversion parameter information. The level standard includes at least one of TTL level standard and RS422 level standard.

[0142] The signal conversion unit 2021 receives conversion parameter information from the encoder counting and alarm unit 2023, and dynamically adjusts the level standard (such as TTL or RS422) of the output single-ended signal according to the conversion parameter information, thus having greater flexibility and compatibility.

[0143] TTL level standard is a digital circuit logic level standard with a high level voltage range of 2.0V to 5.0V and a low level voltage range of 0.0V to 0.8V.

[0144] The RS422 level standard is a differential signal transmission standard that determines the logic state by comparing the voltage difference between two lines. Its high-level voltage range is +2V to +6V, and its low-level voltage range is -2V to -6V, providing strong anti-interference capability.

[0145] For example, such as Figure 7 and Figure 11As shown, the signal conversion unit 2021 also includes SPI_PARB, HITH_CSB, SNGL_CLK, TTL_SDI, D3FLTB_SDO, and D2FLTB_IRQB signal pins. Corresponding SPI_PARB, HITH_CSB, SNGL_CLK, TTL_SDI, D3FLTB_SDO, and D2FLTB_IRQB signal pins can be configured in the encoder counting and alarm unit 2023. Furthermore, the aforementioned signal pins in the encoder counting and alarm unit 2023 are connected to the corresponding signal pins in the signal conversion unit 2021. By providing the above pin signals to the signal conversion unit 2021, the encoder counting and alarm unit 2023 can configure the output level standard of the signal conversion unit 2021 to be either a TTL level standard or an RS422 level standard, etc.

[0146] Among them, the SPI_PARB pin can provide the SPI communication interface, the HITH_CSB pin can be used to select the high threshold mode, the SNGL_CLK pin can be used to select the single pulse clock mode, the TTL_SDI pin can be used for serial data input of TTL level standard, the D3FLTB_SDO pin can be used to indicate a specific fault state, and the D2FLTB_IRQB pin can be used to trigger interrupt handling, etc., but are not limited to these.

[0147] Optional, such as Figure 7 As shown, in the signal conversion unit 2021, the SPI_PARB, HITH_CSB, SNGL_CLK, TTL_SDI, D3FLTB_SDO and D2FLTB_IRQB signal pins can be connected to the chip of the signal conversion unit 2021 through resistors R90, R92, R93, R95, R96 and R98 (33Ω) respectively, but are not limited to this.

[0148] Optional, such as Figure 7 As shown, the SNGL_CLK signal pin can be grounded (GND) through resistor R88, and the TTL_SDI, D3FLTB_SDO and D2FLTB_IRQB signal pins can be connected to the power supply VCC_3.3V through resistors R89, R99 and R101 (10KΩ) respectively, but are not limited to this.

[0149] Figures 12-18 This is a schematic diagram of the structure of a high-speed I / O receiving module provided in an embodiment of the present invention, as shown below. Figures 1-2 , Figures 12-18As shown, optionally, the FPGA module 20 further includes a high-speed I / O receiving module 203 and a data storage module 204. The high-speed I / O receiving module 203 includes a first isolation optocoupler unit 2031, which is electrically connected to the high-speed input interface 32. The data storage module 204 is electrically connected to the first isolation optocoupler unit 2031. The data storage module 204 is used to output control signals through the high-speed output interface 33 according to the trigger signals received by the high-speed input interface 32.

[0150] The first isolation optocoupler unit 2031 is used for electrical isolation to protect the high-speed triggering device from voltage spikes, noise interference, etc., and to ensure stability and reliability.

[0151] In this embodiment, an external device or sensor sends a high-speed trigger signal through the high-speed input interface 32.

[0152] For example, such as Figure 12 As shown, in the high-speed input interface 32, the EXT_IO1, EXT_IO2, EXT_IO3, EXT_IO4 and EXT_IO5 pins can be used to connect external devices or sensors to receive trigger signals.

[0153] The IO_24V pin provides a 24-volt DC power supply.

[0154] The PE pin is for protective ground, used to connect to protective ground to prevent electrical interference.

[0155] Furthermore, the first isolation optocoupler unit 2031 is electrically connected to the high-speed input interface 32 to directly process high-speed trigger signals from external devices or sensors. The trigger signals received by the high-speed input interface 32 are transmitted optically through the first isolation optocoupler unit 2031, avoiding direct electrical connection and achieving electrical isolation, thereby ensuring the safety and stability of trigger signal transmission.

[0156] For example, such as Figure 13 As shown, the first isolation optocoupler unit 2031 includes a first isolation optocoupler unit 2031A. The first isolation optocoupler unit 2031A is connected to the EXT_IO1 pin of the high-speed input interface 32 and is used to convert the trigger signal received by the EXT_IO1 pin of the high-speed input interface 32 into a level suitable for use by the internal logic circuit, and output it through the IO_IN1 pin.

[0157] In the first isolation optocoupler unit 2031A, the IO_24V terminal provides a 24V DC power supply.

[0158] The VCC_3.3V terminal provides a 3.3V DC power supply.

[0159] GND is the ground wire, serving as a common reference point.

[0160] Diode D16 protects the circuit from reverse voltage. When the voltage on EXT_IO1 is lower than ground, diode D16 will conduct, clamping the negative voltage to near ground level to prevent damage to subsequent circuitry.

[0161] Resistor R114 (4.3KΩ) limits the current flowing into the circuit to prevent excessive current from damaging circuit components.

[0162] A capacitor C95 (10pF, 50V) filters out high-frequency noise and ensures the stability of the input signal.

[0163] Optocoupler U11 provides electrical isolation to prevent interference at the input terminal from affecting subsequent circuits. The optocoupler consists of a light-emitting diode (LED) and a phototransistor. The LED emits light when it receives current, and the phototransistor conducts after detecting the light.

[0164] The working principle of the first isolation optocoupler unit 2031A can be summarized as follows: When there is a high-level signal on EXT_IO1, current flows through resistor R114 and diode D16 to the light-emitting diode of optocoupler U11, causing the light-emitting diode to emit light. The light emitted by the light-emitting diode is detected by the phototransistor inside optocoupler U11, causing the phototransistor to conduct, thereby generating a low-level signal at the output of optocoupler U11.

[0165] When the phototransistor of optocoupler U11 is turned off, the output terminal of optocoupler U11 is pulled to a high level (close to VCC_3.3V) through resistor R116 (4.7KΩ) to ensure the stability and reliability of the output signal.

[0166] Resistor R118 (33Ω) limits the charging current flowing through capacitor C95 to prevent excessive current surges when the capacitor is charged instantaneously.

[0167] The IO_IN1 terminal outputs the processed trigger signal to subsequent circuits. Due to the isolation and level conversion of the optocoupler U11, the signal output by the IO_IN1 terminal has good anti-interference ability and stable level.

[0168] Capacitor C94 (10pF, 50V) filters out high-frequency noise in the trigger signal received by the EXT_IO1 pin. Resistor R120 (430Ω) limits the current flowing into optocoupler U11. When an external input signal enters optocoupler U11 through resistor R120, capacitor C94 effectively absorbs and bypasses high-frequency components, ensuring that only relatively pure low-frequency or DC signals can drive the LEDs inside optocoupler U11.

[0169] The first isolation optocoupler unit 2031A electrically isolates, filters, and levels the external input signal (EXT_IO1), ultimately outputting a signal (IO_IN1) suitable for internal logic circuits. Electrical isolation is achieved through the use of optocoupler U11, effectively preventing input interference from affecting subsequent circuits. Simultaneously, a reasonable configuration of resistors and capacitors ensures signal stability and reliability.

[0170] like Figures 14-17 As shown, the first isolation optical coupler unit 2031 also includes a first isolation optical coupler unit 2031B, a first isolation optical coupler unit 2031C, a first isolation optical coupler unit 2031D, and a first isolation optical coupler unit 2031E. The first isolation optocoupler unit 2031B is connected to the EXT_IO2 pin of the high-speed input interface 32, and is used to convert the trigger signal received by the EXT_IO2 pin of the high-speed input interface 32 into a level suitable for use by the internal logic circuit, and output it through the IO_IN2 pin; the first isolation optocoupler unit 2031C is connected to the EXT_IO3 pin of the high-speed input interface 32, and is used to convert the trigger signal received by the EXT_IO3 pin of the high-speed input interface 32 into a level suitable for use by the internal logic circuit, and output it through the IO_IN3 pin; the first isolation optocoupler unit 2031D is connected to the EXT_IO4 pin of the high-speed input interface 32, and is used to convert the trigger signal received by the EXT_IO4 pin of the high-speed input interface 32 into a level suitable for use by the internal logic circuit, and output it through the IO_IN4 pin; the first isolation optocoupler unit 2031E is connected to the EXT_IO5 pin of the high-speed input interface 32, and is used to convert the trigger signal received by the EXT_IO5 pin of the high-speed input interface 32 into a level suitable for use by the internal logic circuit, and output it through the IO_IN5 pin.

[0171] The functions and working principles of the resistors R113, R121, R123, R129, R115, R122, R124, R130, R117, R125, R126, and R131, capacitors C92, C96, C98, C100, C93, C97, C99, and C101, diodes D15, D17, D18, and D19, and optocouplers U10, U12, U13, and U14 in the first isolation optocoupler unit 2031B, the first isolation optocoupler unit 2031C, the first isolation optocoupler unit 2031D, and the first isolation optocoupler unit 2031E, can be found in the description of the first isolation optocoupler unit 2031A above, and will not be repeated here.

[0172] Furthermore, the data storage module 204 is electrically connected to the first isolation optocoupler unit 2031, receives the trigger signal processed by the first isolation optocoupler unit 2031, and processes the trigger signal using its internal logic. When the trigger signal reaches a specific condition (for example, the accumulated number of pulses reaches the preset trigger output pulse comparison value N), the data storage module 204 generates a corresponding control signal. The control signal is transmitted to the external actuator 60 through the high-speed output interface 33 to realize the operation control of the actuator 60.

[0173] For example, such as Figures 13-18 As shown, in the data storage module 204, the IO_IN1, IO_IN2, IO_IN3, IO_IN4, and IO_IN5 pins are respectively connected to the IO_IN1 pin of the first isolation optocoupler unit 2031A, the IO_IN2 pin of the first isolation optocoupler unit 2031B, the IO_IN3 pin of the first isolation optocoupler unit 2031C, the IO_IN4 pin of the first isolation optocoupler unit 2031D, and the IO_IN5 pin of the first isolation optocoupler unit 2031E, and are used to receive external trigger signals. The IO_IN1, IO_IN2, IO_IN3, IO_IN4, and IO_IN5 pins can be connected to different logic units or registers inside the data storage module 204.

[0174] OUT1_1, OUT2_2, OUT3_3, OUT4_4 and OUT5_5 are output pins that can be connected to different actuators 60 to send control signals to the external actuators 60. OUT1_1, OUT2_2, OUT3_3, OUT4_4 and OUT5_5 can be connected to different logic units or registers inside the data storage module 204.

[0175] The VCC_3.3V pin is connected to a 3.3-volt DC power supply.

[0176] Figures 19-25 This is a schematic diagram of the structure of a high-speed I / O output module provided in an embodiment of the present invention, as shown below. Figures 1-2 , Figures 19-25 As shown, the FPGA module 20 also includes a high-speed I / O output module 205 and a data storage module 204. The high-speed I / O output module 205 includes a second isolation optocoupler unit 2051. The data storage module 204 is electrically connected to the second isolation optocoupler unit 2051, and the second isolation optocoupler unit 2051 is electrically connected to the high-speed output interface 33. The data storage module 204 is used to output control signals through the high-speed output interface 33.

[0177] The second isolation optocoupler unit 2051 is used to achieve electrical isolation. It converts the control signal from the data storage module 204 into an optical signal through the light-emitting diode and phototransistor of the internal optocoupler, and then converts it back into an electrical signal for output to the high-speed output interface 33.

[0178] For example, such as Figures 18-25 As shown, the second isolation optical coupler unit 2051 includes a second A isolation optical coupler unit 2051A, a second B isolation optical coupler unit 2051B, a second C isolation optical coupler unit 2051C, a second D isolation optical coupler unit 2051D, and a second E isolation optical coupler unit 2051E.

[0179] The second isolation optocoupler unit 2051A is connected to the OUT1_1 pin of the data storage module 204. It is used to convert the control signal output from the OUT1_1 pin of the data storage module 204 into a high-voltage, high-current control signal that can drive the external actuator 60 (such as the dispensing valve 61, inkjet printhead 62, etc.), and output the control signal through the OUT1_1 pin.

[0180] The second isolation optocoupler unit 2051B is connected to the OUT2_2 pin of the data storage module 204. It is used to convert the control signal output from the OUT2_2 pin of the data storage module 204 into a high-voltage, high-current control signal that can drive the external actuator 60 (such as the dispensing valve 61, inkjet printhead 62, etc.), and output the control signal through the OUT2_2 pin.

[0181] The second isolation optocoupler unit 2051C is connected to the OUT3_3 pin of the data storage module 204. It is used to convert the control signal output from the OUT3_3 pin of the data storage module 204 into a high-voltage, high-current control signal that can drive the external actuator 60 (such as the dispensing valve 61, inkjet printhead 62, etc.), and output the control signal through the OUT3_3 pin.

[0182] The second isolation optocoupler unit 2051D is connected to the OUT4_4 pin of the data storage module 204. It is used to convert the control signal output from the OUT4_4 pin of the data storage module 204 into a high-voltage, high-current control signal that can drive the external actuator 60 (such as the dispensing valve 61, inkjet printhead 62, etc.), and output the control signal through the OUT4_4 pin.

[0183] The second isolation optocoupler unit 2051E is connected to the OUT5_5 pin of the data storage module 204. It is used to convert the control signal output from the OUT5_5 pin of the data storage module 204 into a high-voltage, high-current control signal that can drive the external actuator 60 (such as the dispensing valve 61, inkjet printhead 62, etc.), and output the control signal through the OUT5_5 pin.

[0184] Among them, such as Figure 19 As shown, in the second isolation optocoupler unit 2051A, the OUT1_1 pin is connected to the OUT1_1 pin of the data storage module 204.

[0185] Resistor R135 (330Ω) limits the current flowing into the LED inside optocoupler U15, protecting the LED from overcurrent damage.

[0186] Optocoupler U15 is used to achieve electrical isolation and signal transmission. When the signal input to OUT1_1 is high, the current flows through resistor R135 to the light-emitting diode of optocoupler U15, causing the light-emitting diode to light up. The phototransistor of optocoupler U15 detects the light and turns on, thereby generating a corresponding electrical signal on the output side.

[0187] +24V is the operating power supply for the circuit, providing energy for the subsequent drive circuit.

[0188] IO_24V indicates an externally supplied DC power supply with a voltage of 24V.

[0189] Capacitor C102 (10μF, 50V) is used to filter out high-frequency noise in the power supply and ensure its stability.

[0190] Diode D20 is used to prevent reverse voltage from damaging the circuit.

[0191] Resistor R137 (10KΩ) is used to ensure that transistor Q1 is in the off state when there is no input signal.

[0192] Transistor Q1 is used as a switch. When the phototransistor of optocoupler U15 is turned on, current flows through resistor R137 to the base of transistor Q1, turning on transistor Q1 and thus pulling OUT1_1- low to ground potential.

[0193] Resistor R139 (10KΩ) and capacitor C104 (11μF, 50V) form an RC filter circuit to filter out high-frequency noise on the base of transistor Q1 and ensure the stable operation of transistor Q1.

[0194] Resistor R133 (100KΩ) limits the current through diode D20 and transistor Q1 to prevent excessive current from damaging diode D20 and transistor Q1.

[0195] OUT1_1- is the output signal port. When transistor Q1 is turned on, OUT1_1- is pulled low to ground potential and can be used to drive external actuator 60.

[0196] Fuse F14 is used to protect the circuit from damage caused by overcurrent.

[0197] The working principle of the second-level isolation optocoupler unit 2051A can be summarized as follows: When the OUT1_1 input signal is high, current flows through resistor R135 to the LED of optocoupler U15, causing the LED to emit light. The phototransistor of optocoupler U15 detects the light and conducts, while current flows through resistor R137 to the base of transistor Q1, causing transistor Q1 to conduct. This pulls OUT1_1- low to ground potential, which can then be used to drive the external actuator 60. When the OUT1_1 input signal is low, the LED of optocoupler U15 does not emit light, the phototransistor does not conduct, and transistor Q1 does not conduct, keeping OUT1_1- at a high level.

[0198] The second-level isolation optocoupler unit 2051A uses an optocoupler to electrically isolate, filter, and level-convert the input signal, improving anti-interference capability and safety. Meanwhile, a reasonable configuration of resistors and capacitors ensures the stability and reliability of the circuit.

[0199] like Figures 20-25 As shown, the resistors R136, R143, R144, R150, R138, R145, R146, R151, R140, R147, R148, R152, R134, R141, R142, and R149, and the capacitor C10 in the second isolation optocoupler unit 2051B, the second isolation optocoupler unit 2051C, the second isolation optocoupler unit 2051D, and the second isolation optocoupler unit 2051E are shown. 3. The functions and working principles of devices such as C106, C107, C110, C105, C108, C109, C111, optocouplers U16, U17, U18, U19, transistors Q2, Q3, Q4, Q5, diodes D21, D22, D23, D24, and fuses F15, F16, F17, F18 can be referred to the description of the second isolation optocoupler unit 2051A above, and will not be repeated here.

[0200] Optional, such as Figure 23 As shown, a transient voltage suppressor diode D25 is connected in series between the +24V terminal and the IO_24V terminal to absorb transient voltage spikes in the circuit and protect the circuit from overvoltage damage.

[0201] Optional, such as Figure 24 As shown, capacitors C113 (1nF) and C114 (1nF) are connected between the IO_24V terminal and the signal ground IO_GND to filter out high-frequency noise in the power supply and improve the stability of the power supply.

[0202] Optional, such as Figure 24 As shown, a protective ground PE is connected between the IO_24V terminal and the ground terminal IO_GND to ensure the safety of the circuit.

[0203] Furthermore, such as Figures 19-25 As shown, the second isolation optocoupler unit 2051 is electrically connected to the high-speed output interface 33 to output control signals to the external actuator 60 through the high-speed output interface 33.

[0204] For example, such as Figures 19-25 As shown, in the high-speed output interface 33, the OUT1_1-, OUT2_2-, OUT3_3-, OUT4_4- and OUT5_5- pins are respectively connected to the OUT1_1- pin of the second isolation optocoupler unit 2051A, the OUT2_2- pin of the second isolation optocoupler unit 2051B, the OUT3_3- pin of the second isolation optocoupler unit 2051C, the OUT4_4- pin of the second isolation optocoupler unit 2051D, and the OUT5_5- pin of the second isolation optocoupler unit 2051E.

[0205] In this embodiment, the OUT1_1-, OUT2_2-, OUT3_3-, OUT4_4-, and OUT5_5- pins of the high-speed output interface 33 each correspond to an independent channel to control different external actuators 60. This embodiment is only used as an example to illustrate the support for 5 high-speed IO input channels and 5 high-speed IO output channels, but it is not limited to this.

[0206] IO_GND is the signal ground, used to provide a stable reference potential.

[0207] IO_24V is an externally supplied 24V DC power supply.

[0208] PE serves as protective ground, ensuring the safety of the circuit.

[0209] Optional, such as Figure 2 As shown, the FPGA module 20 also includes a clock management module 206, which includes a phase-locked loop.

[0210] The clock management module 206 provides the clock signals required by the high-speed triggering device, which may include a master clock, a frequency divider clock, a timer, etc., to ensure that each module of the high-speed triggering device works in a predetermined time sequence and frequency, and to maintain the normal operation and coordination of the high-speed triggering device.

[0211] The clock management module 206 includes a phase-locked loop (PLL). The PLL achieves locking by comparing the phase difference between the input signal and the output signal of an adjustable internal oscillator, and adjusting the frequency of the internal oscillator to keep the phase difference constant. The PLL can multiply or divide the input clock to generate clock signals of different frequencies as needed.

[0212] Among them, the clock management module 206 can generate a higher frequency clock signal by using a phase-locked loop, which supports a higher data transmission rate and is conducive to realizing high-speed data communication.

[0213] Optional, such as Figure 2 As shown, the parallel bus processing module 201, encoder counting and alarm module 202, high-speed IO receiving module 203, and high-speed IO output module 205 are all connected to the data access module 204. The data access module 204 can also be used for data storage and retrieval operations, including storing received data into memory or storage devices, and retrieving data from these storage media for use by other modules. As a data relay station, the data access module 204 ensures efficient data transmission and sharing among modules within the system.

[0214] Optionally, the parameter instruction information may also include at least one of the following: encoder type information, encoder filter coefficient configuration information, high-speed input interface function and logic level selection configuration information, filter coefficient configuration information, trigger output pulse comparison value configuration information, trigger output pulse width information, high-speed output interface function setting information, start trigger pulse count, and stop trigger pulse count.

[0215] The encoder type information indicates the type of encoder used (e.g., incremental encoder, absolute encoder, quadrature encoder, etc.). Different types of encoders output signals in different ways and have different decoding logics. The high-speed triggering device can select the appropriate decoding algorithm and processing method based on this information.

[0216] The encoder filter coefficient configuration information is used to set parameters for filtering the encoder signal, which may include the filter order, cutoff frequency, etc. Configuring the encoder filter coefficient configuration information helps to remove noise or interference in the encoder signal and improve position detection accuracy.

[0217] The high-speed input interface function and logic level selection configuration information specifies the function of each high-speed input interface (such as direction signal, clock input, reset signal, etc.) and can set the voltage standard of the input signal (such as TTL, CMOS, LVDS, etc.) to match external sensors or devices, improve the compatibility and flexibility of the high-speed trigger device, and enable it to adapt to different types of input devices and signal standards.

[0218] The filter coefficient configuration information is used to set the digital filtering parameters of the input signal, such as time constant, sampling rate, and filter window size, to further enhance anti-interference capability and ensure the stability of the input signal.

[0219] The trigger output pulse comparison value configuration information is used to set the trigger output pulse comparison value (comparison threshold) of the trigger output control signal, so as to generate an output control signal when the count value reaches the trigger output pulse comparison value, thereby achieving precise position control or synchronous operation.

[0220] The trigger output pulse width information is used to define the duration (e.g., pulse width) of the output control signal to control the action time of the actuator, such as dispensing or inkjet timing.

[0221] The high-speed output interface function setting information is used to define the functions of the high-speed output interface, such as PWM output, pulse + direction output, multi-channel parallel data output, etc., to meet the output requirements of different application scenarios, support multiple control modes, and improve the adaptability of high-speed triggering devices.

[0222] The start trigger pulse count is used to set the number of trigger signal pulses that the high-speed triggering device needs to receive before it starts outputting control signals. The stop trigger pulse count is used to set the number of trigger signal pulses that the high-speed triggering device needs to receive before it automatically stops outputting control signals after completing its task, so as to achieve precise start and stop control based on external events.

[0223] As mentioned earlier, the high-speed triggering device supports three operating modes:

[0224] External high-speed input IO terminal trigger control mode: The FPGA module 20 outputs a control signal through the high-speed output interface 33 based on the trigger signal received by the high-speed input interface 32.

[0225] RS485 trigger control mode: The FPGA module 20 outputs control signals through the high-speed output interface 33 based on the trigger signal provided by the ARM module 10.

[0226] Encoder pulse trigger control function mode: The FPGA module 20 outputs a control signal through the high-speed output interface 33 based on the trigger signal received by the encoder signal input interface 31.

[0227] For example, the external high-speed input IO terminal trigger control mode can set relevant parameter instruction information through RS485 interface 101, connect the external terminal to high-speed input interface 32, and control the trigger output through the trigger start instruction and trigger stop instruction input by the external terminal.

[0228] The trigger configuration process for the external high-speed input I / O terminal trigger control mode may include:

[0229] a. Operation mode configuration: Set the operation mode configuration information to 0, and write the operation mode configuration information through RS485 interface 101 to enable the external high-speed input IO terminal trigger control mode.

[0230] b. Write encoder type information and encoder filter coefficient configuration information.

[0231] c. Write the high-speed input interface function and logic level selection configuration information, define the terminal functions of the high-speed input interface 32 (such as start, stop), select the logic level, and input the filter coefficient configuration information.

[0232] d. Write the trigger output pulse comparison value configuration information, setting the trigger output pulse comparison value. When the trigger output pulse comparison value is positive, it defaults to forward triggering and will not trigger during the reverse process. When the trigger output pulse comparison value is negative, it defaults to reverse triggering and will not trigger during the forward process.

[0233] It should be noted that when modifying the trigger output pulse comparison value configuration information, it must be done after the high-speed triggering device is in the trigger-stop state. If it is necessary to change the trigger direction while the high-speed triggering device is running (e.g., when the motor is running), the triggering must be stopped first, then the trigger output pulse comparison value configuration information must be modified, and then the triggering must be restarted.

[0234] e. Write the trigger output pulse width information to control the duration of the control signal, in μs.

[0235] f. Write the high-speed output interface function setting information, set the high-speed output interface function to trigger output, and define the output logic level (such as active high level / active low level).

[0236] g. Set the external terminal level, input the trigger start command to the high-speed input interface 32 through the external terminal to start the trigger, and the high-speed trigger device program will clear the pulse count value of the current trigger signal to zero and start counting.

[0237] h. When triggering stops, a trigger stop command is input to the high-speed input interface 32 via an external terminal.

[0238] Once triggered, the high-speed triggering device will only trigger according to the sign of the set value in the trigger output pulse comparison value configuration information. It will also cache each trigger point (current trigger position) based on the currently set trigger output pulse comparison value configuration information, ensuring that each trigger position is definite and will not repeat. The trigger cache will only be cleared upon receiving a trigger stop command, awaiting the next trigger start command.

[0239] For example, the overall functionality of the RS485 trigger control mode and the external high-speed input I / O terminal trigger control mode is the same, with only the trigger start and trigger stop functions differing. In the RS485 trigger control mode, the trigger start and trigger stop commands can be sent from the host computer to the high-speed trigger device via the RS485 interface 101. Upon receiving the trigger start or trigger stop command, the high-speed trigger device parses it and begins execution after successful parsing.

[0240] The trigger configuration process for RS485 trigger control mode may include:

[0241] a. Operation mode configuration: Set the operation mode configuration information to 1, and write the operation mode configuration information through RS485 interface 101 to enable RS485 trigger control mode.

[0242] b. Write encoder type information and encoder filter coefficient configuration information.

[0243] c. Write the trigger output pulse comparison value configuration information, setting the trigger output pulse comparison value. When the trigger output pulse comparison value is positive, it defaults to forward triggering and will not trigger during the reverse process. When the trigger output pulse comparison value is negative, it defaults to reverse triggering and will not trigger during the forward process.

[0244] It should be noted that when modifying the trigger output pulse comparison value configuration information, it must be done after the high-speed triggering device is in the trigger-stop state. If it is necessary to change the trigger direction while the high-speed triggering device is running (e.g., when the motor is running), the triggering must be stopped first, then the trigger output pulse comparison value configuration information must be modified, and then the triggering must be restarted.

[0245] d. Write the trigger output pulse width information to control the duration of the control signal, in μs.

[0246] e. Write the high-speed output interface function setting information, set the high-speed output interface function to trigger output, and define the output logic level (such as active high level / active low level).

[0247] f. Send a clear trigger stop command through RS485 interface 101 to ensure that the trigger stop command is 0.

[0248] g. Send a trigger start command through RS485 interface 101 to start the trigger. The high-speed trigger device program will clear the pulse count value of the current trigger signal to zero and start counting.

[0249] h. When triggering stops, a trigger stop command is sent through RS485 interface 101, and the trigger start command value is cleared.

[0250] Once triggered, the high-speed triggering device will only trigger according to the sign of the set value in the trigger output pulse comparison value configuration information. It will also cache each trigger point (current trigger position) based on the currently set trigger output pulse comparison value configuration information, ensuring that each trigger position is definite and will not repeat. The trigger cache will only be cleared upon receiving a trigger stop command, awaiting the next trigger start command.

[0251] For example, the encoder pulse trigger control function mode is different from other operating modes. The user needs to set the number of start trigger pulses (the pulse position at which the trigger begins), the number of stop trigger pulses (the pulse position at which the trigger ends), and the trigger output pulse comparison value. After setting, the trigger start command is sent through the RS485 interface 101 to start waiting for the trigger. After the trigger is completed, the trigger stop command is sent.

[0252] Optionally, after the user sets the number of start trigger pulses, the number of stop trigger pulses, and the comparison value of the trigger output pulse, the high-speed trigger device will check the set values ​​of the number of start trigger pulses, the number of stop trigger pulses, and the comparison value of the trigger output pulse to determine whether the above parameters meet the requirements.

[0253] The trigger configuration process for the encoder pulse trigger control function mode may include:

[0254] a. Operation mode configuration: Set the operation mode configuration information to 2, and write the operation mode configuration information through RS485 interface 101 to enable the encoder pulse trigger control function mode.

[0255] b. Write encoder type information and encoder filter coefficient configuration information.

[0256] c. Write the trigger output pulse comparison value configuration information, setting the trigger output pulse comparison value. When the trigger output pulse comparison value is positive, it defaults to forward triggering and will not trigger during the reverse process. When the trigger output pulse comparison value is negative, it defaults to reverse triggering and will not trigger during the forward process.

[0257] It should be noted that when modifying the trigger output pulse comparison value configuration information, it must be done after the high-speed triggering device is in the trigger-stop state. If it is necessary to change the trigger direction while the high-speed triggering device is running (e.g., when the motor is running), the triggering must be stopped first, then the trigger output pulse comparison value configuration information must be modified, and then the triggering must be restarted.

[0258] d. Set the number of start trigger pulses and the number of stop trigger pulses.

[0259] e. Write the trigger output pulse width information to control the duration of the control signal, in μs.

[0260] f. Write the high-speed output interface function setting information, set the high-speed output interface function to trigger output, and define the output logic level (such as active high level / active low level).

[0261] g. Send a clear trigger stop command through RS485 interface 101 to ensure that the trigger stop command is 0.

[0262] h. Send a trigger start command through RS485 interface 101 to start the trigger. The high-speed trigger device program will clear the pulse count value of the current trigger signal to zero and start counting.

[0263] i. When triggering stops, a trigger stop command is sent through RS485 interface 101, and the trigger start command value is cleared.

[0264] In the encoder pulse trigger control function mode, the number of start trigger pulses, the number of stop trigger pulses, and the trigger output pulse comparison value are preset. After the set values ​​of the start trigger pulse number, the number of stop trigger pulses, and the trigger output pulse comparison value meet the requirements, a trigger start command is sent through the RS485 interface 101 to start trigger output.

[0265] During the triggering process, if the number of trigger signal pulses is not between the number of start trigger pulses and the number of stop trigger pulses (for example, if the motor is not running within the trigger setting range), triggering will not occur.

[0266] Once triggering begins, the high-speed triggering device will only trigger according to the sign of the set value in the trigger output pulse comparison value configuration information. It will also cache each trigger point (current trigger position) based on the currently set trigger output pulse comparison value configuration information, meaning each trigger position is definite and will not repeat. The trigger cache will only be cleared upon receiving a trigger stop command, awaiting the next trigger start command.

[0267] As described above, users can modify the current operating mode and configure parameter command information through the RS485 interface 101. The terminal functions of the high-speed input interface 32 and the high-speed output interface 33 are configurable.

[0268] Optionally, the high-speed IO receiving module 203 and the high-speed IO output module 205 can be composed of custom protocol logic to meet special requirements for speed, timing control, and functional customization.

[0269] Custom protocol logic refers to a non-standardized data communication mechanism implemented in hardware (such as FPGA module 20), which can be flexibly defined according to the needs of specific application scenarios.

[0270] The high-speed triggering device provided in this embodiment of the invention adopts an ARM+FPGA separate processing architecture. The setting of parameter instruction information, reading of status, receiving instructions, and control are handled by the ARM module 10, while the pulse counting of the trigger signal and the output control signal of the high-speed output interface 33 are handled by the FPGA module 20. Parallel processing is achieved through the FPGA module 20, which can start counting immediately after receiving the trigger signal, output control signal immediately after the count reaches the preset trigger output pulse comparison value N, and stop immediately after receiving the trigger stop command. The processing logic can be completely implemented by the hardware circuit of the FPGA module 20, with an extremely fast response speed (nanosecond level). This avoids the delay problem caused by the scanning cycle of traditional PLCs, thereby achieving low-latency triggering, which is suitable for high-speed dispensing, inkjet, laser marking and other applications with extremely sensitive time requirements.

[0271] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0272] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A high-speed triggering device, characterized in that, Including ARM modules and FPGA modules; The FPGA module includes an encoder signal input interface, a high-speed input interface, and a high-speed output interface; The ARM module is communicatively connected to the host computer and the FPGA module. The ARM module is used to receive parameter instruction information provided by the host computer and transmit the parameter instruction information to the FPGA module. The parameter instruction information includes operating mode configuration information; When the operating mode configuration information is the first preset operating mode configuration information, the FPGA module outputs a control signal through the high-speed output interface according to the trigger signal received by the high-speed input interface; When the operating mode configuration information is the second preset operating mode configuration information, the FPGA module outputs the control signal through the high-speed output interface according to the trigger signal provided by the ARM module; When the operating mode configuration information is the third preset operating mode configuration information, the FPGA module outputs the control signal through the high-speed output interface according to the trigger signal received by the encoder signal input interface.

2. The high-speed triggering device according to claim 1, characterized in that, The ARM module includes an RS485 interface; The ARM module and the host computer are connected via the RS485 interface; The host computer transmits the parameter instruction information to the ARM module via the Modbus protocol.

3. The high-speed triggering device according to claim 1, characterized in that, The FPGA module also includes a parallel bus processing module, which includes a FIFO buffer. The parallel bus processing module is connected to the ARM module via a parallel bus.

4. The high-speed triggering device according to claim 1, characterized in that, The FPGA module also includes an encoder counting and alarm module, which includes a signal conversion unit, a filtering unit, and an encoder counting and alarm unit. The filtering unit is connected to the encoder through the encoder signal input interface. The encoder is used to output the trigger signal, and the trigger signal output by the encoder is a differential signal. The filtering unit is used to filter the differential signal. The signal conversion unit is electrically connected to the filtering unit and is used to convert the filtered differential signal into a single-ended signal. The encoder counting and alarm unit is electrically connected to the signal conversion unit and is used to output the control signal through the high-speed output interface according to the single-ended signal.

5. The high-speed triggering device according to claim 4, characterized in that, The signal conversion unit is also used to provide an alarm signal to the encoder counting and alarm unit; The encoder counting and alarm unit is also used to output the control signal through the high-speed output interface according to the alarm signal.

6. The high-speed triggering device according to claim 4, characterized in that, The encoder counting and alarm unit is also used to provide conversion parameter information to the signal conversion unit; The signal conversion unit outputs the single-ended signal corresponding to the level standard according to the conversion parameter information; The level standard includes at least one of the TTL level standard and the RS422 level standard.

7. The high-speed triggering device according to claim 1, characterized in that, The FPGA module further includes a high-speed IO receiving module and a data storage module, wherein the high-speed IO receiving module includes a first isolation optocoupler unit; The first isolation optocoupler unit is electrically connected to the high-speed input interface, and the data storage module is electrically connected to the first isolation optocoupler unit; The data storage module is used to output the control signal through the high-speed output interface based on the trigger signal received by the high-speed input interface.

8. The high-speed triggering device according to claim 1, characterized in that, The FPGA module also includes a high-speed IO output module and a data storage module, wherein the high-speed IO output module includes a second isolation optocoupler unit; The data storage module is electrically connected to the second isolation optocoupler unit, and the second isolation optocoupler unit is electrically connected to the high-speed output interface. The data storage module is used to output the control signal through the high-speed output interface.

9. The high-speed triggering device according to claim 1, characterized in that, The FPGA module also includes a clock management module, which includes a phase-locked loop.

10. The high-speed triggering device according to claim 1, characterized in that, The parameter instruction information also includes at least one of the following: encoder type information, encoder filter coefficient configuration information, high-speed input interface function and logic level selection configuration information, filter coefficient configuration information, trigger output pulse comparison value configuration information, trigger output pulse width information, high-speed output interface function setting information, start trigger pulse count, and stop trigger pulse count.

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