A low-power real-time signal processing method and system

Abstract

The application relates to a low-power real-time signal processing method, which comprises the following steps: collecting a signal, performing analog-to-digital conversion on the signal to obtain a digital signal; performing fast Fourier transform on the digital signal, wherein fixed-point operation is adopted to replace floating-point operation in the fast Fourier transform; dispersively processing the transformed data to obtain a plurality of processing units; and merging and reconstructing the plurality of processing units to obtain a final signal processing result. In the application, the floating-point operation is replaced by the fixed-point operation, the occupation of the digital signal processor resource is reduced without affecting the signal processing precision, and thus the power consumption of the equipment is reduced. Meanwhile, the transformed data is dispersively processed, the signal frequency bands with different energies are distributed to different processing units, the calculation load is dispersed, the equipment jamming or shutdown phenomenon caused by excessive concentration of the calculation amount is avoided, the real-time performance of the signal processing process is improved, and the equipment power consumption is further reduced.

Description

Technical Field

[0001] This application relates to the field of signal processing technology, specifically to a low-power real-time signal processing method and system. Background Technology

[0002] Traditional signal processing architectures used in embedded devices typically employ floating-point arithmetic for complex operations such as FFT. Floating-point operations place high demands on digital signal processor resources, leading to high power consumption and making them unsuitable for power-sensitive embedded devices, such as smart circuit breakers. Furthermore, when processing large amounts of sampled data, traditional architectures often perform all calculations at once, resulting in concentrated computational loads that can easily cause device lag or even crashes, failing to meet real-time requirements.

[0003] The prior art patent application CN202111450127.X discloses a lightweight FFT operation method and its implementation device. It optimizes the pipelined structure, employs hierarchical decomposition to complete FFT digital signal processing, utilizes time-division multiplexing circuits to perform inter-stage processing of signal components during the operation, and utilizes in-situ operations with inter-stage registers. This optimization addresses the characteristics of digital signal processing, such as a large number of signal components and complex storage hierarchy when temporarily storing signal components. It reduces the hardware resource usage required for FFT operations during signal processing, thereby reducing the chip area when applied to DSP chips, achieving a lightweight design effect. This aligns better with the miniaturization characteristics of modern DSP chip design, reducing chip area and consequently lowering static power consumption during operation. This reduces the power consumption during FFT signal processing, ultimately lowering the overall power consumption of the DSP chip.

[0004] However, the aforementioned existing technologies suffer from insufficient real-time performance, especially when processing large amounts of sampled data. Although pipelined architecture optimization and hierarchical decomposition reduce hardware resource usage and chip area, in practical applications, particularly in scenarios with extremely high real-time requirements such as smart circuit breakers, these methods still struggle to meet the demands for rapid response. Furthermore, while the existing technologies have made improvements in low-power design, there is still room for further power reduction while ensuring signal processing accuracy and real-time performance. Summary of the Invention

[0005] To address the aforementioned problems, this invention proposes a low-power real-time signal processing method that replaces floating-point arithmetic with fixed-point arithmetic, optimizes the algorithm flow, distributes the computational load, effectively reduces device power consumption, and improves real-time performance. This application also provides an intelligent circuit breaker that integrates this method to achieve efficient and stable signal processing and control.

[0006] The specific technical solution of this application is: a low-power real-time signal processing method, comprising the following steps:

[0007] S1. Acquire the signal and perform analog-to-digital conversion on the signal to obtain a digital signal;

[0008] S2. Perform a Fast Fourier Transform on the digital signal, in which fixed-point arithmetic is used instead of floating-point arithmetic.

[0009] S3. The transformed data is processed in a distributed manner to obtain multiple processing units;

[0010] S4. Merge and reconstruct the multiple processing units to obtain the final signal processing result.

[0011] The beneficial effects of this invention are as follows:

[0012] By replacing floating-point arithmetic with fixed-point arithmetic, the resource consumption of the digital signal processor is reduced without affecting the signal processing accuracy, thereby lowering the power consumption of the device. Simultaneously, by distributing the transformed data through decentralized processing, signal frequency bands of different energies are allocated to different processing units, thus distributing the computational load and avoiding device lag or crashes caused by excessive concentration of computational load. This improves the real-time performance of the signal processing process and further reduces equipment operating costs. Attached Figure Description

[0013] Figure 1 A flowchart of a low-power real-time signal processing method according to an embodiment of this application;

[0014] Figure 2 A schematic diagram of the structure of an intelligent circuit breaker according to an embodiment of this application;

[0015] Figure 3 A structural diagram of a low-power real-time signal processing system according to an embodiment of this application; Detailed Implementation

[0016] Traditional signal processing architectures used in embedded devices typically employ floating-point arithmetic for complex operations such as FFT. Floating-point arithmetic demands high digital signal processor resources, leading to high power consumption and making it unsuitable for embedded devices with stringent power requirements (such as smart circuit breakers). Furthermore, when processing large amounts of sampled data, traditional architectures often perform all data calculations at once, resulting in concentrated computational loads that can easily cause device lag or even crashes, failing to meet real-time requirements.

[0017] To address the aforementioned problems, this invention proposes a low-power real-time signal processing method that replaces floating-point arithmetic with fixed-point arithmetic, optimizes the algorithm flow, distributes the computational load, effectively reduces device power consumption, and improves real-time performance. This application also provides an intelligent circuit breaker that integrates this method to achieve efficient and stable signal processing and control.

[0018] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0019] In some embodiments, such as Figure 1 As shown, a low-power real-time signal processing method is provided, including the following steps:

[0020] S1. Acquire the signal and perform analog-to-digital conversion on the signal to obtain a digital signal;

[0021] The types of signals acquired include, but are not limited to, current, voltage, and temperature signals, which can be determined based on the application scenario and monitoring requirements. According to known technologies, the acquired signals undergo preprocessing such as filtering and amplification before being sent to an analog-to-digital converter (ADC) for conversion. The sampling rate and resolution of the ADC can be adjusted according to actual needs to minimize the amount of data while ensuring signal quality, thereby reducing the computational burden of subsequent processing.

[0022] S2. Perform a Fast Fourier Transform on the digital signal, in which fixed-point arithmetic is used instead of floating-point arithmetic.

[0023] The core advantages of fixed-point arithmetic over floating-point arithmetic lie in hardware resource and cost savings: specifically, lower power consumption. Fixed-point arithmetic eliminates the need for floating-point units, resulting in a simpler hardware structure and power consumption that can be reduced to 1 / 5–1 / 10 of that of floating-point arithmetic. For example, in battery-powered IoT devices, fixed-point arithmetic can reduce power consumption from 100mW to 5mW.

[0024] Low cost: Microcontrollers supporting fixed-point arithmetic (such as the ARM Cortex-M0) are 30%–50% cheaper than microcontrollers with an FPU (floating-point unit), making them suitable for large-scale deployments. High computational speed and real-time execution efficiency: Fixed-point addition and subtraction require only 1–2 clock cycles, while floating-point operations require 10–20 cycles. In real-time systems such as motor control, fixed-point FFT processing speed can be increased by 50%.

[0025] Greater determinism: Fixed computation time, suitable for strictly real-time scenarios (such as 1ms cycle tasks in automotive onboard computers). Optimized storage and memory: Small storage footprint: 32-bit fixed-point numbers save 50% of storage space compared to 32-bit floating-point numbers (no exponent bits). Low data bandwidth requirements: Suitable for low-speed bus communication (such as CAN bus).

[0026] However, compared to floating-point arithmetic, fixed-point arithmetic has limited precision, especially when dealing with extreme ranges or decimals that require high precision.

[0027] In the low-power real-time signal processing method of this application, the relationship between accuracy and resource consumption is balanced through optimized algorithm design, ensuring that the accuracy of the Fast Fourier Transform meets the requirements of practical applications.

[0028] S3. The transformed data is processed in a distributed manner to obtain multiple processing units;

[0029] For example, high-frequency noise components and low-frequency steady-state components in a voltage signal can be assigned to different processing units. High-frequency noise components, due to their rapid changes, require higher sampling rates and processing speeds, and therefore can be assigned to a dedicated processing unit for fast processing. Low-frequency steady-state components, on the other hand, due to their relatively slow changes, can be assigned to another processing unit for more detailed processing, such as filtering and smoothing. This distributed processing not only improves signal processing speed but also allows for optimized processing based on the signal characteristics of different frequency bands, thereby improving the accuracy and efficiency of signal processing.

[0030] Processing units corresponding to signal frequency bands with similar energy can be merged. For example, processing units for high-frequency noise components and processing units for certain specific frequency harmonic components in voltage signals can be merged into one processing unit because their energy distributions are similar, thereby reducing the number of processing units and lowering the complexity of subsequent processing.

[0031] This processing method not only ensures the accuracy and real-time performance of signal processing, but also effectively reduces the power consumption of the device, making it particularly suitable for embedded devices such as smart circuit breakers that have extremely high requirements for power consumption and real-time performance.

[0032] S4. Merge and reconstruct the multiple processing units to obtain the final signal processing result.

[0033] Building upon the previous step, the multiple processing units that have been processed separately are reconstructed to obtain a complete signal processing result containing the signal characteristics of all frequency bands. This step ensures that no important signal information is lost during processing. Furthermore, by merging and reconstructing, redundant data can be further reduced, improving the efficiency and accuracy of signal processing.

[0034] The voltage signals after the above-mentioned decentralized processing are merged and reconstructed using techniques such as weighted averaging and maximum value selection. The weighted averaging method can assign different weights to different processing units based on their signal energy or importance, resulting in a more accurate signal processing result. The maximum value selection method is suitable for scenarios requiring fast response, selecting the processing unit with the strongest signal strength as the final result.

[0035] This application reduces resource consumption and thus lowers device power consumption by replacing floating-point operations with fixed-point arithmetic. Simultaneously, by distributing the processed data, it avoids the concentration of computational load, effectively preventing device lag and crashes, and improving real-time performance.

[0036] In some embodiments, a method is provided to replace floating-point operations with fixed-point operations in the Fast Fourier Transform, specifically including:

[0037] S2.1 Use long integer arrays to store and process data;

[0038] In this step, the long integer array can be a specially designed array structure that optimizes memory layout and access speed to meet the requirements of fixed-point arithmetic. Each element of the array represents a sample point of signal data, and its value is represented by a fixed-point number, meaning the integer and fractional parts are separated by a fixed bit length. This design ensures data processing accuracy while minimizing hardware resource consumption. Specifically, the long integer array can efficiently store and process large amounts of signal data while supporting fast fixed-point arithmetic, thus meeting the requirements of real-time signal processing.

[0039] S2.2 Perform bitwise operations on long integer arrays to simulate multiplication and division in fixed-point arithmetic;

[0040] S2.3. Using a predefined fixed-point number table, convert long integers into corresponding fixed-point values ​​and perform addition and subtraction operations.

[0041] A fixed-point number table is a predefined table used to map the values ​​of long integers to their corresponding fixed-point values. This table is compiled according to the representation method of fixed-point numbers (i.e., the bit length division between the integer and fractional parts), ensuring the accuracy and efficiency of fixed-point arithmetic. In addition and subtraction operations, by looking up the fixed-point number table, the value of a long integer can be quickly converted to its corresponding fixed-point value, thus enabling precise fixed-point calculations. This method avoids the complexity and high resource consumption of floating-point arithmetic while guaranteeing the precision and real-time performance of signal processing.

[0042] The two methods described above for simulating fixed-point arithmetic through bit manipulation can significantly improve computational efficiency while reducing reliance on the hardware floating-point unit (FPU). For example, multiplication can be implemented using a combination of bit shifting and addition, while division can be approximated iteratively using bit shifting and subtraction. This approach not only reduces power consumption but also maintains high computational accuracy.

[0043] In some embodiments, another method is provided to convert the steps originally involving floating-point operations into integer operations. When calculating complex multiplication, the floating-point parameters a, b, c, d in the floating-point complex multiplication formula (a+bi)×(c+di)=(ac-bd)+(ad+bc)i are converted into integer operations. The specific principle is as follows: the original complex multiplication formula is converted into integer operations.

[0044] In (a+bi)×(c+di)=(ac-bd)+(ad+bc)i, the floating-point parameters a, b, c, d are converted to integers for arithmetic operations.

[0045] Scaling: Multiply the floating-point number by a scaling factor S (e.g., 2). k Then round down to get the integer:

[0046] A=round(aS),B=round(bS);

[0047] C=round(cS), D=round(dS);

[0048] Integer multiplication: Calculating the real and imaginary parts using integer operations.

[0049] Real part: Rint = (AC - BD)

[0050] Imaginary part: Iint = (A.D + BC)

[0051] Scaling compensation: The result needs to be divided by S 2 To restore the actual value, shift to the right:

[0052] Rfinal=Rint>>2k,Ifinal=Iint>>2k

[0053] In the above formula, >> represents a binary right shift, which is equivalent to dividing by 2. 2k .

[0054] In this application, the selection of scaling factor needs to balance precision and overflow prevention. When high precision is required, a larger k value is selected to retain more decimal places. When overflow is prevented, it should be ensured that |AC|max < 2N-1 (N is an integer bit width, such as 32 bits).

[0055] The rounding method used in this implementation is: round() to round to the nearest integer to reduce accumulated error;

[0056] In this embodiment, the complex number multiplication, which originally involved floating-point operations, is converted into integer operations using the above-described calculation method, further reducing the DSP resource consumption while maintaining high computational accuracy. Furthermore, this method effectively balances the relationship between accuracy and overflow prevention through steps such as scaling, integer multiplication, and scaling compensation, ensuring the accuracy of the signal processing results.

[0057] In some embodiments, in order to further reduce power consumption and avoid device crashes caused by concentrated computation when processing data, the data after distributed processing is transformed into multiple processing units, specifically including the following steps: dividing the N-point frequency domain data output after the fast Fourier transform into K sub-frequency bands according to frequency;

[0058] Dynamically adjust sub-band bandwidth based on signal power spectral density (PSD):

[0059] Narrow bandwidth (high resolution) is used in high-energy regions, while wide bandwidth (reduced computational load) is used in low-energy regions.

[0060] S3.2 Allocate processing units according to the energy distribution of the sub-frequency bands, allocate high-performance processing units to sub-frequency bands with energy above the threshold, and allocate low-power processing units to sub-frequency bands with energy below the threshold;

[0061] In this step, flexibly allocating processing units based on energy distribution further optimizes resource utilization. Specifically, high-performance processing units are allocated to higher-energy sub-bands to ensure processing speed and accuracy, while low-power processing units are allocated to lower-energy sub-bands to save power. This method of adaptively adjusting processing resources based on signal characteristics not only improves processing efficiency but also further reduces overall power consumption.

[0062] In some embodiments, the threshold in this application may be set to the median or average value of the signal energy distribution.

[0063] The high-performance processing unit in this application can be a dedicated digital signal processing chip (DSP), designed for high-speed digital signal processing tasks, possessing powerful computing capabilities and low power consumption. These chips integrate fixed-point arithmetic units, enabling efficient fixed-point arithmetic operations to meet the requirements of low-power real-time signal processing. Alternatively, the high-performance processing unit can also be a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC). These hardware platforms, through custom design, can achieve acceleration for specific signal processing tasks, further improving processing efficiency and reducing power consumption.

[0064] The low-power processing unit in this application can be a microcontroller (MCU), such as the ARM Cortex-M series, which is designed with low-power characteristics. They typically integrate basic digital signal processing functions and implement fixed-point arithmetic through software algorithms to reduce power consumption. When selecting a low-power processing unit, a balance is considered between its processing power, power consumption, and cost to ensure that signal processing requirements are met while minimizing the overall power consumption of the device.

[0065] S3.3 further divides the data in the same sub-frequency band into M data blocks, which are then distributed to homogeneous processing units for parallel processing using a Round-Robin scheduling strategy;

[0066] The specific process in this step involves dividing the data within the same sub-frequency band into M data blocks based on time sequence or block size. Then, a Round-Robin scheduling strategy is employed to distribute these data blocks sequentially to multiple homogeneous processing units for parallel processing. The Round-Robin scheduling strategy ensures that each processing unit receives a relatively balanced workload, preventing one unit from being overloaded while others remain idle, thereby improving overall processing efficiency and resource utilization. This data partitioning and parallel processing method further distributes the computational load, reducing the processing pressure on individual processing units and helping to prevent device lag and crashes. Simultaneously, the use of homogeneous processing units facilitates redundant backup and failover, improving system reliability and stability.

[0067] In this embodiment, the Round-Robin scheduling strategy refers to a scheduling method for distributing tasks among multiple processing units. Specifically, it assigns tasks to each available processing unit in a fixed order, taking turns. After all processing units have been assigned tasks once, the scheduler restarts a new round of allocation, and so on. This method ensures that each processing unit receives a relatively balanced workload, avoiding situations where some processing units are overloaded while others are idle, thereby improving overall processing efficiency and resource utilization. In this application, the Round-Robin scheduling strategy is used to sequentially distribute segmented data blocks to multiple homogeneous processing units for parallel processing, thereby distributing the computational load, reducing device power consumption, and improving real-time performance.

[0068] S3.4 Dynamically adjusts the processing unit voltage and clock frequency according to the task computation complexity η, and starts the buck-frequency reduction mode when η<50%; sends instructions to idle processing units to trigger deep sleep mode.

[0069] In this step, to further reduce power consumption, the voltage and clock frequency of the processing unit are dynamically adjusted based on the task's computational complexity. Specifically, when the task's computational complexity η is below 50%, the system activates a buck-and-reduce-frequency mode, reducing power consumption by lowering the voltage and clock frequency of the processing unit. This dynamic adjustment mechanism optimizes energy consumption based on the actual workload, ensuring lower power consumption when handling lighter tasks. Simultaneously, for idle processing units, the system sends a command to trigger a deep sleep mode, further reducing power consumption. Deep sleep mode is a low-power state in which most functions of the processing unit are disabled, retaining only essential basic functions to monitor wake-up events. When a new task needs to be processed, the processing unit can quickly wake up from deep sleep mode and resume normal operation. By dynamically adjusting the processing unit voltage and clock frequency and utilizing deep sleep mode, this application further reduces the overall power consumption of the device and improves energy efficiency.

[0070] In some embodiments, the computational complexity η of a task is calculated by comprehensively evaluating the time and resources required for task execution. Specifically, the computational complexity of a task can be determined by analyzing the time and space complexity of the algorithm, as well as indicators such as CPU utilization and memory usage during actual operation. This method can accurately reflect the computational requirements and resource consumption of the task, thus providing a reliable basis for dynamically adjusting the voltage and clock frequency of the processing unit. In this application, by accurately evaluating the computational complexity of the task, fine control of the energy consumption of the processing unit is achieved, further improving the energy efficiency of the device.

[0071] In some embodiments, during the process of dividing the N-point frequency domain data output after the Fast Fourier Transform into K sub-bands according to frequency, the bandwidth of the sub-bands is dynamically adjusted based on the signal power spectral density, with narrow bandwidth used in high-energy regions and wide bandwidth used in low-energy regions.

[0072] This dynamic adjustment allows for more precise segmentation of signal features, enabling more efficient and targeted subsequent processing. Specifically, in high-energy regions, where signal features are more complex, narrow bandwidth can better capture these subtle characteristics, improving signal processing accuracy. Conversely, in low-energy regions, where signal features are relatively simple, wide bandwidth reduces the amount of data processed, lowering the computational burden and further saving power. This method of dynamically adjusting sub-band bandwidth based on signal power spectral density not only improves signal processing efficiency but also further optimizes overall power consumption.

[0073] In some embodiments, such as Figure 2As shown, this application also provides an intelligent circuit breaker, including a signal acquisition module 1 configured to acquire signals such as current and voltage in a power system in real time; a processing module 2 connected to the signal acquisition module and configured to process the acquired signals according to the method in the above embodiment; and a control module 3 connected to the processing module to control the opening and closing of the circuit breaker according to the analysis results of the processing module.

[0074] In some embodiments, such as Figure 3 As shown, this application also provides a low-power real-time signal processing system, the system including at least one processor 101, a memory 102, an input device 103 and a display device 104. The input device 103 is used to obtain input from the outside. The memory 102 stores instructions. When the instructions are executed by at least one processor 101, the steps of the method described in the method embodiment are implemented, and the running results are displayed on the display device 104, implementing the steps of the method described in the method embodiment.

[0075] The embodiments and functional operations of the subject matter described in this specification can be implemented in the following ways: digital electronic circuits, tangibly implemented computer software or firmware, computer hardware, including the structures disclosed in this specification and their equivalents, or combinations thereof. Embodiments of the subject matter described in this specification can be implemented as one or more computer programs, that is, one or more modules of computer program instructions encoded on one or more tangible non-transitory program carriers, for execution by a data processing device or to control the operation of the data processing device.

[0076] Alternatively or additionally, program instructions may be encoded on artificially generated propagation signals, such as machine-generated electrical, optical, or electromagnetic signals, which are then generated as coded information to be transmitted to an appropriate receiver device executed by data processing equipment. The computer storage medium may be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, or one or more combinations of the above.

[0077] The processing and logic flows described in this specification can be executed by one or more programmable computers, which execute one or more computer programs by processing input data and generating output to run functions. The processing and logic flows can also be executed by special-purpose logic circuitry, such as FPGAs (Field-Programmable Gate Arrays) or ASICs (Application-Specific Integrated Circuits), and the device can also be implemented as special-purpose logic circuitry.

[0078] While this specification contains numerous specific implementation details, these should not be construed as limiting the scope of any invention or the scope of the claims, but rather as descriptions of features that can embody specific embodiments of a particular invention. Specific features described in this specification within the context of an independent embodiment may also be implemented in combination with a single embodiment. Conversely, various features described within the context of a single embodiment may also be implemented independently in multiple embodiments, or in any suitable sub-combination. Furthermore, while features may be described for combination and even initially claimed in this way, one or more features from a claimed combination may be removed from that combination in some cases, and the claimed combination may be redirected to a sub-combination or a variation thereof.

Claims

1. A low-power real-time signal processing method, characterized in that, The steps include the following: S1. Acquire the signal and perform analog-to-digital conversion on the signal to obtain a digital signal; S2. Perform a Fast Fourier Transform on the digital signal, in which fixed-point arithmetic is used instead of floating-point arithmetic. S3. The transformed data is processed in a distributed manner to obtain multiple processing units; S4. Merge and reconstruct the multiple processing units to obtain the final signal processing result; The distributed processing transforms the data to obtain multiple processing units, including: S3.1 Dividing the N-point frequency domain data output after the Fast Fourier Transform into K sub-frequency bands according to frequency; S3.2 Allocate processing units according to the energy distribution of the sub-frequency bands, allocating high-performance processing units to sub-frequency bands with energy above the threshold and low-power processing units to sub-frequency bands with energy below the threshold; S3.3 Further divide the data in the same sub-frequency band into M data blocks, and allocate them to homogeneous processing units for parallel processing through a Round-Robin scheduling strategy; S3.4 Dynamically adjust the voltage and clock frequency of the processing units according to the task computational complexity η, and start the buck-frequency reduction mode when η<50%; send instructions to idle processing units to trigger deep sleep mode; S3.1 dynamically adjusts the sub-band bandwidth based on the signal power spectral density, using narrow bandwidth in the high-energy region and wide bandwidth in the low-energy region.

2. The low-power real-time signal processing method as described in claim 1, characterized in that, The use of fixed-point arithmetic instead of floating-point arithmetic in the Fast Fourier Transform includes: S2.1 Use long integer arrays to store and process data; S2.2 Perform bitwise operations on the long integer array to simulate multiplication and division in fixed-point arithmetic; S2.

3. Using a predefined fixed-point number table, convert the long integer into a corresponding fixed-point value and perform addition and subtraction operations.

3. The low-power real-time signal processing method as described in claim 2, characterized in that, The long integer array is long iRealArray.

4. The low-power real-time signal processing method as described in claim 2, characterized in that, Bitwise operations are performed on the long integer array to simulate multiplication and division in fixed-point arithmetic, including converting the floating-point parameters a, b, c, d in the floating-point complex multiplication formula (a+bi)×(c+di)=(ac−bd)+(ad+bc)i into integer operations.

5. The low-power real-time signal processing method as described in claim 3, characterized in that, Converting the floating-point parameters a, b, c, d in the floating-point complex multiplication formula (a+bi)×(c+di)=(ac−bd)+(ad+bc)i to integer operations specifically includes: Multiply the floating-point number by the scaling factor and round down to get an integer; Intermediate results are obtained by calculating the real and imaginary parts using integer arithmetic. Dividing the intermediate result by the scaling factor yields an approximate floating-point result.

6. The low-power real-time signal processing method as described in claim 5, characterized in that, The scaling factor is dynamically adjusted according to the dynamic range and accuracy requirements of the signal. When the accuracy requirement increases, the scaling factor is decreased; when the dynamic range of the signal is large, the scaling factor is increased.

7. A low-power real-time signal processing system, characterized in that, The system includes at least one processor; and a memory storing instructions that, when executed by the at least one processor, perform the steps of the method according to any one of claims 1-6.

Images