Instruction execution method and apparatus and processor

Abstract

The present disclosure relates to an instruction execution method and device and a processor, comprising: identifying whether an instruction to be executed comprises an extended instruction prefix; if yes, extracting a first field for mapping an operation code of the instruction to be executed from the instruction to be executed; judging whether a second field related to a variable length vector register and a third field related to a variable length mask register are extracted from the instruction to be executed according to the first field; if yes, executing the instruction to be executed according to the first field, the second field, the third field, an operation code comprised by the instruction to be executed and an addressing mode field; if not, executing the instruction to be executed according to the first field, the operation code and the addressing mode field. Thus, the portability of software can be improved and the x86 instruction can be easily extended.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of computers, and in particular, to an instruction execution method and apparatus and a processor. BACKGROUND

[0002] The x86 vector instruction set architecture faces challenges in implementing cross-platform software porting due to its historical compatibility design. The instruction extension mechanism is limited by the variable-length instruction encoding system of x86, and the introduction of new instructions requires complex decoding logic. With the expansion of SIMD bit width from 128 bits to 512 bits, the instruction encoding space is close to saturation. SUMMARY

[0003] Therefore, the present disclosure proposes an instruction execution method and apparatus and a processor, so as to improve the portability of software and easily extend x86 instructions.

[0004] According to a first aspect of the present disclosure, an instruction execution method is provided, which includes: identifying whether a to-be-executed instruction includes an extended instruction prefix; if the to-be-executed instruction includes the extended instruction prefix, extracting a first field for marking an opcode mapping of the to-be-executed instruction from the to-be-executed instruction; judging whether to extract a second field related to a variable-length vector register and a third field related to a variable-length mask register from the to-be-executed instruction according to the first field, wherein the variable-length vector register is used for vector operation, and the variable-length mask register is used for mask control; if it is judged to extract the second field and the third field from the to-be-executed instruction, executing the to-be-executed instruction according to the first field, the second field, the third field, and an opcode and an addressing mode field included in the to-be-executed instruction; if it is judged not to extract the second field and the third field from the to-be-executed instruction, executing the to-be-executed instruction according to the first field, the opcode and the addressing mode field.

[0005] In a possible implementation, the first field includes a first bit field for marking the opcode mapping of the to-be-executed instruction, and judging whether to extract the second field and the third field from the to-be-executed instruction according to the first field includes: judging whether the first bit field is a first value; if it is judged that the first bit field is the first value, it is judged not to extract the second field and the third field from the to-be-executed instruction; if it is judged that the first bit field is a value different from the first value, it is judged to extract the second field and the third field from the to-be-executed instruction.

[0006] In a possible implementation, the executing the to-be-executed instruction according to the first field, the second field, the third field, and an operation code, an addressing mode field included in the to-be-executed instruction comprises: determining information about the variable-length vector register and the variable-length mask register according to the first field, the second field, and the third field; determining a function of the to-be-executed instruction according to the operation code; determining a source register and a destination register of the to-be-executed instruction according to the addressing mode field; and performing an operation corresponding to the function of the to-be-executed instruction on the to-be-executed instruction according to the information, the source register, and the destination register.

[0007] In a possible implementation, the first field further includes a second bit field for accessing an extended register resource, the second field includes a third bit field for accessing an extended register resource and a fourth bit field for identifying a processing to be performed on an inactivated variable-length mask register, and the third field includes a fifth bit field for identifying an index of the variable-length mask register. The determining the information about the variable-length vector register and the variable-length mask register according to the first field, the second field, and the third field comprises: determining an addressable variable-length vector register according to the second bit field and the third bit field; determining a mask operation to be performed on an inactivated variable-length mask register according to the fourth bit field; and determining an activated variable-length mask register according to the fifth bit field.

[0008] In a possible implementation, the performing the operation corresponding to the function of the to-be-executed instruction on the to-be-executed instruction according to the information, the source register, and the destination register comprises: obtaining a source operand according to the source register; loading a plurality of data elements in parallel according to the addressable variable-length vector register; performing the operation corresponding to the function of the to-be-executed instruction on the source operand and data elements in the loaded plurality of data elements that need to participate in the operation and correspond to the activated variable-length mask register, and performing the mask operation on the inactivated variable-length mask register.

[0009] In a possible implementation, the operation corresponding to the function of the to-be-executed instruction comprises: if the operation code is a predetermined operation value, determining that the function of the to-be-executed instruction is a predetermined function, and performing a predetermined operation corresponding to the predetermined function on the to-be-executed instruction, wherein the predetermined operation comprises an addition operation, a subtraction operation, a multiplication operation, a division operation, a shift operation, a logical and operation, a logical and not operation, a logical or operation, a logical same operation, a logical exclusive or operation, a bitwise not operation, an operation of performing a bitwise logical or operation on two source operands and setting a flag bit according to a result, a left shift operation, a right shift operation, a packed bit test mask and flag bit setting operation, or an unpack operation.

[0010] In a possible implementation, when the predetermined operation is the shift operation, the operation corresponding to the function of the to-be-executed instruction comprises: if the operation code is a first operation value, performing a shift operation of moving a source operand from a memory to the activated variable-length mask register on the to-be-executed instruction; if the operation code is a second operation value, performing a shift operation of moving a source operand from the activated variable-length mask register to a memory on the to-be-executed instruction; if the operation code is a third operation value, performing a shift operation of moving a source operand from a general-purpose vector register to the activated variable-length mask register on the to-be-executed instruction; and if the operation code is a fourth operation value, performing a shift operation of moving a source operand from the activated variable-length mask register to a general-purpose vector register on the to-be-executed instruction.

[0011] In a possible implementation, the instruction execution method further comprises: determining a bit width of the shift operation of the variable-length mask register according to the flag bit of the first bit field and whether the to-be-executed instruction comprises a prefix in which the third field has a preset value.

[0012] In a possible implementation, the determination of the bit width of the shift operation of the variable-length mask register according to the flag bit and whether the to-be-executed instruction comprises the prefix in which the third field has the preset value comprises: if the flag bit is 0 and the prefix in which the third field has the preset value is included, the bit width of the shift operation is 1 byte; if the flag bit is 0 and the prefix in which the third field has the preset value is not included, the bit width of the shift operation is 2 bytes; if the flag bit is 1 and the prefix in which the third field has the preset value is included, the bit width of the shift operation is 4 bytes; and if the flag bit is 1 and the prefix in which the third field has the preset value is not included, the bit width of the shift operation is 8 bytes.

[0013] In a possible implementation, the first field further includes a second bit field for accessing an extended register resource, and the executing the to-be-executed instruction according to the first field, the operation code and the addressing mode field includes: determining a variable-length vector register that can be addressed according to the second bit field; determining a function of the to-be-executed instruction according to the operation code; determining a source register and a destination register of the to-be-executed instruction according to the addressing mode field; and performing an operation corresponding to the function of the to-be-executed instruction on the to-be-executed instruction according to the variable-length vector register that can be addressed, the source register and the destination register.

[0014] In a possible implementation, the first field includes a first bit field for marking an operation code mapping of the to-be-executed instruction, and the instruction execution method further includes: if a flag bit of the first bit field is a first flag value, determining that the to-be-executed instruction is a private variable-length vector instruction; and if the flag bit of the first bit field is a second flag value different from the first flag value, determining that the to-be-executed instruction is not the private variable-length vector instruction.

[0015] In a possible implementation, the instruction execution method further includes: updating a load and operation instruction of the variable-length mask register and a mask operation.

[0016] In a possible implementation, the instruction execution method further includes: if an exception occurs during execution of the to-be-executed instruction, reporting the exception to a system register.

[0017] According to a second aspect of the present disclosure, an instruction execution apparatus is provided, which includes: a decoding unit configured to identify whether a to-be-executed instruction includes an extended instruction prefix, and extract a first field for marking an operation code mapping of the to-be-executed instruction from the to-be-executed instruction if the to-be-executed instruction includes the extended instruction prefix; determine whether to extract a second field related to a variable-length vector register and a third field related to a variable-length mask register from the to-be-executed instruction according to the first field, wherein the variable-length vector register is used for vector operation, and the variable-length mask register is used for mask control; and an execution unit configured to execute the to-be-executed instruction according to the first field, the second field, the third field, and an operation code and an addressing mode field included in the to-be-executed instruction if it is determined that the second field and the third field are extracted from the to-be-executed instruction, and execute the to-be-executed instruction according to the first field, the operation code and the addressing mode field if it is determined that the second field and the third field are not extracted from the to-be-executed instruction.

[0018] In a possible implementation, the first field includes a first bit field for marking an opcode mapping of the to-be-executed instruction, and the decoding unit is configured to: determine whether the first bit field is a first value; if it is determined that the first bit field is the first value, determine not to extract the second field and the third field from the to-be-executed instruction; and if it is determined that the first bit field is a value different from the first value, determine to extract the second field and the third field from the to-be-executed instruction.

[0019] In a possible implementation, the execution unit is configured to: determine information about the variable-length vector register and the variable-length mask register according to the first field, the second field, and the third field; determine a function of the to-be-executed instruction according to the opcode; determine a source register and a destination register of the to-be-executed instruction according to the addressing mode field; and perform an operation corresponding to the function of the to-be-executed instruction on the to-be-executed instruction according to the information, the source register, and the destination register.

[0020] In a possible implementation, the first field further includes a second bit field for accessing an extended register resource, the second field includes a third bit field for identifying an addressing range and a fourth bit field for identifying a processing to be performed on an inactivated variable-length mask register, and the third field includes a fifth bit field for identifying an index of the variable-length mask register, and the execution unit is configured to: determine an addressable variable-length vector register according to the second bit field and the third bit field; determine a mask operation to be performed on an inactivated variable-length mask register according to the fourth bit field; and determine an activated variable-length mask register according to the fifth bit field.

[0021] In a possible implementation, the execution unit is configured to: obtain a source operand according to the source register; load a plurality of data elements in parallel according to the addressed variable-length vector register; perform an operation corresponding to the function of the to-be-executed instruction on the source operand and data elements in the loaded plurality of data elements that correspond to the activated variable-length mask register and need to participate in the operation, and perform the mask operation on the inactivated variable-length mask register.

[0022] In a possible implementation, the execution unit is configured to: if the operation code is a predetermined operation value, determine that a function of the to-be-executed instruction is a predetermined function, and perform a predetermined operation corresponding to the predetermined function on the to-be-executed instruction, where the predetermined operation includes an addition operation, a subtraction operation, a multiplication operation, a division operation, a shift operation, a logical and operation, a logical and not operation, a logical or operation, a logical same operation, a logical exclusive or operation, a bitwise not operation, an operation of performing a bitwise logical or operation on two source operands and setting a flag bit according to a result, a left shift operation, a right shift operation, a packed bit test mask and flag bit setting operation, or an unpack operation.

[0023] In a possible implementation, when the predetermined operation is the shift operation, the execution unit is configured to: if the operation code is a first operation value, perform, on the to-be-executed instruction, a source operand movement from a memory to the activated variable-length mask register; if the operation code is a second operation value, perform, on the to-be-executed instruction, a source operand movement from the activated variable-length mask register to the memory; if the operation code is a third operation value, perform, on the to-be-executed instruction, a source operand movement from a general-purpose vector register to the activated variable-length mask register; and if the operation code is a fourth operation value, perform, on the to-be-executed instruction, a source operand movement from the activated variable-length mask register to the general-purpose vector register.

[0024] In a possible implementation, the execution unit is configured to: determine a bit width of the shift operation of the variable-length mask register according to the flag bit of the first bit field and whether the to-be-executed instruction includes a prefix in which the third field has a preset value.

[0025] In a possible implementation, the execution unit is configured to: if the flag bit is 0 and the prefix in which the third field has the preset value is included, determine that the bit width of the shift operation is 1 byte; if the flag bit is 0 and the prefix in which the third field has the preset value is not included, determine that the bit width of the shift operation is 2 bytes; if the flag bit is 1 and the prefix in which the third field has the preset value is included, determine that the bit width of the shift operation is 4 bytes; and if the flag bit is 1 and the prefix in which the third field has the preset value is not included, determine that the bit width of the shift operation is 8 bytes.

[0026] In a possible implementation, the first field further includes a second bit field for accessing an extended register resource, and the execution unit is configured to: determine an addressable variable-length vector register according to the second bit field; determine a function of the to-be-executed instruction according to the operation code; determine a source register and a destination register of the to-be-executed instruction according to the addressing mode field; and perform an operation corresponding to the function of the to-be-executed instruction on the to-be-executed instruction according to the addressable variable-length vector register, the source register, and the destination register.

[0027] In a possible implementation, the first field includes a first bit field for marking an operation code mapping of the to-be-executed instruction, and the decoding unit is configured to: if a flag bit of the first bit field is a first flag value, determine that the to-be-executed instruction is a private variable-length vector instruction; and if the flag bit of the first bit field is a second flag value different from the first flag value, determine that the to-be-executed instruction is not the private variable-length vector instruction.

[0028] In a possible implementation, the instruction execution apparatus further includes an updating unit configured to update a load-and-operation instruction and a mask operation of the variable-length mask register.

[0029] In a possible implementation, the execution unit is configured to: if an exception occurs during execution of the to-be-executed instruction, report the exception to a system register.

[0030] According to a third aspect of the present disclosure, a processor is provided, which includes: 32 variable-length vector registers; 8 variable-length mask registers; 6 variable-length control registers; and the instruction execution apparatus described above.

[0031] By the instruction execution method and apparatus and the processor of the present disclosure, the instruction system architecture is improved, and a variable-length vector architecture is provided, by means of which, by virtue of the vec_len control register, the ele_len control register, and the vrnd control register, the x86 vector instruction can be extended in a new variable-length vector form, so that the portability of software can be improved, and on this basis, a new extended instruction format is defined, and the design of autonomous instruction space coding is completed, so that the instruction can be extended more simply. In addition, by virtue of the vgpr_len control register and the vmtx_len control register, the matrix tensor operation extension can be implemented.

[0032] Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments with reference to the drawings. BRIEF DESCRIPTION OF DRAWINGS

[0033] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments, features, and aspects of the present disclosure and serve to explain the principles of the present disclosure.

[0034] Figure 1 A flowchart illustrating a method of instruction execution 100 according to an embodiment of the present disclosure is shown.

[0035] Figure 2 A schematic diagram illustrating a variable length vector architecture 200 according to an embodiment of the present disclosure is shown.

[0036] Figure 3 A format schematic diagram of a variable length vector according to an embodiment of the present disclosure is shown.

[0037] Figure 4 A format schematic diagram of a general instruction extension according to an embodiment of the present disclosure is shown.

[0038] Figure 5 A format schematic diagram of a vector instruction extension according to an embodiment of the present disclosure is shown.

[0039] Figure 6 A schematic diagram of an ISA extension approach according to an embodiment of the present disclosure is shown.

[0040] Figure 7 A schematic diagram of a micro-architecture SIMD according to an embodiment of the present disclosure is shown.

[0041] Figure 8 A schematic diagram of a micro-architecture decoder according to an embodiment of the present disclosure is shown.

[0042] Figure 9 An example of a variable length masked register load and operation class instruction according to an embodiment of the present disclosure is shown.

[0043] Figure 10 A variable length masked register MOV instruction according to an embodiment of the present disclosure is shown.

[0044] Figure 11 A block diagram of an instruction execution apparatus according to an embodiment of the present disclosure is shown.

[0045] Figure 12 A block diagram of a processor according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0046] Various exemplary embodiments, features, and aspects of the present disclosure will be explained in detail below with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements or elements having a similar function. Although various aspects of embodiments are illustrated in the drawings, the drawings are not necessarily drawn to scale unless specifically noted.

[0047] As used herein, the terms “comprising,” “including,” “having,” or variations thereof are open-ended and include one or more of the stated features, integrals, elements, steps, components, or functions, but do not exclude the presence or addition of one or more other features, integrals, elements, steps, components, functions, or groups thereof.

[0048] When an element is referred to as “connected,” “coupled,” “responding,” or a variation thereof relative to another element, it may be directly connected, coupled, or responding to another element, or there may be an intermediate element present.

[0049] Although the terms first, second, third, etc., may be used herein to describe various elements / operations, these elements / operations should not be limited by these terms. These terms are only used to distinguish one element / operation from another. Therefore, without departing from the teachings of the inventive concept, a first element / operation in some embodiments may be referred to as a second element / operation in other embodiments.

[0050] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0051] Furthermore, to better illustrate this disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art will understand that this disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main points of this disclosure.

[0052] A preferred embodiment

[0053] Figure 1 A flowchart of an instruction execution method 100 according to an embodiment of the present disclosure is shown. In some embodiments, the instruction execution method 100 can be applied to a processor, such as... Figure 12 The processor is 1200. For example... Figure 12 As shown, the processor 1200 may include a register 1210, a decoding unit 1220, and an execution unit 1230.

[0054] Register 1210 can be Figure 2The shown variable length vector architecture, i.e. the registers 1210 can include control registers 210, variable length mask registers 220 and variable length vector registers 230. The control registers 210 can include 6 control registers as follows: vimp_len control register 211, vec_len control register 212, ele_len control register 213, vgpr_len control register 214, vmtx_len control register 215, and vrnd control register 216.

[0055] The vimp_len control register 211 indicates what is the maximum length supported by the vector machine, which can be set to 128 bits, 256 bits, 512 bits. The vec_len control register 212 indicates how many lengths can be operated at one time by the vector machine, which can be set to 4 bits, 8 bits, 16 bits, 32 bits, 64 bits, 128 bits, 256 bits, 512 bits, 1024 bits, 2048 bits, 4096 bits, 8192 bits, 16348 bits, 32768 bits, etc. The ele_len control register 213 indicates what is the length of each element in a vector, such as 4 bits, 8 bits, 16 bits, 32 bits, 64 bits. Through the vimp_len control register 211, the vec_len control register 212, and the ele_len control register 213, the length and size of the variable length vector (LVV) can be controlled.

[0056] The vgpr_len control register 214 indicates the number of times of vector machine operation, such as 2, which means operating 2 times, the first time sending group 0, the second time sending group 1, and operating by the two groups. The vmtx_len control register 215 indicates the length and width of the matrix, such as 2 4, 2 8, if matrix operation is performed, the length and width of the matrix need to be specified. Through the vgpr_len control register 214 and the vmtx_len control register 215, the matrix tensor operation extension can be performed.

[0057] The vrnd control register (Rounding mode) 216 is used to indicate the rounding mode. Through the vrnd control register 216, the rounding mode control can be performed.

[0058] As Figure 2As shown, the variable-length mask register (Lane mask Register) 220 can include 8 variable-length mask registers Ln0 register 221~Ln7 register 228, and for a certain instruction, which one of the 8 variable-length mask registers is selected to be used, such as Ln0 register 221. Among them, the length of the variable-length mask register 220 is equal to the value set by the vec_len control register 212 / the value set by the ele_len control register 213, such as if the vec_len control register 212 is set to 128 bits and the ele_len control register 213 is set to 16 bits, the length of the variable-length mask register 220 is 128 / 16=8, bit 0 control element 0, bit 1 control element 1, bit 2 control element 2…bit 7 control element 8, if the corresponding bit is 1, the value of the element corresponding to the bit is sent out to participate in the operation, if it is addition, the value of the element corresponding to the bit is added, if it is subtraction, the value of the element corresponding to the bit is subtracted; if the corresponding bit is 0, the value of the element corresponding to the bit does not participate in the operation.

[0059] A new group of register types is defined: for example, 0101 represents that the variable-length mask register 220 needs to be accessed at present. The variable-length mask register 220 has a total of 8, each of which is 64 bits, and the specific coding needs to be synchronized with the RAT later.

[0060] As shown in the figure, Figure 2 The variable-length vector register (Vector Register) 230 can include V0 register 231~…V31 register 262, a total of 32 variable-length vector registers, and the length of the variable-length vector register 230 is equal to the value set by the vimp_len control register 211. A new group of register types is defined: for example, 1010 represents that the variable-length vector register 230 needs to be accessed at present. The variable-length vector register 230 has a total of 32, each of which is 128 bits, and can be set by the vimp_len control register 211.

[0061] In a preferred embodiment, as shown in the figure, Figure 1 The instruction execution method 100 can include the following steps:

[0062] In step S110, it is identified whether the to-be-executed instruction includes an extended instruction prefix D6.

[0063] In some embodiments, the to-be-executed instruction can be a vector extended instruction or a normal extended instruction, as shown in the figure, Figure 3As shown, the extended instruction 300 can include a vector extended instruction 310 and a normal extended instruction 320. The vector extended instruction 310 includes a prefix, an extended instruction prefix D6, a P0 field, a P1 field, a P2 field, an opcode, a Mod M / R field, an immediate value, and a shift. The normal extended instruction 320 includes a prefix, an extended instruction prefix D6, a P0 field, an opcode, a Mod M / R field, an immediate value, and a shift. Therefore, the extended instruction 300 has a D6 prefix, and the only difference between the two extended instructions is whether or not the P1 and P2 fields are included.

[0064] Considering that instruction execution method 100 targets extended instructions, while non-extended instructions should be executed according to existing instruction execution methods, the decoding unit 1220 can identify the instruction to be executed to determine whether it has a D6 prefix, thereby determining whether the instruction to be executed is an extended instruction. If it is determined that the instruction to be executed has a D6 prefix, then the instruction to be executed is an extended instruction and needs to be executed according to instruction execution method 100, and the process proceeds to step S130 below. If it is determined that the instruction to be executed does not have a D6 prefix, then the instruction to be executed is not an extended instruction, and it is not necessary to execute the instruction to be executed according to instruction execution method 100. The instruction to be executed can be executed according to existing instruction execution methods. For example, for this instruction to be executed, instruction execution method 100 can be terminated.

[0065] In step S130, a first field (P0 field) for marking the opcode mapping of the instruction to be executed is extracted from the instruction to be executed.

[0066] In some embodiments, the decoding unit 1220 can decode the instruction to be executed in order to extract the P0 field from the instruction to be executed.

[0067] like Figure 3 As shown, the P0 field may include an opmap bit field for marking opcode mapping, a W bit field for defining the granularity (size) of data types, and an RXB bit field. The opmap bit field has a width of 4 bits, the W bit field has a width of 1 bit, and the RXB (Register eXtension Bits) bit field has a width of 3 bits. It is used to access extended register resources. The R bit is used to extend the destination register index, and the X / B bits are used to extend the base / index register index. By combining the RXB bits, 4-bit addressing of a total of 16 general-purpose registers (GPRs) can be achieved. Therefore, the P0 field has a total of 8 bits, of which P0[7:4] is the opmap bit field, P0[3] is the W bit field, and P0[2:0] is the RXB bit field.

[0068] If P0[7:4] is 0000, it represents a 1-byte opcode with only the P0 field and no P1 or P2 fields; if P0[7:4] is 0001, the instruction is 0x0F, which is not a proprietary variable-length vector instruction, such as being compatible with Intel instructions; if P0[7:4] is 0010, the instruction is 0x0F 38, which is not a proprietary variable-length vector instruction, such as being compatible with Intel instructions; if P0[7:4] is 0011, the instruction is 0x0F 3A, which is not a proprietary variable-length vector instruction, such as being compatible with Intel instructions; if P0[7:4] is 1000, it represents a 1-byte opcode with complete P0, P1, and P2 fields, and the instruction is an extended instruction and a vector extended instruction; if P0[7:4] is 1001, the instruction is 0x0F, and the instruction is an LVV instruction; if P0[7:4] is 1010, the instruction is 0x0F. 38, at this time the instruction is LVV instruction; if P0[7:4] is 1011, the instruction is 0x0F 3A, at this time the instruction is LVV instruction; if P0[7:4] is any other value, the instruction is a reserved value.

[0069] For example, such as Figure 6 As shown, the instruction extension method is determined by the value of P0[7]. If P0[7] is 1, the instruction is the instruction extension of this embodiment. The extended instruction can be determined by the value of P0[6:4]. For example, if P0[6:4] is 000, it represents 1 byte opcode; if P0[6:4] is 001, it represents 2 bytes 0fxx; if P0[6:4] is 010, it represents 3 bytes 0f38; if P0[6:4] is 011, it represents 3 bytes 0f3A. If P0[7] is 0, then the instruction is not a private variable-length vector instruction, such as a compatible Intel instruction, and the compatible instruction can be determined according to the value of P0[6:4]. For example, if P0[6:4] is 001, it means 2 bytes 0fxx; if P0[6:4] is 010, it means 3 bytes 0f38; if P0[6:4] is 011, it means 3 bytes 0f3A.

[0070] In step S150, it is judged according to the first field (P0 field) whether to extract the second field (P1 field) related to a variable-length vector register and the third field (P2 field) related to a variable-length mask register from the to-be-executed instruction, wherein the variable-length vector register is used for vector operation, the variable-length mask register is used for mask control, and the variable-length mask register contains the same number of flag bits as the variable-length vector register stores data, which is used to mark whether the corresponding data in the variable-length vector register participates in the calculation execution.

[0071] In some embodiments, as shown in FIG. 4, P0[7:4] is 0000, and the extended instruction 400 only has the P0 field but does not have the P1 field and the P2 field; as shown in FIG. 5, P0[7:4] is 1000 or 1001, and the extended instruction 500 has the P0 field, the P1 field and the P2 field. Therefore, it can be determined according to the value of P0[7:4] whether to extract the P1 field and the P2 field from the to-be-executed instruction. Figure 4 Figure 5 In some embodiments, as shown in FIG. 4, P0[7:4] is 0000, and the extended instruction 400 only has the P0 field but does not have the P1 field and the P2 field; as shown in FIG. 5, P0[7:4] is 1000 or 1001, and the extended instruction 500 has the P0 field, the P1 field and the P2 field. Therefore, it can be determined according to the value of P0[7:4] whether to extract the P1 field and the P2 field from the to-be-executed instruction.

[0072] In some embodiments, the decoding unit 1220 can judge whether the first bit field P0[7:4] is a first value according to whether a certain bit or certain bits of the first bit field (P0[7:4]) included in the first field (P0 field) is / are 1; if it is judged that the certain bit or certain bits of the first bit field is / are not 1, it is judged that the first bit field is the first value, and if it is judged that the certain bit or certain bits of the first bit field is / are all 1, it is judged that the first bit field is a value different from the first value.

[0073] For example, the decoding unit 1220 can judge whether P0[7:4] is the first value according to whether P0[4] is 1; if P0[4] is 1, it is judged that P0[7:4] is a value different from the first value; and if P0[4] is 0, it is judged that P0[7:4] is the first value.

[0074] For another example, the decoding unit 1220 can judge whether P0[7:4] is the first value according to whether P0[7] and P0[4] are both 1; if P0[7] and P0[4] are both 1, it is judged that P0[7:4] is a value different from the first value; and if P0[7] and P0[4] are both 0, it is judged that P0[7:4] is the first value.

[0075] ​In one possible implementation, the decoding unit 1220 can determine whether P0[7:4] is a first value (e.g., 0000); if it is determined that P0[7:4] is a first value, then it is determined that the P1 field and P2 field will not be extracted from the instruction to be executed, and step S150 is determined to be "no", and the following step S190 is executed; if it is determined that P0[7:4] is a value other than the first value (e.g., 1000 or 1001), then it is determined that the P1 field and P2 field will be extracted from the instruction to be executed, and step S150 is determined to be "yes", and the following step S170 is executed.

[0076] In step S170, the instruction to be executed is executed according to the first field (P0 field), the second field (P1 field), the third field (P2 field), and the opcode and addressing mode field (ModR / M field) included in the instruction to be executed.

[0077] In some embodiments, the decoding unit 1220 can determine information related to the variable-length vector register 230 and the variable-length mask register 220 based on the P0, P1, and P2 fields; determine the function of the instruction to be executed based on the opcode; determine the operation to be performed on the instruction to be executed based on the ModR / M field; and perform the operation corresponding to the function of the instruction to be executed based on this information, the source register, and the destination register. The method by which the decoding unit 1220 determines the function of the instruction to be executed based on the opcode and determines the source register and destination register based on the ModR / M field will not be described in detail here.

[0078] like Figure 3 As shown, the P1 field includes the VVVV bit field, the R'X' bit field, and the M / Z bit field. The VVVV bit field has a width of 5 bits and is used to define the third operand. With the help of the VVVV bit field, the existing two operands, such as the first operand and the second operand, can be extended to three operands, such as the first operand, the second operand, and the third operand. The R'X' bit field has a width of 2 bits. By combining the R'X' bits, 5-bit addressing of a total of 32 general-purpose registers (GPRs) can be achieved. The M / Z bit field has a width of 1 bit and is used to define the masking operation of the inactive variable-length mask registers in the variable-length mask register 220. If the M / Z bit field is set to 1, the value of the inactive variable-length mask register corresponding to the original destination register is maintained. If the M / Z bit field is set to 0, the value of the inactive variable-length mask register corresponding to the original destination register is cleared. Therefore, the P1 field has a total of 8 bits, of which P1[7:3] is the VVVV bit field, P1[2:1] is the R'X' bit field, and P1[0] is the M / Z bit field.

[0079] likeFigure 3 As shown, the P2 field includes an Ln field, a pref field, an app field, an RSV field, the Ln field has a bit width of 3 bits, which is used to define which one of the variable length mask registers in the variable length mask registers 220 is used. The pref field has a bit width of 2 bits, which represents a compression field. The app field has a bit width of 1 bit, which represents a factor processing field. The RSV field has a bit width of 2 bits, which represents a reserved field. Therefore, the P2 field has a total of 8 bits, wherein P2[7:5] is the Ln field, P2[4:3] is the pref field, P2[2] is the app field, and P2[1:0] is the RSV field. If P2[4:3] is set to 00, no compression is performed, if P2[4:3] is set to 01, the compression field takes a value of 66, if P2[4:3] is set to 10, the compression field takes a value of F3, and if P2[4:3] is set to 11, the compression field takes a value of F2.

[0080] The decoding unit 1220 can determine the addressable variable length vector register according to the RXB field and the R'X' field, determine which one of the variable length mask registers 220 in the activated variable length mask registers according to the Ln field, and determine the mask operation to be performed on the non-activated variable length mask registers in the variable length mask registers 220 according to the M / Z field. Thus, the register extension (i.e., the addressable variable length vector register) of the vector instruction, the mask control (zero or keep original value), and the variable length mask register to be used can be determined, and further, the information related to the variable length vector register 230 and the variable length mask register 220 can be determined.

[0081] The decoding unit 1220 can send the information to the execution unit 1230, and accordingly, the execution unit 1230 can use the information, the source operands obtained from the source registers, and the destination register to perform the operation corresponding to the function of the to-be-executed instruction.

[0082] In a possible implementation, the execution unit 1230 can obtain the source operands according to the source registers, load multiple data elements in parallel according to the addressable variable length vector register, perform the operation corresponding to the function of the to-be-executed instruction on the source operands and the data elements in the loaded multiple data elements corresponding to the activated variable length mask register and needing to participate in the operation, and perform the mask operation on the non-activated variable length mask register.

[0083] In step S190, the to-be-executed instruction is executed according to the first field (the P0 field), the operation code opcode, and the addressing mode field (the ModR / M field).

[0084] In some embodiments, the execution unit 1230 may determine the addressable variable-length vector register based on the RXB bit field; determine the function of the instruction to be executed based on the opcode to determine the operation to be performed on the instruction to be executed; determine the source register and destination register of the instruction to be executed based on the ModR / M field; and perform the operation corresponding to the function of the instruction to be executed based on the addressable variable-length vector register, source register, and destination register.

[0085] In one possible implementation, the execution unit 1230 can obtain the source operand from the source register; load multiple data elements in parallel from the addressed variable-length vector register; and perform operations on the source operand and the loaded multiple data elements corresponding to the function of the instruction to be executed.

[0086] In some embodiments, such as Figure 7 As shown, the execution unit 1230 can perform coordinated operations on the variable-length vector register 230 and the variable-length mask register 220 to achieve efficient parallel computing. During the vector operation phase, the variable-length vector register 230 supports multiple data types by configuring its bit width. For example, a single 2048-bit register can store 32 64-bit double-precision floating-point numbers or 256 8-bit integers. The execution unit 1230 reads multiple data elements from the variable-length vector register 230 in parallel and performs SIMD operations according to the opcode type (such as ADD / MUL). The register file adopts a multi-bank design, providing sufficient bandwidth to meet the parallel data requirements through cross-access. During the mask control phase, each bit of the variable-length mask register 220 corresponds to a data element of the variable-length vector register 230. 1 indicates that the operation at that position is activated, and 0 indicates that it is suppressed. The mask operation supports conditional execution, such as performing arithmetic operations only on elements that meet the comparison conditions. The dynamic mask length is automatically synchronized with the bit width of the variable-length vector register 230 to ensure operation alignment.

[0087] In some embodiments, such as Figure 8 As shown, matrix tensor operations can be extended through the vgpr_len control register 214 and vmtx_len control register 215. When a vector group is used, if the original encoding register is not divisible by the number of corresponding groups, a report needs to be submitted for general exception handling.

[0088] According to this embodiment, the instruction system architecture is improved, and provides... Figure 2 The variable-length vector architecture shown, with the help of this architecture, such as Figure 7As shown, the x86 vector instructions can be extended in the new variable-length vector form by the vec_len control register 212, the ele_len control register 213 and the vrnd control register 216, so as to improve the software portability (Write Once, Run Anywhere), and on this basis, the new extended instruction format 300 is defined Figure 3 As shown, the new extended instruction format 300 is designed to complete the autonomous instruction space coding, so as to more simply extend the instruction. In addition, as Figure 8 As shown, the matrix tensor operation extension can be implemented by the vgpr_len control register 214 and the vmtx_len control register 215.

[0089] In a possible implementation, the operation corresponding to the function of the to-be-executed instruction includes: if the operation code is a predetermined operation value, it is determined that the function of the to-be-executed instruction is a predetermined function, and the to-be-executed instruction is subjected to a predetermined operation corresponding to the predetermined function, wherein the predetermined operation includes addition operation (LNADD), subtraction operation (LNSUB), multiplication operation (LNMUL), division operation (LNDIV), shift operation (LNMOV), logical and operation (LNAND), logical and not operation (LNANDN), logical or operation (LNOR), logical exclusive or operation (LNXNOR), logical exclusive or operation (LNXOR), bitwise not operation (LNNOT), bitwise logical or operation on two source operands and setting flag according to the result (LNORTEST), left shift operation (LNSHIFTL), right shift operation (LNSHIFTR), packed bit test mask and flag setting operation (LNTEST), or unpacking operation (LNUNPCK).

[0090] In some embodiments, the to-be-executed instruction can include but is not limited to Figure 9 As shown, the LNADD instruction, the LNSUB instruction, the LNMUL instruction, the LNDIV instruction, the LNMOV instruction, the LNAND instruction, the LNANDN instruction, the LNOR instruction, the LNXNOR instruction, the LNXOR instruction, the LNNOT instruction, the LNORTEST instruction, the LNSHIFTL instruction, the LNSHIFTR instruction, the LNTEST instruction, and the LNUNPCK instruction, and the like operation instruction. Each operation instruction has a corresponding operation code, which can be used to uniquely identify the type of operation instruction. Therefore, according to the operation code for what operation value, it can be determined which one of the above operation instructions is the to-be-executed instruction, and the to-be-executed instruction is subjected to the operation corresponding to the operation instruction.

[0091] For example, if the operation code is an operation value corresponding to the LNADD instruction, it is determined that the to-be-executed instruction is the LNADD instruction, and the to-be-executed instruction can be subjected to an ADD operation (addition operation, such as an addition operation on two source operands, ADD Two Masks). The LNADD instruction includes an LNADDW instruction, an LNADDB instruction, an LNADDQ instruction, and an LNADDD instruction, which respectively represent addition of two 16-bit source operands, addition of two 8-bit source operands, addition of two 64-bit source operands, and addition of two 32-bit source operands. It can be seen that W / B / D / Q represent operands of different bit widths, W represents 2 bytes (16 bits), B represents 1 byte (8 bits), D represents 8 bytes (64 bits), and Q represents 4 bytes (32 bits).

[0092] If the operation code is an operation value corresponding to the LNSUB instruction, it is determined that the to-be-executed instruction is the LNSUB instruction, and the to-be-executed instruction can be subjected to a SUB operation (subtraction operation, such as a subtraction operation on two source operands, SUB Two Masks). The LNSUB instruction includes an LNSUBW instruction, an LNSUBB instruction, an LNSUBQ instruction, and an LNSUBD instruction, which respectively represent subtraction of two 16-bit source operands, subtraction of two 8-bit source operands, subtraction of two 64-bit source operands, and subtraction of two 32-bit source operands.

[0093] If the operation code is an operation value corresponding to the LNMUL instruction, it is determined that the to-be-executed instruction is the LNMUL instruction, and the to-be-executed instruction can be subjected to a MUL operation (multiplication operation, such as a multiplication operation on two source operands, MUL Two Masks). The LNMUL instruction includes an LNMULW instruction, an LNMULB instruction, an LNMULQ instruction, and an LNMULD instruction, which respectively represent multiplication of two 16-bit source operands, multiplication of two 8-bit source operands, multiplication of two 64-bit source operands, and multiplication of two 32-bit source operands.

[0094] If the operation code is an operation value corresponding to the LNDIV instruction, it is determined that the to-be-executed instruction is the LNDIV instruction, and the to-be-executed instruction can be subjected to a DIV operation (division operation, such as a division operation on two source operands, DIV Two Masks). The LNDIV instruction includes an LNDIVW instruction, an LNDIVB instruction, an LNDIVQ instruction, and an LNDIVD instruction, which respectively represent division of two 16-bit source operands, division of two 8-bit source operands, division of two 64-bit source operands, and division of two 32-bit source operands.

[0095] If the operation code is the operation value corresponding to the LNMOV instruction, it is determined that the to-be-executed instruction is the LNMOV instruction, and the MOV operation (move operation, such as move operation on the source operand, Move From and to Mask Registers) can be performed on the to-be-executed instruction. The LNMOV instruction includes the LNMOVW instruction, the LNMOVB instruction, the LNMOVQ instruction, and the LNMOVD instruction, which respectively represent the move operation on the 16-bit source operand, the move operation on the 8-bit source operand, the move operation on the 64-bit source operand, and the move operation on the 32-bit source operand.

[0096] If the operation code is the operation value corresponding to the LNAND instruction, it is determined that the to-be-executed instruction is the LNAND instruction, and the AND operation (logical AND operation, such as logical AND operation on two source operands, Bitwise Logical AND Masks) can be performed on the to-be-executed instruction. The LNAND instruction includes the LNANDW instruction, the LNANDB instruction, the LNANDQ instruction, and the LNANDD instruction, which respectively represent the logical AND operation on the 16-bit source operand, the logical AND operation on the 8-bit source operand, the logical AND operation on the 64-bit source operand, and the logical AND operation on the 32-bit source operand.

[0097] If the operation code is the operation value corresponding to the LNANDN instruction, it is determined that the to-be-executed instruction is the LNANDN instruction, and the ANDN operation (logical AND NOT operation, such as logical AND NOT operation on two source operands, Bitwise Logical AND NOT Masks) can be performed on the to-be-executed instruction. The LNANDN instruction includes the LNANDNW instruction, the LNANDNB instruction, the LNANDNQ instruction, and the LNANDND instruction, which respectively represent the logical AND NOT operation on the 16-bit source operand, the logical AND NOT operation on the 8-bit source operand, the logical AND NOT operation on the 64-bit source operand, and the logical AND NOT operation on the 32-bit source operand.

[0098] If the operation code is the operation value corresponding to the LNOR instruction, it is determined that the to-be-executed instruction is the LNOR instruction, and the OR operation (logical OR operation, such as logical OR operation on two source operands, Bitwise Logical OR Masks) can be performed on the to-be-executed instruction. The LNOR instruction includes the LNORW instruction, the LNORB instruction, the LNORQ instruction, and the LNORD instruction, which respectively represent the logical OR operation on the 16-bit source operand, the logical OR operation on the 8-bit source operand, the logical OR operation on the 64-bit source operand, and the logical OR operation on the 32-bit source operand.

[0099] If the opcode is the op value corresponding to the LNXNOR instruction, then the instruction to be executed is determined to be an LNXNOR instruction, and an XNOR operation (logical XNOR operation, such as performing a logical XNOR operation on two source operands, Bitwise Logical XNOR Masks) can be performed on the instruction to be executed. The LNXNOR instructions include LNXNORW, LNXNORB, LNXNORQ, and LNXNORD instructions, which respectively represent performing a logical XNOR operation on 16-bit source operands, 8-bit source operands, 64-bit source operands, and 32-bit source operands.

[0100] If the opcode is the op value corresponding to the LNXOR instruction, then the instruction to be executed is determined to be an LNXOR instruction, which can perform an XOR operation (logical XOR operation, such as performing a logical XOR operation on two source operands, Bitwise Logical XOR Masks) on the instruction to be executed. The LNXOR instructions include LNXORW, LNXORB, LNXORQ, and LNXORD instructions, which respectively represent performing a logical XOR operation on 16-bit source operands, 8-bit source operands, 64-bit source operands, and 32-bit source operands.

[0101] If the opcode is the op value corresponding to the LNNOT instruction, then the instruction to be executed is determined to be an LNNOT instruction, and a NOT operation (bitwise inversion, such as bitwise inversion of the source operand, NOTMask Register) can be performed on the instruction to be executed. The LNNOT instructions include LNNOTW, LNNOTB, LNNOTQ, and LNNOTD, which respectively represent bitwise inversion of a 16-bit source operand, a 8-bit source operand, a 64-bit source operand, and a 32-bit source operand.

[0102] If the operation code is the operation value corresponding to the LNORTEST instruction, it is determined that the to-be-executed instruction is the LNORTEST instruction, and the to-be-executed instruction can be subjected to the ORTEST operation (the operation of performing a bitwise logical OR operation on two source operands and setting a flag bit according to a result, OR Masks and Set Flags). The LNORTEST instruction includes the LNORTESTW instruction, the LNORTESTB instruction, the LNORTESTQ instruction, and the LNORTESTD instruction, which respectively represent performing a bitwise logical OR operation on two source operands of 16 bits and setting a flag bit according to a result, performing a bitwise logical OR operation on two source operands of 8 bits and setting a flag bit according to a result, performing a bitwise logical OR operation on two source operands of 64 bits and setting a flag bit according to a result, and performing a bitwise logical OR operation on two source operands of 32 bits and setting a flag bit according to a result.

[0103] If the operation code is the operation value corresponding to the LNSHIFTL instruction, it is determined that the to-be-executed instruction is the LNSHIFTL instruction, and the to-be-executed instruction can be subjected to the SHIFTL operation (a left shift operation, Shift Left Mask Registers). The LNSHIFTL instruction includes the LNSHIFTLW instruction, the LNSHIFTLB instruction, the LNSHIFTLQ instruction, and the LNSHIFTLD instruction, which respectively represent performing a left shift operation on a source operand of 16 bits, performing a left shift operation on a source operand of 8 bits, performing a left shift operation on a source operand of 64 bits, and performing a left shift operation on a source operand of 32 bits.

[0104] If the operation code is the operation value corresponding to the LNSHIFTR instruction, it is determined that the to-be-executed instruction is the LNSHIFTR instruction, and the to-be-executed instruction can be subjected to the SHIFTR operation (a right shift operation, Shift Right Mask Registers). The LNSHIFTR instruction includes the LNSHIFTRW instruction, the LNSHIFTRB instruction, the LNSHIFTRQ instruction, and the LNSHIFTRD instruction, which respectively represent performing a right shift operation on a source operand of 16 bits, performing a right shift operation on a source operand of 8 bits, performing a right shift operation on a source operand of 64 bits, and performing a right shift operation on a source operand of 32 bits.

[0105] If the operation code is an operation value corresponding to the LNTEST instruction, it is determined that the to-be-executed instruction is the LNTEST instruction, and the to-be-executed instruction can be subjected to a TEST operation (Packed Bit Test Masks and Set Flags). The LNTEST instruction includes an LNTESTW instruction, an LNTESTB instruction, an LNTESTQ instruction, and an LNTESTD instruction, which respectively represent that a 16-bit source operand is subjected to a packed bit test operation and a flag bit is set according to a result, an 8-bit source operand is subjected to a packed bit test operation and a flag bit is set according to a result, a 64-bit source operand is subjected to a packed bit test operation and a flag bit is set according to a result, and a 32-bit source operand is subjected to a packed bit test operation and a flag bit is set according to a result.

[0106] If the operation code is an operation value corresponding to the LNUNPCK instruction, it is determined that the to-be-executed instruction is the LNUNPCK instruction, and the to-be-executed instruction can be subjected to an UNPCK operation (Unpack for Mask Registers). The LNUNPCK instruction includes an LNUNPCKBW instruction, an LNUNPCKWD instruction, and an LNUNPCKDQ instruction, which respectively represent that an 8-bit source operand is unpacked into a 16-bit destination operand, a 16-bit source operand is unpacked into a 32-bit destination operand, and a 32-bit source operand is unpacked into a 64-bit destination operand.

[0107] In a possible implementation, when the predetermined operation is the moving operation (MOV instruction), the to-be-executed instruction is subjected to an operation corresponding to a function of the to-be-executed instruction, including: if the operation code is a first operation value (0x90), the to-be-executed instruction is subjected to an operation of moving a source operand from a memory to the activated variable-length mask register; if the operation code is a second operation value (0x91), the to-be-executed instruction is subjected to an operation of moving a source operand from the activated variable-length mask register to the memory; if the operation code is a third operation value (0x92), the to-be-executed instruction is subjected to an operation of moving a source operand from a general vector register to the activated variable-length mask register; and if the operation code is a fourth operation value (0x93), the to-be-executed instruction is subjected to an operation of moving a source operand from the activated variable-length mask register to the general vector register.

[0108] In certain embodiments, as Figure 10If the executable instruction is 0xd6 p0 p1 p2 0x90, the executable instruction corresponds to an operation class instruction of Mov mem / LNreg to LNreg, wherein Modrm:r / m specifies the source register and Modrm:reg specifies the destination register. If the executable instruction is 0xd6 p0 p1 p2 0x91, the executable instruction corresponds to an operation class instruction of Mov LNreg to mem, wherein Modrm:r / m specifies the source register and Modrm:reg specifies the destination register. If the executable instruction is 0xd6 p0 p1 p2 0x92, the executable instruction corresponds to an operation class instruction of Mov Greg to LNreg, wherein Modrm:r / m specifies the source register and Modrm:reg specifies the destination register. If the executable instruction is 0xd6 p0 p1 p2 0x93, the executable instruction corresponds to an operation class instruction of Mov LNreg to Greg, wherein Modrm:r / m specifies the source register and Modrm:reg specifies the destination register.

[0109] In a possible implementation, the instruction execution method 100 can further include: determining the bit width of the move operation of the variable-length mask register according to a flag bit (bit 3) of the first bit field and whether the to-be-executed instruction includes a prefix with the value of the third field being a preset value.

[0110] In the x86 architecture assembly language, MOV class instructions are used for data transfer operations, and are divided into the following types according to the bit width of the operands: MOVB (byte transfer), operating 8-bit data (1 byte); MOVW (word transfer), operating 16-bit data (2 bytes); MOVD (double word transfer), operating 32-bit data (4 bytes); MOVQ (quad word transfer), operating 64-bit data (8 bytes).

[0111] In some embodiments, for the LNmov class instruction, the bit width of the operand can be determined to be one of 1 byte, 2 bytes, 4 bytes and 8 bytes according to whether P0[7] and P2[4:3] are set to 01.

[0112] In a possible implementation, if P0[7] is 0 and the compressed bit field takes the value 66, the bit width of the move operation is 1 byte, the instruction is an LNmovB instruction; if P0[7] is 0 and the compressed bit field does not take the value 66, the bit width of the move operation is 2 bytes, the instruction is an LNmovW instruction; if P0[7] is 1 and the compressed bit field takes the value 66, the bit width of the move operation is 4 bytes, the instruction is an LNmovD instruction; if P0[7] is 1 and the compressed bit field does not take the value 66, the bit width of the move operation is 8 bytes, the instruction is an LNmovQ instruction.

[0113] In a possible implementation, the instruction execution method 100 can further include updating the load and operation instruction and the mask operation of the variable-length mask register.

[0114] In some embodiments, the updating of the load and operation instruction and the mask operation of the variable-length mask register 220 can include, but is not limited to Figure 9 the example shown.

[0115] In a possible implementation, the instruction execution method 100 can further include reporting an exception to a system register if the exception occurs during execution of the to-be-executed instruction.

[0116] In some embodiments, during execution of the to-be-executed instruction by the execution unit 1230, if an exception such as a precision exception occurs, the execution unit 1230 can generate an Ldlvcsr instruction, where the bit width of the Ldlvcsr instruction is 32 bits, [6:0] represents the cause of the exception, [12:7] represents whether the exception is masked, [14:13] represents a rounding control, and [31:15] represents a reserved RSV. Thus, the exception is reported to the system register by means of the Ldlvcsr instruction, and the cause of the exception can be determined according to [6:0] of the instruction, so that the exception can be processed in a corresponding manner. Details of processing the exception are not described herein.

[0117] A preferred embodiment

[0118] Figure 11 A block diagram of an instruction execution apparatus 1100 according to an embodiment of the present disclosure is shown. As Figure 11 shown, the instruction execution apparatus 1100 can include a decoding unit 1110 and an execution unit 1120.

[0119] The decoding unit 1110 is configured to identify whether an instruction to be executed comprises an extended instruction prefix, extract a first field for marking an opcode map of the instruction to be executed from the instruction to be executed if the instruction to be executed comprises the extended instruction prefix, and determine whether to extract a second field related to a variable-length vector register and a third field related to a variable-length mask register from the instruction to be executed according to the first field, wherein the variable-length vector register is used for vector operation, and the variable-length mask register is used for mask control, and the variable-length mask register contains the same number of marking bits as the variable-length vector register stores data, and is used for marking whether corresponding data in the variable-length vector register participates in calculation execution.

[0120] The execution unit 1120 is configured to execute the instruction to be executed according to the first field, the second field, the third field, and an opcode and an addressing mode field comprised in the instruction to be executed if the second field and the third field are extracted from the instruction to be executed, and execute the instruction to be executed according to the first field, the opcode, and the addressing mode field if the second field and the third field are not extracted from the instruction to be executed.

[0121] In a possible implementation, the first field comprises a first bit field for marking an opcode map of the instruction to be executed, and the decoding unit 1110 is configured to determine whether the first bit field is a first value, determine that the second field and the third field are not extracted from the instruction to be executed if it is determined that the first bit field is the first value, and determine that the second field and the third field are extracted from the instruction to be executed if it is determined that the first bit field is a value different from the first value.

[0122] In a possible implementation, the execution unit 1120 is configured to determine information related to the variable-length vector register and the variable-length mask register according to the first field, the second field, and the third field, determine a function of the instruction to be executed according to the opcode, determine a source register and a destination register of the instruction to be executed according to the addressing mode field, and perform an operation corresponding to the function of the instruction to be executed on the instruction to be executed according to the information, the source register, and the destination register.

[0123] In a possible implementation, the first field further includes a second bit field for accessing an extended register resource, the second field includes a third bit field for accessing the extended register resource and a fourth bit field for identifying a processing to be performed on an inactivated variable-length mask register, the third field includes a fifth bit field for identifying an index of the variable-length mask register, and the execution unit 1120 is configured to: determine an addressable variable-length vector register according to the second bit field and the third bit field; determine a mask operation to be performed on the inactivated variable-length mask register according to the fourth bit field; and determine the activated variable-length mask register according to the fifth bit field.

[0124] In a possible implementation, the execution unit 1120 is configured to: obtain a source operand according to the source register; load a plurality of data elements in parallel according to the addressable variable-length vector register; and perform an operation corresponding to the function of the to-be-executed instruction on the source operand and data elements in the loaded plurality of data elements that correspond to the activated variable-length mask register and need to participate in the operation, and perform the mask operation on the inactivated variable-length mask register.

[0125] In a possible implementation, the execution unit 1120 is configured to: if the operation code is a predetermined operation value, determine that the function of the to-be-executed instruction is a predetermined function, and perform a predetermined operation corresponding to the predetermined function on the to-be-executed instruction, where the predetermined operation includes an addition operation, a subtraction operation, a multiplication operation, a division operation, a shift operation, a logical AND operation, a logical NAND operation, a logical OR operation, a logical XNOR operation, a logical XOR operation, a bitwise NOT operation, an operation of performing a bitwise logical OR operation on two source operands and setting a flag bit according to a result, a left shift operation, a right shift operation, a packed bit test mask and flag setting operation, or an unpack operation.

[0126] In a possible implementation, when the predetermined operation is the shift operation, the execution unit 1120 is configured to: if the operation code is a first operation value, perform a move operation of moving a source operand from a memory to the activated variable-length mask register on the to-be-executed instruction; if the operation code is a second operation value, perform a move operation of moving a source operand from the activated variable-length mask register to the memory on the to-be-executed instruction; if the operation code is a third operation value, perform a move operation of moving a source operand from a general-purpose vector register to the activated variable-length mask register on the to-be-executed instruction; and if the operation code is a fourth operation value, perform a move operation of moving a source operand from the activated variable-length mask register to the general-purpose vector register on the to-be-executed instruction.

[0127] In a possible implementation, the execution unit 1120 is configured to determine the bit width of the move operation of the variable-length mask register according to the flag bit of the first bit field and whether the to-be-executed instruction includes the prefix with the preset value of the third field.

[0128] In a possible implementation, the execution unit 1120 is configured to determine the bit width of the move operation as 1 byte if the flag bit is 0 and the prefix with the preset value is included, determine the bit width of the move operation as 2 bytes if the flag bit is 0 and the prefix with the preset value is not included, determine the bit width of the move operation as 4 bytes if the flag bit is 1 and the prefix with the preset value is included, and determine the bit width of the move operation as 8 bytes if the flag bit is 1 and the prefix with the preset value is not included.

[0129] In a possible implementation, the first field further includes a second bit field for accessing an extended register resource, and the execution unit 1120 is configured to determine an addressable variable-length vector register according to the second bit field, determine the function of the to-be-executed instruction according to the operation code, determine the source register and the destination register of the to-be-executed instruction according to the addressing mode field, and perform an operation corresponding to the function of the to-be-executed instruction on the to-be-executed instruction according to the addressable variable-length vector register, the source register and the destination register.

[0130] In a possible implementation, the first field includes a first bit field for marking the operation code mapping of the to-be-executed instruction, and the decoding unit 1110 is configured to determine that the to-be-executed instruction is a private variable-length vector instruction if the flag bit of the first bit field is a first flag value, and determine that the to-be-executed instruction is not the private variable-length vector instruction if the flag bit of the first bit field is a second flag value different from the first flag value.

[0131] In a possible implementation, the instruction execution apparatus 1100 further includes an updating unit (not shown) configured to update the load and operation instruction and the mask operation of the variable-length mask register.

[0132] In a possible implementation, the execution unit 1120 is configured to report an exception to a system register if the exception occurs during the execution of the to-be-executed instruction.

[0133] In some embodiments, the apparatus provided by the embodiments of the present disclosure has functions or includes modules that can be used to perform the methods described in the above method embodiments, and the specific implementation can refer to the description of the above method embodiments. For brevity, details are not repeated here.

[0134] Having described above several embodiments of the disclosure, any modifications and variations that fall within the scope of the described embodiments are also contemplated. It is also contemplated that the application covered by the claims extends to any alternative combination of claim elements not specifically disclosed. The use of the terms "preferably," "preferably," "preferred," and "has been preferred" in the description above indicates that the described feature is but one replacement for the term "the technology."

Claims

1. A method of instruction execution, the method comprising: The method comprises: identifying whether an instruction to be executed comprises an extended instruction prefix; if the instruction to be executed comprises the extended instruction prefix, extracting a first field for indicating an opcode map of the instruction to be executed from the instruction to be executed; judging whether a second field related to a variable-length vector register and a third field related to a variable-length mask register are extracted from the instruction to be executed according to the first field, wherein the variable-length vector register is used for vector operation and the variable-length mask register is used for mask control; if it is judged that the second field and the third field are extracted from the instruction to be executed, executing the instruction to be executed according to the first field, the second field, the third field, and an opcode and an addressing mode field comprised in the instruction to be executed; if it is judged that the second field and the third field are not extracted from the instruction to be executed, executing the instruction to be executed according to the first field, the opcode and the addressing mode field.

2. The method according to claim 1, wherein the first field comprises a first bit field for indicating the opcode map of the instruction to be executed, and the judging whether the second field and the third field are extracted from the instruction to be executed according to the first field comprises: judging whether the first bit field is a first value; if it is judged that the first bit field is the first value, judging that the second field and the third field are not extracted from the instruction to be executed; and if it is judged that the first bit field is a second value different from the first value, judging that the second field and the third field are extracted from the instruction to be executed. The executing the instruction to be executed according to the first field, the second field, the third field, and the opcode and the addressing mode field comprised in the instruction to be executed comprises: determining information related to the variable-length vector register and the variable-length mask register according to the first field, the second field and the third field; determining a function of the instruction to be executed according to the opcode; determining a source register and a destination register of the instruction to be executed according to the addressing mode field; and performing an operation corresponding to the function of the instruction to be executed on the instruction to be executed according to the information, the source register and the destination register.

4. The method according to claim 3, wherein the first field further comprises a second bit field for accessing an extended register resource, the second field comprises a third bit field for accessing the extended register resource and a fourth bit field for identifying a processing to be performed by an inactivated variable-length mask register, and the third field comprises a fifth bit field for identifying an index of the variable-length mask register, and the determining the information related to the variable-length vector register and the variable-length mask register according to the first field, the second field and the third field comprises: determining addressable variable-length vector registers according to the second bit field and the third bit field; and determining a mask operation to be performed by the inactivated variable-length mask register according to the fourth bit field. ​ ​ ​ 3. The method of claim 1, wherein, ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ determine an activated variable-length mask register according to the fifth bit field.

5. The instruction execution method of claim 4, wherein, perform an operation corresponding to the function of the to-be-executed instruction on the to-be-executed instruction according to the information, the source register and the destination register, including: obtain a source operand according to the source register; parallel load a plurality of data elements according to the addressed variable-length vector register; perform the operation corresponding to the function of the to-be-executed instruction on the source operand and the data elements of the loaded plurality of data elements that correspond to the activated variable-length mask register and need to participate in the operation, and perform the mask operation on the inactivated variable-length mask register.

6. The instruction execution method of claim 3, wherein, perform an operation corresponding to the function of the to-be-executed instruction on the to-be-executed instruction, including: if the operation code is a predetermined operation value, determine that the function of the to-be-executed instruction is a predetermined function, and perform a predetermined operation corresponding to the predetermined function on the to-be-executed instruction, wherein the predetermined operation includes addition, subtraction, multiplication, division, shift, logical and, logical and-not, logical or, logical same or, logical exclusive or, bitwise inversion, bitwise logical or operation on two source operands and setting a flag bit according to the result, left shift, right shift, packed bit test mask and flag bit setting operation, or unpacking operation.

7. The instruction execution method of claim 6, wherein, when the predetermined operation is the shift operation, performing the operation corresponding to the function of the to-be-executed instruction on the to-be-executed instruction includes: if the operation code is a first operation value, performing the to-be-executed instruction to move the source operand from the memory to the activated variable-length mask register; if the operation code is a second operation value, performing the to-be-executed instruction to move the source operand from the activated variable-length mask register to the memory; if the operation code is a third operation value, performing the to-be-executed instruction to move the source operand from the general-purpose vector register to the activated variable-length mask register; if the operation code is a fourth operation value, performing the to-be-executed instruction to move the source operand from the activated variable-length mask register to the general-purpose vector register.

8. The instruction execution method according to claim 7, wherein: the first field includes a first bit field for marking operation code mapping of the to-be-executed instruction, the instruction execution method further includes: determining a bit width of a move operation of the variable-length mask register according to a flag bit of the first bit field and whether the to-be-executed instruction includes a prefix of the third field with a preset value.

9. The instruction execution method of claim 8, wherein, determining the bit width of the move operation of the variable-length mask register according to the flag bit and whether the to-be-executed instruction includes the prefix of the third field with the preset value, including: if the flag bit is 0 and the prefix with the preset value is included, the bit width of the move operation is 1 byte; if the flag bit is 0 and the prefix with the preset value is not included, the bit width of the move operation is 2 bytes; If the flag bit is 1 and a prefix with a preset value is included, the bit width of the move operation is 4 bytes; If the flag bit is 1 and a prefix with a preset value is not included, the bit width of the move operation is 8 bytes.

10. The instruction execution method of claim 1, wherein the first field further comprises a second bit field for accessing an extended register resource, and the execution of the to-be-executed instruction according to the first field, the operation code and the addressing mode field comprises: determining a variable-length vector register that can be addressed according to the second bit field; determining a function of the to-be-executed instruction according to the operation code; determining a source register and a destination register of the to-be-executed instruction according to the addressing mode field; and performing an operation corresponding to the function of the to-be-executed instruction on the to-be-executed instruction according to the variable-length vector register that can be addressed, the source register and the destination register.

11. The instruction execution method of claim 1, wherein the first field comprises a first bit field for marking an operation code mapping of the to-be-executed instruction, and the instruction execution method further comprises: if a flag bit of the first bit field is a first flag value, determining that the to-be-executed instruction is a private variable-length vector instruction; and if the flag bit of the first bit field is a second flag value different from the first flag value, determining that the to-be-executed instruction is not the private variable-length vector instruction. Further comprising: a load and operation instruction of the variable-length mask register and a mask operation. Further comprising: if an exception occurs during the execution of the to-be-executed instruction, reporting the exception to a system register. Further comprising: a decoding unit configured to identify whether a to-be-executed instruction comprises an extended instruction prefix, and if the to-be-executed instruction comprises the extended instruction prefix, extract a first field for marking an operation code mapping of the to-be-executed instruction from the to-be-executed instruction, and determine whether to extract a second field related to a variable-length vector register and a third field related to a variable-length mask register from the to-be-executed instruction according to the first field, wherein the variable-length vector register is used for vector operation, and the variable-length mask register is used for mask control; and an execution unit configured to execute the to-be-executed instruction according to the first field, the second field, the third field, and an operation code and an addressing mode field included in the to-be-executed instruction if it is determined that the second field and the third field are extracted from the to-be-executed instruction, and execute the to-be-executed instruction according to the first field, the operation code and the addressing mode field if it is determined that the second field and the third field are not extracted from the to-be-executed instruction.

15. The instruction execution apparatus of claim 14, wherein the first field comprises a first bit field for marking an operation code mapping of the to-be-executed instruction, and the decoding unit is configured to: determine whether the first bit field is a first value; if it is determined that the first bit field is the first value, determine that the second field and the third field are not extracted from the to-be-executed instruction. ​ ​ ​ ​ ​ ​ 12. The method of claim 1, wherein, ​ ​ 13. The method of claim 1, wherein: ​ ​ 14. An instruction execution apparatus, characterized by comprising: ​ ​ ​ ​ ​ ​ ​ ​ If it is judged that the first bit field is other value different from the first value, it is judged that the second field and the third field are extracted from the to-be-executed instruction.

16. The instruction execution apparatus of claim 14, wherein, The execution unit is configured to: determine information related to the variable-length vector register and the variable-length mask register according to the first field, the second field and the third field; determine the function of the to-be-executed instruction according to the operation code; determine the source register and the destination register of the to-be-executed instruction according to the addressing mode field; perform an operation corresponding to the function of the to-be-executed instruction on the to-be-executed instruction according to the information, the source register and the destination register.

17. The instruction execution apparatus according to claim 16, wherein the first field further comprises a second bit field for accessing an extended register resource, the second field comprises a third bit field for accessing an extended register resource and a fourth bit field for identifying a processing to be performed on an inactivated variable-length mask register, and the third field comprises a fifth bit field for identifying an index of the variable-length mask register, the execution unit is configured to: determine an addressable variable-length vector register according to the second bit field and the third bit field; determine a mask operation to be performed on an inactivated variable-length mask register according to the fourth bit field; determine an activated variable-length mask register according to the fifth bit field.

18. The instruction execution apparatus of claim 17, wherein, the execution unit is configured to: obtain a source operand according to the source register; parallel load a plurality of data elements according to the addressable variable-length vector register; perform an operation corresponding to the function of the to-be-executed instruction on the source operand and the data elements of the loaded plurality of data elements which correspond to the activated variable-length mask register and need to participate in the operation, and perform the mask operation on the inactivated variable-length mask register.

19. The instruction execution apparatus of claim 16, wherein, the execution unit is configured to: if the operation code is a predetermined operation value, determine that the function of the to-be-executed instruction is a predetermined function, and perform a predetermined operation corresponding to the predetermined function on the to-be-executed instruction, wherein the predetermined operation comprises an addition operation, a subtraction operation, a multiplication operation, a division operation, a shift operation, a logical and operation, a logical and not operation, a logical or operation, a logical same operation, a logical exclusive or operation, a bitwise not operation, an operation of performing a bitwise logical or operation on two source operands and setting a flag bit according to a result, a left shift operation, a right shift operation, a packed bit test mask and flag setting operation, or an unpack operation.

20. The instruction execution apparatus of claim 19, wherein, When the predetermined operation is the shift operation, the execution unit is configured to: if the operation code is a first operation value, perform a move operation on the to-be-executed instruction to move a source operand from a memory to an activated variable-length mask register; if the operation code is a second operation value, perform a move operation on the to-be-executed instruction to move a source operand from the activated variable-length mask register to a memory; if the operation code is a third operation value, perform a move operation on the to-be-executed instruction to move a source operand from a general-purpose vector register to the activated variable-length mask register; If the opcode is a fourth operation value, the instruction to be executed is to move a source operand from the activated variable length mask register to a general purpose vector register.

21. The instruction execution apparatus of claim 20, wherein, the first field includes a first bit field to flag a mapping of an opcode of the instruction to be executed, the execution unit is configured to: determine a bit width of a move operation of the variable length mask register according to a flag bit of the first bit field and whether the instruction to be executed includes a prefix with a preset value of the third field.

22. The instruction execution apparatus of claim 21, wherein, the execution unit is configured to: if the flag bit is 0 and includes the prefix with the preset value, determine the bit width of the move operation as 1 byte; if the flag bit is 0 and does not include the prefix with the preset value, determine the bit width of the move operation as 2 bytes; if the flag bit is 1 and includes the prefix with the preset value, determine the bit width of the move operation as 4 bytes; if the flag bit is 1 and does not include the prefix with the preset value, determine the bit width of the move operation as 8 bytes.

23. The instruction execution apparatus of claim 14, wherein, the first field further includes a second bit field to access an extended register resource, the execution unit is configured to: determine an addressable variable length vector register according to the second bit field; determine a function of the instruction to be executed according to the opcode; determine a source register and a destination register of the instruction to be executed according to the addressing mode field; perform an operation corresponding to the function of the instruction to be executed on the instruction to be executed according to the addressable variable length vector register, the source register and the destination register.

24. The instruction execution apparatus of claim 14, wherein, the first field includes a first bit field to flag a mapping of an opcode of the instruction to be executed, the decode unit is configured to: if a flag bit of the first bit field is a first flag value, determine that the instruction to be executed is a private variable length vector instruction; if the flag bit of the first bit field is a second flag value different from the first flag value, determine that the instruction to be executed is not the private variable length vector instruction.

25. The instruction execution apparatus of claim 14, wherein, further comprising: an update unit to update a load and operation instruction and a mask operation of the variable length mask register.

26. The instruction execution apparatus of claim 14, wherein, the execution unit is configured to: if an exception occurs during execution of the instruction to be executed, report the exception to a system register.

27. A processor, comprising: comprising: registers including 32 variable length vector registers, 8 variable length mask registers, 6 variable length control registers; a decode unit in the instruction execution apparatus according to any one of claims 14-26, the processor further comprises: an execution unit in the instruction execution apparatus according to any one of claims 14-26.

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