A CPU dynamic power allocation method for improving system throughput

Abstract

The application discloses a CPU dynamic power distribution method for improving system throughput, comprising the following steps: S1, collecting real-time performance monitoring counter data of each CPU core, obtaining current load characteristic group performance bottleneck risk degree of each core; S2, constructing a load risk prediction model to predict the performance bottleneck risk degree to obtain a risk trend factor, collecting basic power budget data of each CPU core, combining the risk trend factor to obtain an optimal temporary power budget, and outputting a forward-looking power budget bias strategy based on the optimal temporary power budget; S3, performing power consumption modeling based on the power budget bias strategy and a chip constitution factor to construct an optimal V-f mapping table; and S4, based on the optimal V-f mapping, issuing V-f parameters through a CPU power management interface and forming a closed-loop feedback, so that the dynamic power distribution of the CPU is realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power distribution, in particular to a CPU dynamic power distribution method for improving system throughput. BACKGROUND

[0002] With the continuous development of computer technology, the contradiction between CPU performance demand and power consumption control is increasingly prominent. In the early stage, the voltage and frequency of the CPU are mostly statically configured, that is, fixedly set according to the design specifications. Although this method is simple, it cannot be dynamically adjusted according to the actual load, resulting in waste of performance or power consumption. Later, an adjustment method based on static power budget appeared, which roughly divides the V-f combination of each core through the pre-set power budget, but does not consider the process deviation existing in the chip manufacturing process, that is, the difference in chip constitution.

[0003] At present, the existing CPU dynamic power distribution method lacks consideration of chip constitution when generating power budget bias strategy. Under the same power budget, the core with poor constitution may not be able to run stably at high frequency due to insufficient power budget, resulting in performance bottleneck or unstable work. On the other hand, when constructing the voltage-frequency mapping table, a unified relationship model is often used, ignoring the difference in constitution of individual cores, so that the generated voltage-frequency combination is not the optimal choice for each core. Either the power consumption is too high to exceed the budget, or the performance is not optimal, so it is impossible to maximize the performance under the power budget constraint. Therefore, a CPU dynamic power distribution method for improving system throughput is proposed. SUMMARY

[0004] In order to overcome the above-mentioned defects of the prior art, in order to achieve the above-mentioned purpose, the present application proposes the following technical scheme:

[0005] A CPU dynamic power distribution method for improving system throughput, comprising:

[0006] S1: collecting real-time performance monitoring counter data of each CPU core to obtain the current responsible feature composition performance bottleneck risk degree of each core;

[0007] S2: constructing a load risk prediction model to predict the performance bottleneck risk degree to obtain a risk trend factor, collecting basic power budget data of each CPU core, and combining the risk trend factor to obtain an optimal temporary power budget, and outputting a forward-looking power budget bias strategy based on the optimal temporary power budget;

[0008] The load risk prediction model comprises a feature embedding layer, a time series attention layer, a load risk fusion layer and a prediction output layer. The performance bottleneck risk degree is input through the feature embedding layer, and the risk trend factor is output through the prediction output layer;

[0009] S3: Based on the power budget bias strategy and the chip's physical factor, the power consumption is modeled to build the optimal V-f mapping table;

[0010] S4: Based on the optimal V-f mapping, the V-f parameters are issued through the CPU power management interface to form a closed-loop feedback, and the dynamic power distribution of the CPU is realized.

[0011] The feature embedding layer maps three types of load features, including PMC, memory access PMC, and instruction PMC, to a unified feature space and embeds them through a fully connected layer to obtain a memory feature embedding vector E.

[0012] The timing attention layer assigns weights to load features at different times based on their importance in predicting future risk levels for the current load. to obtain a timing attention output vector wherein, is the key vector dimension, is the query matrix, is the key matrix, is the value matrix.

[0013] The load risk fusion layer calculates the gating weights for load features based on the corresponding timing attention output vectors , respectively, and then element-wise multiplies each feature embedding vector with the corresponding gating weight and adds them to obtain a fused risk feature vector .

[0014] The prediction output layer predicts the performance bottleneck risk level at the future time based on the fused risk feature vector : , wherein, is a fully connected layer.

[0015] The risk trend factor acquisition process is as follows:

[0016] Compare the performance bottleneck risk level at the future time with the current performance bottleneck risk level to obtain the risk trend factor: wherein, when the predicted load is rising, when the predicted load is falling.

[0017] The process of obtaining the optimal temporary power budget combined with the risk trend factor is as follows:

[0018] According to the basic power budget , combine the risk trend factor to calculate the risk compensation bias Then, the optimal temporary power budget is obtained according to the risk compensation bias amount: Wherein, is the optimal temporary power budget, is the risk compensation coefficient.

[0019] The process of outputting the prospective power budget bias strategy based on the optimal temporary power budget is:

[0020] Optimal temporary power budget for all CPU cores Global constraints and adjustments are made to calculate the sum of all core temporary power budgets And compare it with the total power budget of the system When , it proves that the preliminary power allocation scheme exceeds the power consumption limit of the system and needs to be adjusted, at this time, the scaling factor is calculated;

[0021] Then, based on the scaling factor Optimize the risk compensation bias amount of each CPU core, the adjusted bias amount is represented as Finally, the power budget bias strategy of the CPU core is represented as ;

[0022] Finally, the number of each CPU core is matched with the corresponding power budget bias strategy Arrange it into a mapping table form to obtain the prospective power budget bias strategy.

[0023] The process of obtaining the physical factor of the chip is:

[0024] Quantitatively represent the chip and record the lowest voltage at which the core works stably at the current frequency, denoted as Where i is the index number, is the test frequency, based on the test frequency Obtain the physical factor of the CPU core at the frequency The calculation formula is Wherein, is the average minimum stable voltage at the test frequency

[0025] The process of power consumption modeling based on the power budget bias strategy and the physical factor of the chip is:

[0026] The power consumption rule of the stable voltage V is defined in combination with the physical factor of the chip:

[0027] ; ​​

[0028] Will By substituting the power consumption formula into the model, and iterating through different test frequencies f, the corresponding power consumption is calculated. The model is completed by finding the highest frequency at which power consumption is less than or equal to the power budget, thus achieving the goal of maximizing performance within the power budget. The formula is expressed as:

[0029] ;

[0030] Where k is a constant related to the CPU architecture, and C is the core's equivalent capacitance.

[0031] The process of constructing the optimal Vf mapping table is as follows:

[0032] Set the scan interval of the test frequency as ,in This is the lowest operating frequency supported by the CPU. It is the highest operating frequency designed for the CPU;

[0033] Traverse the scan interval and calculate power consumption, starting from the highest frequency. Start by iterating down to lower frequencies. For each frequency, determine the CPU core's quality factor. and the average minimum stable voltage of the same model Calculate the stable minimum voltage at this frequency. Then, by substituting the power consumption modeling formula, the CPU cores at different test frequencies are obtained. Power consumption ;

[0034] Determine different test frequencies Power consumption Is it less than or equal to the power budget of the CPU core? Find the first one that satisfies The optimal frequency is denoted as The corresponding minimum stable voltage at this time is Obtain the stable minimum voltage for each CPU core. All core Organized into core numbers and By combining the mapping tables, the optimal Vf mapping table is obtained.

[0035] The present invention has the following beneficial effects:

[0036] In this invention, firstly, a power budget bias strategy for risk compensation is implemented based on the performance bottleneck risk level. For cores with high risk levels, it means that their current workload is heavy and they need more power resources to maintain efficient operation. The power budget bias strategy will proactively allocate more power budget to these cores, enabling them to work at a higher performance level. For example, when a core is processing a complex computing task, due to the increase in power budget, it can complete integer operations, floating-point operations, etc., more quickly, reducing the processing time of computing tasks, thereby improving the computing power of a single core and promoting the overall improvement of CPU throughput, enabling the CPU to process more computing tasks per unit time.

[0037] Finally, by constructing an optimal Vf mapping table, fully considering the chip's inherent characteristics, and combining it with a power budget bias strategy, the optimal Vf combination under its power budget constraint is found for each core. For cores with better inherent characteristics, they can stably operate at higher frequencies at lower voltages. For cores with relatively poor inherent characteristics, a Vf combination that satisfies their stable operation and maximizes performance can also be found, enabling the CPU to process more data and tasks in the same amount of time. At the same time, once a change in the operating state of a core is detected, such as an increase in the risk of a performance bottleneck or an actual power consumption exceeding the budget, the risk of the performance bottleneck will be reassessed, the power budget bias strategy will be adjusted, and the Vf mapping table and dynamically set instructions will be optimized. This will prevent performance degradation due to load fluctuations and maintain efficient operation at all times, thereby continuously ensuring and improving the CPU's throughput. This allows the CPU to stably handle a large number of tasks and meet the needs of complex application scenarios. Attached Figure Description

[0038] Figure 1 This is a flowchart illustrating the steps of a CPU dynamic power allocation method for improving system throughput proposed in this invention. Detailed Implementation

[0039] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0040] Example: Figure 1 As shown, the present invention proposes a CPU dynamic power allocation method to improve system throughput, comprising:

[0041] S1: Collect real-time performance monitoring counter data for each CPU core to obtain the current performance bottleneck risk level of each core's responsible features.

[0042] Collecting PMC data of performance monitoring counters in CPU cores and quantifying to determine load characteristics, including:

[0043] Computing PMC: reflecting the pressure of core computing units, such as integer operation unit utilization, floating point operation delay, etc.

[0044] Memory PMC reflects the influence of memory on computing, such as L1 cache miss rate, memory access waiting period, etc.

[0045] Instruction PMC is related to the smoothness of instruction flow, such as instruction out-of-order execution stall period, branch prediction failure times, etc.

[0046] Load characteristics are represented as , represents computing PMC, represents memory PMC, represents instruction PMC;

[0047] The collected computing PMC, memory PMC and instruction PMC parameters are preprocessed, and each PMC parameter is normalized to convert PMC parameters of different dimensions into comparable values. Then, according to the different influence of each item on the computing bottleneck, the corresponding weight is allocated, and the normalized item values are weighted and summed to obtain the performance bottleneck risk degree, which is represented by the formula:

[0048] , wherein represents the performance bottleneck risk degree, is the corresponding weight.

[0049] S2: Constructing a load risk prediction model to predict the performance bottleneck risk degree to obtain a risk trend factor, collecting the basic power budget data of each CPU core, and combining the risk trend factor to obtain an optimal temporary power budget, and outputting a forward-looking power budget bias strategy based on the optimal temporary power budget;

[0050] Based on historical load characteristics , a load risk prediction model is constructed to predict future performance bottleneck risk degree, the implementation process is as follows:

[0051] In order to accurately capture the complex correlation between load characteristics and future risk degree, a load risk prediction model is designed to integrate computing PMC, memory PMC and instruction PMC in load characteristics, and to mine time series dependency to predict future performance bottleneck risk degree;

[0052] The load risk prediction model includes feature embedding layer, time series attention layer, load risk fusion layer and prediction output layer, wherein:

[0053] The feature embedding layer maps the three types of load features, i.e., the load features of the computation PMC, the load features of the memory access PMC, and the load features of the instruction PMC, into a unified feature space and embeds them through a fully connected layer to obtain a memory access feature embedding vector E;

[0054] The time sequence attention layer is based on the load features at different time points The importance of predicting the future risk degree of the current load is that the load features at different time points The reasonable weights are allocated, the time sequence length is t, and the load features of the last t sampling periods are considered The load features are multiplied by the query weight matrix , the key weight matrix , and the value weight matrix respectively to obtain the query matrix , the key matrix , and the value matrix ;

[0055] Then, the product of the query matrix and the transpose of the key matrix is calculated, and the result is divided by the square root of the dimension of the key vector (to prevent the gradient from disappearing due to the large inner product), and then the attention weight is obtained through the softmax function. Finally, the attention weight is multiplied by the value matrix to obtain the time sequence attention output vector In this way, the network can automatically identify which time point information in the time sequence feature is more critical to predicting the future risk degree, and thus give higher weights;

[0056] The load risk fusion layer is based on the time sequence attention output vectors corresponding to different load features The gate weight calculation is performed on the load features and the time sequence attention output vectors respectively, the load features are processed through a fully connected layer FC, and the gate weight of the instruction feature is obtained through a Sigmoid activation function : Meanwhile, the gate weight of the memory access feature vector is obtained: E is the memory access feature embedding vector, and the gate weight of the time sequence attention output vector is: ;

[0057] The load risk fusion layer elementwisely multiplies each feature embedding vector and the corresponding gate weight, and then adds them to obtain the fused risk feature vector ;

[0058] The prediction output layer obtains the fused risk feature vector Predict the performance bottleneck risk degree at future time: , represents the full connection layer;

[0059] Determine the training target based on the load risk prediction model, so that the performance bottleneck risk degree at future time is minimized, select the optimizer for training, use the stochastic gradient descent Adam optimizer, constantly adjust the load risk prediction model, learn the correlation pattern between load features and future risk degree, after training, for any input load feature , the load risk prediction model can output the predicted future performance bottleneck risk degree ;

[0060] Compare the future performance bottleneck risk degree and the current performance bottleneck risk degree to obtain a risk trend factor, that is , that is When the predicted load rises, it will amplify the performance bottleneck risk degree, When the predicted load decreases, it will reduce the performance bottleneck risk degree;

[0061] Determine the basic power budget of each CPU core , which is directly determined by the average power consumption of the core during historical operation, by collecting the power consumption data of the core under different workloads in the past period of time, and obtaining the average power consumption value after statistical analysis, which is used as the basic power budget ;

[0062] Obtain the optimal temporary power budget by combining the risk trend factor, the process is:

[0063] According to the basic power budget , combine the risk trend factor to calculate the risk compensation bias , and then obtain the optimal temporary power budget according to the risk compensation bias: , wherein is the optimal temporary power budget, is the risk compensation coefficient;

[0064] Specifically, the risk compensation coefficient determination process is:

[0065] Under different workloads, different performance pressures are applied to the CPU core, and then the value of is adjusted, and the performance of the core under different risk compensation coefficients is observed, such as task execution time, instruction throughput and power consumption, by comparing the performance improvement amplitude and power consumption increase amplitude corresponding to different risk compensation coefficients , find an optimal value that can balance the bottleneck relief effect and power consumption constraint, and determine the risk compensation coefficient After that, the risk compensation bias of each core is calculated based on the performance bottleneck risk degree of the core and the base power budget P ;

[0066] Then, the forward-looking power budget bias strategy is output based on the optimal temporary power budget, and the process is as follows:

[0067] Optimal temporary power budget for all cores Global constraints and adjustments are made to calculate the sum of the temporary power budgets of all cores , and compare it with the total power budget of the system , when , it proves that the preliminary power allocation scheme exceeds the power consumption limit of the system and needs to be adjusted, at this time, the scaling factor is calculated

[0068] Then, the risk compensation bias of each CPU core is optimized and adjusted based on the scaling factor , and the adjusted bias is represented as , and finally, the power budget bias strategy of the CPU core is represented as ;

[0069] Finally, the number of each CPU core and the corresponding power budget bias strategy are arranged into a mapping table form to obtain the forward-looking power budget bias strategy

[0070] Specifically, since the load risk prediction model is introduced, the strategy can more accurately match the future load changes of the core, and provide more actual demand power constraints for subsequent construction of the optimal V-f mapping table considering the chip constitution, to achieve a more optimal balance between performance improvement and power consumption control. For those cores with high performance bottleneck risk, it often means that the current load is heavy and close to performance saturation. If you want to improve the overall throughput of the system, these cores need more power support to release performance. Through the risk compensation power budget bias strategy, more power budget can be allocated to high-risk cores in advance to ensure that these cores have enough power to improve their running efficiency and provide power foundation for throughput improvement.

[0071] S3: Perform power consumption modeling to build an optimal V-f mapping table based on the power budget bias strategy and the constitution factor of the chip

[0072] The process of obtaining the constitution factor of the chip is as follows:

[0073] ​First, the chip is quantitatively characterized, and the physical condition of each core is quantified by offline testing. For each CPU core, start from the lowest frequency and gradually increase the frequency. At each fixed frequency, start from the lowest voltage and gradually increase the voltage. Monitor the working state of the core until the CPU core has an error or instability (such as frequent hardware exceptions).

[0074] At this time, record the lowest voltage at which the core can work stably at the current frequency, denoted as , where i is the index number, is the test frequency, and the physical condition factor of the i-th CPU core at the frequency is defined as , and the calculation formula is , where is the average minimum stable voltage of the same type of core at the frequency obtained by statistical analysis after the same offline test on a large number of cores of the same type;

[0075] If , it means that the physical condition of the CPU core at the test frequency is better than the average level of the same type of core, and if , it means that its physical condition is worse than the average level. Through the physical condition factor, the voltage demand characteristics of each core at different frequencies can be accurately described, providing a basis for the selection of V-f (voltage-frequency) combinations in the future;

[0076] The process of power budget bias strategy and chip physical condition factor based power consumption modeling is as follows:

[0077] The power consumption rule of stable voltage V is defined based on the physical condition factor of the chip, that is, the CPU core must meet the following condition to work stably at the test frequency

[0078] ;

[0079] Specifically, is the lowest voltage at which the CPU core can work stably at the test frequency . In order to maximize the performance of the core within the power budget, that is, to increase the test frequency as much as possible, the lowest voltage that satisfies the stable condition should be selected, because the lower the voltage, the lower the power consumption, which can reserve power consumption space for higher frequency, that is, take ;

[0080] Substitute into the power consumption rule for modeling. Given the physical condition factor and the power budget (the maximum power consumption allowed), by iterating through different test frequencies f, the corresponding power consumption​ , so as to find the highest frequency with power consumption ≤ power budget, achieve the goal of maximizing performance within the power budget, complete modeling, and the power consumption modeling formula is expressed as:

[0081] ;

[0082] wherein k is a constant related to the CPU architecture, and C is the equivalent capacitance of the core;

[0083] Specifically, by , the power consumption at different frequencies can be analyzed under the condition of known core physique and power budget, and then the V-f combination that meets the power consumption constraint and has the highest frequency as possible is found, so as to balance performance and power consumption;

[0084] The process of constructing the optimal V-f mapping table is as follows:

[0085] Set the frequency scanning range, and according to historical data, determine a test frequency scanning interval as , wherein is the lowest working frequency supported by the CPU, is the highest working frequency designed by the CPU;

[0086] Then traverse the scanning interval and calculate the power consumption, starting from the highest frequency , and traversing to lower frequencies in turn. For each frequency, according to the physique factor of the CPU core and the average minimum stable voltage of the same model , the stable minimum voltage at this frequency is calculated as , and then substituted into the power consumption modeling formula to obtain the power consumption of the CPU core at different test frequencies ; ;

[0087] Determine whether is less than or equal to the power budget of the CPU core , find the optimal frequency that meets for the first time (the first one in the traversal from high to low), and record it as . At this time, the stable minimum voltage corresponding to it is , generate a V-f mapping table, and obtain the stable minimum voltage corresponding to each CPU core as . Arrange all the cores into a mapping table of core number and combination, that is, the optimal V-f mapping table considering the chip physique. The optimal V-f mapping contains the dynamic setting instructions of each CPU core;

[0088] Specifically, different chip body cores have different voltage (V) and frequency (f) combinations for stable operation. The present scheme constructs an optimal V-f mapping table considering the chip body, and customizes the most suitable V-f combination for each core. Under the constraint of power budget, cores with good body can operate at a higher frequency at a lower voltage, and cores with slightly poor body can also find the highest stable frequency within their power budget. The improvement of frequency directly means that the core processes instructions and data faster, and can complete more calculations or memory operations per unit time, thereby effectively improving the throughput of a single core.

[0089] S4: Based on the optimal V-f mapping, the V-f parameters are issued through the CPU power management interface to form a closed-loop feedback, and the dynamic power distribution of the CPU is realized.

[0090] The optimal V-f mapping table records the optimal voltage and optimal frequency combination corresponding to each CPU core. The optimal frequency is converted into a binary code recognizable by the frequency control register according to the mapping relationship specified in the CPU architecture manual, and the corresponding write instruction is generated. For voltage configuration, according to hardware design, the is converted into a write instruction in the form of binary code that the voltage control register can receive.

[0091] After the CPU core receives these instructions, the internal hardware circuit will automatically respond and trigger the work of modules such as voltage regulator and clock generator. If it is found that the performance bottleneck risk of a core is rising, for example:

[0092] The calculation PMC data shows that the integer operation unit utilization is continuously too high, causing a performance bottleneck, indicating that the current V-f setting may not meet the workload requirements;

[0093] At this time, it is necessary to rebuild the optimal V-f mapping table and generate new dynamic setting instructions, and then issue them through the CPU power management interface to realize dynamic allocation of power resources.

[0094] In the application, several formulas involved are calculated by taking their numerical values after dimensionless, and the establishment of the formula is obtained by collecting a large amount of data to simulate the formula of the nearest real situation. Some coefficients or weights in the formula are set by the person skilled in the art according to the actual situation, so this will not be described in detail.

[0095] The above-described embodiments can be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented by software, the above-described embodiments can be implemented in whole or in part in the form of a computer program product. A person of ordinary skill in the art can be aware that units and algorithm steps of the examples described in connection with the embodiments disclosed herein can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether the functions are performed by hardware or software depends on the specific application and design constraints of the technical solutions.

[0096] Although embodiments of the present application have been shown and described, it would be appreciated by those skilled in the art that changes, modifications, substitutions and variations can be made to these embodiments without departing from the principles and spirit of the application, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A CPU dynamic power allocation method for improving system throughput, characterized in that, include: S1: Collect real-time performance monitoring counter data for each CPU core to obtain the current performance bottleneck risk level of each core's responsible features. S2: Construct a load risk prediction model to predict the risk level of performance bottlenecks and obtain risk trend factors. Collect basic power budget data for each CPU core and combine it with risk trend factors to obtain the optimal temporary power budget. Output a forward-looking power budget bias strategy based on the optimal temporary power budget. The process of the forward-looking power budget bias strategy based on the optimal temporary power budget output is as follows: Optimal temporary power budget for all CPU cores Perform global constraints and adjustments, and calculate the sum of all core temporary power budgets. and compare it with the system's total power budget. When comparing, Calculate the scaling factor. ; Then, based on the scaling factor Risk compensation bias for each CPU core After optimization and adjustment, the adjusted bias is expressed as follows: Ultimately, the CPU core's power budget bias strategy is expressed as: ; Finally, the number of each CPU core is associated with its corresponding power budget bias strategy. Organize the data into a mapping table to obtain a forward-looking electricity budget bias strategy; The load risk prediction model includes a feature embedding layer, a temporal attention layer, a load risk fusion layer, and a prediction output layer. The performance bottleneck risk level is input through the feature embedding layer, and the risk trend factor is output through the prediction output layer. S3: Construct the optimal Vf mapping table by power budget bias strategy and chip quality factor; The process of obtaining the body constitution factor of the chip is as follows: The chip is quantitatively characterized, and the minimum voltage at which the core can operate stably at the current frequency is recorded, denoted as . where i is the index number. For test frequency, based on test frequency Obtain CPU core frequency lower body constitution factors The calculation formula is: ,in, For test frequency The lowest average stable voltage; The process of constructing the optimal Vf mapping table is as follows: Set the scan interval of the test frequency as ,in This is the lowest operating frequency supported by the CPU. It is the highest operating frequency designed for the CPU; Traverse the scan interval and calculate power consumption, starting from the highest frequency. Start by iterating down to lower frequencies. For each frequency, determine the CPU core's quality factor. and the average minimum stable voltage of the same model Calculate the stable minimum voltage at this frequency = Then, by substituting the power consumption modeling formula, the CPU cores at different test frequencies are obtained. Power consumption ; Determine different test frequencies Power consumption Is it less than or equal to the power budget of the CPU core? Find the first one that satisfies The optimal frequency is denoted as The corresponding minimum stable voltage at this time is Obtain the stable minimum voltage for each CPU core. All core Organized into core numbers and By combining the mapping tables, the optimal Vf mapping table is obtained; S4: Based on the optimal Vf mapping, Vf parameters are sent through the CPU power management interface and a closed-loop feedback is formed to realize the dynamic power allocation of the CPU.

2. The CPU dynamic power allocation method for improving system throughput according to claim 1, characterized in that, The feature embedding layer maps the three types of load features—computation-type PMC, memory-type PMC, and instruction-type PMC—into a unified feature space and embeds them through a fully connected layer to obtain the memory-type feature embedding vector E. The temporal attention layer predicts the future risk of the current load based on the importance of different load characteristics, which are load characteristics at different times. Assign weights to obtain the temporal attention output vector. ,in, The dimension of the key vector. For querying the matrix, The key matrix, It is a value matrix; The load risk fusion layer is based on the temporal attention output vector corresponding to different load characteristics. For load characteristics respectively Temporal attention output vector The gating weights are calculated by multiplying each feature embedding vector element-wise with its corresponding gating weight, and then summing the results to obtain the fused risk feature vector. ; The prediction output layer is based on the fused risk feature vector. Predict the risk level of performance bottlenecks in the future: , This indicates a fully connected layer.

3. The CPU dynamic power allocation method for improving system throughput according to claim 2, characterized in that, The process for obtaining the risk trend factors is as follows: Risk of performance bottlenecks in future moments The risk trend factor is obtained by comparing it with the current performance bottleneck risk level: ,in, The load is predicted to increase. Predict load decreases during a downturn.

4. The CPU dynamic power allocation method for improving system throughput according to claim 3, characterized in that, The process of obtaining the optimal temporary electricity budget by combining risk trend factors is as follows: According to the basic electricity budget Calculate the risk compensation bias by combining risk trend factors. Then, the optimal temporary power budget is obtained based on the risk compensation bias: ,in, For the optimal temporary electricity budget, This is the risk compensation coefficient.

5. The CPU dynamic power allocation method for improving system throughput according to claim 4, characterized in that, The process of power consumption modeling based on the power budget bias strategy and the chip's quality factor is as follows: The power consumption rule for the stable voltage V is defined based on the chip's quality factor: ； Will By substituting the power consumption formula into the model, and iterating through different test frequencies f, the corresponding power consumption is calculated. The model is completed by finding the highest frequency at which power consumption is less than or equal to the power budget, thus achieving the goal of maximizing performance within the power budget. The formula is expressed as: ； Where k is a constant related to the CPU architecture, and C is the core's equivalent capacitance.

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