Task processing method and device, equipment, vehicle, chip and storage medium

Abstract

The invention relates to a task processing method, device and equipment, a vehicle, a chip and a storage medium, and belongs to the field of intelligent cabins and task processing. The method comprises the steps of obtaining a task queue of a processor core of target equipment; and under the condition that the task queue has the repeated task identifiers, determining that the processor core is in a task blocking state. Therefore, the task queue of the processor core of the target equipment is obtained, the processor core is determined to be in the task blocking state under the condition that the task queue has the repeated task identifiers, whether the processor core is in the task blocking state can be determined only by determining whether the task queue of the processor core has the repeated task identifiers, and the method is simple and easy to implement; whether the processor core is in the task blocking state or not can be effectively and rapidly detected, the detection efficiency of whether the processor core is in the task blocking state or not is improved, the task processing performance of the processor core is further improved, and the method is suitable for application scenes such as an intelligent cabin.

Description

Technical Field

[0001] This disclosure relates to the fields of intelligent cockpit and mission processing technology, and more particularly to a mission processing method, apparatus, electronic device, vehicle, chip, and storage medium. Background Technology

[0002] Processor cores may be in a blocked state due to task timeouts, lack of available resources, or other reasons. This leads to longer task execution times and slower response times, impacting the processor core's task processing performance. To improve processor core task processing performance, it's possible to detect whether a processor core is in a blocked state. However, current detection methods are complex and cannot quickly detect whether a processor core is in a blocked state. Summary of the Invention

[0003] This disclosure provides a task processing method, apparatus, electronic device, vehicle, chip, and storage medium to at least solve the problems of related detection methods, which suffer from complex steps and inability to quickly detect whether a processor core is in a task-blocked state. The technical solution of this disclosure is as follows:

[0004] According to a first aspect of the present disclosure, a task processing method is provided, comprising: acquiring a task queue of a processor core of a target device; and determining that the processor core is in a task blocked state if duplicate task identifiers exist in the task queue.

[0005] According to a second aspect of the present disclosure, a task processing apparatus is provided, comprising: an acquisition module configured to acquire a task queue of a processor core of a target device; and a determination module configured to determine that the processor core is in a task blocked state if duplicate task identifiers exist in the task queue.

[0006] According to a third aspect of the present disclosure, an electronic device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, it implements the steps of the task processing method described in the first aspect of the present disclosure.

[0007] According to a fourth aspect of the present disclosure, a vehicle is provided, including a processor; a memory for storing processor-executable instructions; wherein the processor is configured to implement the steps of the task processing method described in the first aspect of the present disclosure.

[0008] According to a fifth aspect of the present disclosure, a computer-readable storage medium is provided that stores computer program instructions thereon, which, when executed by a processor, implement the steps of the task processing method described in the first aspect of the present disclosure.

[0009] According to a sixth aspect of the present disclosure, a chip is provided, the chip including an interface circuit and a processing circuit coupled to each other, the interface circuit being used to input or output signals, and the processing circuit being configured to implement the steps of the task processing method described in the first aspect of the present disclosure.

[0010] According to a seventh aspect of the present disclosure, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps of the task processing method described in the first aspect of the present disclosure.

[0011] The technical solution provided by the embodiments of this disclosure brings at least the following beneficial effects: It obtains the task queue of the processor core of the target device, and determines that the processor core is in a task-blocked state if duplicate task identifiers exist in the task queue. Therefore, it is only necessary to determine whether the processor core is in a task-blocked state by checking if duplicate task identifiers exist in the processor core's task queue. This is simple and easy to implement, and can effectively and quickly detect whether the processor core is in a task-blocked state, improving the detection efficiency and thus improving the task processing performance of the processor core. It is suitable for application scenarios such as smart cockpits.

[0012] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0013] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure, and are not intended to unduly limit this disclosure.

[0014] Figure 1 This is a flowchart illustrating a task processing method according to an exemplary embodiment.

[0015] Figure 2 This is a flowchart illustrating a task processing method according to another exemplary embodiment.

[0016] Figure 3 This is a flowchart illustrating a task processing method according to another exemplary embodiment.

[0017] Figure 4 This is a schematic diagram illustrating a task processing method according to an exemplary embodiment.

[0018] Figure 5 This is a schematic diagram of the structure of a task processing device according to an exemplary embodiment.

[0019] Figure 6 This is a schematic diagram of the structure of a vehicle according to an exemplary embodiment.

[0020] Figure 7 This is a schematic diagram of the structure of a chip according to an exemplary embodiment. Detailed Implementation

[0021] To enable those skilled in the art to better understand the technical solutions of this disclosure, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings.

[0022] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this disclosure described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure as detailed in the appended claims.

[0023] The following description, with reference to the accompanying drawings, describes a task processing method, apparatus, electronic device, vehicle, chip, and storage medium according to embodiments of the present disclosure.

[0024] Figure 1 This is a flowchart illustrating a task processing method according to an exemplary embodiment, such as... Figure 1 As shown, the task processing method of this disclosure includes the following steps.

[0025] S101, Obtain the task queue of the processor core of the target device.

[0026] It should be noted that the execution subject of the task processing method in this embodiment is an electronic device, such as a target device, server, chip, etc., and the server may include a cloud server, distributed server, etc. The task processing method in this embodiment can be executed by the task processing device in this embodiment, and the task processing device in this embodiment can be configured in any electronic device to execute the task processing method in this embodiment.

[0027] The target equipment is not limited in many ways. For example, it may include vehicles, terminal equipment, robots, smart home devices, smart office equipment, servers, etc. Vehicles include in-vehicle terminals (such as in-vehicle displays) and in-vehicle controllers (such as in-vehicle embedded controllers). Terminal devices may include mobile phones, tablets, wearable devices (such as smartwatches and smart glasses), robots may include industrial robots, cleaning robots, collaborative robots, and autonomous mobile robots, smart home devices may include televisions and speakers, and smart office equipment may include projectors and displays.

[0028] A processor core, also called a processor module or simply a core, is the basic computing unit of a CPU (Central Processing Unit). There is no strict limit to the number of processor cores a target device may contain; for example, it can have one or more. When a target device has multiple processor cores, the task queues for each core may differ.

[0029] Optionally, the task queue is used to store task identifiers of tasks that the processor core has not yet executed, as well as task identifiers of tasks that have not yet completed execution. It should be noted that unexecuted tasks refer to tasks that have not yet started execution, and tasks that have not yet completed execution refer to tasks that have started execution but have not yet finished.

[0030] Optionally, the task identifiers in the task queue are sorted from earliest to latest according to the execution order of the tasks, that is, the earlier the execution order of the task, the higher its task identifier is in the task queue.

[0031] It should be noted that there are no strict restrictions on how the execution order of tasks is determined. For example, the execution order of tasks can be determined based on their priority. For example, tasks can be sorted from highest to lowest priority to obtain the execution order of tasks. That is, the higher the priority of a task, the earlier it is executed, which can ensure that high-priority tasks are executed first.

[0032] For example, taking the target device as an on-board controller, such as Figure 4 As shown, the CPU of the vehicle controller includes processor cores 0 to 3. Each of processor cores 0 to 3 is equipped with tasks 1 to 3. Processor core 3 is also equipped with task 4. Processor cores 0 to 2 are not equipped with task 4. The task identifiers of tasks 1 to 4 are a, b, c, and d, respectively.

[0033] Task 1 is the first ISR (Interrupt Service Routine) task, Task 2 is a task with a trigger period of 2ms, Task 3 is a task with a trigger period of 5ms, and Task 4 is the second ISR task with a trigger period of 1ms. The second ISR task is used to determine whether processor cores 0 to 3 are in a task blocked state. The first ISR task refers to all other ISR tasks besides the second ISR task.

[0034] Tasks 2 through 4 are all periodic tasks, triggered at set times according to their respective trigger cycles. The priority of tasks 4, 1, 2, and 3 decreases in that order. The trigger cycle, also called the activation cycle or scheduling cycle, refers to the time interval between two consecutive triggers of a periodic task.

[0035] The task queues for processor core 0 are a, b, and c; the task queues for processor core 1 are a, b, b, and c; the task queues for processor core 2 are a, b, and c; and the task queues for processor core 3 are d, a, b, and c. The task identifiers in the task queues are sorted from earliest to latest according to the order in which the tasks are executed.

[0036] S102, if there are duplicate task identifiers in the task queue, determine that the processor core is in a task blocked state.

[0037] Understandably, if the processor core causes task X to not execute or not complete execution due to task timeout, lack of available resources, or other reasons, the task identifier of task X cannot be removed from the task queue. In addition, when task X is retried according to the triggering cycle, the task identifier of task X will be added back to the task queue, resulting in multiple task identifiers of task X in the task queue.

[0038] At this time, multiple tasks X are triggered simultaneously. Since the previously triggered task X has not been executed or has not been completed, the task X triggered later cannot be executed. That is, although the trigger time of the task X triggered later has been reached, it cannot be executed on time. It can be determined that the processor core is in a task blocking state.

[0039] Processor cores may be in a blocked state due to task timeouts, lack of available resources, or other reasons. This leads to longer task execution times and slower response times, impacting the processor core's task processing performance. To improve processor core task processing performance, it's possible to detect whether a processor core is in a blocked state. However, current detection methods are complex and cannot quickly detect whether a processor core is in a blocked state.

[0040] In this solution, it is only necessary to determine whether the processor core is in a task blocking state by checking whether there are duplicate task identifiers in the processor core's task queue. This method is simple and easy to implement, and can effectively and quickly detect whether the processor core is in a task blocking state, thereby improving the detection efficiency of whether the processor core is in a task blocking state and thus improving the task processing performance of the processor core.

[0041] For example, continuing with processor cores 0 to 3, the task queues of processor core 1 are a, b, b, and c. The task queue of processor core 1 contains a duplicate task identifier b, which indicates that processor core 1 is in a task blocked state.

[0042] The task processing method provided in the embodiments of this disclosure obtains the task queue of the processor core of the target device, and determines that the processor core is in a task blocked state if duplicate task identifiers exist in the task queue. Therefore, it is only necessary to determine whether the processor core is in a task blocked state by checking if duplicate task identifiers exist in the processor core's task queue. This method is simple and easy to implement, and can effectively and quickly detect whether the processor core is in a task blocked state, improving the detection efficiency and thus improving the task processing performance of the processor core.

[0043] For example, the task processing method provided in this disclosure can be applied to smart cockpits. For instance, it can obtain the task queue of the processor core of the vehicle controller. If there are duplicate task identifiers in the task queue, it can determine that the processor core of the vehicle controller is in a task blocking state. This can effectively and quickly detect whether the processor core of the vehicle controller is in a task blocking state, thereby improving the detection efficiency of whether the processor core of the vehicle controller is in a task blocking state, and thus improving the task processing performance of the processor core of the vehicle controller and optimizing the driving experience.

[0044] For example, the task processing method provided in this disclosure can be applied to terminal devices. For instance, the task queue of the mobile phone's processor core can be obtained. If there are duplicate task identifiers in the task queue, it can be determined that the mobile phone's processor core is in a task blocking state. This can effectively and quickly detect whether the mobile phone's processor core is in a task blocking state, thereby improving the detection efficiency of whether the mobile phone's processor core is in a task blocking state, and thus improving the task processing performance of the mobile phone's processor core and optimizing the driving experience.

[0045] Figure 2 This is a flowchart illustrating a task processing method according to another exemplary embodiment, such as... Figure 2 As shown, the task processing method of this disclosure includes the following steps.

[0046] S201, Obtain the task queue of the processor core of the target device.

[0047] S202, if there are duplicate task identifiers in the task queue, determine that the processor core is in a task blocked state.

[0048] The details of steps S201-S202 can be found in the above embodiments and will not be repeated here.

[0049] S203, if the task queues are consistent at multiple consecutive time points, determine that the processor core is in a task blocked state.

[0050] It is understandable that if the processor core causes task Y to not be executed or not to be completed for a long time due to task timeout, lack of available resources, etc., and task Y is not executed or not completed, the processor core cannot trigger or execute other tasks, resulting in the task queues being consistent at multiple consecutive time points.

[0051] Even if task Z, whose execution order is later than task Y, reaches its trigger time, it cannot be executed on time, which indicates that the processor core is in a task blocked state.

[0052] Optionally, if the task queues are consistent across multiple consecutive time points, determining that a processor core is in a task-blocked state includes at least one of the following methods:

[0053] Method 1: Obtain the first task with the shortest trigger cycle among processor core deployments. If the duration of the task queue is consistently greater than or equal to the trigger cycle of the first task at multiple consecutive time points, determine that the processor core is in a task blocking state.

[0054] Therefore, if the duration of the task queue at multiple consecutive time points is greater than or equal to the triggering period of the first task, it indicates that the first task cannot be re-triggered according to the triggering period, and it can be determined that the processor core is in a task blocking state.

[0055] Method 2: If the task queues are consistent across multiple consecutive time points, and the first task identifier in the task queue at multiple consecutive time points is the task identifier of the ISR task, then the processor core is determined to be in a task blocking state, and the task identifiers in the task queue are sorted from earliest to latest according to the execution order of the tasks.

[0056] Alternatively, if the task queues are consistent across multiple consecutive time points, and the task that the processor core is not executing or has not completed is an ISR task, then the processor core is determined to be in a task blocked state.

[0057] Therefore, if the task queues at multiple consecutive time points are consistent, and the first task in the task queue at multiple consecutive time points is identified as the task identifier of the ISR task, it indicates that the ISR task has not been executed or has not been completed for a long period of time. If the ISR task has not been executed or has not been completed, the processor core cannot trigger or execute other tasks, and it can be determined that the processor core is in a task blocked state.

[0058] For example, continuing with processor core 0, the first task deployed on processor core 0 with the shortest trigger cycle is task 2, which has a trigger cycle of 2ms. The system checks whether processor core 0 is in a task blocked state using a 1ms detection cycle.

[0059] If the task queue of processor core 0 is a, b, c at 0ms, a, b, c at 1ms, and a, b, c at 2ms, and the task queues of processor core 0 are consistent at 0ms, 1ms, and 2ms, and the duration of the consistency of the task queues of processor core 0 at 0ms, 1ms, and 2ms reaches 2ms, and the first task in the task queues of processor core 0 at 0ms, 1ms, and 2ms is identified by the task identifier 'a' of the first ISR task, it indicates that the first ISR task has not been executed or has not been completed for a relatively long period of time. If the first ISR task has not been executed or has not been completed, processor core 0 cannot trigger or execute other tasks, such as causing task 2 to be unable to be re-triggered according to the triggering cycle. It can be determined that processor core 0 is in a task blocked state.

[0060] S204 executes the task blocking process of the processor core.

[0061] It should be noted that the task blocking handling process is not limited in many ways, and different processor cores may correspond to different task blocking handling processes. For details on the task blocking handling process, please refer to the following embodiments, which will not be repeated here.

[0062] Optionally, before executing the task blocking processing flow for the processor core, the method further includes updating the cumulative number of times the processor core is in a task blocking state, and determining that the cumulative number is greater than or equal to a set number, and / or determining that the duration of the processor core being in a task blocking state is greater than or equal to a set duration. This allows for the counting of the cumulative number of times the processor core is in a task blocking state, and the execution of the task blocking processing flow when the cumulative number is large, and / or when the duration of the processor core being in a task blocking state is long, thus avoiding frequent execution of the task blocking processing flow and saving computing resources.

[0063] It should be noted that the cumulative count refers to the number of times a processor core is in a task-blocked state at multiple consecutive time points. For example, continuing with processor core 0, at a detection cycle of 1ms, if processor core 0 is in a task-blocked state at 0ms, the cumulative count is determined to be 1. If processor core 0 is in a task-blocked state at 1ms, the cumulative count is determined to be 2. If processor core 0 is in a task-blocked state at 2ms, the cumulative count is determined to be 3. If processor core 0 is not in a task-blocked state at 3ms, the cumulative count is reset to 0.

[0064] There are no strict limitations on the number of times or the duration. For example, the number of times can be set to 3, and the duration can be set to 5ms.

[0065] It should be noted that this disclosure does not impose any restrictions on the execution sequence of steps S201 to S204. Figure 2 The example only demonstrates the parallel execution of steps S202 and S203. For instance, steps S201, S203, and S204 can be implemented as standalone embodiments.

[0066] The task processing method provided in the embodiments of this disclosure determines that a processor core is in a task-blocked state when the task queues are consistent across multiple consecutive time points. Therefore, it is only necessary to determine whether the task queues of the processor core are consistent across multiple consecutive time points to determine whether the processor core is in a task-blocked state. This method is simple and easy to implement, and can effectively and quickly detect whether a processor core is in a task-blocked state, improving the detection efficiency and thus improving the task processing performance of the processor core.

[0067] In addition, after determining that the processor core is in a task blocking state, the process also includes executing the task blocking handling procedure of the processor core. This allows for timely handling of task blocking-related issues with the processor core, preventing it from remaining in a task blocking state for an extended period and helping to improve the task processing performance of the processor core.

[0068] Figure 3 This is a flowchart illustrating a task processing method according to another exemplary embodiment, such as... Figure 3 As shown, the task processing method of this disclosure includes the following steps.

[0069] S301, retrieve the task queue of the processor core of the target device.

[0070] S302, if there are duplicate task identifiers in the task queue, determine that the processor core is in a task blocked state.

[0071] S303 determines that the processor core is in a task blocked state when the task queues are consistent at multiple consecutive time points.

[0072] The relevant content of steps S301-S303 can be found in the above embodiments, and will not be repeated here.

[0073] S304 identifies the second task that caused the processor core to be in a task-blocked state.

[0074] It should be noted that the second task refers to the task that causes the processor core to be in a task blocking state, such as the second task including the task of timeout processing.

[0075] Optionally, determining the second task that causes the processor core to be in a task blocking state includes obtaining the task identified by the first task identifier in the task queue as the second task.

[0076] Alternatively, if there are duplicate task identifiers in the task queue, the task identified by the most recent duplicate task identifier in the task queue will be designated as the second task.

[0077] In this task queue, each task identifier is sorted from earliest to latest according to the execution order of the tasks.

[0078] Therefore, the second task causing the processor core to be in a blocked state can be determined simply by looking at the task queue. This is simple and easy to do, and can effectively and quickly locate the second task, improving the efficiency of locating the blocked task position and thus improving the task processing performance of the processor core.

[0079] For example, continuing with processor core 1, if the task queue of processor core 1 is a, b, b, c, and there is a duplicate task identifier b in the task queue of processor core 1, it can be determined that processor core 1 is in a task blocked state. The task identified by the most recent duplicate task identifier b in the task queue of processor core 1 is retrieved as the second task.

[0080] For example, continuing with processor core 0, if the task queue of processor core 0 is a, b, c at 0ms, a, b, c at 1ms, and a, b, c at 2ms, and the task queues of processor core 0 are consistent at 0ms, 1ms, and 2ms, it can be determined that processor core 0 is in a task blocked state. The first ISR task identified by the task identifier 'a' that is the first task in the task queue of processor core 0 at 0ms, 1ms, and 2ms is obtained and used as the second task.

[0081] S305, based on the second task, determines the task blocking information of the processor core.

[0082] Optionally, based on the second task, the task blocking information of the processor core is determined, including obtaining at least one of the task identifier, execution duration, and timeout duration of the second task as task blocking information.

[0083] Optionally, task blocking information of the processor core is determined based on the second task, including determining task blocking information based on the priority of the second task. Thus, task blocking information can be determined taking into account the priority of the second task.

[0084] Optionally, task blocking information is determined based on the priority of the second task, including determining whether the priority of the second task is the target priority. If the priority of the second task is the target priority, the information of the current thread of the processor core is obtained as the task blocking information. If the priority of the second task is not the target priority, the information of the thread associated with the second task is used as the task blocking information.

[0085] It should be noted that there are no excessive restrictions on the priority of objectives, such as the priority of ISR tasks.

[0086] Optionally, if no target task is deployed on the processor core, the target priority is the highest priority among all tasks deployed on the processor core. In this embodiment, when the second task has the highest priority, the processor core cannot execute any other tasks besides the second task if the second task has not been completed. Especially if the second task is an ISR task, the processor core cannot trigger or execute other tasks, and thus can obtain the information of the processor core's current thread as task blocking information. Conversely, if the second task does not have the highest priority, the processor core may pause the execution of the second task and execute other tasks with higher priority than the second task if the second task has not been completed, and thus can obtain the information of the thread associated with the second task as task blocking information.

[0087] The target task is used to determine whether the processor core of the target device is in a task blocked state. There are no strict limitations on the target task; for example, it can include an ISR task. The trigger period for the target task is 1ms.

[0088] For example, continuing with processor cores 0 to 3, the target task in this embodiment is the second ISR task.

[0089] The task queues of processor core 1 are a, b, b, and c. The presence of a duplicate task identifier b in the task queue indicates that processor core 1 is in a blocked state. Task 2, identified by the most recent duplicate task identifier b in the task queue of processor core 1, is retrieved as the second task.

[0090] Processor core 1 has no second ISR task deployed. The priority of the first ISR task is the highest priority among all tasks deployed on processor core 1. The priority of task 2 is not the highest priority among all tasks deployed on processor core 1. Information such as the thread associated with task 2, the task identifier b of task 2, the execution duration of task 2, and the timeout duration of task 2 can be obtained as task blocking information for processor core 1.

[0091] For example, if the task queue of processor core 0 is a, b, c at 0ms, a, b, c at 1ms, and a, b, c at 2ms, and the task queues of processor core 0 are consistent at 0ms, 1ms, and 2ms, it can be determined that processor core 0 is in a task blocked state. The first ISR task identified by the task identifier 'a' that is the first task in the task queue of processor core 0 at 0ms, 1ms, and 2ms is obtained and used as the second task.

[0092] Processor core 0 has no second ISR task deployed. The priority of the first ISR task is the highest priority of all tasks deployed on processor core 0. It can obtain information such as the current thread of processor core 0, the task identifier 'a' of the first ISR task, the execution duration of the first ISR task, and the timeout duration of the first ISR task, as the task blocking information of processor core 0.

[0093] Optionally, if a target task is deployed on the processor core and its priority is the highest priority, then the target priority is the next highest priority. In this embodiment, if the second task's priority is the next highest priority, and the second task has not been completed, the processor core cannot execute the target task or any other tasks besides the second task. The processor core can obtain the information of its current thread as task blocking information. Conversely, if the second task's priority is not the next highest priority, and the second task has not been completed, the processor core may pause the execution of the second task and execute other tasks with higher priorities. In this case, the processor core can obtain the information of the thread associated with the second task as task blocking information.

[0094] For example, the task queues of processor core 3 are d, a, b, and c. Processor core 3 has a second ISR task deployed, and the priority of the second ISR task is the highest priority of all tasks deployed on processor core 3.

[0095] If the second task is task 2, the priority of task 2 is not the next priority after the highest priority of each task deployed by processor core 3. Information such as the thread associated with task 2, the task identifier b of task 2, the execution duration of task 2, and the timeout duration of task 2 can be obtained as task blocking information of processor core 3.

[0096] If the second task is the first ISR task, the priority of the first ISR task is the next priority after the highest priority of each task deployed on processor core 3. It can obtain information such as the current thread of processor core 3, the task identifier a of the first ISR task, the execution duration of the first ISR task, and the timeout duration of the first ISR task, as the task blocking information of processor core 3.

[0097] S306 stores task blocking information.

[0098] S307, Remove the second task from the task queue.

[0099] Optionally, before removing the second task from the task queue, it is also included to determine whether the second task meets the removal conditions. Therefore, the second task can be removed from the task queue only if the removal conditions are met, ensuring that removing the second task does not affect the normal operation of the processor core and improving the operational reliability of the processor core.

[0100] There are no strict restrictions on the removal conditions; for example, the task type of the second task can be set as the type.

[0101] It should be noted that this disclosure does not limit the execution sequence of steps S301 to S307. For example, steps S301, S302, and S304 can be implemented as independent embodiments; steps S301, S302, S304, and S305 can be implemented as independent embodiments; steps S301, S302, and S304-S306 can be implemented as independent embodiments; steps S301, S302, S304, and S307 can be implemented as independent embodiments; steps S301, S303, S304, and S305 can be implemented as independent embodiments; steps S301, S303-S306 can be implemented as independent embodiments; and steps S301, S303, S304, and S307 can be implemented as independent embodiments.

[0102] The task processing method provided in the embodiments of this disclosure identifies a second task that causes the processor core to be in a task blocking state, determines task blocking information of the processor core based on the second task, stores the task blocking information, and removes the second task from the task queue. Thus, the second task causing the processor core to be in a task blocking state can be identified, i.e., the task blocking location of the processor core can be located; and / or, considering the second task, the task blocking information of the processor core can be accurately obtained; and / or, the task blocking information can be stored, i.e., the task blocking information can be saved to support root cause analysis, anomaly backtracking, and other processing; and / or, the second task can be removed from the task queue, thereby releasing the processor core from the task blocking state and improving the operational reliability of the processor core.

[0103] Based on any of the above embodiments, the task blocking process of the processor core further includes at least one of the following operations:

[0104] Operation 1: Generate target indication information.

[0105] The target indication information is used to indicate at least one of the following:

[0106] The processor core is in a task blocked state;

[0107] The second task encountered an error;

[0108] Processor core task blocking information.

[0109] This allows for the generation of target indication information, promptly informing users that the processor core is in a task-blocked state, that a second task has encountered an error, and other processor core task-blocking information, making it easier for users to understand.

[0110] Operation 2: Visualize and / or broadcast the target indication information.

[0111] Therefore, target instruction information can be conveyed to users through visual display and / or voice broadcast, so as to inform users in a timely manner that the processor core is in a task blocking state, the second task has encountered an error, and the processor core's task blocking information, thus simplifying user operation.

[0112] Operation 3: Send target indication information to the terminal device and / or the target device. The target indication information is used by the terminal device and / or the target device for visual display and / or voice broadcast.

[0113] Therefore, target indication information can be sent to terminal devices and / or target devices, so that the terminal devices and / or target devices can convey the target indication information to users through visual display and / or voice broadcast, and promptly inform users that the processor core is in a task blocking state, the second task has encountered an error, the processor core's task blocking information, etc., simplifying user operation.

[0114] Based on any of the above embodiments, the method further includes creating a target task, which is used to determine whether the processor core of the target device is in a task blocking state, and triggering the target task according to its triggering cycle. This enables periodic detection of whether the processor core is in a task blocking state.

[0115] For details regarding the target task, please refer to the above embodiments, which will not be repeated here.

[0116] Optionally, the target task is deployed on at least one processor core of the target device, and the target task is used to determine whether the processor core on which the target task is deployed is in a task blocking state.

[0117] Alternatively, the target task is deployed on the target processor core of the target device, and the target task is used to determine whether any processor core of the target device is in a task blocking state.

[0118] Therefore, the task processing method disclosed herein is applicable to multi-core processor application scenarios and can detect whether at least one processor core of a multi-core processor is in a task blocking state.

[0119] It should be noted that there are no strict restrictions on the number of target processor cores; for example, there can be one or more.

[0120] For example, continuing with processor cores 0 to 3, the target task in this embodiment is the second ISR task. The deployment methods of the second ISR task can include the following situations:

[0121] The first case, such as Figure 4 As shown, processor cores 0 to 2 do not have a second ISR task deployed, while processor core 3 has a second ISR task deployed. The second ISR task is used to determine whether processor cores 0 to 3 are in a task blocking state.

[0122] It should be noted that, Figure 4 The deployment method of the second ISR task shown is merely an example of the deployment method of the second ISR task of this disclosure, and is not a limitation on the deployment method of the second ISR task of this disclosure.

[0123] In the second scenario, processor cores 0 through 3 are all equipped with a second ISR task. The second ISR task deployed on processor core 0 is used to determine whether processor core 0 is in a task blocking state. The second ISR task deployed on processor core 1 is used to determine whether processor core 1 is in a task blocking state. The second ISR task deployed on processor core 2 is used to determine whether processor core 2 is in a task blocking state. The second ISR task deployed on processor core 3 is used to determine whether processor core 3 is in a task blocking state.

[0124] In the third scenario, processor cores 2 and 3 both have a second ISR task deployed. The second ISR task deployed by processor core 2 is used to determine whether processor cores 0 and 2 are in a task blocking state, and the second ISR task deployed by processor core 3 is used to determine whether processor cores 1 and 3 are in a task blocking state.

[0125] It should be noted that, in addition to the three situations mentioned above, the deployment of the second ISR task may also include other situations, which will not be elaborated here.

[0126] Optionally, the method further includes obtaining the load information of each processor core of the target device, and determining the target processor core from among the processor cores based on the load information. This allows for the determination of the target processor core by taking into account the load information of each processor core of the target device, avoiding situations where a high load on the target processor core leads to low detection efficiency for whether the processor core is in a task-blocked state. It ensures rapid detection of whether a processor core is in a task-blocked state, improving the detection efficiency and thus improving the task processing performance of the processor core.

[0127] It should be noted that there are no strict restrictions on load information, such as utilization rate and load rate.

[0128] For example, based on load information, the target processor core can be determined from among the processor cores. This includes sorting the processor cores according to their load information from smallest to largest and selecting the top N processor cores as the target processor cores, or selecting processor cores whose load information is less than or equal to a set threshold as the target processor cores. Thus, the target processor core with the lowest load can be selected from among the processor cores to execute the target task.

[0129] There are no strict restrictions on N; for example, it can be 1, 2, etc.

[0130] Figure 5 This is a schematic diagram illustrating the structure of a task processing apparatus according to an exemplary embodiment. (Refer to...) Figure 5 The task processing apparatus 500 of this embodiment includes: an acquisition module 501 and a determination module 502.

[0131] The acquisition module 501 is configured to acquire the task queue of the processor core of the target device.

[0132] The determination module 502 is configured to determine that the processor core is in a task blocked state when there are duplicate task identifiers in the task queue.

[0133] In some possible implementations, the determining module 502 is further configured to determine that the processor core is in a task blocked state when the task queues are consistent at multiple consecutive time points.

[0134] In some possible implementations, the determining module 502 is further configured to: obtain the first task with the smallest trigger cycle deployed by the processor core; and determine that the processor core is in a task blocking state if the duration of the task queue is consistent with the trigger cycle of the first task at multiple consecutive time points.

[0135] In some possible implementations, the device 500 further includes an execution module, which, after determining that the processor core is in a task blocking state, is configured to execute the task blocking processing flow of the processor core.

[0136] In some possible implementations, before executing the task blocking process of the processor core, the execution module is further configured to: update the cumulative number of times the processor core is in a task blocking state, and determine that the cumulative number is greater than or equal to a set number; and / or, determine that the duration of the processor core being in a task blocking state is greater than or equal to a set duration.

[0137] In some possible implementations, the execution module is further configured to perform at least one of the following operations:

[0138] Identify the second task that causes the processor core to be in a task-blocked state;

[0139] Based on the second task, determine the task blocking information of the processor core;

[0140] Store the task blocking information;

[0141] Remove the second task from the task queue.

[0142] In some possible implementations, the execution module is further configured to determine the task blocking information based on the priority of the second task.

[0143] In some possible implementations, the execution module is further configured to: determine whether the priority of the second task is a target priority; if the priority of the second task is the target priority, obtain the current thread information of the processor core as the task blocking information; if the priority of the second task is not the target priority, use the thread information associated with the second task as the task blocking information.

[0144] In some possible implementations, the execution module is further configured to: obtain at least one of the following information of the second task: task identifier, execution duration, and timeout duration, as the task blocking information.

[0145] In some possible implementations, the execution module is further configured to: acquire tasks that the processor core has not yet finished executing, and use them as the second task; or, if there are duplicate task identifiers in the task queue, use the task identified by the most recent duplicate task identifier as the second task, wherein the task identifiers in the task queue are sorted from earliest to latest according to the execution order of the tasks.

[0146] In some possible implementations, the execution module is further configured to perform at least one of the following operations:

[0147] Generate target indication information;

[0148] The target indication information is displayed visually and / or broadcast aloud.

[0149] Send the target indication information to the terminal device and / or the target device, wherein the target indication information is used by the terminal device and / or the target device for visual display and / or voice broadcast;

[0150] The target indication information is used to indicate at least one of the following:

[0151] The processor core is in a task blocked state;

[0152] The second task encountered an error;

[0153] The processor core's task blocking information.

[0154] In some possible implementations, the device 500 further includes a processing module configured to: create a target task, the target task being used to determine whether the processor core of the target device is in a task blocking state; and trigger the target task according to the triggering cycle of the target task.

[0155] In some possible implementations, the target task is deployed on at least one processor core of the target device, and the target task is used to determine whether the processor core on which the target task is deployed is in a task blocking state; or,

[0156] The target task is deployed on the target processor core of the target device, and the target task is used to determine whether any processor core of the target device is in a task blocking state.

[0157] In some possible implementations, the processing module is further configured to: acquire load information of each processor core of the target device; and, based on the load information, determine the processor core from which the target task is to be deployed.

[0158] Regarding the apparatus in the above embodiments, the specific manner in which each module performs its operation has been described in detail in the embodiments related to the method, and will not be elaborated upon here.

[0159] The task processing apparatus provided in the embodiments of this disclosure acquires the task queue of the processor core of the target device. If duplicate task identifiers exist in the task queue, it determines that the processor core is in a task blocked state. Therefore, it is only necessary to determine whether the processor core's task queue contains duplicate task identifiers to determine whether the processor core is in a task blocked state. This method is simple and easy to implement, and can effectively and quickly detect whether the processor core is in a task blocked state, improving the detection efficiency and thus improving the task processing performance of the processor core. It is suitable for applications such as smart cockpits.

[0160] To implement the above embodiments, this disclosure also proposes an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the program, it implements the steps of the task processing method provided in this disclosure. For example, the electronic device may include a vehicle.

[0161] To implement the above embodiments, this disclosure also proposes a vehicle, including a processor; a memory for storing processor-executable instructions; wherein the processor is configured to implement the steps of the task processing method provided in this disclosure.

[0162] Figure 6 This is a schematic diagram illustrating the structure of a vehicle according to an exemplary embodiment. For example, vehicle 600 can be a hybrid vehicle, a non-hybrid vehicle, an electric vehicle, a fuel cell vehicle, or other types of vehicles. Vehicle 600 can be an autonomous vehicle, a semi-autonomous vehicle, or a non-autonomous vehicle.

[0163] Reference Figure 6 The vehicle 600 may include various subsystems, such as an infotainment system 610, a perception system 620, a decision control system 630, a drive system 640, and a computing platform 650. The vehicle 600 may also include more or fewer subsystems, and each subsystem may include multiple components. Furthermore, each subsystem and each component of the vehicle 600 can be interconnected via wired or wireless means.

[0164] In some embodiments, the infotainment system 610 may include a communication system, an entertainment system, and a navigation system, etc.

[0165] The perception system 620 may include several sensors for sensing information about the environment surrounding the vehicle 600. For example, the perception system 620 may include a global positioning system (which may be GPS, BeiDou, or other positioning systems), an inertial measurement unit (IMU), lidar, millimeter-wave radar, ultrasonic radar, and a camera device.

[0166] The decision control system 630 may include a computing system, a vehicle controller, a steering system, a throttle, and a braking system.

[0167] The drive system 640 may include components that provide powered motion to the vehicle 600. In one embodiment, the drive system 640 may include an engine, an energy source, a transmission system, and wheels. The engine may be one or a combination of internal combustion engines, electric motors, and compressed air engines. The engine is capable of converting energy provided by the energy source into mechanical energy.

[0168] Some or all of the functions of vehicle 600 are controlled by computing platform 650. Computing platform 650 may include at least one processor 651 and memory 652, and processor 651 may execute instructions 653 stored in memory 652.

[0169] Processor 651 can be any conventional processor, such as a commercially available CPU. The processor may also include, for example, a Graphics Processing Unit (GPU), a Field Programmable Gate Array (FPGA), a System on Chip (SOC), an Application Specific Integrated Circuit (ASIC), or a combination thereof.

[0170] The memory 652 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk or optical disk.

[0171] In addition to instruction 653, memory 652 can also store data, such as road maps, route information, vehicle position, direction, speed, and other data. The data stored in memory 652 can be used by computing platform 650.

[0172] In this embodiment of the disclosure, processor 651 may execute instructions 653 to implement all or part of the steps of the task processing method provided in this disclosure.

[0173] In this embodiment of the vehicle, the task queue of the processor core of the target device is obtained. If duplicate task identifiers exist in the task queue, it is determined that the processor core is in a task blocking state. Therefore, it is only necessary to determine whether the processor core's task queue contains duplicate task identifiers to determine whether the processor core is in a task blocking state. This method is simple and easy to implement, and can effectively and quickly detect whether the processor core is in a task blocking state, thereby improving the detection efficiency of whether the processor core is in a task blocking state and thus improving the task processing performance of the processor core. It is suitable for application scenarios such as smart cockpits.

[0174] To implement the above embodiments, this disclosure also proposes a computer-readable storage medium storing computer program instructions thereon, which, when executed by a processor, implement the steps of the task processing method provided in this disclosure.

[0175] Alternatively, the computer-readable storage medium may be ROM, random access memory (RAM), CD-ROM, magnetic tape, floppy disk, and optical data storage device, etc.

[0176] To implement the above embodiments, this disclosure also proposes a chip including an interface circuit and a processing circuit coupled to each other, wherein the interface circuit is used to input or output signals, and the processing circuit is configured to implement the steps of the task processing method provided in this disclosure.

[0177] Figure 7 This is a schematic diagram illustrating the structure of a chip according to an exemplary embodiment. See also... Figure 7 The diagram shown is a schematic representation of the structure of chip 700, but is not limited thereto.

[0178] Chip 700 includes processing circuit 701, which is configured to perform any of the above task processing methods.

[0179] In some embodiments, chip 700 further includes one or more interface circuits 702. Optionally, interface circuit 702 is connected to memory 703, and interface circuit 702 can be used to receive signals from memory 703 or other devices, and interface circuit 702 can be used to send signals to memory 703 or other devices. For example, interface circuit 702 can read instructions stored in memory 703 and send the instructions to processing circuit 701.

[0180] In some embodiments, the interface circuit 702 performs at least one of the communication steps such as sending and / or receiving in the above method, and the processing circuit 701 performs other steps.

[0181] In some embodiments, the terms interface circuit, interface, transceiver pin, transceiver, etc., can be used interchangeably.

[0182] In some embodiments, chip 700 further includes one or more memories 703 for storing instructions. Optionally, all or part of the memories 703 may be located outside of chip 700.

[0183] To implement the above embodiments, this disclosure also proposes a computer program product, including a computer program that, when executed by a processor, implements the steps of the task processing method provided in this disclosure.

[0184] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the following claims.

[0185] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. A task processing method, characterized in that, include: Obtain the task queue of the processor core of the target device; If duplicate task identifiers exist in the task queue, the processor core is determined to be in a task blocked state.

2. The method according to claim 1, characterized in that, The method further includes: If the task queues are consistent across multiple consecutive time points, it is determined that the processor core is in a task blocked state.

3. The method according to claim 2, characterized in that, Determining that the processor core is in a task blocked state when the task queues are consistent at multiple consecutive time points includes: Obtain the first task with the shortest trigger cycle for the processor core deployment; If the duration of the task queue is consistently greater than or equal to the triggering period of the first task at multiple consecutive time points, the processor core is determined to be in a task blocked state.

4. The method according to any one of claims 1-3, characterized in that, After determining that the processor core is in a task blocked state, the process further includes: The task blocking process of the processor core is executed.

5. The method according to claim 4, characterized in that, Before the task blocking process of executing the processor core, the following is also included: Update the cumulative number of times the processor core is in a task blocked state, and determine that the cumulative number is greater than or equal to a set number; and / or, The duration during which the processor core is in a task-blocked state is determined to be greater than or equal to a set duration.

6. The method according to claim 4, characterized in that, The task blocking process for executing the processor core includes at least one of the following operations: Identify the second task that causes the processor core to be in a task-blocked state; Based on the second task, determine the task blocking information of the processor core; Store the task blocking information; Remove the second task from the task queue.

7. The method according to claim 6, characterized in that, The step of determining the task blocking information of the processor core based on the second task includes: Based on the priority of the second task, the task blocking information is determined.

8. The method according to claim 7, characterized in that, Determining the task blocking information based on the priority of the second task includes: Determine whether the priority of the second task is the target priority; If the priority of the second task is the target priority, obtain the current thread information of the processor core as the task blocking information; If the priority of the second task is not the target priority, the information of the thread associated with the second task shall be used as the task blocking information.

9. The method according to claim 6, characterized in that, The step of determining the task blocking information of the processor core based on the second task includes: Obtain at least one of the following information from the second task: task identifier, execution duration, and timeout duration, as the task blocking information.

10. The method according to claim 6, characterized in that, The determination of the second task that causes the processor core to be in a task-blocked state includes: The task identified by the first task identifier in the task queue is selected as the second task; or... If there are duplicate task identifiers in the task queue, the task identified by the most recent duplicate task identifier in the task queue shall be designated as the second task. The task identifiers in the task queue are sorted from earliest to latest according to the execution order of the tasks.

11. The method according to claim 6, characterized in that, The task blocking process for executing the processor core further includes at least one of the following operations: Generate target indication information; The target indication information is displayed visually and / or broadcast aloud. Send the target indication information to the terminal device and / or the target device, wherein the target indication information is used by the terminal device and / or the target device for visual display and / or voice broadcast; The target indication information is used to indicate at least one of the following: The processor core is in a task blocked state; The second task encountered an error; The processor core's task blocking information.

12. The method according to any one of claims 1-3, characterized in that, The method further includes: Create a target task, which is used to determine whether the processor core of the target device is in a task blocking state; The target task is triggered according to its triggering cycle.

13. The method according to claim 12, characterized in that, The target task is deployed on at least one processor core of the target device, and the target task is used to determine whether the processor core on which the target task is deployed is in a task blocking state; or... The target task is deployed on the target processor core of the target device, and the target task is used to determine whether any processor core of the target device is in a task blocking state.

14. The method according to claim 13, characterized in that, The method further includes: Obtain the load information of each processor core of the target device; Based on the load information, the target processor core is determined from the processor cores.

15. A task processing device, characterized in that, include: The acquisition module is configured to acquire the task queue of the processor cores of the target device. The determination module is configured to determine that the processor core is in a task blocked state if there are duplicate task identifiers in the task queue.

16. The apparatus according to claim 15, characterized in that, The determining module is further configured to: If the task queues are consistent across multiple consecutive time points, it is determined that the processor core is in a task blocked state.

17. The apparatus according to claim 16, characterized in that, The determining module is further configured to: Obtain the first task with the shortest trigger cycle for the processor core deployment; If the duration of the task queue is consistently greater than or equal to the triggering period of the first task at multiple consecutive time points, the processor core is determined to be in a task blocked state.

18. An electronic device, characterized in that, It includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, it implements the steps of the method according to any one of claims 1-14.

19. A vehicle, characterized in that, include: processor; Memory used to store processor-executable instructions; The processor is configured as follows: The steps for implementing the method according to any one of claims 1-14.

20. A computer-readable storage medium having computer program instructions stored thereon, characterized in that, When executed by a processor, the program instructions implement the steps of the method described in any one of claims 1-14.

21. A chip, characterized in that, The chip includes an interface circuit and a processing circuit coupled to each other. The interface circuit is used to input or output signals, and the processing circuit is configured to implement the steps of the method according to any one of claims 1-14.

22. A computer program product, characterized in that, It includes a computer program, which, when executed by a processor, implements the steps of the method according to any one of claims 1-14.

Images