Offset mode switching method and system

Abstract

The invention provides a bias mode switching method which can be applied to the technical field of computers. The method is applied to an accelerator, the accelerator comprises a monitor, a controller and a page table management unit, data interaction is performed between the accelerator and a host based on a computer fast interconnection protocol, and the method comprises the following steps: acquiring associated information of a target data page through the monitor for evaluation to obtain an evaluation result, the associated information comprises access information which is obtained by the monitor from the accelerator and the host and is related to the target data page; in response to the evaluation result representing that the associated information meets the bias switching condition, notifying the controller through the monitor to generate a bias switching request according to the bias switching condition; a page table management unit is called through a controller according to a bias switching request, a target bias field representing a target bias mode is written into a page table item of a target data page, and the target bias field indicates a path for accessing the target data page based on a computer fast interconnection protocol. The invention further provides a bias mode switching system.

Description

Technical Field

[0001] This application relates to the field of computer technology, specifically to the field of data processing, and more specifically to a bias mode switching method and system. Background Technology

[0002] As accelerators are increasingly used in artificial intelligence and big data scenarios, most data read and write operations on the accelerator should be performed in device bias mode to facilitate fast reading and writing of target data on the accelerator and thus accelerate computation. Only a small number of cases that require interaction with the host should switch the device bias mode to host bias mode to facilitate reading and writing target data in the host memory.

[0003] Current bias switching technologies either rely on the host machine for execution, using pre-installed software to determine bias switching, or they allow the accelerator to automatically adjust its bias state based on the target data page and its cache state, without depending on host software. The former is heavily reliant on the host, increasing the host's data processing load, which in turn increases the host's burden and reduces its performance. The latter, because it relies on the accelerator for natural judgment, can only handle simple distinctions and cannot be applied in complex scenarios. In particular, when the accelerator is used in artificial intelligence and big data scenarios, the data processing performance based on bias switching is poor, leading to difficulties in reading and writing data. Summary of the Invention

[0004] In view of the above problems, this application provides a method and system for switching the bias mode of data to improve the data read and write performance of accelerators in complex scenarios.

[0005] According to a first aspect of this application, a bias mode switching method is provided, applied to an accelerator, the accelerator including a monitor, a controller, and a page table management unit, the accelerator and a host interacting with each other based on the Computer Fast Interconnect Protocol (CHIPP). The method includes: obtaining and evaluating the association information of a target data page through the monitor to obtain an evaluation result, the association information including access information related to the target data page obtained by the monitor from the accelerator and the host; responding to the evaluation result indicating that the association information meets the bias switching conditions, the monitor notifies the controller to generate a bias switching request based on the target bias mode corresponding to the bias switching conditions; the controller calls the page table management unit according to the bias switching request to write a target bias field representing the target bias mode into the page table entry of the target data page, the target bias field indicating the path to access the target data page based on the CHIPP.

[0006] A second aspect of this application provides a bias mode switching system, comprising a host and an accelerator, wherein the accelerator and the host interact with each other via a Computer Fast Interconnect Protocol (CHIPP). The accelerator includes: a monitoring module, configured to acquire and evaluate the association information of a target data page, obtaining an evaluation result; the association information including access information related to the target data page acquired by the monitoring module from the accelerator and the host; a controller module, configured to receive a notification from the monitoring module in response to the evaluation result indicating that the association information satisfies the bias switching conditions, and generate a bias switching request based on the target bias mode corresponding to the bias switching conditions; and a page table management unit module, configured to, in response to the bias switching request, write a target bias field representing the target bias mode into a page table entry of the target data page, the target bias field indicating the path to access the target data page based on the CHIPP.

[0007] According to the bias mode switching method and system of this application, the target data page is evaluated by the accelerator's monitor to obtain the evaluation result. Then, in response to the evaluation result indicating that the associated information meets the bias switching conditions, the monitor notifies the controller to generate a bias switching request based on the target bias mode corresponding to the bias switching conditions. Then, the accelerator's controller calls the page table management unit according to the bias switching request to write the target bias field representing the target bias mode into the page table entry of the target data page, thus completing the bias mode switching. Since the entire process is completed by the accelerator's monitor and controller, the bias mode switching method of this application is completely led by the accelerator, thus eliminating the need for host-led participation to complete the bias mode switching. Therefore, regardless of whether the target data page is in the accelerator or the host, the monitor can obtain the relevant access information of the target data page and obtain the associated information, thereby dynamically controlling the access path of the target data page between the accelerator and the host, which can reduce the host's computing burden and improve the response speed and data processing efficiency of bias switching. Attached Figure Description

[0008] The above-mentioned contents, other objects, features and advantages of this application will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0009] Figure 1 This illustration schematically depicts an application scenario of the bias mode switching method, apparatus, and device according to embodiments of this application.

[0010] Figure 2 A flowchart illustrating a bias mode switching method according to an embodiment of this application is shown schematically.

[0011] Figure 3This illustration schematically shows the data flow between functional components in the bias mode switching method according to an embodiment of this application when the device is an accelerometer;

[0012] Figure 4 The diagram illustrates a page table entry involved in the bias mode switching method according to an embodiment of this application.

[0013] Figure 5 This schematically illustrates a structural block diagram of a bias mode switching system according to an embodiment of the present application;

[0014] Figure 6 A block diagram schematically illustrates an electronic device suitable for implementing a bias mode switching method according to an embodiment of this application. Detailed Implementation

[0015] The embodiments of this application will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of this application. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of this application for ease of explanation. However, it will be apparent that one or more embodiments may be implemented without these specific details. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of this application.

[0016] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The terms “comprising,” “including,” etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0017] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0018] When using expressions such as "at least one of A, B and C", they should generally be interpreted in accordance with the meaning that is commonly understood by those skilled in the art (e.g., "a system having at least one of A, B and C" should include, but is not limited to, a system having A alone, a system having B alone, a system having C alone, a system having A and B, a system having A and C, a system having B and C, and / or a system having A, B and C, etc.).

[0019] Figure 1 The diagram illustrates an application scenario of the bias mode switching method according to an embodiment of this application.

[0020] like Figure 1 As shown, application scenario 100 according to this embodiment may include a first terminal device 101, a second terminal device 102, a third terminal device 103, a network 104, and a server 105. The network 104 serves as a medium for providing a communication link between the first terminal device 101, the second terminal device 102, the third terminal device 103, and the server 105. The network 104 may include various connection types, such as wired or wireless communication links, or fiber optic cables, etc.

[0021] Users can use the first terminal device 101, the second terminal device 102, and the third terminal device 103 to interact with the server 105 via the network 104 to receive or send messages, etc. Various communication client applications can be installed on the first terminal device 101, the second terminal device 102, and the third terminal device 103, such as shopping applications, web browser applications, search applications, instant messaging tools, email clients, social media platform software, etc. (for example only).

[0022] The first terminal device 101, the second terminal device 102, and the third terminal device 103 can be various electronic devices with displays and support web browsing, including but not limited to smartphones, tablets, laptops, and desktop computers.

[0023] Server 105 can be a server that provides various services, such as a backend management server that supports websites browsed by users using the first terminal device 101, the second terminal device 102, and the third terminal device 103 (this is just an example). The backend management server can analyze and process data such as received user requests, and feed back the processing results (such as web pages, information, or data obtained or generated according to user requests) to the terminal devices.

[0024] It should be noted that the bias mode switching method provided in this application embodiment can be executed by server 105. Accordingly, the bias mode switching method provided in this application embodiment can also be executed by a server or server cluster that is different from server 105 and is capable of communicating with the first terminal device 101, the second terminal device 102, the third terminal device 103 and / or server 105.

[0025] It should be understood that Figure 1 The number of terminal devices, networks, and servers shown is merely illustrative. Depending on implementation needs, any number of terminal devices, networks, and servers can be included.

[0026] The following will be based on Figure 1 The described scene, through Figures 2-4 The bias mode switching method of the application embodiments is described in detail.

[0027] Figure 2 A flowchart illustrating a bias mode switching method according to an embodiment of this application is shown.

[0028] like Figure 2 As shown, the bias mode switching method of this embodiment includes operations S210 to S230. This method is applied to an accelerator, which includes a monitor, a controller, and a page table management unit. The accelerator and the host interact with each other based on the Computer Fast Interconnect Protocol. The method specifically includes the following:

[0029] In operation S210, the associated information of the target data page is obtained and evaluated by the monitor to obtain the evaluation result. The associated information includes access information related to the target data page obtained by the monitor from the accelerator and the host. In operation S220, in response to the evaluation result indicating that the associated information meets the bias switching conditions, the monitor notifies the controller to generate a bias switching request according to the target bias mode corresponding to the bias switching conditions. In operation S230, the controller calls the page table management unit according to the bias switching request to write the target bias field representing the target bias mode into the page table entry of the target data page. The target bias field indicates the path to access the target data page based on the computer fast interconnect protocol.

[0030] This accelerator is a CXL accelerator, which communicates with the host based on the CXL (Compute Express Link) protocol. Essentially, this accelerator is a storage device with local memory; it will be referred to as the "device" below. Since the accelerator's device memory may be accessed by two processors—the accelerator itself and the host it communicates with—and both the accelerator and the host have their own memory, different bias modes are used depending on the target data. Host bias mode requires host intervention to perform data consistency checks before accessing the target data page. For example, when the target data page is data submitted to the device memory by the host, the accelerator needs to perform consistency checks through the host when accessing its own device memory. This is suitable for scenarios where the host transmits data to the device or reads results. In this case, under host bias mode, the target data page can be directly read / written / modified in the host's memory, allowing the host to access the target data page. Device bias mode does not require host intervention and allows the accelerator to access its own stored data pages. For example, when the target data is data directly sent to the device by a third party, the device can read / write / modify the data page. In this case, under device bias mode, the target data page can be directly read / written / modified in the accelerator's device memory.

[0031] As an example, the accelerator includes a monitor, a controller, and a page table management unit. First, the monitor monitors the data of the accelerator and host connected via the CXL protocol. Data passing through the accelerator and the host are considered target data pages. When the monitor listens for a target data page, it first obtains the associated information of the target data page. This associated information includes access information related to the target data page obtained by the monitor from the accelerator and the host. Then, the monitor evaluates this associated information to obtain an evaluation result. Based on this result, it determines whether the associated information meets the offset switching condition. If it does, the monitor then... The controller generates an offset switching request based on the target offset mode corresponding to the offset switching conditions. Then, the page table management unit writes the target offset field, which represents the target offset mode, into the page table entry of the target data page. Since the target offset field indicates the path to access the target data page based on the Computer Fast Interconnect Protocol, the operation of writing the target offset field into the page table entry can directly complete the offset mode switching, thereby improving the efficiency of offset mode switching and reducing the time consumption of offset switching. Moreover, the entire offset switching operation process is led by the device without the need for host intervention, thereby reducing the computing burden of the host.

[0032] In this embodiment, the associated information of the target data page includes at least one of the following: the cache hit rate of the target data page in the accelerator and the host, the current remaining memory of the accelerator, the current remaining memory of the host, the bias instruction in the access request, and the persistent storage requirements of the target data page.

[0033] Therefore, based on the association information of the target data page, the target bias mode corresponding to the target data page can be quickly identified. Then, the device can initiate a switch to the target bias mode corresponding to the side with a higher cache hit rate of the target data page, or the target bias mode corresponding to the side with sufficient memory. This frees up memory space and achieves the effect of comprehensive memory resource management. Alternatively, the bias mode can be switched to the target bias mode indicated by the bias instruction in the access request, or the target bias mode corresponding to persistent storage requirements. This improves the overall adaptability of the bias mode and the target data page, thereby reducing the host load and improving data processing efficiency.

[0034] Correspondingly, the target bias mode corresponding to the bias switching condition is determined through at least one of the following operations: determining the target bias mode as a device bias mode in response to the target data page's cache hit rate on the accelerator being greater than or equal to a hit rate threshold; determining the target bias mode as a host bias mode in response to the target data page's cache hit rate on the host being greater than or equal to a hit rate threshold; determining the target bias mode as a host bias mode in response to the accelerator's current remaining memory being less than or equal to a memory threshold; determining the target bias mode as a device bias mode in response to the host's current remaining memory being less than or equal to a memory threshold; using the bias mode indicated by the bias instruction as the target bias mode; determining the target bias mode as a host bias mode in response to the target data page having persistent storage requirements; and determining the target bias mode as a device bias mode in response to the target data page not having persistent storage requirements.

[0035] As an example, when evaluating the target data, it is sufficient to obtain a series of related information such as the cache hit rate of the target data page on the accelerator and the host, the current remaining memory of the accelerator, the current remaining memory of the host, the bias instructions in the access request, and the persistent storage requirements of the target data page. Different related information corresponds to different target bias modes.

[0036] On one hand, after obtaining the cache hit rate of the target data in the device or host, the cache hit rate is compared with a preset hit rate threshold. If the cache hit rate of the target data in the device is higher than the preset device hit rate threshold, the target bias mode can be determined to be the device bias mode. If the current bias mode is the host bias mode, then the current bias mode is inconsistent with the bias mode corresponding to the target data, and the target bias mode can be switched to the device bias mode. Conversely, if the cache hit rate of the target data in the host is higher than the preset host hit rate threshold, and the current bias mode is the device bias mode, then the current bias mode is inconsistent with the bias mode corresponding to the target data, and the target bias mode can be determined to be the host bias mode. It should be noted that if the target bias mode is the same as the current bias mode, switching is not necessary, or the device controller can initiate a switching operation. Since the current bias mode is itself the target bias mode, even if a switch is initiated, the bias mode after the switch will still be the same as the current bias mode.

[0037] On the other hand, the current remaining memory of the accelerator and the current remaining memory of the host are obtained. The current remaining memory can be calculated by calculating the storage utilization rate of the current accelerator or host. The remaining memory can be calculated by obtaining the storage utilization rate of the accelerator or host. If the current remaining memory of the accelerator is less than or equal to the memory threshold, the target bias mode can be determined to be the host bias mode. If the current remaining memory of the host is less than or equal to the memory threshold, the target bias mode can be determined to be the device bias mode. This aspect is consistent with the first aspect mentioned above. In the specific switching process, if the current bias mode is different from the target bias mode, the switch can be performed directly. If the target bias mode is the same as the current bias mode, the switch can be skipped or the device controller can initiate the switching operation. Since the current bias mode is itself the target bias mode, even if the switch is initiated, the bias mode after the switch will still be the same as the current bias mode.

[0038] The specific values ​​of the hit rate threshold and memory threshold mentioned above are not limited and can be determined according to the specific application of the host and device. In a specific example, the hit rate threshold can be 15% and the memory threshold can be 20% of the total storage of the device / host itself.

[0039] Therefore, when the target data is frequently accessed by the device or host, the device initiates a switch from host / device bias mode to device / host bias mode to reduce access latency; when the device or host has insufficient memory, the device initiates a switch to the target bias mode corresponding to the side with sufficient memory to release memory space and achieve the effect of comprehensive memory resource management.

[0040] On the other hand, if the identifier identifying the source of the target data is a third-party application identifier, it means that the source of the target data is a third-party application. Therefore, the bias mode indicated by the bias instruction sent by the third-party application needs to be used as the target bias mode. If the target bias mode is different from the current bias mode, the current bias mode is not consistent with the target bias mode. The current bias mode can be directly switched to the target bias mode indicated by the bias instruction. If the target bias mode is the same as the current bias mode, there is no need to switch, or the device controller can initiate the switch. Since the current bias mode is itself the target bias mode, even if a switch is initiated, the bias mode after the switch will still be the same as the current bias mode.

[0041] Furthermore, when monitoring target data, the data retention period of the target data can also be obtained. If the target data page has persistent storage requirements, the target bias mode is determined to be host bias mode to facilitate long-term storage of the target data. If the target data page does not have persistent storage requirements, the target bias mode is determined to be device bias mode, thereby achieving comprehensive management of the storage space of devices and hosts and improving storage utilization.

[0042] In this embodiment, before evaluating the associated information of the target data page obtained through the monitor, the method further includes: monitoring access information of the device memory for the accelerator and monitoring access information of the host memory for the host through the monitor to receive access requests for the target data page, which is stored in the device memory or the host memory.

[0043] Figure 3 This diagram illustrates the data flow between functional components involved in the bias mode switching method of this embodiment when the device is an accelerator. As an example, data pages passing through the accelerator and the host are both target data pages. This target data is also related to the access information of the accelerator and the host. In other words, the device's access information is monitored by the monitor, and the host's access information is also monitored by the monitor. Therefore, in... Figure 3 In the illustrated embodiment, all target data can be monitored by the accelerator's own monitor, which is the accelerator's own monitor, i.e., the device's own monitor. Therefore, in Figure 3 In the illustrated embodiment, the monitor is a device monitor 310. After the device or host receives the access information, the device monitor 310 can monitor the access information of the device memory for the accelerator and the access information of the host memory for the host to receive access requests for the target data page. The target data page is stored in the device memory or the host memory, which facilitates the device monitor to make subsequent judgments. After detecting that the bias switching condition is met, the device controller is notified to perform the subsequent bias mode switching operation, which facilitates the accelerator to lead the bias mode switching process, thereby reducing the host's computing burden and improving the performance of bias switching.

[0044] That is, the above-mentioned monitoring and judgment of target data operations are performed by the device's own device monitor 310. After the device monitor detects that the target data meets the bias switching conditions, it notifies the controller through operation S310. In this embodiment, the controller is also part of the device itself. Therefore, in this embodiment, the controller is the device controller 320. The specific bias mode switching operation is performed by the device's own device controller 320, thereby solving the technical problem that current bias switching methods either use preset software in the host to perform bias switching, increasing the host load, or allow the device to perform bias switching naturally based on the current request and cache state without relying on the host software, resulting in the inability to apply in complex scenarios. This reduces the host load while improving the performance of bias switching.

[0045] In this embodiment, the host includes a proxy unit, and the method further includes: in response to the evaluation result indicating that the associated information meets the bias switching condition, embedding interrupt information into a flow control unit data packet based on the computer fast interconnect protocol; sending the flow control unit data packet to the proxy unit through the controller to instruct the host to interrupt access to the target data page based on the interrupt information, in order to wait for the bias mode to switch; in the event of an interruption, in response to the inconsistency between the current bias mode in the page table entry and the target bias mode, synchronizing the cached data of the target data page between the accelerator's device memory and the host's host memory using a cache coherence protocol.

[0046] As an example, by operating S320, an interrupt message is sent to the host agent based on the CXL Flit (Flow Control Unit). The flow control unit contains information waiting for the bias state to switch. The flow control unit data packet can be a Flit data packet, that is, the operation interrupts the access to the target data page based on the Flit data packet with additional interrupt information. In other words, the controller sends a Flit data packet carrying interrupt information to the agent unit to instruct the host to interrupt the access to the target data page based on the interrupt information. At the same time, based on the operation of S330, a bias switching request is triggered to wait for the bias mode to switch, thereby quickly interrupting the operation of the current bias mode and laying the foundation for the rapid execution of the bias mode switch.

[0047] Then, the page table management unit 330 manages the page table entries of the target data and performs operations S340. By modifying the attribute fields in the page table entries, the bias mode of the target data is changed, thereby switching to the target bias mode.

[0048] However, in the event of an interruption, the current bias mode in the page table entry is inconsistent with the target bias mode. Data that has been processed under the current bias mode has not yet been actually stored in the cache. This data is dirty data formed during the bias switching process. Therefore, it is necessary to use a cache coherence protocol to synchronize the cache data of the target data page between the accelerator's device memory and the host's host memory to eliminate dirty data.

[0049] Specifically, the steps for eliminating dirty data are related to whether the target bias mode is device bias mode or host bias mode. In this embodiment, the accelerator also includes a device cache, and the host also includes a host cache. Synchronizing the cached data of the target data page between the accelerator's device memory and the host's host memory using a cache consistency protocol includes: when the current bias mode is host bias mode and the target bias mode is device bias mode, migrating the cached data in the host cache to the host memory, and then synchronizing it from the host memory to the device memory via a universal serial bus; or, when the current bias mode is device bias mode and the target bias mode is host bias mode, migrating the cached data in the device cache to the device memory, and then synchronizing it from the device memory to the host memory via a universal serial bus.

[0050] As an example, when the current bias mode is host bias mode and the target bias mode is device bias mode, operation S350 needs to be performed first to migrate the cached data in the host cache to the host memory, and then operation S360 needs to be performed to synchronize from the host memory to the device memory via the universal serial bus. That is, when the target bias mode is host bias mode, before storing the target data according to the storage address indicated by the target bias mode, it is first necessary to obtain the dirty data generated during the storage of the target data in host bias mode. This dirty data is the cached data of the target data that has been modified in device bias mode but has not yet been stored in the device. Then, the dirty data is stored in the device memory of the device to avoid the loss of cached data and ensure the integrity of the target data storage.

[0051] In this embodiment, the accelerator further includes a device cache, and the host further includes a host cache. Synchronizing the cached data of the target data page between the accelerator's device memory and the host's host memory using a cache consistency protocol includes: when the current bias mode is host-biased mode and the target bias mode is device-biased mode, in response to the host memory having a shared physical space for both the accelerator and the host, migrating the cached data in the host cache to the shared physical space, and mapping the shared physical space to the accelerator; or, when the current bias mode is device-biased mode and the target bias mode is host-biased mode, in response to the device memory having a shared physical space for both the accelerator and the host, migrating the cached data in the device cache to the shared physical space, and mapping the shared physical space to the host.

[0052] In a specific example, suppose the target data contains one hundred data entries. Before the switch, the bias mode is device bias mode, and the target bias mode to switch to is host bias mode. That is, while in device bias mode, six data entries are about to be stored. These six data entries have been modified or cached, but have not yet been permanently stored in the device. If the bias field of the target data has been modified or cached, and the switch to target bias mode is about to begin, these six data entries are considered dirty data generated in device bias mode. Before executing target bias mode, these six data entries need to be stored in the device memory corresponding to the device bias mode. Then, the dirty data in the device memory is stored in the host memory. The remaining ninety-four target data entries can be stored normally according to the subsequent host bias mode, thereby avoiding the loss of cached data and ensuring the integrity of the target data storage.

[0053] Taking the current bias mode as host bias mode and the target bias mode as device bias mode as an example, when storing dirty data from device memory through the host's host memory, if the device memory and host memory have shared physical storage space, the dirty data can be stored in the shared physical storage space. Furthermore, as mentioned above, if the device memory and host memory do not have shared physical storage space, the dirty data is copied from device memory to the host's host memory via a preset transfer bus.

[0054] In a specific example, if the device has five physical storage spaces, one of which is a shared physical storage space with the host, and the other four are independent physical storage spaces for the device, then in this case, dirty data in the device can be stored in the physical storage space shared by the device and the host. Thus, when the target bias mode is host-biased, the host can directly access the shared physical space when it needs to access the target data. If the device and the host do not have shared physical storage space, dirty data can be copied from the device's memory to the host's memory via a pre-defined transfer bus. Therefore, when shared physical storage space is available, the device is prioritized to store its own dirty data in its own shared physical storage space for the host to access, thereby reducing the device's workload and operational burden.

[0055] The above operation describes the process of storing dirty data from the device to the host when the target bias mode is host bias mode. This facilitates the host's access to the dirty data (which becomes ordinary target data after being stored on the host). Since the device's computing power is not as strong as the host's, dirty data is preferentially stored in the shared physical storage space when both have shared physical storage space. However, if the target bias mode is device bias mode, then the bias mode before the switch is host bias mode, and the host's computing power is relatively stronger. Therefore, in this embodiment, when the target bias mode is device bias mode, dirty data generated during the storage of target data in host bias mode can be obtained first. Dirty data refers to cached data of target data that has been modified in host bias mode but has not yet been stored on the host. The dirty data is stored in the host's host memory. The dirty data is then copied from the host memory to the device memory of the device via a preset transmission bus.

[0056] Furthermore, in another embodiment, when the target bias mode is a device bias mode, the method further includes: migrating dirty data generated by caching the target data in host bias mode from the host memory to the device's local memory based on a preset lazy migration algorithm. The lazy migration algorithm is as follows: when the target data needs to be accessed, the dirty data generated by caching the target data in host bias mode is migrated from the host memory to the device's local memory.

[0057] As an example, dirty data was generated when caching target data in the host-biased mode before the switch. However, this dirty data did not need to be processed immediately; it could simply be stored in the host memory. After the switch, when the dirty data was needed in the device-biased mode, it was then migrated from the host memory to the device's local memory. This allows only the necessary data to be stored, reducing the total amount of data stored on the device and lessening the storage burden.

[0058] In another embodiment, when the target bias mode is the device bias mode, since the host has relatively strong computing performance, when processing dirty data, it obtains the dirty data in the host bias mode, stores the dirty data in the host memory, and then directly copies the dirty data to the device memory of the device via a preset transmission bus. In this way, the shared physical storage space is avoided and the shared physical storage space is reserved for the device with relatively poor computing performance, thereby balancing the computing power between the host and the device.

[0059] In this embodiment, in response to completing the synchronization between the device memory of the accelerator and the host memory of the host, the method further includes: when the current bias mode is host bias mode and the target bias mode is device bias mode, executing a cache line invalidation command on cached data in the host cache through a proxy unit, the proxy unit being used to return a success signal to the controller when deleting cached data; or, when the current bias mode is device bias mode and the target bias mode is host bias mode, executing a cache line invalidation command on cached data in the device cache through the controller.

[0060] As an example, to ensure that subsequent accesses use the new bias mapping, the device manager or host agent needs to be notified via S370, and then cached entries related to the page in the host and device are invalidated based on operation S380. This invalidates cached entries for the target data prior to the bias switch, ensuring that subsequent accesses use the target bias mode to map the target data, improving the stability and accuracy of subsequent data usage.

[0061] More specifically, in this embodiment, in operation S230, writing the target bias field representing the target bias mode into the page table entry of the target data page by calling the page table management unit through the controller includes: writing the target valid bit, target bias mode type, target permission bit, target storage address, and target caching policy into the page table entry through the page table management unit. The target bias mode type is associated with the target storage address and the target caching policy, respectively. Among them, the target valid bit is used to indicate the availability status of the target data page, the target bias mode type is used to indicate the target bias mode, the target permission bit is used to indicate the access permission of the accelerator, the target storage address is used to indicate storing the target data page in the device memory of the accelerator or the host memory of the host, and the target caching policy is used to indicate caching the target data page according to the write-through policy or the write-back policy.

[0062] Figure 4 A schematic diagram of the page table entries involved in the bias mode switching method of this embodiment is shown.

[0063] The page table entries for this target data can be obtained from Figure 3 The page table is managed by the preset page table management unit 330 shown, wherein the page table entry is used to describe the attributes of the target data, and the page table entry is as follows: Figure 4As shown, the target data includes various attribute fields describing the target data. Among them, the attribute field for switching the bias of the target data is the bias attribute field, also known as the bias field. This bias field may include a valid bit, a target bias mode type, a permission bit, a target caching policy, an address pointer representing the target storage address, and the physical address associated with the address pointer. This physical address is the target storage address. In this embodiment, the target bias mode type is the bias type corresponding to the target bias mode. Changing the bias field of the target data can change the bias mode of the target data, that is, the page table management unit writes the representation in the page table entry of the target data page. The target bias field of the target bias mode can switch the current bias mode to the target bias mode. In this example, if the target data meets the bias switching conditions, the bias switching can be performed directly. That is, by using multiple target bias fields of the target bias mode, the multiple current bias fields representing the bias mode in the page table entries of the target data can be updated to completely modify the bias fields of the target data, forming the target bias field. The default program can execute the target bias mode based on the target bias field. The target bias mode is either host bias mode or device bias mode, thereby switching the bias mode to the target bias mode most suitable for the target data.

[0064] In a specific example, Figure 3 , Figure 4 In the specific example shown, the page table entries for the target data are managed through a multi-level page table management unit 330. Each page table entry (PTE) contains a bias attribute field, which indicates the current bias mode of the data page for that target data. The essence of bias switching is to change the access path and ownership of the data by modifying the bias field in the page table entry and simultaneously adjusting mechanisms such as cache consistency and data migration.

[0065] This page table entry may include: a valid bit, indicating whether the page's memory data is available (0 for unavailable, 1 for available); a bias type (1 bit or 0 bit), indicating the page's current bias mode (0 = Host Bias, 1 = Device Bias); and a cache policy, associated with the bias mode and determining the specific caching behavior of the target data page, such as storing it on the host or on the device. Host Bias represents the host bias mode, typically using a Write-Through (WT) strategy to ensure timely consistency of host memory data. Device Bias represents the device bias mode, typically using a Write-Back (WB) strategy to leverage the high speed of the device's local memory, reducing cache refreshes and improving write performance. Access Permissions: Indicates the access permissions (read / write / execute) of a device or host, configured by the host via CXL commands; Address Pointer: Points to different address spaces depending on the bias type; Host Bias indicates the host bias mode, pointing to the host's physical memory address (such as host memory mapped via space mapping, or host memory mapped via CXL MAU (Memory Access Unit); Device Bias indicates the device bias mode, pointing to the device's local memory address, such as the private address space of the device's internal DRAM (Dynamic Random Access Memory).

[0066] Therefore, the bias mode of the target data can be changed by modifying the attribute fields in the page table entries, thereby enabling targeted storage of the target data.

[0067] Based on this, bias switching can be achieved by modifying the content of the bias field, reducing the complexity of bias switching and improving switching efficiency.

[0068] After switching the bias mode to the target bias mode, operation S390 can be performed to cause the host agent to return a switching success signal to the requester, and the device will use the new target bias mode path when accessing the page subsequently.

[0069] exist Figure 3 , Figure 4In the specific example shown, taking the switch from host bias mode to device bias mode as an example, in operation S310, the device monitor notifies the device controller after detecting that the target data meets the bias switching conditions; operation S320 causes the device controller to send an interrupt message to the host agent through the flow control minimum unit based on the CXL protocol. This interrupt message contains information waiting for the bias state switch, and simultaneously, operation S330 triggers a bias switching request; operation S340, based on the bias switching request, causes the page table management unit to find the PTE (Page Table). Entry (page table entry) changes the bias field in the page table entry from the bias field indicated by the host bias mode to the bias field indicated by the device bias mode (and vice versa), thereby updating the address pointer (target storage address, such as changing from the host's memory address to the device's memory address). Then, if the switch involves dirty data, the cache needs to be refreshed based on the CXL protocol. For example, when switching from host bias mode to device bias mode, operation S350 is required to make the host refresh the dirty data in the cache to host memory 350, i.e., host caching. Then, operation S360 is performed to have the host copy the data in host memory 350 to device memory 340 through the PCIe (Peripheral Component Interconnect Express) bus, or lazy migration is used, which does not process the data in host memory in time, but waits until the target data (data page) is needed in host memory before it is migrated from host memory to device memory. Conversely, to switch from device bias mode to host bias mode, the S350 device must first flush dirty data in its cache to device memory 340 (i.e., perform device caching), and then the S360 device copies data from its device memory to host memory 350 via the PCIe bus. Furthermore, to ensure that subsequent accesses use the new bias mapping, operation S370 notifies the device manager or host agent. For example, if the target bias mode is device bias mode, after switching the bias mode to device bias mode, operation S380 notifies the host to invalidate (delete) the cache entry for the target data in the host, such as through the CXL.cache Invalidate command / cache line invalidation command, to ensure that subsequent accesses use the new bias mode to map the target data. Conversely, if the target bias mode is host bias mode, after switching the bias mode to host bias mode, operation S380 notifies the device to invalidate (delete) the cache entry for the target data in the device, to ensure that subsequent accesses use the host bias mode to map the target data. After switching to the target bias mode, operation S390 the host agent returns a switch success signal so that the device will use the new target bias mode path when accessing the data page of the target data in the future.

[0070] Therefore, the current bias switching methods either use pre-installed software in the host to perform bias switching, which increases the host load, or allow the device to perform bias switching automatically based on the current request and cache state without relying on the host software, which leads to technical problems that cannot be applied in complex scenarios. The solution is to reduce the host load while improving the performance of bias switching.

[0071] like Figure 5 As shown, this application also provides a bias mode switching system 500, which includes a host and an accelerator. The accelerator and the host interact with each other based on the Fast Interconnect Protocol. The accelerator includes: a monitor module 510, used to obtain and evaluate the association information of a target data page through a controller, obtaining an evaluation result. The association information includes access information related to the target data page obtained by the monitor from the accelerator and the host; a controller module 520, used to receive a notification from the monitor in response to the evaluation result indicating that the association information meets the bias switching conditions, and to generate a bias switching request based on the target bias mode corresponding to the bias switching conditions; and a page table management unit module 530, used to respond to the bias switching request by writing a target bias field representing the target bias mode into the page table entry of the target data page through the page table management unit. The target bias field indicates the path to access the target data page based on the Fast Interconnect Protocol.

[0072] In this embodiment, the monitor module 510 monitors access information for the device memory of the accelerator and access information for the host memory of the host in order to receive access requests for the target data page, which is stored in the device memory or the host memory.

[0073] In response to the evaluation results indicating that the associated information meets the bias switching conditions, the interrupt information is embedded in the flow control unit data packet based on the computer fast interconnect protocol. The controller sends the flow control unit data packet to the agent unit to instruct the host to interrupt access to the target data page based on the interrupt information, in order to wait for the bias mode to switch. In the event of an interruption, in response to the inconsistency between the current bias mode in the page table entry and the target bias mode, the cached data of the target data page is synchronized between the accelerator's device memory and the host's host memory using a cache coherence protocol.

[0074] The accelerator also includes a device cache, and the host also includes a host cache. The cache coherence protocol is used to synchronize cached data of the target data page between the accelerator's device memory and the host's host memory. This includes: when the current bias mode is host-biased and the target bias mode is device-biased, migrating cached data from the host cache to host memory, and then synchronizing it from host memory to device memory via a Universal Serial Bus; or, when the current bias mode is device-biased and the target bias mode is host-biased, migrating cached data from the device cache to device memory, and then synchronizing it from device memory to host memory via a Universal Serial Bus.

[0075] The accelerator also includes a device cache, and the host also includes a host cache. The cache coherence protocol is used to synchronize cached data of the target data page between the accelerator's device memory and the host's host memory. This includes: when the current bias mode is host-biased and the target bias mode is device-biased, in response to the host memory having a shared physical space for both the accelerator and the host, migrating cached data in the host cache to the shared physical space and mapping the shared physical space to the accelerator; or, when the current bias mode is device-biased and the target bias mode is host-biased, in response to the device memory having a shared physical space for both the accelerator and the host, migrating cached data in the device cache to the shared physical space and mapping the shared physical space to the host.

[0076] In response to completing synchronization between the device memory of the accelerator and the host memory of the host, the method further includes: when the current bias mode is host bias mode and the target bias mode is device bias mode, executing a cache line invalidation command on cached data in the host cache through an agent unit, the agent unit being used to return a success signal to the controller when deleting cached data; or, when the current bias mode is device bias mode and the target bias mode is host bias mode, executing a cache line invalidation command on cached data in the device cache through the controller. The controller module 520 calls the page table management unit in the page table management unit module 530 to write the target bias field representing the target bias mode into the page table entry of the target data page. This includes writing the target validity bit, target bias mode type, target permission bit, target storage address, and target caching policy into the page table entry through the page table management unit. The target bias mode type is associated with the target storage address and the target caching policy, respectively. The target validity bit is used to indicate the availability status of the target data page, the target bias mode type is used to indicate the target bias mode, the target permission bit is used to indicate the access permissions of the accelerator, the target storage address is used to indicate whether the target data page is stored in the device memory of the accelerator or the host memory of the host, and the target caching policy is used to indicate whether the target data page is cached according to the write-through policy or the write-back policy.

[0077] The associated information of the target data page includes at least one of the following: the cache hit rate of the target data page on the accelerator and the host, the current remaining memory of the accelerator, the current remaining memory of the host, the bias instruction in the access request, and the persistent storage requirements of the target data page.

[0078] The target bias mode corresponding to the bias switching condition is determined by at least one of the following operations: determining the target bias mode as a device bias mode in response to the target data page's cache hit rate on the accelerator being greater than or equal to a hit rate threshold; determining the target bias mode as a host bias mode in response to the target data page's cache hit rate on the host being greater than or equal to a hit rate threshold; determining the target bias mode as a host bias mode in response to the accelerator's current remaining memory being less than or equal to a memory threshold; determining the target bias mode as a device bias mode in response to the host's current remaining memory being less than or equal to a memory threshold; using the bias mode indicated by the bias instruction as the target bias mode; determining the target bias mode as a host bias mode in response to the target data page having persistent storage requirements; and determining the target bias mode as a device bias mode in response to the target data page not having persistent storage requirements.

[0079] According to embodiments of this application, the monitor module 510, controller module 520, and page table management unit module 530 can be implemented in a single module, or any one of these modules can be split into multiple modules. Alternatively, at least some of the functions of one or more of these modules can be combined with at least some of the functions of other modules and implemented in a single module. According to embodiments of this application, at least one of the monitor module 510, controller module 520, and page table management unit module 530 can be at least partially implemented as hardware circuitry, such as a field-programmable gate array (FPGA), a programmable logic array (PLA), a system-on-a-chip, a system-on-a-substrate, a system-on-package, an application-specific integrated circuit (ASIC), or any other reasonable method of integrating or packaging circuitry, or implemented in software, hardware, or firmware, or in any suitable combination of any of these three implementation methods. Alternatively, at least one of the monitor module 510, controller module 520, and page table management unit module 530 can be at least partially implemented as a computer program module, which, when run, can perform corresponding functions.

[0080] Figure 6 A block diagram schematically illustrates an electronic device suitable for implementing a bias mode switching method according to an embodiment of this application.

[0081] like Figure 6As shown, an electronic device 600 according to an embodiment of this application includes a processor 601, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 602 or a program loaded from a storage portion 608 into a random access memory (RAM) 603. The processor 601 may include, for example, a general-purpose microprocessor (e.g., a CPU), an instruction set processor, and / or a special-purpose microprocessor (e.g., an application-specific integrated circuit (ASIC)), etc. The processor 601 may also include onboard memory for caching purposes. The processor 601 may include a single processing unit or multiple processing units for performing different actions of the method flow according to an embodiment of this application.

[0082] RAM 603 stores various programs and data required for the operation of electronic device 600. Processor 601, ROM 602, and RAM 603 are interconnected via bus 604. Processor 601 executes various operations of the method flow according to embodiments of this application by executing programs in ROM 602 and / or RAM 603. It should be noted that the programs may also be stored in one or more memories other than ROM 602 and RAM 603. Processor 601 may also execute various operations of the method flow according to embodiments of this application by executing programs stored in said one or more memories.

[0083] According to embodiments of this application, the electronic device 600 may further include an input / output (I / O) interface 605, which is also connected to a bus 604. The electronic device 600 may also include one or more of the following components connected to the input / output (I / O) interface 605: an input section 606 including a keyboard, mouse, etc.; an output section 607 including a cathode ray tube (CRT), liquid crystal display (LCD), etc., and a speaker, etc.; a storage section 608 including a hard disk, etc.; and a communication section 609 including a network interface card such as a LAN card, modem, etc. The communication section 609 performs communication processing via a network such as the Internet. A drive 610 is also connected to the input / output (I / O) interface 605 as needed. A removable medium 611, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., is installed on the drive 610 as needed so that computer programs read from it can be installed into the storage section 608 as needed.

[0084] This application also provides a computer-readable storage medium, which may be included in the device / apparatus / system described in the above embodiments; or it may exist independently and not assembled into the device / apparatus / system. The computer-readable storage medium carries one or more programs, which, when executed, implement the method according to the embodiments of this application.

[0085] According to embodiments of this application, the computer-readable storage medium can be a non-volatile computer-readable storage medium, such as including but not limited to: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this application, the computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. For example, according to embodiments of this application, the computer-readable storage medium may include ROM 602 and / or RAM 603 and / or one or more memories other than ROM 602 and RAM 603 described above.

[0086] Embodiments of this application also include a computer program product comprising a computer program containing program code for performing the methods shown in the flowchart. When the computer program product is run on a computer system, the program code is used to enable the computer system to implement the bias mode switching method provided in the embodiments of this application.

[0087] When the computer program is executed by the processor 601, it performs the functions defined in the system / apparatus of this application embodiment. According to the embodiments of this application, the systems, apparatuses, modules, units, etc., described above can be implemented by computer program modules.

[0088] In one embodiment, the computer program may rely on a tangible storage medium such as an optical storage device or a magnetic storage device. In another embodiment, the computer program may also be transmitted and distributed in the form of signals over a network medium, and downloaded and installed via the communication section 609, and / or installed from the removable medium 611. The program code contained in the computer program can be transmitted using any suitable network medium, including but not limited to: wireless, wired, etc., or any suitable combination thereof.

[0089] In such an embodiment, the computer program can be downloaded and installed from a network via the communication section 609, and / or installed from the removable medium 611. When the computer program is executed by the processor 601, it performs the functions defined in the system of this application embodiment. According to the embodiments of this application, the systems, devices, apparatuses, modules, units, etc., described above can be implemented by computer program modules.

[0090] According to embodiments of this application, program code for executing the computer programs provided in the embodiments of this application can be written in any combination of one or more programming languages. Specifically, these computational programs can be implemented using high-level procedural and / or object-oriented programming languages, and / or assembly / machine languages. Programming languages ​​include, but are not limited to, languages ​​such as Java, C++, Python, "C", or similar programming languages. The program code can be executed entirely on the user's computing device, partially on the user's device, partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0091] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0092] Those skilled in the art will understand that the features described in the various embodiments of this application can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in this application. In particular, the features described in the various embodiments of this application can be combined and / or combined in various ways without departing from the spirit and teachings of this application. All such combinations and / or combinations fall within the scope of this application.

[0093] The embodiments of this application have been described above. However, these embodiments are merely illustrative and not intended to limit the scope of this application. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. Without departing from the scope of this application, those skilled in the art can make various substitutions and modifications, all of which should fall within the scope of this application.

Claims

1. A bias mode switching method, characterized in that, Applied to an accelerator, the accelerator including a monitor, a controller, and a page table management unit, the accelerator and the host interact with each other based on a computer rapid interconnect protocol, the method comprising: The monitor obtains and evaluates the association information of the target data page to obtain an evaluation result. The association information includes access information related to the target data page obtained by the monitor from the accelerator and the host. In response to the evaluation result indicating that the associated information meets the bias switching condition, the monitor notifies the controller to generate a bias switching request based on the target bias mode corresponding to the bias switching condition; The controller invokes the page table management unit according to the bias switching request, and writes the target bias field, which represents the target bias mode, into the page table entry of the target data page. The target bias field indicates the path to access the target data page based on the computer fast interconnect protocol.

2. The method according to claim 1, characterized in that, Before evaluating the associated information of the target data page obtained through the monitor, the method further includes: The monitor monitors access information to the device memory of the accelerator and access information to the host memory of the host in order to receive access requests for the target data page, which is stored in the device memory or the host memory.

3. The method according to claim 1, characterized in that, The host includes a proxy unit, and the method further includes: In response to the evaluation result indicating that the associated information satisfies the bias switching condition, the interruption information is embedded in the flow control unit data packet based on the computer fast interconnect protocol; The controller sends the flow control unit data packet to the agent unit to instruct the host to interrupt access to the target data page based on the interrupt information, in order to wait for the bias mode to switch; In the event of an interruption, in response to a discrepancy between the current bias mode in the page table entry and the target bias mode, the cached data of the target data page is synchronized between the accelerator's device memory and the host's host memory using a cache coherence protocol.

4. The method according to claim 3, characterized in that, The accelerator further includes a device cache, and the host further includes a host cache. The step of synchronizing the cached data of the target data page between the device memory of the accelerator and the host memory of the host using a cache consistency protocol includes: When the current bias mode is host bias mode and the target bias mode is device bias mode, the cached data in the host cache is migrated to the host memory, and then synchronized from the host memory to the device memory via a universal serial bus; or... When the current bias mode is device bias mode and the target bias mode is host bias mode, the cached data in the device cache is migrated to the device memory, and then synchronized from the device memory to the host memory via the Universal Serial Bus.

5. The method according to claim 3, characterized in that, The accelerator further includes a device cache, and the host further includes a host cache. The step of synchronizing the cached data of the target data page between the device memory of the accelerator and the host memory of the host using a cache consistency protocol includes: When the current bias mode is host bias mode and the target bias mode is device bias mode, in response to the host memory having a shared physical space between the accelerator and the host, the cached data in the host cache is migrated to the shared physical space, and the shared physical space is mapped to the accelerator; or, When the current bias mode is device bias mode and the target bias mode is host bias mode, in response to the device memory having a shared physical space between the accelerator and the host, the cached data in the device cache is migrated to the shared physical space, and the shared physical space is mapped to the host.

6. The method according to claim 4, characterized in that, In response to completing synchronization between the device memory of the accelerator and the host memory of the host, the method further includes: When the current bias mode is host bias mode and the target bias mode is device bias mode, the proxy unit executes a cache line invalidation command on the cached data in the host cache, and the proxy unit returns a success signal to the controller when deleting the cached data; or... When the current bias mode is device bias mode and the target bias mode is host bias mode, the controller executes a cache line invalidation command on the cached data in the device cache.

7. The method according to claim 1, characterized in that, The step of calling the page table management unit through the controller to write the target bias field representing the target bias mode into the page table entry of the target data page includes: The page table management unit writes the target valid bit, target bias mode type, target permission bit, target storage address, and target caching policy into the page table entry, wherein the target bias mode type is associated with the target storage address and the target caching policy, respectively. Wherein, the target valid bit is used to indicate the availability status of the target data page, the target bias mode type is used to indicate the target bias mode, the target permission bit is used to indicate the access permissions of the accelerator, the target storage address is used to indicate storing the target data page in the device memory of the accelerator or the host memory of the host, and the target caching policy is used to indicate caching the target data page according to a write-through policy or a write-back policy.

8. The method according to claim 2, characterized in that, The associated information of the target data page includes at least one of the following: The target data page is determined by the cache hit rate of the accelerator and the host, the current remaining memory of the accelerator, the current remaining memory of the host, the bias instruction in the access request, and the persistent storage requirements of the target data page.

9. The method according to claim 8, characterized in that, The target bias mode corresponding to the bias switching condition is determined by at least one of the following operations: In response to the target data page having a cache hit rate greater than or equal to a hit rate threshold on the accelerator, the target bias mode is determined to be a device bias mode; In response to the target data page having a cache hit rate on the host that is greater than or equal to the hit rate threshold, the target bias mode is determined to be a host bias mode; In response to the accelerator's current remaining memory being less than or equal to a memory threshold, the target bias mode is determined to be a host bias mode; In response to the host's current remaining memory being less than or equal to the memory threshold, the target bias mode is determined to be a device bias mode; The bias mode indicated by the bias instruction is taken as the target bias mode; In response to the target data page having persistent storage requirements, the target bias mode is determined to be host bias mode; In response to the fact that the target data page does not have a persistent storage requirement, the target bias mode is determined to be a device bias mode.

10. A bias mode switching system, characterized in that, The system includes a host and an accelerator, and the accelerator and the host interact with each other based on the Computer Fast Interconnect Protocol. The accelerator includes: The monitoring module is used to obtain the association information of the target data page through the monitor and evaluate it to obtain the evaluation result. The association information includes access information related to the target data page obtained by the monitor from the accelerator and the host. The controller module is used to receive a notification from the monitor in response to the evaluation result indicating that the associated information meets the bias switching condition, and to generate a bias switching request according to the target bias mode corresponding to the bias switching condition. The page table management unit module is used to respond to the bias switching request by writing a target bias field representing the target bias mode into the page table entry of the target data page through the page table management unit. The target bias field indicates the path to access the target data page based on the computer fast interconnect protocol.

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