Universal interface algorithm acceleration device and acceleration method

Abstract

The invention provides a universal interface algorithm acceleration device and an acceleration method. The universal interface algorithm acceleration device comprises a configuration unit used for performing information configuration on a to-be-executed software task; the algorithm scheduling acceleration unit is used for reading a software task, performing data analysis on the software task to obtain configuration information and data required by an algorithm, and writing the configuration information and the data into the algorithm module; the SPIRNG unit is used for acquiring a random number from an external random source according to a task requirement and writing the random number into the algorithm module; after algorithm calculation is finished, the algorithm scheduling acceleration unit obtains an algorithm end mark and reads an algorithm result, the algorithm result is placed at a result output address specified by the configuration unit, an algorithm state is updated, and the updated algorithm state is transmitted to the configuration unit; the configuration unit schedules the updated task state and the related address of the acceleration unit according to the algorithm so as to execute the task. According to the method, extra time except algorithm calculation can be reduced, and the actual application efficiency of the algorithm is improved.

Description

Technical Field

[0001] This application belongs to the field of embedded chip technology, and in particular relates to a general interface algorithm acceleration device and acceleration method. Background Technology

[0002] During the invocation of the general interface algorithm, the general interface algorithm module needs to be configured multiple times. During the configuration process, multiple CPU operations and multiple DMA operations are required for data transfer. These CPU configuration and DMA operations consume a lot of extra time, thereby reducing the actual performance of the algorithm. Summary of the Invention

[0003] In view of this, this application aims to propose a general interface algorithm acceleration device and acceleration method to solve the problem of reducing the number of CPU interventions and DMA startups.

[0004] To achieve the above objectives, the technical solution of this application is implemented as follows:

[0005] In a first aspect, this application provides a general interface algorithm acceleration device, including a configuration unit, an SPI_RNG unit, and an algorithm scheduling acceleration unit connected together;

[0006] The configuration unit is configured to configure information for the software task to be executed.

[0007] The algorithm scheduling acceleration unit is configured to read software tasks and parse data from the software tasks to obtain the configuration information and data required by the algorithm, and write the configuration information and data to the backend algorithm module for algorithm calculation.

[0008] The SPI_RNG unit is configured to obtain random numbers from an external random source according to task requirements and write them into the algorithm module;

[0009] In response to the end of algorithm computation, the algorithm scheduling acceleration unit obtains the algorithm end flag and reads the algorithm result, places the algorithm result at the result output address specified by the configuration unit, updates the algorithm state, and transmits the updated algorithm state to the configuration unit. The configuration unit executes the corresponding task according to the updated task state and related address of the algorithm scheduling acceleration unit; wherein the updated task state corresponds to the algorithm state.

[0010] Secondly, based on the same inventive concept, this application also provides a general interface algorithm acceleration method, including:

[0011] Configure information for the software tasks to be executed;

[0012] Read the software task and parse the data from the software task to obtain the configuration information and data required by the algorithm. Obtain random numbers from an external random source and write the random numbers, configuration information and data into the algorithm.

[0013] In response to the end of the algorithm computation, obtain the algorithm end flag and read the algorithm result, update the algorithm state according to the algorithm result, update the task state and related addresses based on the updated algorithm state, and execute the corresponding task.

[0014] Thirdly, based on the same inventive concept, this application also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the method described in the second aspect.

[0015] Fourthly, based on the same inventive concept, this application also provides a non-transitory computer-readable storage medium, wherein the non-transitory computer-readable storage medium stores computer instructions for causing the computer to perform the method as described in the second aspect.

[0016] Compared with existing technologies, the general interface algorithm acceleration device and acceleration method described in this application have the following advantages:

[0017] The general-purpose interface algorithm acceleration device described in this application reads software tasks through an algorithm scheduling acceleration unit, parses the configuration operations and data required by the algorithm from the software tasks, and then completes the configuration of the algorithm flow and the transmission of data through its own general-purpose bus interface. This greatly reduces the number of times the CPU intervenes and the number of times the CPU configures DMA to start, thereby greatly reducing the extra time outside of algorithm calculation and effectively improving the efficiency of the algorithm in actual application. Attached Figure Description

[0018] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0019] Figure 1 This is a schematic diagram of the structure of a general interface algorithm acceleration device according to an embodiment of this application;

[0020] Figure 2 This is a flowchart of a general interface algorithm acceleration method according to an embodiment of this application;

[0021] Figure 3 This is a schematic diagram of the hardware structure of the electronic device described in an embodiment of this application. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0023] It should be noted that, unless otherwise defined, the technical or scientific terms used in the embodiments of this application should have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms "first," "second," and similar terms used in the embodiments of this application do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are only used to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0024] The embodiments of this application are described in detail below with reference to the accompanying drawings.

[0025] Please see Figure 1 As shown, this embodiment provides a general interface algorithm acceleration device, including a configuration unit, an SPI_RNG unit, and an algorithm scheduling acceleration unit connected to each other;

[0026] The configuration unit is configured to configure information for the software task to be executed.

[0027] The algorithm scheduling acceleration unit is configured to read software tasks and parse data from the software tasks to obtain the configuration information and data required by the algorithm, and write the configuration information and data to the backend algorithm module for algorithm calculation.

[0028] The SPI_RNG unit is configured to obtain random numbers from an external random source according to task requirements and write them into the algorithm module;

[0029] In response to the end of algorithm computation, the algorithm scheduling acceleration unit obtains the algorithm end flag and reads the algorithm result, places the algorithm result at the result output address specified by the configuration unit, updates the algorithm state, and transmits the updated algorithm state to the configuration unit. The configuration unit executes the corresponding task according to the updated task state and related address of the algorithm scheduling acceleration unit; wherein, the updated task state corresponds to the algorithm state.

[0030] Specifically, in this embodiment, the configuration unit has a general-purpose bus slave interface BUS_S for receiving CPU configurations. To minimize the number of CPU interventions, this unit only needs to perform CPU configuration three times: configuring the algorithm scheduling acceleration unit to read the address of the software task, configuring the address of the algorithm result output after the algorithm is completed, and the number of software tasks, totaling three parameters. This unit is also responsible for obtaining the algorithm scheduling status from the algorithm scheduling acceleration unit and updating the status of the above three parameters accordingly. Additionally, this unit can control the SPI_RNG unit to write a specific number of random numbers to a specific address (only for initial debugging).

[0031] The SPI_RNG unit contains a general-purpose bus main interface BUS_M3, used to directly write the required random numbers to the algorithm or a specified address. In general-purpose interface algorithms, externally generated random numbers are required. If these are obtained from an external source via a general CPU path and then written to the algorithm, a significant amount of operation time is wasted. To reduce this time, the SPI_RNG unit in this device can directly obtain random numbers from an external random source and then send them directly to the algorithm module (which works in conjunction with the algorithm scheduling acceleration unit; the algorithm module refers to a module with a general-purpose configuration interface (such as AHB, OPB, etc.) that runs an algorithm internally; the algorithm used in this embodiment is a quantum-resistant algorithm, but other algorithms can also run, which will not be elaborated here) through the general-purpose bus main interface. This greatly reduces the time required to obtain random numbers and improves algorithm efficiency.

[0032] Existing technologies typically configure algorithm scheduling acceleration units via software. While this approach offers flexibility, its significant drawback is its slow speed. The CPU executes software instructions, and then the algorithm is configured via the bus, resulting in an extremely lengthy scheduling process that negatively impacts algorithm execution efficiency. To address these issues, this embodiment implements the necessary configuration and data for the algorithm through tasks. The algorithm scheduling acceleration unit then parses these tasks and directly schedules the algorithm, saving time wasted on the CPU and bus.

[0033] The algorithm scheduling acceleration unit is the core unit of the acceleration device. It obtains the number of tasks to be executed from the configuration unit, retrieves the tasks from the specified address based on the number of tasks, parses the tasks, and extracts the data required by the algorithm from the tasks (the tasks include the type and attributes of the algorithm, as well as the data required by the algorithm; one of the tasks of the algorithm scheduling acceleration unit is to parse the type and attributes of the algorithm and allocate subsequent data based on the parsed information). Then, it sends the data to the algorithm module through a general interface and obtains random numbers from the SPI_RNG unit according to the task requirements, and sends the random numbers to the algorithm module. When the algorithm calculation is completed, the algorithm scheduling acceleration unit obtains the algorithm end flag from the algorithm module and then updates the algorithm status to the configuration unit. The configuration unit updates the task status and related addresses according to the status of the algorithm scheduling acceleration unit, and completes the corresponding task.

[0034] To elaborate further, the algorithm scheduling acceleration unit receives task requests and task addresses from the configuration unit. It uses the general-purpose bus main interface BUS_M1 to retrieve the task from the specified address (i.e., reads the task from the backend storage unit, writes it to the algorithm module via the general-purpose bus main interface BUS_M2, and after the algorithm finishes, reads the result from the algorithm module via the BUS_M1 interface and writes it to the result address via the BUS_M2 interface). The unit then parses the task using its internal parsing logic (the parsing process involves the algorithm scheduling acceleration unit retrieving the task from the specified address, analyzing the special fields in the task to determine the algorithm type and attributes, and extracting the configuration information and data required by the algorithm from the task). Then, the configuration information and data are written into the algorithm through the BUS_M2 interface. Because the algorithm does not always need random numbers, but requires external random number input at certain times, the algorithm scheduling acceleration unit will control the acquisition of random numbers according to the state of the algorithm. When random numbers are needed, the algorithm scheduling acceleration unit will send the random number request, the address of the requested random number, and the data to the SPI_RNG unit. The SPI_RNG unit will write the random numbers required by the algorithm into the algorithm module through the BUS_M3 interface according to the requested address and the number of random numbers, and after writing is completed, send the rng_done flag to the algorithm scheduling acceleration unit to tell the scheduling unit that it can proceed to the next operation.

[0035] After the algorithm finishes computation, the algorithm scheduling acceleration unit obtains the algorithm end flag from the algorithm, reads the algorithm result from the algorithm, places it in the result output address specified by the configuration unit, and then updates the algorithm status to the configuration unit. The configuration unit updates the task status and related addresses according to the status of the algorithm scheduling acceleration unit, and completes the corresponding task.

[0036] It should be noted that when random numbers are not needed, 128 four-byte random numbers will be pre-fetched as random numbers to be used next time. When the algorithm needs random numbers, these random numbers are sent directly to the algorithm module. If the number of pre-fetched random numbers is insufficient, more random numbers will be fetched from an external random source.

[0037] The device protected in this embodiment reads the software task through an algorithm scheduling acceleration unit, parses the configuration operations and data required by the algorithm from the software task, and then completes the configuration of the algorithm flow and the transmission of data through its own general-purpose bus interface. This greatly reduces the number of CPU interventions and the number of CPU configuration DMA startups, thereby significantly reducing the extra time beyond algorithm computation and effectively improving the practical application efficiency of the algorithm. The table below shows a performance comparison of the two algorithms before and after acceleration using the acceleration device of this embodiment, as detailed below:

[0038] Algorithm Name Performance before acceleration (times / second) Performance after acceleration (times / second) Remark Kyber 3244 5300 The algorithm itself involves relatively little computation, while software scheduling accounts for a larger portion, thus resulting in a greater improvement. Dilithium 1034 1290 The algorithm itself involves a large amount of computation, while software scheduling is relatively less, so the performance improvement is not as good as Kyber.

[0039] It should be noted that the above description describes some embodiments of this application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in a different order than that shown in the above embodiments and still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0040] Based on the same inventive concept, corresponding to the methods of any of the above embodiments, the embodiments of this application also provide a general interface algorithm acceleration method.

[0041] like Figure 2 As shown, the general interface algorithm acceleration method includes the following steps:

[0042] Step S101: Configure information for the software task to be executed;

[0043] Step S102: Read the software task and parse the data from the software task to obtain the configuration information and data required by the algorithm. Obtain random numbers from an external random source and write the random numbers, configuration information and data into the algorithm.

[0044] Step S103: In response to the end of the algorithm calculation, obtain the algorithm end flag and read the algorithm result, update the algorithm state according to the algorithm result, update the task state and related addresses based on the updated algorithm state, and execute the corresponding task.

[0045] Through the cooperation of steps S101, S102, and S103, the original cumbersome algorithm configuration process and DMA configuration process can be simplified to only a few simple configurations to complete the use of the algorithm. Furthermore, after the first algorithm configuration is completed, the next algorithm configuration can be completed during the algorithm's calculation process, thus making the entire algorithm process streamlined. The entire algorithm process is almost entirely the calculation process, thereby greatly improving the algorithm's calculation efficiency and accelerating the algorithm process.

[0046] The methods described above are used to implement the corresponding apparatus in any of the foregoing embodiments and have the beneficial effects of the corresponding apparatus embodiments, which will not be repeated here.

[0047] Based on the same inventive concept, corresponding to the methods of any of the above embodiments, embodiments of this application also provide an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the methods described in any of the above embodiments.

[0048] Figure 3 This embodiment illustrates a more specific hardware structure of an electronic device, which may include a processor 1010, a memory 1020, an input / output interface 1030, a communication interface 1040, and a bus 1050. The processor 1010, memory 1020, input / output interface 1030, and communication interface 1040 are interconnected internally via the bus 1050.

[0049] The processor 1010 can be implemented using a general-purpose CPU (Central Processing Unit), microprocessor, application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this specification.

[0050] The memory 1020 can be implemented in the form of ROM (Read Only Memory), RAM (Random Access Memory), static storage device, dynamic storage device, etc. The memory 1020 can store the operating system and other applications. When the technical solutions provided in the embodiments of this specification are implemented by software or firmware, the relevant program code is stored in the memory 1020 and is called and executed by the processor 1010.

[0051] The input / output interface 1030 is used to connect input / output modules to realize information input and output. The input / output modules can be configured as components in the device (not shown in the figure) or externally connected to the device to provide corresponding functions. Input devices may include keyboards, mice, touch screens, microphones, various sensors, etc., and output devices may include displays, speakers, vibrators, indicator lights, etc.

[0052] The communication interface 1040 is used to connect a communication module (not shown in the figure) to enable communication between this device and other devices. The communication module can communicate via wired means (such as USB, Ethernet cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.).

[0053] Bus 1050 includes a pathway for transmitting information between various components of the device, such as processor 1010, memory 1020, input / output interface 1030, and communication interface 1040.

[0054] It should be noted that although the above-described device only shows the processor 1010, memory 1020, input / output interface 1030, communication interface 1040, and bus 1050, in specific implementations, the device may also include other components necessary for normal operation. Furthermore, those skilled in the art will understand that the above-described device may only include the components necessary for implementing the embodiments of this specification, and not necessarily all the components shown in the figures.

[0055] The electronic devices described above are used to implement the corresponding methods in any of the foregoing embodiments and have the beneficial effects of the corresponding method embodiments, which will not be repeated here.

[0056] Based on the same inventive concept, corresponding to the methods of any of the above embodiments, this application also provides a non-transitory computer-readable storage medium that stores computer instructions for causing the computer to perform the methods described in any of the above embodiments.

[0057] The computer-readable medium of this embodiment includes permanent and non-permanent, removable and non-removable media, and information storage can be implemented by any method or technology. Information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transfer medium that can be used to store information accessible by a computing device.

[0058] The computer instructions stored in the storage medium of the above embodiments are used to cause the computer to perform the methods described in any of the above embodiments, and have the beneficial effects of the corresponding method embodiments, which will not be repeated here.

[0059] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of this application (including the claims) is limited to these examples; within the framework of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of the embodiments of this application as described above, which are not provided in the details for the sake of brevity.

[0060] Additionally, to simplify the description and discussion, and to avoid obscuring the embodiments of this application, the well-known power / ground connections to integrated circuit (IC) chips and other components may or may not be shown in the provided drawings. Furthermore, the apparatus may be shown in block diagram form to avoid obscuring the embodiments of this application, and this also takes into account the fact that the details of the implementation of these block diagram apparatuses are highly dependent on the platform on which the embodiments of this application will be implemented (i.e., these details should be fully understood by those skilled in the art). While specific details (e.g., circuits) have been set forth to describe exemplary embodiments of this application, it will be apparent to those skilled in the art that the embodiments of this application can be implemented without these specific details or with variations thereof. Therefore, these descriptions should be considered illustrative rather than restrictive.

[0061] Although this application has been described in conjunction with specific embodiments thereof, many substitutions, modifications, and variations of these embodiments will be apparent to those skilled in the art from the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may be used with the embodiments discussed.

[0062] The embodiments of this application are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the embodiments of this application should be included within the protection scope of this application.

Claims

1. A universal interface algorithm acceleration device, characterized in that: This includes a configuration unit, an SPI_RNG unit, and an algorithm scheduling acceleration unit that are connected to each other; The configuration unit is configured to configure information for the software task to be executed. The algorithm scheduling acceleration unit is configured to read software tasks and parse data from the software tasks to obtain the configuration information and data required by the algorithm, and write the configuration information and data to the backend algorithm module for algorithm calculation. The SPI_RNG unit is configured to obtain random numbers from an external random source according to task requirements and write them into the algorithm module; In response to the end of algorithm computation, the algorithm scheduling acceleration unit obtains the algorithm end flag and reads the algorithm result, places the algorithm result at the result output address specified by the configuration unit, updates the algorithm state, and transmits the updated algorithm state to the configuration unit. The configuration unit executes the corresponding task according to the updated task state and related address of the algorithm scheduling acceleration unit; wherein the updated task state corresponds to the algorithm state.

2. The apparatus according to claim 1, characterized in that: The configuration unit is equipped with a general-purpose bus slave interface for receiving CPU configuration information, including the address of the software task, the address of the algorithm result output, and the number of software tasks.

3. The apparatus according to claim 1, characterized in that: The configuration unit is also configured to control the SPI_RNG unit to write a predetermined number of random numbers to the target address.

4. The apparatus according to claim 1, characterized in that: The algorithm scheduling acceleration unit is equipped with a first general-purpose bus main interface and a second general-purpose bus main interface. The software task is read from the specified target address through the first general-purpose bus main interface, and the configuration information and data are written to the algorithm module through the second general-purpose bus main interface.

5. The apparatus according to claim 4, characterized in that: The algorithm scheduling acceleration unit reads the software task from the specified target address, parses the special fields in the task to obtain the type, attributes and data required by the algorithm, and writes the parsed information to the algorithm module.

6. The apparatus according to claim 1, characterized in that: The SPI_RNG unit is equipped with a third general-purpose bus interface for writing random numbers to the algorithm module; The algorithm scheduling acceleration unit obtains the random number according to the state control of the algorithm. In response to the need for the random number, it sends the address and data requesting the random number to the SPI_RNG unit. The SPI_RNG unit writes the random number into the algorithm module through the third general-purpose bus interface, and sends a stop flag bit to the algorithm scheduling acceleration unit after writing is completed.

7. The apparatus according to claim 1, characterized in that: If the random number is not needed, 128 four-byte random numbers are pre-fetched and sent directly to the algorithm module. If the number of pre-fetched random numbers is insufficient, random numbers are obtained from an external random source.

8. A general interface algorithm acceleration method, applied to the general interface algorithm acceleration device according to any one of claims 1-7, characterized in that, include: Configure information for the software tasks to be executed; Read the software task and parse the data from the software task to obtain the configuration information and data required by the algorithm. Obtain random numbers from an external random source and write the random numbers, configuration information and data into the algorithm. In response to the end of the algorithm computation, obtain the algorithm end flag and read the algorithm result, update the algorithm state according to the algorithm result, update the task state and related addresses based on the updated algorithm state, and execute the corresponding task.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the program, implements the method of claim 8.

10. A non-transitory computer-readable storage medium, characterized in that, in, The non-transitory computer-readable storage medium stores computer instructions for causing a computer to perform the method of claim 8.

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