Computing device and chip

Abstract

The invention provides a computing device and a chip. The computing device comprises a mainboard, a function board, a Retimer chip, a BMC, a CPLD and a memory. The CPLD is used for acquiring configuration information of the function board; the BMC is used for determining target firmware corresponding to the configuration information from a plurality of preset firmware according to the configuration information of the function board, and burning the target firmware in the memory; and the retiming chip is used for loading the target firmware from the memory so as to process the signal from the function board. According to the method and the device, the self-adaptive upgrading of the Retimer chip firmware can be realized. Besides, the BMC can match the corresponding target firmware for different bandwidth requirements in the plurality of preset firmware without developing a plurality of Retimer single boards with similar functions but different firmware, so that the development and storage cost is remarkably saved.

Description

Technical Field

[0001] This application relates to the field of server technology, and more particularly to a computing device and chip. Background Technology

[0002] In current servers, retimer chips are primarily used to relay signals across high-speed serial bus (Peripheral Component Interconnect Express, PCIe) links, thus addressing signal attenuation or distortion caused by long-distance transmission. However, the same PCIe port may be combined with various expansion cards, hard drive backplanes, etc., forming different system configurations. The firmware of the retimer chip corresponding to that PCIe port must be upgraded and restarted synchronously with the configuration changes to take effect; otherwise, the entire system will malfunction.

[0003] Typically, retimer chips are installed on expansion cards or hard drive backplanes to form a retimer board. For expansion cards or hard drive backplanes with fixed configurations, firmware corresponding to the fixed configuration needs to be burned into the corresponding retimer chip to obtain a retimer chip adapted to the fixed configuration. Therefore, when the overall system configuration changes, the corresponding retimer chip needs to be replaced. However, developing retimer chips adapted to different configurations presents problems such as high development and storage costs, and complex operation procedures. Summary of the Invention

[0004] This application provides a computing device and chip that can adaptively upgrade the firmware of the Retimer chip according to different system configurations, save development and storage costs, and can complete the reconfiguration by simply changing the cable connections when the system is reconfigured, without having to replace multiple Retimer boards. The operation is relatively simple and the maintenance is relatively convenient.

[0005] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0006] In a first aspect, embodiments of this application provide a computing device, including: a motherboard, a retimer chip, a BMC, a CPLD, a memory, and a function board coupled to the motherboard. The BMC, CPLD, and memory are located on the motherboard, and the retimer chip is coupled to the memory. The CPLD is coupled to the BMC and the function board and is used to acquire configuration information of the function board. The BMC is used to determine the bandwidth requirement information of the retimer chip based on the configuration information of the function board; determine the target firmware corresponding to the bandwidth requirement information from a plurality of preset firmware, and burn the target firmware into the memory. The retimer chip is used to load the target firmware from the memory to process signals from the function board.

[0007] Based on this solution, the corresponding bandwidth requirements can be determined according to the configuration information of different function boards, and then the corresponding target firmware can be matched to achieve adaptive upgrades of the Retimer chip firmware. This allows the Retimer chip to process signals from the function boards based on the upgraded firmware. Furthermore, BMC can match the corresponding target firmware for different bandwidth requirements from multiple preset firmwares, eliminating the need to develop Retimer boards adapted to different configurations, significantly saving development and storage costs. At the same time, changes to the function board configuration can be completed simply by adjusting the cable connections, without replacing multiple Retimer boards, making operation simpler and maintenance more convenient.

[0008] In some embodiments of this application, the BMC is specifically used to: determine the bandwidth requirement information of the retiming chip based on the mapping relationship between the configuration information of the function board and the bandwidth requirement information of the retiming chip; and determine the firmware corresponding to the bandwidth requirement information as the target firmware from multiple preset firmwares.

[0009] Based on this solution, when the mapping relationship between the configuration information of the function board and the bandwidth requirement information of the retiming chip can accurately reflect the configuration information of the function board and the bandwidth requirement information of the retiming chip, the bandwidth requirement information of the retiming chip corresponding to the configuration information of the function board can be accurately determined, and thus the target firmware corresponding to the bandwidth requirement information can be accurately determined.

[0010] In some embodiments of this application, the CPLD includes multiple signal input terminals, and the motherboard further includes a first connector and multiple first resistors corresponding to the multiple signal input terminals respectively; the function board further includes a second connector and at least one second resistor; one end of the multiple first resistors is coupled to the corresponding signal input terminal, and the other end of the multiple first resistors is coupled to a power supply terminal; the first connector includes a first end and a second end, the first end includes multiple first pins, the second end includes multiple second pins corresponding to the multiple first pins respectively, and the multiple first pins are coupled to the multiple signal input terminals respectively; the second connector includes a third end and a fourth end, the third end includes multiple third pins, the fourth end includes multiple fourth pins corresponding to the multiple third pins respectively, and the multiple third pins are coupled to the multiple second pins respectively; the multiple fourth pins are either left floating or coupled to one end of the second resistor, and the other end of the second resistor is coupled to a ground terminal.

[0011] Based on this scheme, by setting pull-up resistors for each signal input terminal of the CPLD and establishing corresponding couplings between multiple pins of the first and second connectors, a signal path is established between each signal input terminal of the CPLD and the corresponding fourth pin of the second connector. In this way, when the configuration of the function board can be reflected by setting the fourth pin to be left floating or to be coupled to the ground terminal through the second resistor, the configuration information of the function board can be accurately transmitted to the signal input terminal of the CPLD.

[0012] In some embodiments of this application, the configuration information includes multiple data bits, the number of which corresponds to the number of multiple signal input terminals; a CPLD is used to determine the level of the data bit corresponding to the fourth pin in the configuration information as a first level when the fourth pin is floating; and to determine the level of the data bit corresponding to the fourth pin in the configuration information as a second level when the fourth pin is coupled to one end of the second resistor.

[0013] Based on this scheme, it can be ensured that the data bits in the configuration information completely correspond to the state of the corresponding fourth pin.

[0014] In some embodiments of this application, the BMC is used to determine that the function board is not inserted in the computing device when each data bit of the configuration information is at a first level.

[0015] Based on this solution, the configuration of the computing device without inserted function boards can be accurately reflected by each data bit of the configuration information, which is more comprehensive.

[0016] In some embodiments of this application, the configuration information includes an even number of data bits greater than 3.

[0017] Based on this solution, since the number of data bits included in the configuration information is an even number greater than 3, it can fully distinguish the configurations of 8 or more function boards, and can meet the actual requirements when both the motherboard and the function board include connectors with 2 pins mapped to the same pin.

[0018] In some embodiments of this application, the BMC is further configured to: obtain bandwidth information of the burned firmware stored in the memory; and, if the bandwidth information of the burned firmware does not include bandwidth requirement information, determine the target firmware corresponding to the bandwidth requirement information from a plurality of preset firmwares, and burn the target firmware into the memory.

[0019] Based on this solution, the bandwidth information of the already programmed firmware is first obtained through the BMC. Only when the bandwidth information of the already programmed firmware includes the bandwidth requirement information corresponding to the target firmware is the target firmware determined from multiple preset firmwares, and the firmware upgrade of the Retimer chip is performed. In this way, the resource waste caused by programming the target firmware into the memory can be avoided when the current firmware of the Retimer chip meets the configuration requirements of the function board, that is, when the current firmware of the Retimer chip is the target firmware.

[0020] In some embodiments of this application, the CPLD is specifically used to acquire configuration information of the function board when the computing device is in a powered-off state; the BMC is also used to: control the computing device to remain powered-off when the computing device is in a powered-off state; and determine the bandwidth requirement information of the retiming chip according to the configuration information; if the bandwidth information of the already burned firmware does not include the bandwidth requirement information, determine the target firmware from multiple preset firmwares, burn the target firmware into the memory, and allow the computing device to power on; or, if the bandwidth information of the already burned firmware includes the bandwidth requirement information, allow the computing device to power on.

[0021] Based on this solution, when the computing device is powered off, the configuration information of the function board is obtained through the CPLD, the power-on of the computing device is restricted through the BMC, and the target firmware is burned into the memory, or the bandwidth information of the already burned firmware, including bandwidth requirement information, is allowed before the computing device is powered on. This ensures that the firmware upgrade of the Retimer chip occurs before the computing device is powered on, which to a certain extent avoids upgrade interruption, prevents hardware damage, ensures correct configuration, and improves upgrade efficiency. Furthermore, by completing the firmware upgrade of the Retimer chip while the computing device is powered off, the problem of long configuration time caused by the computing device's VCC power-on and then restarting can be avoided.

[0022] In some embodiments of this application, the Retimer chip is also used to load the firmware corresponding to the bandwidth requirement information from the memory, when the bandwidth information of the firmware includes bandwidth requirement information, in order to process signals from the function board.

[0023] Based on this solution, if the bandwidth information of the already burned firmware includes the bandwidth requirement information corresponding to the target firmware, the BMC does not need to burn the target firmware into the memory. The Retimer chip can directly load the already burned firmware corresponding to the bandwidth requirement information from the memory, avoiding the waste of resources caused by burning the target firmware into the memory.

[0024] In some embodiments of this application, the BMC is also used for: reading back the burned firmware stored in the memory; determining that the target firmware has been successfully burned if the burned firmware includes the target firmware; determining that the target firmware has failed to burn if the burned firmware does not include the target firmware, and re-burning the target firmware in the memory; and generating burning failure information if the number of times the target firmware has been burned exceeds a preset number.

[0025] Based on this solution, after the BMC programs the target firmware into the memory, it checks the target firmware. If the programmed firmware is inconsistent with the target firmware, multiple programming attempts are made. If the number of programming attempts exceeds a preset limit, a warning is issued indicating that the Retimer chip 1013 has failed. Furthermore, manual intervention can be used to ensure the continued operation of the computing device.

[0026] In some embodiments of this application, the motherboard further includes a switching switch, which is coupled to the BMC, CPLD, memory and Retimer chip respectively; the CPLD is also used to generate a first switching signal; the switching switch is used to conduct a first data path between the BMC and the memory based on the first switching signal; the BMC is specifically used to read the bandwidth information of the burned firmware from the memory when the first data path between the BMC and the memory is conducted.

[0027] Based on this scheme, the first switching signal generated by the CPLD controls the switching switch to conduct the first data path between the BMC and the memory. This allows the BMC to read the bandwidth information of the burned firmware from the memory when the first data path between the BMC and the memory is conducted, so as to determine whether the firmware of the Retimer chip is the target firmware and avoid the waste of resources caused by burning the target firmware to the memory when the firmware of the Retimer chip is the target firmware.

[0028] In some embodiments of this application, the motherboard further includes a switching switch, which is coupled to the BMC, CPLD, memory, and Retimer chip respectively; the CPLD is further configured to generate and transmit a second switching signal in response to the power-on operation of the computing device; the switching switch is configured to conduct a second data path between the retimer chip and the memory based on the second switching signal; the retimer chip is configured to load target firmware from the memory to process signals from the function board after the computing device has been powered on and the second data path between the retimer chip and the memory has been conducted.

[0029] Based on this scheme, a second switching signal is generated by the CPLD to control the switching switch to conduct the second data path between the Retimer chip and the memory, ensuring that the Retimer chip can load the target firmware from the memory to process signals from the function board when the second data path between the Retimer chip and the memory is conducted.

[0030] In some embodiments of this application, the CPLD is further configured to save configuration information and generate a save completion signal; the BMC is further configured to read configuration information from the CPLD based on the save completion signal.

[0031] Based on this scheme, the BMC reads the configuration information from the CPLD only after the CPLD has finished saving the configuration information, which can avoid reading the wrong configuration information when writing all the configuration information to the TYPE register.

[0032] In some embodiments of this application, the Retimer chip is located on the motherboard.

[0033] Based on this solution, by placing the Retimer chip on the motherboard, not only can the cost be reduced, but the signal quality and system integration can also be improved.

[0034] Secondly, embodiments of this application provide a firmware upgrade method applied to a computing device. The computing device includes a motherboard, a Retimer chip, a BMC, a CPLD, a memory, and a function board coupled to the motherboard. The Retimer chip is coupled to the memory. The method includes:

[0035] The CPLD acquires the configuration information of the function board;

[0036] Based on the configuration information of the function board, BMC determines the target firmware corresponding to the bandwidth requirement information from multiple preset firmwares and burns the target firmware into the memory.

[0037] The Retimer chip loads the target firmware from memory to process signals from the function board.

[0038] In some embodiments of this application, the BMC determines the target firmware corresponding to the bandwidth requirement information from multiple preset firmwares based on the configuration information, including: determining the bandwidth requirement information of the retiming chip based on the mapping relationship between the configuration information of the function board and the bandwidth requirement information of the retiming chip; and determining the firmware corresponding to the bandwidth requirement information as the target firmware from multiple preset firmwares.

[0039] In some embodiments of this application, the CPLD includes multiple signal input terminals, the motherboard further includes a first connector and multiple first resistors corresponding to the multiple signal input terminals respectively; the functional board further includes a second connector and at least one second resistor; one end of each of the multiple first resistors is coupled to the corresponding signal input terminal, and the other end of each of the multiple first resistors is coupled to a power supply terminal; the first connector includes a first end and a second end, the first end includes multiple first pins, the second end includes multiple second pins corresponding to the multiple first pins respectively, and the multiple first pins are coupled to the multiple signal input terminals respectively; the second connector includes a third end and a fourth end, the third end includes multiple third pins, the fourth end includes multiple fourth pins corresponding to the multiple third pins respectively, and the multiple third pins are coupled to the multiple second pins respectively; the multiple fourth pins are either left floating or coupled to one end of the second resistor, and the other end of the second resistor is coupled to a ground terminal. The configuration information includes multiple data bits, the number of which corresponds to the number of multiple signal input terminals; the CPLD can obtain the configuration information of the function board by: when the fourth pin is floating, the CPLD determines that the level of the data bit corresponding to the fourth pin in the configuration information is the first level; when the fourth pin is coupled to one end of the second resistor, the CPLD determines that the level of the data bit corresponding to the fourth pin in the configuration information is the second level.

[0040] In some embodiments of this application, the BMC determines the target firmware corresponding to the bandwidth requirement information from multiple preset firmwares and burns the target firmware into the memory, including: the BMC obtaining the bandwidth information of the burned firmware stored in the memory; if the bandwidth information of the burned firmware does not include the bandwidth requirement information, the BMC determines the target firmware corresponding to the bandwidth requirement information from multiple preset firmwares and burns the target firmware into the memory.

[0041] In some embodiments of this application, the CPLD obtains the configuration information of the function board, including: the CPLD obtains the configuration information of the function board when the computing device is in a powered-off state;

[0042] The firmware upgrade method also includes: the BMC controlling the computing device to remain powered down while the computing device is in a powered-off state; and determining the bandwidth requirement information of the retiming chip based on the configuration information; if the bandwidth information of the already burned firmware does not include the bandwidth requirement information, determining the target firmware from multiple preset firmwares, burning the target firmware into the memory, and allowing the computing device to power on; or, if the bandwidth information of the already burned firmware includes the bandwidth requirement information, allowing the computing device to power on.

[0043] In some embodiments of this application, the firmware upgrade method further includes: reading back the burned firmware stored in the BMC memory; if the burned firmware includes the target firmware, determining that the target firmware has been successfully burned; if the burned firmware does not include the target firmware, determining that the target firmware has failed to burn, and re-burning the target firmware in the memory; if the number of times the target firmware has been burned exceeds a preset number, generating burning failure information.

[0044] In some embodiments of this application, the motherboard further includes a switching switch, which is coupled to the BMC, CPLD, memory, and retiming chip respectively; the method further includes: the CPLD generating a first switching signal; the switching switch conducting a first data path between the BMC and the memory based on the first switching signal; the BMC obtaining bandwidth information of the burned firmware stored in the memory, which may include: the BMC reading the bandwidth information of the burned firmware from the memory when the first data path between the BMC and the memory is conducted.

[0045] In some embodiments of this application, the motherboard further includes a switching switch, which is coupled to the BMC, CPLD, memory, and retiming chip respectively; the method further includes: the CPLD generating and transmitting a second switching signal in response to a power-on operation of the computing device; the switching switch conducting a second data path between the Retimer chip and the memory based on the second switching signal; the Retimer chip loading target firmware from the memory to process signals from the function board, including: loading the target firmware from the memory to process signals from the function board after the computing device has been powered on and the second data path between the retiming chip and the memory is conducted.

[0046] In some embodiments of this application, the method further includes: the CPLD saving the configuration information and generating a save completion signal; and the BMC reading the configuration information from the CPLD based on the save completion signal.

[0047] Thirdly, embodiments of this application provide a firmware upgrade device, which includes: an acquisition module, a firmware upgrade module, and a loading module;

[0048] The acquisition module is used to acquire configuration information of the function board through the CPLD;

[0049] The firmware upgrade module is used to determine the bandwidth requirement information of the retiming chip based on the configuration information through the BMC; determine the target firmware corresponding to the bandwidth requirement information from multiple preset firmwares, and burn the target firmware into the memory;

[0050] The loading module is used to load the target firmware from memory via the Retimer chip to process signals from the function board.

[0051] Fourthly, this application provides another firmware upgrade method applied to BMC, the method comprising:

[0052] Obtain the configuration information of the function board;

[0053] Based on the configuration information of the function board, the target firmware corresponding to the configuration information of the function board is determined from multiple preset firmwares, and the target firmware is burned into the memory to process the signals from the function board.

[0054] Fifthly, embodiments of this application provide a chip for acquiring configuration information of a function board, the function board being coupled to the motherboard where the chip is located; determining the target firmware corresponding to the configuration information from multiple preset firmware according to the configuration information, and burning the target firmware into a memory, the target firmware being used to configure a Retimer chip, the Retimer chip being used to process signals from the function board.

[0055] In a sixth aspect, embodiments of this application provide a storage medium storing a computer program for executing the firmware upgrade method provided in the first aspect above.

[0056] In a seventh aspect, embodiments of this application provide a computer program product that, when instructions in the computer program product are executed by a processor, performs the firmware upgrade method provided in the second aspect above. Attached Figure Description

[0057] Figure 1 This is a schematic diagram of the structure of a computing device provided in an embodiment of this application.

[0058] Figure 2 This is a schematic diagram of another computing device provided in an embodiment of this application.

[0059] Figure 3 This is a schematic diagram of the structure of another computing device provided in an embodiment of this application.

[0060] Figure 4 This is a schematic diagram of the structure of another computing device provided in an embodiment of this application.

[0061] Figure 5A This is a schematic diagram of the structure of another computing device provided in an embodiment of this application.

[0062] Figure 5B This is a schematic diagram of the structure of another computing device provided in an embodiment of this application.

[0063] Figure 5C This is a schematic diagram of the structure of another computing device provided in an embodiment of this application.

[0064] Figure 5DThis is a schematic diagram of the structure of another computing device provided in an embodiment of this application.

[0065] Figure 6 This is a schematic diagram of the structure of another computing device provided in an embodiment of this application.

[0066] Figure 7A This is a flowchart illustrating a firmware upgrade method provided in an embodiment of this application.

[0067] Figure 7B This is a flowchart illustrating another firmware upgrade method provided in an embodiment of this application.

[0068] Figure 8 This is a flowchart illustrating another firmware upgrade method provided in an embodiment of this application.

[0069] Figure 9 This is a schematic diagram of the firmware upgrade device provided in an embodiment of this application. Detailed Implementation

[0070] The technical solutions of the embodiments of this application will now be described with reference to the accompanying drawings. To facilitate a clear description of the technical solutions of the embodiments of this application, the use of terms such as "first," "second," etc., in the embodiments of this application is for illustrative purposes and to distinguish the objects being described. There is no particular order between them, nor does it indicate a specific limitation on the number of devices in the embodiments of this application, and they do not constitute any limitation on the embodiments of this application.

[0071] The following describes the relevant technical terms used in the embodiments of this application:

[0072] A computing device is an electronic device used to perform computing tasks. Computing devices can include personal computers, servers, embedded computers, and supercomputers, etc. This application uses a server as an example for illustrative purposes. The server in this application can be a standalone physical server, a server cluster or distributed system composed of multiple physical servers, or a cloud server providing basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, cloud communication, middleware services, domain name services, security services, content delivery networks (CDNs), and big data and artificial intelligence platforms. When the aforementioned server is a server cluster or distributed system composed of multiple physical servers, the multiple physical servers can form a blockchain, with each physical server being a node on the blockchain. The physical type of the server can include rack servers, cabinet servers, high-density servers, graphics processing unit (GPU) servers, tower servers, blade servers, artificial intelligence (AI) servers, etc. This application does not limit the type of server in its embodiments.

[0073] A board management controller (BMC) is a controller in a computing device that manages the motherboard. As an independent processor embedded in the computing device, the BMC can monitor the device's hardware and software information, health status, and operational status. It should be noted that the BMC can also be called an integrated lights-out (iLO), integrated Dell remote access (IDRAC), hardware device management (HDM), integrated management module (IMM), etc. This application does not limit the name of the BMC in its embodiments.

[0074] A complex programmable logic device (CPLD) is a programmable device on the motherboard of a computing device that is responsible for processing low-level hardware logic. Through the burned firmware (logic program), it realizes low-level functions such as the startup timing of the computing device, power control, parsing and responding to hardware status monitoring signals, and converting and driving key interface signals, providing logical support for the stable startup of the computing device, hardware collaborative operation, and basic fault protection.

[0075] A retimer chip is a key chip used in high-speed signal transmission links. Its main function is to reshape, regenerate, and relay high-speed signals that have attenuated or become distorted after long-distance transmission or interference, in order to restore the integrity of the signal and ensure the stability and reliability of data transmission.

[0076] Electrically erasable programmable read-only memory (EEPROM) is a type of non-volatile memory that can be erased and reprogrammed multiple times.

[0077] Firmware is a special type of embedded software stored in the non-volatile memory (EEPROM) of the Retimer chip. It is responsible for controlling the chip to perform precise signal conditioning, timing calibration, and protocol adaptation for high-speed signal links such as PCIe. It is a key component to ensure the stability of high-speed data transmission within the server.

[0078] The standby power domain (STBY) refers to the circuitry area in a computing device that provides independent power for standby mode (low-power mode), ensuring that critical functions (such as remote management and fast wake-up) continue to operate when the main system is powered off. Devices or circuits in the STBY power domain must function normally when the computing device is in standby mode (plugged in, but VCC is not powered on).

[0079] The VCC power domain refers to the circuit area primarily responsible for providing a stable positive voltage to digital logic circuits, processor cores, and high-speed peripherals. Devices or circuits located in the VCC power domain can only function properly after VCC is powered on.

[0080] This application provides a computing device including a motherboard, a function board coupled to the motherboard, a Retimer chip, a BMC, a CPLD, and a memory. The BMC, CPLD, and memory are located on the motherboard, and the Retimer chip is coupled to the memory. The CPLD acquires configuration information of the function board. The BMC determines the bandwidth requirement information of the Retimer chip based on the configuration information of the function board. It determines the target firmware corresponding to the bandwidth requirement information from multiple preset firmwares and burns the target firmware into the memory corresponding to the Retimer chip. The Retimer chip loads the target firmware from the memory to process signals from the function board. This computing device can determine the corresponding bandwidth requirements based on the configuration information of different function boards, and then match the corresponding target firmware, realizing adaptive firmware upgrades of the Retimer chip, enabling the Retimer chip to process signals from the function board based on the upgraded firmware. Furthermore, the BMC can match the corresponding target firmware for different bandwidth requirements from multiple preset firmwares, eliminating the need to develop multiple Retimer boards with similar functions but different firmware, significantly saving development and storage costs. Meanwhile, the function board configuration can be changed simply by adjusting the cable connections, without having to replace multiple Retimer boards, making operation simpler and maintenance more convenient.

[0081] Figure 1 This is a schematic diagram of the structure of a computing device provided for an embodiment of the application. Figure 1 As shown, the computing device 10 includes a motherboard 101, a function board 102 coupled to the motherboard 101, a Retimer chip 1013, a BMC 1011, a CPLD 1012, and a memory 1014; the BMC 1011, CPLD 1012, and memory 1014 are located on the motherboard; the Retimer chip 1013 is coupled to the memory 1014.

[0082] CPLD 1012, coupled to BMC 1011 and function board 102, is used to obtain configuration information of function board 102.

[0083] BMC 1011 is used to determine the target firmware corresponding to the configuration information from multiple preset firmware according to the configuration information of function board 102, and burn the target firmware into memory 1014.

[0084] The Retimer chip 1013 is used to load the target firmware from the memory 1014 to process signals from the function board 102.

[0085] The computing device 10 may be a server, and the function board 102 may include an expansion board and / or a hard disk backplane, and is coupled to the Retimer chip 1014 according to the configuration requirements of the function board 102. The memory 1014 may be the EEPROM of the Retimer chip 1013.

[0086] The CPLD 1012 and BMC 1011 can be coupled via a local bus or an inter-integrated circuit (I2C) bus. The CPLD 1012 and function board 102 can be coupled via a signal communication cable.

[0087] The Retimer chip 1014 and the memory 1014 can also be coupled via the I2C bus.

[0088] The Retimer chip 1013 can be located on the motherboard 101 or on a separate circuit board. This embodiment of the application does not limit the location of the Retimer chip 1013. (See reference...) Figure 1 As shown, this application embodiment takes the Retimer chip 1013 located on the motherboard 101 as an example for illustrative purposes.

[0089] Understandably, if the Retimer chip 1013 is located on the motherboard, it can not only reduce costs but also improve signal quality and system integration.

[0090] Configuration information can be used to indicate the configuration of function board 102 and may include multiple data bits. This application embodiment does not limit the number of data bits in the configuration information; this application embodiment uses an example where the configuration information includes 6 data bits for illustrative purposes. Specifically, taking a high-speed serial bus (peripheral component interconnect express, PCIe) interface including the Central Processing Unit (CPU) corresponding to 16 channels (i.e., PCIe x16 configuration) as an example, the configuration of function board 102 may include x16, x8x8, x8x4x4, x4x4x8, and x4x4x4x4. Among them, x16 means that the PCIe x16 interface is not split into channels and provides a complete PCIe x16 interface directly; x8x8 means that the PCIe x16 interface is split into two independent x8 interfaces; x8x4x4 means that the PCIe x16 interface is split into one x8 interface and two independent x4 interfaces; x4x4x8 means that the PCIe x16 interface is split into one x8 interface and two independent x4 interfaces, with the x8 interface located at the end; x4x4x4x4 means that the PCIe x16 interface is split into four independent x4 interfaces.

[0091] The level of each data bit in the configuration information can be a first level or a second level. In some examples, the first level can be a logic low level "0" and the second level can be a logic high level "1". In other examples, the first level can be a logic high level "1" and the second level can be a logic low level "0". This application embodiment does not limit the type of the first level and the second level. This application embodiment uses the example of the first level being a logic high level "1" and the second level being a logic low level "0" for illustrative purposes. Taking a configuration information including 6 data bits as an example, the configuration information may include "001010", "001001", "001100", "100001", and "100100", and may correspond to the configurations x16, x8x8, x8x4x4, x4x4x8, and x4x4x4x4 of the function board 102, respectively.

[0092] This application embodiment does not limit the timing of firmware upgrades for the Retimer chip 1013; firmware upgrades can be performed either when the computing device 10 is in a powered-off state or after the computing device 10 is powered on. This application embodiment uses a firmware upgrade performed by the CPLD 1012 when the computing device 10 is in a powered-off state as an example for illustrative purposes. That is, the CPLD 1012 can receive configuration information from the function board 102 when the computing device 10 is in a powered-off state.

[0093] The S5 state (soft shutdown) of a server, as defined in the Advanced Configuration and Power Interface (ACPI) specification, is the state of the server when it is plugged in but the power button is not pressed. In the S5 state, although the server is connected to power, all hardware (including the CPU, memory, hard drive, etc.) receives no power, with only a very low current maintained for some circuitry (such as the power button response). Taking computing device 10 as an example, computing device 10 being in a shutdown state means the server is in the S5 state.

[0094] It is understood that when computing device 10 is in a powered-off state, the devices or circuits operating in computing device 10 are considered to be in the standby power domain (STBY). For example, if BMC 1011 and CPLD 1012 are operating when computing device 10 is powered-off, then it can be determined that both BMC 1011 and CPLD 1012 are in the STBY power domain.

[0095] The BMC 1011 can pre-store firmware corresponding to multiple configuration information. The BMC 1011 can use the firmware corresponding to the configuration information from the pre-stored firmware as the target firmware. For example, if the BMC 1011 pre-stores firmware 1, firmware 2, firmware 3, firmware 4, and firmware 5 corresponding to "001010", "001001", "001100", "100001", and "100100" respectively: If the configuration information is 001010, the BMC 1011 can use firmware 1 corresponding to 001010 as the target firmware. If the configuration information is 100001, the BMC 1011 can use firmware 4 corresponding to 100001 as the target firmware.

[0096] For example, when the computing device 10 is in a powered-off state, the CPLD 1012 can receive configuration information from the function board 102, and the BMC 1011 can read the configuration information of the function board 102 from the CPLD 1012, determine the target firmware corresponding to the configuration information from a plurality of preset firmware, and burn the target firmware into the memory 1014. Thus, the Retimer chip 1013 can load the target firmware from the memory 1014 after the computing device 10 is powered on, in order to process the signals from the function board 102.

[0097] The computing device provided in this application embodiment can determine the corresponding bandwidth requirements based on the configuration information of different function boards, and then match the corresponding target firmware to achieve adaptive upgrades of the Retimer chip firmware. This allows the Retimer chip to process signals from the function boards based on the upgraded firmware. Furthermore, the BMC can match the corresponding target firmware for different bandwidth requirements from multiple preset firmwares, eliminating the need to develop Retimer boards adapted to different configurations, significantly saving development and storage costs. Simultaneously, changes to the function board configuration can be completed simply by adjusting the cable connections, without replacing multiple Retimer boards, making operation simpler and maintenance more convenient.

[0098] Continue to refer to Figure 1 As shown, in some embodiments of this application, BMC 1011 is specifically used to determine the bandwidth requirement information of the retiming chip based on the mapping relationship between the configuration information of the function board and the bandwidth requirement information of the Retimer chip; and to determine the firmware corresponding to the bandwidth requirement information as the target firmware from multiple preset firmwares.

[0099] The bandwidth requirement information of the Retimer chip 1013 corresponds to the configuration of the function board 102. Therefore, the configuration information of the function board 102, "001010", "001001", "001100", "100001", and "100100", can respectively correspond to the bandwidth requirement information of the Retimer chip 1013, x16, x8x8, x8x4x4, x4x4x8, and x4x4x4x4. The correspondence between the configuration information of the function board 102 and the bandwidth requirement information of the Retimer chip 1013 can be seen in Table 1 below.

[0100]

[0101]

[0102] This application embodiment does not specifically limit the correspondence between the configuration information of the function board 102 and the bandwidth requirement information of the Retimer chip 1013. This application embodiment takes Table 1 as an example to illustrate the correspondence between the configuration information of the function board 102 and the bandwidth requirement information of the Retimer chip 1013.

[0103] Table 1 above can be pre-stored in BMC 1011. After BMC 1011 reads the configuration information of function board 102 from CPLD 1012, it can query Table 1 through the configuration information to determine the bandwidth requirement information of Retimer chip 1013. For example, if BMC 1011 reads the configuration information of function board 102 from CPLD 1012 as 100001, then BMC can query Table 1 through 100001 to determine the bandwidth requirement information of Retimer chip 1013 as x4x4x8.

[0104] Since the configuration information corresponds to the bandwidth requirement information of the Retimer chip 1013, the firmware corresponding to the configuration information pre-stored in the BMC 1011 can be firmware corresponding to the bandwidth requirement information of multiple pre-stored Retimer chips 1013. Therefore, the target firmware can be the firmware corresponding to the bandwidth requirement information of the Retimer chip 1013 among the multiple pre-stored firmware.

[0105] Taking the pre-stored firmware 1, firmware 2, firmware 3, firmware 4, and firmware 5 corresponding to x16, x8x8, x8x4x4, x4x4x8, and x4x4x4x4 in the BMC 1011 as an example, if the bandwidth requirement information of the Retimer chip 1013 is x4x4x8, then the BMC 1011 can use firmware 4 corresponding to x4x4x8 as the target firmware; if the bandwidth requirement information of the Retimer chip 1013 is x4x4x4x4, then the BMC 1011 can use firmware 5 corresponding to x4x4x4x4 as the target firmware.

[0106] The computing device provided in this application embodiment can accurately determine the bandwidth requirement information of the retiming chip corresponding to the configuration information of the function board when the mapping relationship between the configuration information of the function board and the bandwidth requirement information of the retiming chip can accurately reflect the configuration information of the function board and the bandwidth requirement information of the retiming chip. In turn, it can accurately determine the target firmware corresponding to the bandwidth requirement information.

[0107] like Figure 2 As shown above, in the above Figure 1 Based on the embodiment shown, the motherboard 101 also includes a CPU 1015, and the CPU 1015 also includes a PCIe interface 1015a. The PCIe interface 1015a and the Retimer chip 1013, and the Retimer chip 1013 and the function board 102 are all coupled through a PCIe bus to relay signals in the PCIe link.

[0108] Continue to refer to Figure 2 As shown, in some examples, the motherboard 101 further includes a first connector 1016, and the function board 102 includes a second connector 1021 and a physical slot 1022. The first connector 1016 and the second connector 1021 may each include a first data terminal and a second data terminal for adapting to the PCIe bus. The PCIe interface 1015a is coupled to the Retimer chip 1013, the Retimer chip 1013 is coupled to the first data terminal of the first connector 1016, the first data terminal of the first connector 1016 is coupled to the second data terminal of the second connector 1021, and the second data terminal of the second connector 1021 is coupled to the physical slot 1022 via the PCIe bus to transmit data output from the PCIe interface 1015a to an expansion device inserted into the physical slot 1022. This expansion device may include a network card, a non-volatile memory express solid-state drive (NVMe SSD), a graphics processing unit (GPU), etc.

[0109] Continue to refer to Figure 2 As shown, the first connector 1016 and the second connector 1021 may also include a first signal terminal and a second signal terminal for transmitting configuration information, respectively, so that the CPLD 1012 and the function board 102 can also be coupled through the first connector 1016 and the second connector 1021. In some examples, the CPLD 1012 and the first signal terminal of the first connector 1016, and the first signal terminal of the first connector 1016 and the second signal terminal of the second connector 1021 can be coupled through communication cables.

[0110] Taking an example where the first signal terminal includes a first terminal and a second terminal, and the second signal terminal includes a third terminal and a fourth terminal. Figure 3 As shown above, in the above Figure 2 Based on the embodiment shown, the CPLD 1012 includes multiple signal input terminals, the main board 101 also includes a first connector 1016 and multiple first resistors R1 corresponding to the multiple signal input terminals respectively; the function board 102 also includes a second connector 1021 and at least one second resistor R2.

[0111] One end of each of the multiple first resistors R1 is coupled to a corresponding signal input terminal, and the other end of each of the multiple first resistors R1 is coupled to the power supply terminal VDD;

[0112] The first connector 1016 includes a first end 1016a and a second end 1016b. The first end 1016a includes a plurality of first pins, and the second end 1016b includes a plurality of second pins corresponding to the plurality of first pins respectively. The plurality of first pins are respectively coupled to a plurality of signal input terminals.

[0113] The second connector 1021 includes a third end 1021a and a fourth end 1021b. The third end 1021a includes a plurality of third pins, and the fourth end 1021b includes a plurality of fourth pins corresponding to the plurality of third pins respectively. The plurality of third pins are coupled to the plurality of second pins respectively.

[0114] Multiple fourth pins are either left floating or coupled to one end of the second resistor R2, and the other end of the second resistor R2 is coupled to the ground terminal GND.

[0115] For example, the signal input terminal of CPLD 1012 refers to the terminal used to receive configuration signals from function board 102. The number of signal input terminals of CPLD 1012 may correspond to the number of pins for connecting communication cables included in the first connector 1016 and / or the second connector 1021. If both the first connector 1016 and / or the second connector 1021 include 4 pins, then the number of signal input terminals of CPLD 1012 is 4; if both the first connector 1016 and / or the second connector 1021 include 6 pins, then the number of signal input terminals of CPLD 1012 is 6. This application embodiment does not limit the number of signal input terminals of CPLD 1012. This application embodiment uses an even number of signal input terminals of CPLD 1012 greater than 3 as an example for illustrative purposes. This application embodiment uses a number of signal input terminals of CPLD 1012 of 6 as an example for illustrative purposes.

[0116] The positive terminal of the power supply can be the connection terminal corresponding to the positive terminal of a DC power supply. This application does not limit the voltage of the positive terminal of the power supply; however, this application uses an example where the voltage of the positive terminal of the power supply is 3.3V (volts) for illustrative purposes.

[0117] The first resistor R1 is a pull-up resistor, and its resistance value can be 4.7kΩ (kiloohms) or 10kΩ. In this embodiment, the resistance value of the first resistor R1 is not limited. This embodiment uses a resistance value of 4.7kΩ as an example for illustrative purposes.

[0118] The second resistor R2 is a pull-down resistor, and its resistance value can be 200Ω or 100Ω. In this embodiment, the resistance value of the second resistor R2 is not limited. This embodiment uses a resistance value of 4.7kΩ as an example for illustrative purposes.

[0119] Taking the CPLD 1012, which includes six signal input terminals, as an example, the motherboard 101 may include six first resistors R1, the first end 1016a of the first connector 1016 may include six first pins, the second end 1016b may include six second pins, the third end 1021a of the second connector 1021 may include six third pins, and the fourth end 1021b may include six fourth pins. That is, from the six fourth pins to the six signal input terminals of the CPLD 1012, there are six independent signal transmission paths.

[0120] Taking the fourth terminal 1021b, which includes six fourth pins, as an example, the number of second resistors R2 can be any positive integer less than or equal to six, and is related to the configuration of function board 102. Taking Table 1 above as an example, the configuration information of each function board 102 includes four "0"s (second level), meaning the number of second resistors R2 is four. This application embodiment does not limit the number of second resistors R2; this application embodiment uses a number of four second resistors R2 as an example for illustrative purposes.

[0121] In other embodiments of this application, the BMC is further configured to determine that no function board is inserted into the computing device when each data bit of the configuration information is at a first level. Thus, the configuration information can more accurately and comprehensively reflect the configuration of the computing device without a function board inserted.

[0122] For ease of understanding, Figure 4 Taking the configuration of function board 102 as x8x4x4 and the fourth end 1021b of the second connector 1021 including 6 fourth pins as an example, referring to Table 1, the configuration information corresponding to the configuration of function board 102 x8x4x4 is 001100. Therefore, it is necessary to construct the configuration information 001100 by configuring the state of the 6 fourth pins and then pass the configuration information 001100 to the 6 signal input terminals of CPLD 1012.

[0123] In some examples of this application, the configuration information includes multiple data bits, the number of which corresponds to the number of multiple signal data terminals; the CPLD 1012 is used to determine the level of the data bit corresponding to the fourth pin in the configuration information as a first level when the fourth pin is floating; and to determine the level of the data bit corresponding to the fourth pin in the configuration information as a second level in response to the fourth pin being coupled to one end of the second resistor R2.

[0124] In some embodiments of this application, the configuration information includes an even number of data bits greater than 3. Since motherboards and function boards often contain two connectors with the same pin mapping, using an even number of data bits greater than 3 can adapt to multi-connector scenarios, meet the requirements for distinguishing 8 or more configurations, and satisfy practical needs.

[0125] For example, leaving the fourth pin floating indicates a logic high level "1". Connecting the fourth pin to one end of the second resistor R2 and the other end of R2 to ground indicates a logic low level "0". If the first level represents a logic high level "1" and the second level represents a logic low level "0", then when the fourth pin is at the first level, the first level is transmitted to the corresponding signal input of the CPLD 1012, making the data bit in the configuration signal corresponding to the fourth pin at the first level; when the fourth pin is at the second level, the second level is transmitted to the corresponding signal input of the CPLD 1012, making the data bit in the configuration signal corresponding to the fourth pin at the second level. This ensures that the data bits in the configuration information completely correspond to the state of the corresponding fourth pin.

[0126] Taking the configuration information constructed by configuring the states of the six fourth pins as an example, the six fourth pins can be configured sequentially as grounded via R2, grounded via R2, floating, floating, grounded via R2, and grounded via R2 to construct configuration information 001100. Furthermore, the multiple signal input terminals of the CPLD 1012 can receive the configuration information 001100, representing the x8x4x4 configuration, transmitted from the function board 102.

[0127] The computing device provided in this application provides a signal path between each signal input terminal of the CPLD and the corresponding fourth pin of the second connector by setting pull-up resistors for each signal input terminal of the CPLD and by corresponding coupling between multiple pins of the first connector and the second connector. In this way, when the configuration of the function board can be reflected by setting the fourth pin to be floating or coupled to the ground terminal through the second resistor, the configuration information of the function board can be accurately transmitted to the signal input terminal of the CPLD.

[0128] Taking the PCIe interface 1015a configured as PCIe x16, with the high-speed connector supporting only 8 lanes as an example, refer to... Figure 4 As shown, in Figure 3Based on the illustrated embodiment, the first connector 1016 may include a first high-speed connector 1016c and a second high-speed connector 1016d. The second connector 1021 may include a third connector 1021c and a fourth connector 1021d. Specifically, the first data terminal may include a first sub-data terminal corresponding to the first high-speed connector 1016c and a second sub-data terminal corresponding to the second high-speed connector 1016d; the first terminal 1016a may include a first sub-signal terminal corresponding to the first high-speed connector 1016c and a second sub-signal terminal corresponding to the second high-speed connector 1016d; the second terminal 1016b may include a third sub-signal terminal corresponding to the first high-speed connector 1016c and a fourth sub-signal terminal corresponding to the second high-speed connector 1016d; the third terminal 1021a may include a fifth sub-signal terminal corresponding to the third high-speed connector 1021c and a sixth sub-signal terminal corresponding to the fourth high-speed connector 1021d; and the fourth terminal 1021b may include a seventh sub-signal terminal corresponding to the third high-speed connector 1021c and an eighth sub-signal terminal corresponding to the fourth high-speed connector 1021d.

[0129] The first high-speed connector 1016c is coupled to the three signal input terminals of the CPLD 1012, and the second high-speed connector 1016d can be coupled to the other three signal input terminals of the CPLD 1012; the first high-speed connector 1016c can be coupled to the third connector 1021c, and the second high-speed connector 1016d is coupled to the fourth connector 1021d.

[0130] Taking the CPLD 1012, which includes 6 signal input terminals, as an example, the first sub-signal terminal can correspond to the 3 first pins in the first terminal 1016a, the second sub-signal terminal can correspond to the other 3 first pins in the first terminal 1016a; the third sub-signal terminal can correspond to the 3 second pins in the second terminal 1016b, the fourth sub-signal terminal can correspond to the other 3 second pins in the second terminal 1016b; the fifth sub-signal terminal can correspond to the 3 third pins in the third terminal 1021a, the sixth sub-signal terminal can correspond to the other 3 third pins in the third terminal 1021a; the seventh sub-signal terminal can correspond to the 3 fourth pins in the fourth terminal 1021b, and the eighth sub-signal terminal can correspond to the other 3 fourth pins in the fourth terminal 1021b.

[0131] Continue to refer to Figure 4As shown, the Retimer chip 1013 is coupled to the first high-speed connector 1016c, the Retimer chip 1013 is coupled to the second high-speed connector 1016d, the first high-speed connector 1016c is coupled to the third high-speed connector 1021c, the second high-speed connector 1016d is coupled to the fourth high-speed connector 1021d, the third high-speed connector 1021c is coupled to the physical slot 1022, and the fourth high-speed connector 1021d is coupled to the physical slot 1022 via a PCIe bus to transmit the data output from the PCIe interface 1015a to the expansion device inserted into the physical slot 1022.

[0132] like Figure 5A As shown above, in the above Figure 4 Based on the illustrated embodiment, the functional board 102 may include an expansion board 102a. The expansion board 102a may include x16 physical slots SLOT1 and SLOT2, and x8 high-speed connectors 3, 4, 5, and 6. The physical slots 1022 correspond to all slots of the x16 physical slots SLOT1; the high-speed connector 3 corresponds to the third high-speed connector 1021c, and the high-speed connector 4 corresponds to the fourth high-speed connector 1021d.

[0133] pass Figure 5A It can be seen that the x8 high-speed connector 3 and x8 high-speed connector 4 in the expansion board are coupled to the same physical slot SLOT1, that is, the configuration of the function board 102 is x16, which corresponds completely to the setting state of the fourth pin.

[0134] like Figure 5B As shown above, in the above Figure 4 Based on the illustrated embodiment, the function board 102 may include, for example: Figure 5A The expansion board 102a shown has physical slot 1022 corresponding to 8 slots in x16 physical slot SLOT1 and 8 slots in x16 physical slot SLOT2; high-speed connector 3 corresponds to the third high-speed connector 1021c, and high-speed connector 5 corresponds to the fourth high-speed connector 1021d.

[0135] pass Figure 5B It can be seen that the high-speed connector 3 of x8 in the expansion board is coupled to the physical slot SLOT1, and the high-speed connector 4 of x8 is coupled to the physical slot SLOT2. That is, the configuration of the function board 102 is x8x8, which corresponds completely to the setting state of the fourth pin.

[0136] like Figure 5C As shown above, in the above Figure 4 Based on the illustrated embodiment, the function board 102 may include, for example: Figure 5AThe expansion board 102a and hard drive backplane 102b are shown. The hard drive backplane 102b includes a high-speed connector 7, a high-speed connector 8, and four physical slots NVMe0, NVMe1, NVMe2, and NVMe3. Among them, high-speed connector 7 corresponds to the third high-speed connector 1021c, and high-speed connector 3 corresponds to the fourth high-speed connector 1021d.

[0137] pass Figure 5C It can be seen that the high-speed connector 7 of x8 in the expansion board is coupled to the physical slots NVMe0 and NVMe1, and the high-speed connector 3 of x8 is coupled to the 8 slots in the physical slot SLOT1 of x16. That is, the configuration of the function board 102 is x4x4x8, which corresponds completely to the setting state of the fourth pin.

[0138] like Figure 5D As shown above, in the above Figure 4 Based on the embodiment shown, the function board 102 may include a hard disk backplane 102b as shown in FIG. 5c. High-speed connector 7 corresponds to the third high-speed connector 1021c, and high-speed connector 8 corresponds to the fourth high-speed connector 1021d.

[0139] pass Figure 5D It can be seen that the high-speed connector 7 of x8 in the expansion board is coupled to the physical slots NVMe0 and NVMe1, and the high-speed connector 8 of x8 is coupled to the physical slots NVMe2 and NVMe3. That is, the configuration of the function board 102 is x4x4x4x4, which corresponds completely to the setting state of the fourth pin.

[0140] In some embodiments of this application, reference continues to be made to Figure 1 As shown, CPLD 1012 is also used to save configuration information and generate a save completion signal; BMC 1011 is also used to read configuration information from CPLD 1012 based on the save completion signal.

[0141] Upon receiving configuration information, the CPLD 1012 writes the configuration information into its internal configuration information register (also known as the TYPE register). After receiving all configuration information and writing it to the TYPE register, the CPLD 1012 sets the value of the read completion register to 1 (default is 0) to indicate that all configuration information has been saved. The BMC 1011 can read the value of the read completion register in the CPLD 1012 via I2C or the local bus. If the value of the read completion register is 0, it waits for 1 second and continues reading until the value of the read completion register is 1. Then, it reads the value of the TYPE register in the CPLD 1012 to obtain the configuration information.

[0142] The computing device provided in this application embodiment reads the configuration information from the CPLD only after the CPLD has finished saving the configuration information, which can avoid reading the wrong configuration information when writing all the configuration information to the TYPE register.

[0143] In some embodiments of this application, reference continues to be made to Figure 1 As shown, BMC 1011 is specifically used to obtain the bandwidth information of the burned firmware stored in memory 1014; when the bandwidth information of the burned firmware does not include bandwidth requirement information, it determines the target firmware corresponding to the bandwidth requirement information from multiple preset firmwares and burns the target firmware in memory 1014.

[0144] For example, the memory 1014 may include a bandwidth information register, which may include bandwidth information of the burned firmware. Thus, the BMC 1011 can obtain the bandwidth information of the burned firmware by reading the bandwidth information register, compare the bandwidth information of the burned firmware with the bandwidth requirement information, and if the bandwidth information of the burned firmware does not include the bandwidth requirement information, determine the target firmware corresponding to the bandwidth requirement information from multiple preset firmwares, and burn the target firmware into the memory 1014 to complete the firmware upgrade of the retiming chip.

[0145] The computing device provided in this application embodiment first obtains the bandwidth information of the already burned firmware through the BMC, and only determines the target firmware from multiple preset firmwares and performs firmware upgrade on the Retimer chip if the bandwidth information of the already burned firmware includes the bandwidth requirement information corresponding to the target firmware. In this way, the resource waste caused by burning the target firmware to the memory can be avoided when the current firmware of the Retimer chip meets the configuration requirements of the function board, that is, when the current firmware of the Retimer chip is the target firmware.

[0146] In some embodiments of this application, reference continues to be made to Figure 1 As shown, CPLD 1012 is specifically used to obtain configuration information of function board 102 when computing device 10 is in a powered-off state; BMC 1011 is also used to: control computing device 10 to maintain a powered-off state when computing device 10 is in a powered-off state; and determine the bandwidth requirement information of Retimer chip according to configuration information; if the bandwidth information of the already burned firmware does not include bandwidth requirement information, determine the target firmware from multiple preset firmware, burn the target firmware into memory, and allow computing device 10 to power on; or, if the bandwidth information of the already burned firmware includes bandwidth requirement information, allow computing device 10 to power on.

[0147] When the computing device 10 is in a powered-off state, controlling the computing device 10 to remain powered down may include: when the computing device 10 is powered off, the BMC 1011 controls the computing device 10 not to respond to power-on commands. In some examples, the BMC 1011 may write a 1 to the power-on restriction register of the CPLD 1012 when the computing device 10 is powered off, thereby restricting the CPLD 1012 from controlling the VCC power supply of the computing device 10 to power on. This application embodiment does not limit the order in which the BMC 1011 writes a 1 to the power-on restriction register of the CPLD 1012 and the CPLD 1012 generates the first switching signal. This application embodiment exemplifies this by showing that the BMC 1011 writes a 1 to the power-on restriction register of the CPLD 1012 and the CPLD 1012 generates the first switching signal simultaneously.

[0148] For example, after completing the firmware upgrade of the Retime chip 1013, the BMC 1011 can write 0 to the power-on limit register of the CPLD 1012 to allow the CPLD 1012 to control the VCC power supply of the computing device 10 to power on.

[0149] The computing device provided in this application embodiment, when the computing device is in a powered-off state, obtains the configuration information of the function board through the CPLD, restricts the power-on of the computing device through the BMC, and only allows the computing device to power on after the target firmware is burned into the memory, or the bandwidth information of the already burned firmware includes bandwidth requirement information. This ensures that the firmware upgrade of the Retimer chip occurs before the computing device is powered on, which to a certain extent avoids upgrade interruption, prevents hardware damage, ensures correct configuration, and improves upgrade efficiency. Furthermore, by completing the firmware upgrade of the Retimer chip while the computing device is powered off, the problem of long configuration time caused by the computing device's VCC power-on and then restarting can be avoided.

[0150] In some embodiments of this application, the Retimer chip 1013 is used to load the firmware corresponding to the bandwidth requirement information from the memory 1014 when the bandwidth information of the firmware includes bandwidth requirement information, so as to process the signals from the function board 102.

[0151] The computing device provided in this application embodiment, when the bandwidth information of the already burned firmware includes the bandwidth requirement information corresponding to the target firmware, does not require the BMC to burn the target firmware into the memory. The Retimer chip can directly load the already burned firmware corresponding to the bandwidth requirement information from the memory, thus avoiding the waste of resources caused by burning the target firmware into the memory.

[0152] In some embodiments of this application, BMC 1011 is also used to read back the burned firmware stored in memory 1014; if the burned firmware includes the target firmware, determine that the target firmware has been successfully burned; if the burned firmware does not include the target firmware, determine that the target firmware has failed to burn and re-burn the target firmware in memory 1014; if the number of times the target firmware has been burned exceeds a preset number, generate burning failure information.

[0153] The preset number of times can be any integer greater than or equal to 2. In some examples, the preset number of times can be 3. This application embodiment does not limit the size of the preset number of times. This application embodiment uses a preset number of times of 3 as an example for illustrative explanation.

[0154] For example, if the bandwidth information in the already burned firmware does not include bandwidth requirement information, the BMC can clear the firmware burning count register in the BMC and retrieve the firmware corresponding to the bandwidth requirement information from the BMC's non-volatile memory, and upgrade the EEPROM via the I2C channel. After the firmware upgrade is complete, the firmware burning count register value is incremented by 1. Then, the file in the EEPROM is read back and compared with the firmware corresponding to the bandwidth requirement information retrieved from the BMC's non-volatile memory. If the comparison result is consistent, it indicates that the burning is correct, and the EEPROM firmware upgrade operation can be ended, switching to the normal VCC power-on process. If the comparison result is inconsistent, it checks whether the value of the firmware burning count register exceeds 3. If it does not exceed 3, the target firmware is burned to the EEPROM again. After the burning is complete, the value of the firmware burning count register is incremented by 1, and it is checked whether the EEPROM firmware value is consistent with the retrieved firmware. After repeating the burning 3 times, if the firmware burning count register value exceeds 3, the burning is considered unsuccessful, and the BMC generates and issues an alarm.

[0155] The computing device provided in this application embodiment checks the target firmware after the BMC burns it into the memory. If the burned firmware is inconsistent with the target firmware, it performs multiple burning attempts. If the number of burning attempts exceeds a preset number, a warning is issued indicating that the Retimer chip 1013 has failed to alarm. Furthermore, subsequent intervention can be performed manually to ensure the operation of the computing device.

[0156] like Figure 6 As shown above, in the above Figure 1 Based on the illustrated embodiment, in one possible implementation, the motherboard 101 may further include a switch 1017, which may be coupled to the BMC 1011, CPLD 1012, memory 1014 and Retimer chip 1013 respectively.

[0157] The CPLD 1012 is also used to generate the first switching signal;

[0158] The switching switch 1017 is used to connect the first data path between the BMC 1011 and the memory 1014 based on the first switching signal;

[0159] BMC 1011 is specifically used to read bandwidth information of the burned firmware from memory 1014 when the first data path between BMC 1011 and memory 1014 is open.

[0160] Exemplarily, the switch 1017 can be one of an electromagnetic relay, a solid-state relay (SSR), or an analog switch. This application embodiment does not limit the type of switch 1017; this application embodiment uses an analog switch as an example for illustrative purposes. For example, the switch 1017 can be a single-pole double-throw analog switch chip including one common terminal and two switching terminals.

[0161] In some examples, the control terminal of the switch 1017 is coupled to the CPLD 1012, the common terminal is coupled to the memory 1014, one switching terminal is coupled to the BMC 1011, and the other switching terminal is coupled to the Retimer chip 1013.

[0162] The first switching signal can be a control signal for the switch 1017. In some examples, the first switching signal can be a logic high level "1" or a logic low level "0". This application does not limit the type of the first switching signal.

[0163] When the control terminal of the switch 1017 receives the first switching signal from the CPLD 1012, it connects the common terminal to one of the switching terminals, thereby connecting the memory 1014 coupled to the common terminal and the BMC 1011 coupled to one of the switching terminals, thus forming a first data path between the memory 1014 and the BMC 1011. Therefore, the BMC 1011 can read the bandwidth information of the burned firmware from the memory 1014 through the first data path between the memory 1014 and the BMC 1011.

[0164] The computing device provided in this application embodiment generates a first switching signal through a CPLD to control a switching switch to conduct a first data path between the BMC and the memory. This enables the BMC to read the bandwidth information of the burned firmware from the memory when the first data path between the BMC and the memory is conducted, so as to determine whether the firmware of the Retimer chip is the target firmware and avoid the waste of resources caused by burning the target firmware to the memory when the firmware of the Retimer chip is the target firmware.

[0165] Continue as Figure 6 As shown, the CPLD 1012 is also used to generate a second switching signal in response to the power-on operation of the computing device 10;

[0166] The switching switch 1017 is used to connect the second data path between the Retimer chip 1013 and the memory 1014 based on the second switching signal.

[0167] The Retimer chip is used to load target firmware from memory 1014 to process signals from function board 102 after the computing device 10 has been powered on and the second data path between Retimer chip 1013 and memory 1014 is open.

[0168] The second switching signal is also a control signal for the switch 1017, and its level is different from that of the first switching signal. If the first switching signal can be a logic high level "1", then the second switching signal is a logic low level "0". If the first switching signal can be a logic low level "0", then the second switching signal is a logic high level "1". The type of the second switching signal is not limited in this embodiment.

[0169] When the computing device 10 receives a power-on command (power-on operation), the CPLD 1012 generates a second switching signal and transmits it to the control terminal of the switch 1017. Upon receiving the second switching signal from the CPLD 1012, the control terminal of the switch 1017 establishes a connection between its common terminal and another switching terminal, thereby establishing a connection between the memory 1014 coupled to the common terminal and the Retimer chip 1013 coupled to the other switching terminal, forming a second data path between the memory 1014 and the Retimer chip 1013. Therefore, after the computing device 10 is powered on, the Retimer chip 1013 can load the target firmware from the memory 1014 based on the second data path between the memory 1014 and the Retimer chip 1013 to process signals from the function board 102.

[0170] The computing device provided in this application embodiment generates a second switching signal through a CPLD to control a switching switch to conduct the second data path between the Retimer chip and the memory, ensuring that the Retimer chip can load the target firmware from the memory to process signals from the function board 102 when the second data path between the Retimer chip and the memory is conducted.

[0171] Specifically, CPLD 1012 is used to acquire configuration information of function board 102 when computing device 10 is in a powered-off state; BMC 1011 is used to control computing device 10 to maintain a powered-off state when computing device 10 is in a powered-off state; and according to the configuration information, determine the bandwidth requirement information of Retimer chip, determine the target firmware corresponding to the bandwidth requirement information from multiple preset firmware, and burn the target firmware into the memory corresponding to Retimer chip; after completing the firmware upgrade of Retimer chip 1013, allow computing device 10 to power on.

[0172] When the computing device 10 is in a powered-off state, controlling the computing device 10 to remain powered down may include: when the computing device 10 is powered off, the BMC 1011 controls the computing device 10 not to respond to power-on commands. In some examples, the BMC 1011 may write a 1 to the power-on restriction register of the CPLD 1012 when the computing device 10 is powered off, thereby restricting the CPLD 1012 from controlling the VCC power supply of the computing device 10 to power on. This application embodiment does not limit the order in which the BMC 1011 writes a 1 to the power-on restriction register of the CPLD 1012 and the CPLD 1012 generates the first switching signal. This application embodiment exemplifies this by showing that the BMC 1011 writes a 1 to the power-on restriction register of the CPLD 1012 and the CPLD 1012 generates the first switching signal simultaneously.

[0173] For example, after completing the firmware upgrade of the Retimer chip 1013, the BMC 1011 can write 0 to the power-on limit register of the CPLD 1012 to allow the CPLD 1012 to control the VCC power supply of the computing device 10 to power on.

[0174] The computing device provided in this application embodiment, by completing the firmware upgrade of the Retimer chip while the computing device is in a powered-off state, avoids the problem of long configuration time caused by the computing device being powered on and then restarted. Furthermore, by allowing the computing device to power on only after the Retimer chip's firmware upgrade is complete, it ensures that the firmware upgrade occurs before the computing device powers on, thus avoiding upgrade interruptions, preventing hardware damage, ensuring correct configuration, and improving upgrade efficiency to a certain extent.

[0175] Continue to refer to Figure 1As shown, this application embodiment provides a chip 1011, which is used to acquire configuration information of a function board, wherein the function board is coupled to the motherboard where the chip is located; determine the target firmware corresponding to the configuration information from a plurality of preset firmware according to the configuration information, and burn the target firmware into the memory, wherein the target firmware is used to configure a retiming chip, and the retiming chip is used to process signals from the function board. In one possible implementation, the chip may specifically be a BMC.

[0176] and Figure 1 Corresponding to the computing device 10 shown, this application embodiment also provides a firmware upgrade method, applied to, for example... Figure 1 The computing device 10 shown is, for example Figure 7A As shown, the firmware upgrade method may include the following steps 701 to 703.

[0177] Step 701: The CPLD obtains the configuration information of the function board and sends it to the BMC.

[0178] Step 702: Based on the configuration information, the BMC determines the target firmware corresponding to the configuration information from multiple preset firmwares and burns the target firmware into the memory.

[0179] Step 703: The Retimer chip loads the target firmware from the memory to process signals from the function board.

[0180] The beneficial technical effects corresponding to the exemplary embodiments of the above firmware upgrade method can be found in the corresponding beneficial technical effects in the above computing device embodiment section, and will not be repeated here.

[0181] This application embodiment further provides a firmware upgrade method, applied to, for example, Figure 1 The BMC 1011 shown is as follows: Figure 7B As shown, the firmware upgrade method may include the following steps 704 and 705.

[0182] Step 704: Obtain the configuration information of the function board.

[0183] Step 705: Determine the target firmware corresponding to the configuration information from multiple preset firmware according to the configuration information, and burn the target firmware into the memory.

[0184] Figure 8 This is a flowchart illustrating another firmware upgrade method provided in an embodiment of this application. Figure 8 As shown, the firmware upgrade method may include the following steps 801 to 818.

[0185] Step 801: Plug in the power supply to the computing device. The BMC and CPLD are powered on and initialized.

[0186] Step 802: The CPLD controls the switching switch to connect the connection path between the EEPROM and the BMC.

[0187] The connection path between EEPROM and BMC corresponds to the first data path.

[0188] Step 803: The CPLD reads the configuration signals from the input signal terminals and writes the configuration signals into the TYPE register. After the CPLD has read all the configuration signals from the input signal terminals, it sets the read completion register to 1.

[0189] Step 804: The BMC writes 1 to the CPLD's power-on restriction register to restrict the VCC power supply of the computing device.

[0190] Step 804 can be performed simultaneously with step 802.

[0191] Step 805: BMC reads the bandwidth information of the firmware already burned into the EEPROM.

[0192] Step 805 is executed after step 802.

[0193] Step 806: The BMC reads the value of the read completion register in the CPLD. Is the value of the read completion register 0? If yes, delay for 1 second and continue to execute step 806; otherwise, proceed to step 807.

[0194] Step 807: The BMC reads the value of the TYPE register of the CPLD, determines the bandwidth requirement information corresponding to the value of the TYPE register, and compares the consistency of the bandwidth requirement information with the bandwidth information of the already burned firmware.

[0195] Step 808: Does the bandwidth requirement information match the bandwidth information of the already burned firmware? If yes, proceed to step 809; otherwise, proceed to step 812.

[0196] Step 809: The BMC writes 0 to the CPLD's power-on restriction register to enable the VCC power supply of the computing device.

[0197] Step 810: After receiving the power-on command, the CPLD controls the switching switch to connect the EEPROM and the Retimer chip, and controls the VCC power supply of the computing device to be powered on.

[0198] Step 811: The Retimer chip loads the burned firmware from the EEPROM, completes the configuration of parameters such as bandwidth of the Retimer chip, and the system powers on.

[0199] Step 812: Clear the firmware flashing count register in the BMC.

[0200] Step 813: The BMC obtains the target firmware corresponding to the bandwidth requirement information and burns the target firmware into the EEPROM.

[0201] Step 814: Increment the value of the firmware flashing count register in the BMC by 1.

[0202] Step 815: Read back the burned firmware in the EEPROM and compare the consistency between the burned firmware and the target firmware.

[0203] Step 816: Is the burned firmware consistent with the target firmware? If yes, proceed to step 809; otherwise, proceed to step 817.

[0204] Step 817: Does the value of the firmware flashing count register in the BMC exceed 3? If yes, proceed to step 818; otherwise, proceed to step 813.

[0205] Step 818: BMC generates a burning failure message.

[0206] Corresponding to the aforementioned embodiments of the firmware upgrade method, this application also provides an embodiment of a firmware upgrade device. Figure 9 As shown, the firmware upgrade device 90 may include an acquisition module 901, a firmware upgrade module 902, and a loading module 903 located in the CPLD;

[0207] The acquisition module 901 is used to acquire the configuration information of the function board through the CPLD.

[0208] The firmware upgrade module 902 is used to determine the target firmware corresponding to the configuration information from multiple preset firmwares based on the configuration information through the BMC, and to burn the target firmware into the memory;

[0209] Loading module 903 is used to load target firmware from memory via the Retimer chip to process signals from the function board.

[0210] In addition to the methods and devices described above, embodiments of this application may also provide a computer program product, including computer program instructions, which, when executed by a processor, cause the processor to perform the steps of the firmware upgrade methods of various embodiments of this application described in the above method embodiment section.

[0211] Computer program products can be written in any combination of one or more programming languages ​​to perform the operations of the embodiments of this application. These programming languages ​​include object-oriented programming languages ​​such as Java and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on the user's computing device, partially on the user's computing device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0212] Furthermore, embodiments of this application may also be computer-readable storage media storing computer program instructions thereon, which, when executed by a processor, cause the processor to perform the steps in the firmware upgrade methods of various embodiments of this application described in the above-described method embodiment section.

[0213] Computer-readable storage media may take the form of any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may include, but is not limited to, systems, apparatuses, or devices that are electrical, magnetic, optical, electromagnetic, infrared, or semiconductor, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: electrical connections having one or more wires, portable disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0214] The basic principles of this application have been described above with reference to specific embodiments. However, the advantages, benefits, and effects mentioned in this application are merely examples and not limitations, and should not be considered as essential features of each embodiment of this application. Furthermore, the specific details of the above embodiments are for illustrative and facilitative purposes only, and are not limitations. These details do not restrict this application from being implemented using the aforementioned specific details.

[0215] Those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

[0216] Furthermore, the embodiments described above are merely specific embodiments of this application and are not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made based on the technical solution of this application should be included within the scope of protection of this application.

Claims

1. A computing device, characterized in that, It includes a motherboard, a retiming chip, a baseboard management controller (BMC), a programmable logic device (CPLD), a memory, and a functional board coupled to the motherboard, wherein the BMC, the CPLD, and the memory are located on the motherboard; The retiming chip is coupled to the memory; The CPLD is coupled to the BMC and the function board, and is used to obtain the configuration information of the function board; The BMC is used to determine the target firmware corresponding to the configuration information from multiple preset firmware according to the configuration information of the function board, and to burn the target firmware into the memory; The retiming chip is used to load the target firmware from the memory to process signals from the function board.

2. The computing device according to claim 1, characterized in that, The BMC is specifically used for: Based on the mapping relationship between the configuration information of the function board and the bandwidth requirement information of the retiming chip, the bandwidth requirement information of the retiming chip is determined. From the plurality of preset firmware, the firmware corresponding to the bandwidth requirement information is determined as the target firmware.

3. The computing device according to claim 1, characterized in that, The CPLD includes multiple signal input terminals, and the motherboard further includes a first connector and multiple first resistors corresponding to the multiple signal input terminals; the function board further includes a second connector and at least one second resistor. One end of each of the plurality of first resistors is coupled to the corresponding signal input terminal, and the other end of the plurality of first resistors is coupled to the power supply terminal; The first connector includes a first end and a second end. The first end includes a plurality of first pins, and the second end includes a plurality of second pins corresponding to the plurality of first pins respectively. The plurality of first pins are respectively coupled to the plurality of signal input ends. The second connector includes a third end and a fourth end. The third end includes a plurality of third pins, and the fourth end includes a plurality of fourth pins corresponding to the plurality of third pins respectively. The plurality of third pins are coupled to the plurality of second pins respectively. The plurality of fourth pins are either left floating or coupled to one end of the second resistor, and the other end of the second resistor is coupled to the ground terminal.

4. The computing device according to claim 3, characterized in that, The configuration information includes multiple data bits, and the number of the multiple data bits corresponds to the number of the multiple signal input terminals; The CPLD is used to determine, when the fourth pin is floating, that the level of the data bit corresponding to the fourth pin in the configuration information is a first level; When the fourth pin is coupled to one end of the second resistor, the level of the data bit corresponding to the fourth pin in the configuration information is determined to be the second level.

5. The computing device according to claim 1, characterized in that, The BMC is also used for: Obtain the bandwidth information of the burned firmware stored in the memory; If the bandwidth information of the already burned firmware does not include the bandwidth requirement information, the target firmware corresponding to the bandwidth requirement information is determined from the plurality of preset firmware, and the target firmware is burned into the memory.

6. The computing device according to claim 5, characterized in that, The CPLD is specifically used to obtain the configuration information of the function board when the computing device is in a powered-off state; The BMC is also used for: When the computing device is in a powered-off state, the computing device is controlled to remain powered down; and the bandwidth requirement information of the retiming chip is determined according to the configuration information. If the bandwidth information of the already burned firmware does not include the bandwidth requirement information, the target firmware is determined from the plurality of preset firmware, the target firmware is burned into the memory, and the computing device is powered on; or... If the bandwidth information of the burned firmware includes the bandwidth requirement information, the computing device is allowed to power on.

7. The computing device according to claim 5, characterized in that, The BMC is also used for: Read back the burned firmware stored in the memory; If the burned firmware includes the target firmware, it is determined that the target firmware was successfully burned. If the target firmware is not included in the already burned firmware, and the burning of the target firmware is determined to have failed, the target firmware is re-burned into the memory; If the number of times the target firmware is burned exceeds a preset number, a burning failure message is generated.

8. The computing device according to claim 5, characterized in that, The motherboard also includes a switching switch, which is coupled to the BMC, the CPLD, the memory and the retiming chip respectively; The CPLD is also used to generate a first switching signal; The switching switch is used to connect the first data path between the BMC and the memory based on the first switching signal; Specifically, the BMC is used to read the bandwidth information of the burned firmware from the memory when the first data path between the BMC and the memory is open.

9. The computing device according to any one of claims 1-8, characterized in that, The motherboard also includes a switching switch, which is coupled to the BMC, the CPLD, the memory and the retiming chip respectively; The CPLD is also used to generate and transmit a second switching signal in response to the power-on operation of the computing device; The switching switch is used to connect the second data path between the retiming chip and the memory based on the second switching signal; The retiming chip is used to load the target firmware from the memory after the computing device is powered on, and when the second data path between the retiming chip and the memory is open, in order to process signals from the function board.

10. The computing device according to any one of claims 1-8, characterized in that, The retiming chip is located on the motherboard.

11. A chip, characterized in that, The chip is used for: Obtain the configuration information of the function board, which is coupled to the motherboard where the chip is located; The target firmware corresponding to the configuration information is determined from multiple preset firmwares based on the configuration information, and the target firmware is burned into the memory. The target firmware is used to configure the retiming chip, and the retiming chip is used to process signals from the function board.

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