Stacked chip rapid wiring method, computer device and readable storage medium

Abstract

The application provides a stacked chip rapid wiring method, a computer device and a readable storage medium. The method comprises the following steps: obtaining chip design parameters; creating a multi-dimensional array according to the chip design parameters, wherein the multi-dimensional array contains the state of each wiring point of the chip in the horizontal, vertical and diagonal directions; identifying the obstacles of wiring and the physical relationship of the obstacles according to the multi-dimensional array; when wiring the network, cutting the multi-dimensional array according to the minimum containing rectangle of the network, and generating a reference for executing the cutting; obtaining the starting point and the ending point of the wiring to be performed; starting from the starting point, determining the next wiring point on the cutting surface according to the preset wiring rule until the wiring reaches the ending point; and updating the multi-dimensional array every time a wiring point is determined on the cutting surface, marking the wiring point as an occupied state, and updating the wiring path in each direction. The computer device and the readable storage medium can realize the above method. The application can improve the wiring efficiency of the 2.5D chip.

Description

Technical Field

[0001] This invention relates to the field of chip design technology, and more specifically, to a method for rapid routing of stacked chips and a computer device and computer-readable storage medium for implementing this method. Background Technology

[0002] With the development of chip technology, 2.5D stacked chips have been widely used. The routing method for 2.5D stacked chips typically involves converting the 2.5D stacked chip into an equivalent 2D chip, completing the routing on the equivalent 2D chip, and then converting it back to the 2.5D stacked chip form. The conversion method between 2.5D stacked chips and equivalent 2D chips usually treats a chiplet as a corresponding miniaturized 2D chip. This routing algorithm generally uses a maze algorithm or the A* algorithm. These algorithms typically model the routing space as a chessboard, requiring the routing to connect one cell to another.

[0003] Taking a two-node network as an example, when routing, one connection point is set as the starting point and the other connection point as the ending point. The main steps of routing are: First, start from the starting point and propagate outwards in a wave-like manner ("wave propagation"). Each step propagates one cell and these cells are labeled with the propagation order. If an obstacle is encountered, the propagation path stops. If a path reaches the ending point, the propagation of all paths stops. Start backtracking from the ending point, searching for a cell with a smaller label at each step and using it as the new backtracking starting point. When the backtracking reaches the starting point, the backtracking stops. All the cells traversed during the backtracking are the routing path.

[0004] However, since 2.5D stacked chips are composed of multiple chips stacked horizontally, the size of the chips in 2.5D chips is much larger than that of the basic unit or macro in traditional two-dimensional chips, typically by one or even several orders of magnitude. This results in a much longer wiring length for 2.5D stacked chips, leading to the following drawbacks when using the above algorithm:

[0005] First, routing path selection and obstacle avoidance in routing algorithms need to be performed over a larger area, which requires more memory and computing resources, resulting in longer execution times; this problem becomes more and more serious as the integration scale of 2.5D stacked chips increases.

[0006] Second, the routing algorithm creates corresponding track network information based on information such as the minimum containment rectangle of the network. The track network is dynamically created and initialized with information such as obstacles and connection pins involved in the routing. For a chip with a high connection density, the area of ​​the minimum containment rectangle of the current network will be covered by far more than one network, causing this track network to be repeatedly built and initialized. In the scenario of 2.5D chips, since the network length is relatively longer than that of 2D chips, the track network that needs to be repeatedly built and initialized is larger, and it contains more networks, requiring more repetitions, thus resulting in long routing time and requiring the algorithm to consume more memory resources.

[0007] Third, each step of propagation and backtracking is a "grid," which cannot support the need for regular routing in long networks over large areas, such as horizontal-priority straight-line routing, vertical-priority straight-line routing, 135° routing, and various combinations of these three rules. These rules are crucial for the routing of 2.5D stacked chips and directly affect SI (System Integrity) metrics. One routing rule that improves SI metrics is to combine the priority direction of the current routing layer with 135° routing at bends.

[0008] Fourth, since already used locations will be marked as obstacle areas, to efficiently utilize wiring resources, the wiring algorithm of the 2.5D chip needs to ensure that newly laid lines meet a certain line spacing with obstacles, while also minimizing resource consumption. Existing algorithms lack corresponding processing methods.

[0009] It is evident that existing wiring methods for 2.5D chips suffer from problems such as excessive memory consumption, large computational load, and excessively long computation time. Summary of the Invention

[0010] The primary objective of this invention is to provide a method for rapid routing of stacked chips that requires less computation, has high computational efficiency, and consumes less memory resources.

[0011] A second objective of the present invention is to provide a computer device for implementing the above-described method for rapid routing of stacked chips.

[0012] A third objective of this invention is to provide a readable storage medium that implements the above-described fast routing method for stacked chips.

[0013] To achieve the first objective of this invention, the stacked chip rapid routing method provided by this invention includes: acquiring chip design parameters; creating a multidimensional array based on the chip design parameters, the multidimensional array containing the status of each routing point of the chip in the horizontal, vertical, and diagonal directions; identifying routing obstacles and their physical relationships based on the multidimensional array, and identifying routing paths in each direction and the position information of the points constituting these routing paths; when routing the network, slicing the multidimensional array according to the minimum containment rectangle of the network, and generating a reference to execute the slice; acquiring the start point and end point to be routed, and determining the next routing point on the slice according to a pre-set routing rule starting from the start point, until routing reaches the end point; updating the multidimensional array for each routing point determined on the slice, marking the routing point as occupied, and simultaneously updating the routing paths in each direction and the position information of the points constituting these routing paths.

[0014] As can be seen from the above scheme, the present invention reduces the amount of computation of stacked chips and improves computational efficiency by setting up a multidimensional array, and by slicing the multidimensional array and executing slicing reference, and by performing routing calculations on the slice. For each routing point, the multidimensional array records its state changes. In this way, the amount of computation of stacked chips can be reduced, thereby improving computational efficiency, and the required computing resources are less.

[0015] A preferred approach is that the multidimensional array includes marker information in multiple directions, with each direction's marker information including the current node's occupancy status, position identifier, line segment length, or cursor position.

[0016] Therefore, by using multidimensional arrays to calculate information such as the occupancy status of the current node and the length of the line segment in each direction, the number of available wiring points in each direction can be clearly calculated, thus providing accurate information for subsequent wiring calculations.

[0017] A further approach is to update the marking information in each direction of the multidimensional array if a wiring point on the current node is occupied.

[0018] This demonstrates that by synchronously updating the marking information in multiple directions, it becomes possible to accurately determine feasible routing directions.

[0019] A further approach is to determine the number and range of wiring points occupied by an obstacle when identifying wiring obstacles based on the multidimensional array, according to the size of the identified obstacle on the cross-section.

[0020] This demonstrates that this method can clearly mark the extent of obstacles and areas where wiring is not possible.

[0021] A further approach is that when a routing point is determined on a cross section, if the current routing point is on a routing layer, then the points in the media layers adjacent to that routing layer that are located above and below the routing point are also marked as occupied or reserved.

[0022] Therefore, by marking the points on the upper and lower dielectric layers as occupied or reserved, it is possible to ensure that the wiring of the multi-layer cabling layer has sufficient spacing, and to ensure that the electrical and heat dissipation performance meets the requirements.

[0023] A further approach is to identify a routing point on the cross section, designate that routing point as a new occupancy point, and determine whether the new occupancy point meets the conditions for merging with an existing occupancy point. If so, merge the new occupancy point with the existing occupancy point.

[0024] Therefore, by merging new occupancy points with existing occupancy points, the number of occupancy points that need to be recorded can be reduced, thereby saving storage space.

[0025] A further approach is to determine whether the new occupied point meets the conditions for merging with an existing occupied point, including: whether the new occupied point is directly adjacent to an existing occupied point; if so, then the new occupied point is directly merged with the adjacent existing occupied point.

[0026] An alternative approach is to determine whether the new occupied point meets the conditions for merging with an existing occupied point, including: determining whether the distance between the new occupied point and the existing occupied point is within a preset range; if so, merging the new occupied point, the existing occupied point, and the points between the new occupied point and the existing occupied point.

[0027] Therefore, by merging adjacent or spaced points that are less than a preset range, the amount of data to be stored can be simplified.

[0028] To achieve the second objective described above, the computer device provided by the present invention includes a processor and a memory. The memory stores a computer program, and when the computer program is executed by the processor, it implements each step of the above-described fast wiring method for stacked chips.

[0029] To achieve the third objective mentioned above, the storage medium provided by the present invention stores a computer program, which, when executed by a processor, implements each step of the above-described fast wiring method for stacked chips. Attached Figure Description

[0030] Figure 1 This is a flowchart of an embodiment of the stacked chip rapid routing method of the present invention.

[0031] Figure 2 This is a schematic diagram of a cross-section in an embodiment of the rapid routing method for stacked chips of the present invention.

[0032] Figure 3 This is a schematic diagram of the dielectric layer occupancy in an embodiment of the fast routing method for stacked chips of the present invention.

[0033] Figure 4 This is a schematic diagram of a multi-dimensional cross-section in an embodiment of the rapid routing method for stacked chips of the present invention.

[0034] Figure 5 This is a schematic diagram of horizontal wiring in an embodiment of the fast wiring method for stacked chips of the present invention.

[0035] Figure 6 This is a schematic diagram of vertical routing in an embodiment of the stacked chip rapid routing method of the present invention.

[0036] Figure 7 This is a schematic diagram of the wiring from the lower left to the upper right in an embodiment of the stacked chip rapid wiring method of the present invention.

[0037] Figure 8 This is a schematic diagram of the wiring from the upper right to the lower left in an embodiment of the stacked chip rapid wiring method of the present invention.

[0038] Figure 9 This is a schematic diagram showing the occupation of wiring points during horizontal wiring in an embodiment of the stacked chip fast wiring method of the present invention.

[0039] Figure 10 This is a schematic diagram showing the occupation of routing points during vertical routing in an embodiment of the stacked chip fast routing method of the present invention.

[0040] Figure 11 This is a schematic diagram showing the occupation of routing points when routing from the lower left to the upper right in an embodiment of the stacked chip fast routing method of the present invention.

[0041] Figure 12 This is a schematic diagram showing the occupation of routing points when routing from the top left to the bottom right in an embodiment of the stacked chip fast routing method of the present invention.

[0042] Figure 13 This is a flowchart illustrating the rapid routing method for stacked chips according to the present invention, which utilizes cross-sections for routing.

[0043] Figure 14 This is a schematic diagram illustrating the principle of using cross-sections for wiring in an embodiment of the stacked chip rapid wiring method of the present invention.

[0044] Figure 15 (a) to Figure 15 (d) is a schematic diagram of each step of the first wiring method in the embodiment of the stacked chip fast wiring method of the present invention.

[0045] Figure 16 (a) to Figure 16(c) is a schematic diagram of each step of the second routing method in the embodiment of the stacked chip fast routing method of the present invention.

[0046] Figure 17 (a) to Figure 17 (b) is a schematic diagram of the steps of the third routing method in the embodiment of the stacked chip fast routing method of the present invention.

[0047] The present invention will be further described below with reference to the accompanying drawings and embodiments. Detailed Implementation

[0048] The rapid routing method for stacked chips of the present invention is used for rapid routing of 2.5D stacked chips, improving routing efficiency and reducing the demand for computing hardware resources. The method of the present invention can be implemented on a computer device having a processor and a memory, the memory being a readable storage medium of the present invention, on which a computer program is stored, and which, when executed by the processor, provides the aforementioned rapid routing method for stacked chips.

[0049] Example of a rapid routing method for stacked chips:

[0050] See Figure 1 In this embodiment, step S1 is first executed to obtain chip design parameters. For example, relevant information such as chip design and process is loaded, including the size information of the 2.5D packaged chip, such as the size of the silicon interposer or the substrate size, and the information of the wiring layer, such as the number of layers and the setting of the wiring path (track) of the metal layer, and the information of the dielectric layer, such as the size of the vias in the dielectric layer, the type and size of the via array, etc.

[0051] Next, step S2 is executed to create a multidimensional array. In this embodiment, a multidimensional array is created using design and process-related information. The created multidimensional array has three dimensions, named x, y, and z, meaning it's a three-dimensional array created along three dimensions. x and y are the two horizontal arrays, corresponding to the network formed by the wiring paths in the metal layer. z corresponds to the wiring layer and the dielectric / via (TSV) layer. Typically, wiring layers and dielectric layers are interleaved. For example, z=0 represents the first wiring layer, z=1 represents the first dielectric layer, z=2 represents the second wiring layer, and so on. Each point in the created multidimensional array represents the resource usage at that location.

[0052] Furthermore, the created multidimensional array contains the status of each routing point of the chip in the horizontal, vertical, and diagonal directions. Based on this multidimensional array, obstacles that the chip may encounter during routing can be identified, along with their physical relationships, such as their specific coordinates, whether they are adjacent, and the layer they belong to. Additionally, the multidimensional array can also identify routing paths in each direction and the positional information of the points constituting those paths, such as the specific location of each point on each routing path. Used routing areas and via areas are represented as obstacles in the multidimensional array. A connection in a routing network is a line with a width attribute. The corresponding x and y points in the routing area covered by the layer it belongs to are marked as occupied. The corresponding x and y points in the routing area covered by the dielectric layers above and below it are also marked as reserved, only usable by the current routing network. Other routing networks cannot use these vias, otherwise a short circuit will occur.

[0053] Then, in step S3, when routing the network, the multidimensional array is segmented according to the minimum containment rectangle of the network, and a reference for executing the segment is generated. Since each network is selected and the routing process is executed in a pre-defined order, typically sequentially network by network, when routing a network, the multidimensional array is segmented according to the minimum containment rectangle of that network, and a reference for executing its segment is generated. The reference for executing the segment does not copy the multidimensional array; it only constrains the range of data that needs to be accessed, providing an address for accessing the data. Therefore, it avoids the problem of repeatedly constructing routing resource data structures in the case of large-scale network routing. It can be seen that the reference for the segment executed in this embodiment does not cause data copying, and the data range of the segment is very small. Using the method of this invention, the solution space for routing is data pointing to the segment representing a smaller data set, and after routing is completed, the area covered by the current routing is marked as occupied.

[0054] See Figure 2 Since the current routing operation is within the xOy plane, the size of the cross-section is determined based on the minimum rectangle of the routing. For example, if the x-axis start and end coordinates of the cross-section are [x1, x2] and the y-axis start and end coordinates are [y1, y2], then the routing range is limited to the area between [x1, x2] and [y1, y2]. Assume the current routing will directly cover... Figure 2 Points numbered 16 to 19 will be marked as occupied. Additionally, because the distance between points numbered 1 to 15 and the already marked occupied points (points numbered 16 to 19) is too small, if these points are used for routing, the new routing will not meet the specific line spacing requirements. For example, if the line width is x, the line spacing is 2x. Therefore, points numbered 1 to 15 will be marked as occupied.

[0055] In addition, such as Figure 3 As shown, in a certain dielectric layer, if the size of an occupied point is small, for example, the size of occupied point number 1 is small, it will only directly occupy the point it occupies. If the size of the occupied point is large, for example, the size of occupied point number 2 is relatively large, it will not only occupy the area it covers, but also the surrounding area. Therefore, points numbered 3 to 10 will not be marked as occupied. Figure 2 and Figure 3 It can be seen that the resource usage calculation methods for the dielectric layer and the wiring layer are the same.

[0056] See Figure 4 In the three-dimensional direction, if the current routing needs to be performed on layer Z1, the coordinates of the routing area on the x-axis and y-axis are [x1, x2] and [y1, y2], respectively. Figure 4 The green section represents the routing layer (Z1), while layers Z0 and Z2 are dielectric layers. When resources in a routing layer are occupied, the corresponding resources in the dielectric layers must also be marked as reserved or occupied. For example, if points in the Z1 layer with coordinates between [x1, x2] and [y1, y2] are marked as occupied, then in the Z0 and Z2 layers, points with coordinates between [x1, x2] and [y1, y2] are marked as reserved. This means that these resources in the Z0 and Z2 layers can only be occupied by the nets that reserve them. Therefore, the use of multidimensional arrays and their sectional techniques can circumvent the problems of mesh reconstruction, creation, and initialization for routing paths in metallic layers in traditional techniques, improving the efficiency of routing calculations.

[0057] The following describes the data structure of objects stored in a multidimensional array. In this embodiment, the multidimensional array includes the following information: the current position in four directions (horizontal, vertical, and diagonal). The data structure describing the state uses 8 bytes, and the specific structure is as follows:

[0058]

[0059] As can be seen from the table above, each direction uses 2 bytes to record the status of each wiring point. The descriptions of each field are as follows:

[0060]

[0061] In the initial stage, all points in the network are idle, such as... Figure 5 As shown, assuming wiring is done in the horizontal direction, then in Figure 5 Within the wiring area shown, the length of each row of free wiring points is 12; as shown... Figure 6 As shown, if the wiring is vertical, the length of each column of free wiring points is 9; as Figure 7As shown, if routing proceeds from the bottom left to the top right, the length of the longest free routing point on the diagonal is 9; Figure 8 As shown, if the routing direction is from the top left to the bottom right, the length of the longest free routing point on the diagonal is also 9.

[0062] See Figure 9 Suppose that during routing, a point is occupied, for example, the red point in the diagram is set as a routing point and is occupied. Then, the state of each routing point in that row needs to be updated in the multidimensional array. For example, if the two blue routing points are set as the start and end points of an empty line segment, the position identifier and length value of that line segment need to be updated. For points after the occupied point, i.e. Figure 9 The green dots are points that will be used for subsequent wiring. Therefore, the status of the green dots needs to be updated, including their location markers and line segment lengths.

[0063] Similarly, in the vertical direction, see Figure 10 If a red point is set as a routing point and is occupied, the status of each routing point in this column needs to be updated in the multidimensional array. For example, if the two blue routing points are set as the start and end points of an empty line segment, the position identifier and length value of this line segment need to be updated. For points after the occupied point, i.e. Figure 10 The green dots are points that will be used for subsequent wiring. Therefore, the status of the green dots needs to be updated, including their location markers and line segment lengths.

[0064] The same applies to the diagonal, such as Figure 11 and Figure 12 As shown, if a red point is set as a routing point and is occupied, the state of each routing point on the corresponding diagonal needs to be updated in the multidimensional array. For example, if the two blue routing points are set as the start and end routing points of an empty line segment, the position identifier and line segment length value of this line segment need to be updated. For points after the occupied point, i.e., the green points in the figure, since these points are the points that need to be routed later, the state of the green points needs to be updated, and the position identifier, line segment length value, and other information of the green points need to be updated.

[0065] Furthermore, for newly added occupancy points, it is necessary to determine whether the new occupancy point can be merged with existing occupancy points. Therefore, in this embodiment, after determining a routing point on the cross-section and identifying it as a new occupancy point, it is also necessary to determine whether the new occupancy point meets the conditions for merging with existing occupancy points. If the merging conditions are met, the new occupancy point needs to be merged with the existing occupancy point. Specifically, it can be determined whether the new occupancy point is directly adjacent to an existing occupancy point. If so, the new occupancy point is directly merged with the adjacent existing occupancy point; or, determining whether the new occupancy point meets the conditions for merging with existing occupancy points includes: determining whether the distance between the new occupancy point and the existing occupancy point is within a preset range. If so, the new occupancy point, the existing occupancy point, and the points between the new occupancy point and the existing occupancy point are merged. Through the above method, new occupancy points can be merged with existing occupancy points, thereby reducing the number of occupancy points that need to be recorded, and thus achieving the goal of saving storage space.

[0066] See you later Figure 1 After executing step S3, step S4 is executed last, performing routing based on the cross-section. For example, the start and end points of the line segment to be routed are obtained. Starting from the start point, the next routing point is determined on the cross-section according to pre-defined routing rules, until routing reaches the end point. During the routing process, the multidimensional array is updated for each routing point determined on the cross-section, marking the routing point as occupied. Furthermore, the available routing paths in each direction and the position information of the points constituting the routing paths must be updated synchronously, meaning the data in the multidimensional array is updated synchronously.

[0067] The following is combined with Figure 13 The specific routing process is described below. First, step S11 is executed to obtain the starting point of the routing and begin routing from that point. Then, step S12 is executed to determine if the frontier queue is empty. If it is empty, it means there are no line segments to be routed, and the routing process is terminated directly. If the frontier queue is not empty, step S13 is executed to obtain a point in the frontier queue, and step S14 is executed to determine if the currently obtained point is the end point of the routing. If it is the end point, it means the line segment has been routed, and the routing process ends. If the current point is not the end point of the routing, step S15 is executed to obtain the preferred routing direction. In this embodiment, the preferred routing direction of the 2.5D stacked chip is determined by the following rules: First, horizontal / vertical direction is preferred, which is represented by straight line segments in the horizontal / vertical direction; Second, same-layer routing is preferred and a 135° line segment turn is used, which is represented by horizontal line segments being connected to vertical line segments by straight line segments in the 45° or 135° direction.

[0068] After determining the preferred routing direction, step S16 is executed to determine whether any obstacles are found within the step length, that is, to determine whether any points are occupied. If an obstacle is found, step S17 is executed to obtain the next adjacent point of the current point in the preferred routing direction. Then step S18 is executed to determine whether the next adjacent point is a point on the shortest routing path from the starting point. If so, the next adjacent point is determined as the routing point, and step S19 is executed to update the starting point and path length information of each step. If the result of step S18 is negative, step S17 is returned to obtain another adjacent point.

[0069] If the judgment result of step S16 is negative, then step S20 is executed, prioritizing line segments are set according to the relative positions of the starting and ending points of the discovered obstacle line segments, and step S21 is executed, performing pattern routing from the current point to the starting point of the priority line segment. Finally, step S22 is executed, prioritizing line segment routing is performed, and the process returns to step S12 until the leading queue is empty.

[0070] The following is combined with Figure 14 The routing process is described below. For example, if we need to route to points 1 and 2, we set up a line segment connecting them. Point 1 is designated as the starting point for the routing. Starting from this point, we check the status of the points around the perimeter and at the diagonal corners. When checking the status of point A, we can identify it as the starting point of a line with a length of 8 grid nodes. By analyzing the fly-through lines from point 1 to point 2 and the obstacles starting from point A, when routing from pin 1, while maintaining the required spacing, we can maximize the use of routing resources by routing along the obstacles from left to right, while also achieving neat routing of multiple network groups.

[0071] The requirements for the priority path finding algorithm for network routing include: First, the obstacles to routing of 2.5D stacked chips are mainly: (1) the track intersection resources occupied by the already routed network in the routing layer; (2) the track intersection resources occupied by the vias used by the already routed network to cross the current routing layer. Second, in an ideal case, the algorithm framework of the A* algorithm includes: heuristic values ​​(generally based on the distance from the target focus) to guide the direction of routing; using a stack to store the neighbor nodes to be explored, named "node stack to be explored"; using a dictionary to store each step of routing; using a dictionary to store the length of each routing path. Third, the determination of routing priority direction: horizontal / vertical direction priority, which is represented by straight line segments in the horizontal / vertical direction; same-layer routing priority and using 135° line segment corners, which is represented by connecting the horizontal line segment with the vertical line segment through a straight line segment in the 45° or 135° direction.

[0072] In this way, obstacles mostly appear in straight lines, and the preferred path also needs to be a straight line. This embodiment is based on the A* algorithm framework, optimizing the nodes entering the node stack to be explored based on wiring rules. For example, if the wiring rules do not allow 90° turns, then specific line spacing requirements are met; the wiring path and the node stack to be explored are set based on the obstacle direction and the network's current preferred wiring direction.

[0073] The following is combined with Figure 15 (a) to Figure 15 (d) This section describes the various stages of the first wiring method in this embodiment. First, as... Figure 15 As shown in (a), the starting point of the wiring is S, the preferred direction of wiring is the x-axis direction, which is the horizontal direction, and the ending point of wiring is T. During wiring, the search begins from the starting point S, and an obstacle point B1 is found. The length and direction of the obstacle can be determined from the information of obstacle point B1. Information about other points around the starting point S is also obtained, such as the information of multiple points with serial numbers 1, 2, 3, 4, 5, 6, and 7. According to the pattern wiring, the order of the neighboring points to be explored at the starting point S is 7, 6, 5, 4, 3, 2, and 1. The order of these multiple points entering the node stack to be explored is 1, 2, 3, 4, 5, 6, and 7. The starting point of the preferred path is set to point number 7 based on the preferred direction. During the path exploration and selection process, it is necessary to obtain the available wiring paths in each direction and identify the length of the wiring paths, that is, to determine the number of points that can be wired before encountering obstacles under each available wiring path. The preferred path is the longest available wiring path under the current available wiring resources. Wiring is performed based on the preferred direction wiring path, making the chip wiring more regular. Furthermore, the preferred direction wiring path is longer, which increases the step size of each exploration step, thereby improving the wiring speed of the chip.

[0074] Then, as Figure 15 As shown in (b), routing from the starting point S to point 7 is completed using pattern routing. Point 7 is determined to be the starting point of the preferred direction routing. According to the preferred segment routing and combined with the design rules, point 6A cannot be used for routing because routing cannot have 90° turns. Therefore, point 6A will not be added to the node stack to be explored. Thus, the order of the node stack to be explored is 7A, 8A, 9A, 10A. Based on the above rules, the path of the preferred direction routing is determined to pass through multiple points with serial numbers 7, 8, 9, and 10.

[0075] Then, as Figure 15As shown in (c), the wiring is carried out starting from point 10. Since no obstacles are found, the wiring from point 10 to the terminal point T can be completed in the traditional A* algorithm. Point 11A is added to the stack of nodes to be explored, and point 11 constitutes the last node of the current path.

[0076] Finally, as Figure 15 As shown in (d), the remaining road segments are routed using the traditional A* algorithm until the termination point T is reached.

[0077] This embodiment also improves upon the first wiring method described above, see [link to documentation]. Figure 16 (a) The starting point of the routing is S, the preferred routing direction is the x-axis direction, which is the horizontal direction, and the ending point of the routing is T. During routing, it is necessary to search for the routing path from the starting point S to the point with index 7. Then, the point with index 7 is explored. It is found that the path from the starting point S, the point with index 7, and the point with index 6A forms a right angle, which does not meet the 135° routing rule. Therefore, the point with index 6A is not added to the node stack to be explored, thus narrowing the exploration range.

[0078] Then, as Figure 16 (b) and Figure 16 As shown in (c), when setting the preferred path start point, the influence of line spacing needs to be considered. When routing from the starting point S to the preferred routing segment start point, the influence of line spacing should be considered. That is, the point with the serial number B1 cannot be used for routing, and the point with the serial number 7A is selected for routing.

[0079] This embodiment also improves the first wiring method described above in another way, see [link to relevant documentation]. Figure 17 (a) The line connecting points numbered 7 and 8 is the optimal path, while... Figure 17 In (b), the line connecting points 7b and 8 is the optimal path. In this method, the endpoint of the optimal path is determined by starting from point 8 and reaching the endpoint T, where the changes in the x-axis and y-axis are the same. If an obstacle is found on the optimal path, that obstacle is the furthest point of the optimal path routing. Routing from the starting point S to this furthest point is then directly implemented, and the content of the node stack to be explored is set according to the design rules. This method enables rule-based routing and fully utilizes resources to implement routing around obstacles and new networks.

[0080] This invention loads the routing resource data structure into memory all at once using a multidimensional array, accelerating routing speed through memory access and computation. Furthermore, by using the multidimensional array and references based on its aspects—since the aspect references do not copy the multidimensional array but only constrain the range of data requiring the specified range, providing a single address for data access—this invention avoids the problem of repeatedly constructing the routing resource data structure in large-scale network routing, thus improving routing efficiency.

[0081] Furthermore, this invention updates and calculates the longest available resource segment and the longest used resource segment in the four directions (horizontal, vertical, and diagonal) in real time, and solves for the preferred candidate exploration paths. These paths are often much longer than 1, thereby improving the low exploration efficiency caused by the A* algorithm's exploration step size of 1. The method of this invention calculates fewer polylines, which can improve the efficiency of wiring.

[0082] Finally, to improve the utilization of routing resources, the candidate preferred exploration path supports line segments attached to obstacles, which represent already routed networks. Therefore, this invention creates preferred candidate exploration paths based on routing rules (such as 135° turn routing), preferred routing direction, longest available line segment, and longest occupied line segment (representing a network that has been routed). In the scenario of 2.5D chip routing, multiple networks between two chips have similar directions, and these networks can achieve neater routing by routing through the preferred candidate exploration path.

[0083] Computer device embodiment:

[0084] The computer device in this embodiment can be a desktop computer or a data center or data station, which has a processor, a memory, and a computer program stored in the memory and executable on the processor, such as an information processing program for implementing the above-described information processing method. When the processor executes the computer program, it implements each step of the above-described stacked chip fast routing method.

[0085] For example, a computer program can be divided into one or more modules, one or more of which are stored in memory and executed by a processor to complete the various modules of the present invention. One or more modules can be a series of computer program instruction segments capable of performing a specific function, which describe the execution process of the computer program in a terminal device.

[0086] The processor referred to in this invention can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor can be a microprocessor or any conventional processor. The processor is the control center of the terminal device, connecting various parts of the terminal device through various interfaces and lines.

[0087] Memory can be used to store computer programs and / or modules. The processor implements various functions of the terminal device by running or executing the computer programs and / or modules stored in the memory, and by accessing data stored in the memory. Memory may mainly include a program storage area and a data storage area. The program storage area may store the operating system, applications required for at least one function, etc.; the data storage area may store data created based on the use of the mobile phone, etc. In addition, memory may include high-speed random access memory, and may also include non-volatile memory, such as hard disks, RAM, plug-in hard disks, smart media cards (SMC), secure digital cards (SD cards), flash cards, at least one disk storage device, flash memory device, or other volatile solid-state storage devices.

[0088] Storage medium examples:

[0089] If a computer program stored in a computer device is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments of the present invention can also be implemented by a computer program instructing related hardware. This computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the various steps of the above-described rapid wiring method for stacked chips.

[0090] Computer programs include computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. Computer-readable media can include: any entity or device capable of carrying computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc. It should be noted that the content included in computer-readable media can be appropriately added to or subtracted according to the requirements of legislation and patent practice in a jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electrical carrier signals and telecommunication signals.

[0091] Finally, it should be emphasized that the above are merely preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention can have various changes and modifications. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. Rapid routing methods for stacked chips, including: Obtain chip design parameters; Its features are: A multidimensional array is created based on the chip's design parameters. The multidimensional array has three dimensions: the x and y directions correspond to the network formed by the wiring paths in the metal layer, and the z direction corresponds to the wiring layer and the dielectric layer / via layer. The multidimensional array contains the status of each wiring point of the chip in the horizontal, vertical and diagonal directions. Based on the multidimensional array, obstacles to wiring and the physical relationship of the obstacles are identified, and the paths that can be wired in each direction and the position information of the points that constitute the wiring path are identified. When routing the network, the multidimensional array is sliced ​​according to the minimum containment rectangle of the network, and a reference for executing the slice is generated. When executing the reference for the slice, the address of the access data is provided and the range of the data to be accessed is constrained. Obtain the start point and end point of the routing to be done. Starting from the start point, determine the next routing point on the cut surface according to the preset routing rules, until the routing reaches the end point. For each routing point determined on the cross-section, the multidimensional array is updated, the routing point is marked as occupied, and the routing paths in each direction and the position information of the points constituting the routing paths are updated in real time to update and calculate the longest available resource segment and the longest used resource segment in the horizontal, vertical and diagonal directions, and to solve for the preferred candidate exploration path.

2. The method for rapid routing of stacked chips according to claim 1, characterized in that: The multidimensional array includes marker information in multiple directions, and the marker information in each direction includes the current node's occupancy status, position identifier, line segment length, or cursor position.

3. The method for rapid routing of stacked chips according to claim 2, characterized in that: If a wiring point on the current node is occupied, the marking information in each direction of the multidimensional array is updated.

4. The method for rapid routing of stacked chips according to any one of claims 1 to 3, characterized in that: When identifying obstacles in the wiring based on the multidimensional array, it is also necessary to determine the number and range of wiring points occupied by the obstacle based on the size of the identified obstacle on the cross-section.

5. The method for rapid routing of stacked chips according to any one of claims 1 to 3, characterized in that: When a routing point is determined on the cross-section, if the current routing point is on the routing layer, then the points in the dielectric layer adjacent to the routing layer that are located above and below the routing point are also marked as occupied or reserved.

6. The method for rapid routing of stacked chips according to any one of claims 1 to 3, characterized in that: After a wiring point is determined on the cross-section, the wiring point is designated as a new occupied point, and it is determined whether the new occupied point meets the conditions for merging with an existing occupied point. If so, the new occupied point is merged with the existing occupied point.

7. The method for rapid routing of stacked chips according to claim 6, characterized in that: Determining whether a new occupied point meets the conditions for merging with an existing occupied point includes: determining whether the new occupied point is directly adjacent to an existing occupied point; if so, the new occupied point is directly merged with the adjacent existing occupied point.

8. The method for rapid routing of stacked chips according to claim 6, characterized in that: Determining whether a new occupied point meets the conditions for merging with an existing occupied point includes: determining whether the distance between the new occupied point and the existing occupied point is within a preset range; if so, merging the new occupied point, the existing occupied point, and the points between the new occupied point and the existing occupied point.

9. A computer device, characterized in that, It includes a processor and a memory, the memory storing a computer program, which, when executed by the processor, implements the various steps of the stacked chip rapid routing method as described in any one of claims 1 to 8.

10. A readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by the processor, it implements the various steps of the stacked chip fast routing method as described in any one of claims 1 to 8.

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