Silicon wafer edge defect detection method and system under special chamfering process

Abstract

The invention provides a silicon wafer edge defect detection method and system under a special chamfering process, and belongs to the field of semiconductors, and the method comprises the steps: obtaining a chamfered silicon wafer edge image; carrying out layer-by-layer convolution on the edge image of the silicon wafer to extract target contour features, capturing local detail features in the target contour features by utilizing grouped convolution, and then carrying out global average pooling and activation function calculation to obtain a defect probability; screening out defective images in the edge images of the silicon wafer according to the defect probability; extracting edge texture features of the image of the defect; performing multi-channel dynamic convolution kernel weighting and feature fusion on the extracted edge texture features, and performing spatial enhancement on fused feature information to obtain enhanced target features; and performing regression calculation based on the enhanced target features, and outputting a defect bounding box. The silicon wafer edge defect automatic detection method is deployed on an industrial site, so that the yield and the productivity of the silicon wafer are greatly improved.

Description

Technical Field

[0001] This invention belongs to the field of semiconductors, specifically relating to a method and system for detecting edge defects in silicon wafers under a special chamfering process. Background Technology

[0002] In semiconductor manufacturing, the core objective of silicon wafer edge inspection is to identify geometric defects (such as chipping, cracks, and scratches), surface roughness, chamfer quality, and edge contour integrity at the wafer edges. These defects may originate from processes such as slicing, grinding, and polishing. If they are not detected in time, they can lead to a decrease in chip yield in subsequent processes and even affect device performance.

[0003] In actual production, there are two stages: primary chamfering and secondary chamfering. After primary chamfering, the silicon wafer edge has no special texture, the edge is clear, and the grayscale difference between the defect area and the normal area is large with obvious grayscale boundaries. Therefore, a grayscale threshold setting can be used to capture the defect area, extract the defect feature image, and then feed it into a deep learning classification network for classification. The secondary chamfering process is performed after high-precision polishing to further optimize stress distribution, suppress thin film deposition defects, reduce ion implantation sputtering, and achieve more refined silicon wafer edge polishing. The edge image of secondary chamfering has intersecting stripes and textures similar to defects, making detection more difficult. Traditional grayscale threshold segmentation cannot identify and locate defects, so it cannot detect defects on the silicon wafer edge after secondary chamfering. Summary of the Invention

[0004] To address the problem of identifying and locating edge defects in silicon wafers during the chamfering process, this invention provides a method and system for detecting edge defects in silicon wafers under a special chamfering process.

[0005] To achieve the above objectives, the present invention provides the following technical solution: A method for detecting edge defects in silicon wafers under a special chamfering process includes the following steps: Obtain the edge image of the beveled silicon wafer; perform layer-by-layer convolution on the edge image to extract target contour features, and use grouped convolution to capture local detail features in the target contour features; perform global average pooling and activation function calculation on the local detail features to obtain the defect probability; and filter out defective images from the edge image of the silicon wafer based on the defect probability. Extract edge texture features from the image of the defect; perform multi-channel dynamic convolution kernel weighting on the extracted edge texture features; perform feature fusion on the weighted multi-channel features; perform spatial enhancement on the fused feature information to obtain the enhanced target features; perform regression calculation based on the enhanced target features to output the defect bounding box.

[0006] Preferably, the cropped image is processed by a lightweight residual binary classification neural network model to filter out defective images. Specifically, the lightweight residual binary classification neural network model uses a ResNet34 residual network as the backbone network and introduces an EMA mechanism for grouped convolutions to capture local detail features in the target contour features; DP convolution replaces the first traditional convolution in ResNet34; and GS convolution replaces the second traditional convolution in ResNet34.

[0007] Preferably, the defective image is processed by the SiED-YOLO object detection network to obtain the defect bounding box. Specifically, the SiED-YOLO object detection network is based on the YOLO network architecture and introduces a dual-axis attention mechanism (DAA) module after convolution. This module is used to perform multi-channel dynamic convolution kernel weighting on the extracted edge texture features and to fuse the weighted multi-channel features. The receptive field is adaptively adjusted using the learnable convolution kernel of the DyC-C2f module to optimize the multi-scale feature response.

[0008] Preferably, when training the SiED-YOLO object detection network, the Inner-IoU loss function is used to calculate the model error, and the model parameters are adjusted according to the error; the Inner-IoU loss function sets a scale adjustment factor to control the scaling ratio of the auxiliary bounding box.

[0009] Preferably, the acquisition of the edge image of the beveled silicon wafer specifically involves using a dual CCD line array camera, in conjunction with a ring light source, to acquire the elongated edge image of the upper and lower beveled arc surfaces of the silicon wafer after the secondary bevel.

[0010] Preferably, the defect bounding box includes the defect's location, size, category probability, and detection confidence.

[0011] This invention provides a silicon wafer edge defect detection system under a special chamfering process, specifically comprising: An image classification module is used to acquire the edge image of the beveled silicon wafer; to extract target contour features by performing layer-by-layer convolution on the edge image of the silicon wafer, and to capture local detail features in the target contour features by using grouped convolution; to calculate the defect probability by performing global average pooling and activation function on the local detail features; and to filter out defective images in the edge image of the silicon wafer based on the defect probability.

[0012] The defect detection module is used to extract the edge texture features of the image of the defect; to perform multi-channel dynamic convolution kernel weighting on the extracted edge texture features; to perform feature fusion on the weighted multi-channel features; to perform spatial enhancement on the fused feature information to obtain the enhanced target features; and to perform regression calculation based on the enhanced target features to output the defect bounding box.

[0013] The present invention also provides a computer device, including a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps described in the method for detecting silicon wafer edge defects under a special chamfering process.

[0014] The present invention also provides a computer-readable storage medium storing a computer program that, when loaded by a processor, can execute the steps described in the method for detecting silicon wafer edge defects under a special chamfering process.

[0015] The silicon wafer edge defect detection method provided by this invention under a special chamfering process has the following beneficial effects: This invention acquires images of silicon wafers after a secondary chamfering process at the edges, and uses convolutional dynamics for multi-scale feature extraction to reduce the missed detection of minute defects. Grouped convolutions capture local detail features, minimizing the impact of image noise. Defect images are obtained by filtering based on the identified defects. The defect images are then fused and enhanced with multi-branch features combining spatial and channel dimensions. By independently modeling and fusing attention weights in both dimensions, the model's processing capability in complex image backgrounds is improved, enhancing defect recognition accuracy. By using machine vision processing to replace human visual inspection, automated detection of silicon wafer edge defects is achieved and can be deployed in industrial settings, significantly improving silicon wafer yield and production capacity. Attached Figure Description

[0016] To more clearly illustrate the embodiments and design schemes of the present invention, the accompanying drawings required for this embodiment will be briefly described below. The drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a flowchart of a silicon wafer edge defect detection method under a special chamfering process according to an embodiment of the present invention.

[0018] Figure 2 This is a network structure diagram of a lightweight residual binary classification neural network model in an embodiment of the present invention.

[0019] Figure 3 This is a structural diagram of the SiED-YOLO target detection network in an embodiment of the present invention.

[0020] Figure 4 This is a structural diagram of the DAA dual-axis attention module in an embodiment of the present invention. Detailed Implementation

[0021] To enable those skilled in the art to better understand and implement the technical solutions of the present invention, the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments. The following embodiments are only used to more clearly illustrate the technical solutions of the present invention and should not be construed as limiting the scope of protection of the present invention.

[0022] Example This invention provides a method for detecting edge defects in silicon wafers under a special chamfering process, such as... Figure 1 As shown, the specific steps include: Step 1: In a darkroom environment, an automatic image acquisition system for silicon wafer edges is designed to achieve high-resolution imaging of the upper and lower chamfered arc surfaces of the silicon wafer after secondary chamfering. Two elongated images of the silicon wafer edge, each measuring 768*1520000 pixels, are obtained from a single wafer. Unlike general inspection systems based on single-light source, single-view camera, this system employs a dual-CCD line array camera in conjunction with a ring light source, solving the unique challenge of acquiring images of large silicon wafer edges. By symmetrically arranging the two cameras at ±45° positions around the silicon wafer's rotation axis, synchronous high-resolution imaging of the upper and lower chamfered arc surfaces is achieved. The uniform diffuse illumination from the ring light source effectively suppresses reflections from the silicon wafer's arc surfaces, preventing defects from being overwhelmed by strong light or reflections. The system eliminates the need for complex polarizing filters or dynamic dimming devices, ensuring stability in the production environment.

[0023] Step 2: Using an image cropping algorithm, the edge image of the long strip silicon wafer is cropped proportionally and partially (the next image is cropped from the middle of the previous image) to ensure that defect information is not lost while completing image normalization (cropping from 768*7520000 to 768*768).

[0024] Step 3: Using the ResNet34 residual network as the backbone network reference architecture, an EMA mechanism is introduced after the convolutions. The first traditional convolution in ResNet34 is replaced with a DP convolution; the second traditional convolution in ResNet34 is replaced with a GS convolution, resulting in a lightweight residual binary classification neural network model, as shown below. Figure 2 As shown, this demonstrates the classification of samples with and without defects. The specific steps of the lightweight residual binary classification neural network model are as follows:

[0025] S31: The lightweight residual binary classification neural network model receives data input from the upstream image cropping algorithm, namely a large number of small images of silicon wafer edges with a size of 768×768, each image is accompanied by its physical coordinate marking information on the original silicon wafer edge.

[0026] S32: Image data is sequentially passed through a lightweight residual network structure: (1) First, the input is via 7×7DP convolution, which significantly reduces the number of parameters while preserving a large receptive field and efficiently extracts primary edge features.

[0027] (2) The network then enters the lightweight module stacking stage, which includes four sets of repeating structures, each consisting of three core components connected in series.

[0028] (3) The image enters the DP convolution, replacing the standard convolution with the depthwise convolution, which significantly reduces the number of parameters while ensuring its feature extraction capability.

[0029] (4) Next, it enters GS convolution. Through group calculation and channel shuffling strategy, it further compresses the computation cost while retaining the feature expression ability, and works with DPConv to achieve layer lightweighting.

[0030] (5) Then, the efficient multi-scale attention EMA module for cross-space learning is entered. The EMA module is embedded after each set of convolution operations to enhance the response to subtle defects while suppressing background noise interference.

[0031] (6) Finally, the jump connection is entered, and the input features are directly connected to the output of the EMA module to avoid gradient vanishing and ensure effective training of deep networks.

[0032] (7) The end of the layer compresses the feature dimension through global average pooling, connects the binary fully connected layer and the Sigmoid activation function, and outputs the single-valued defect probability P.

[0033] S33: Output the small images with defects after removing the "defect-free" images.

[0034] Step 4: Construct the SEWDS-3 database of edge defects in secondary chamfered silicon wafers based on the selected defective images.

[0035] Step 5: Based on the YOLO network architecture, a dual-axis attention mechanism (DAA) module is introduced after convolution. A dynamic convolutional feature pyramid centered on the DyC-C2f module is designed for feature fusion, and an Inner-IOU loss function is introduced to train the SiED-YOLO object detection network, as shown below. Figure 3 As shown, this enables the classification and location of defects.

[0036] S51: The defective silicon wafer edge image is input into the 768×768 image and fed into the Stem Feature section for initial convolution processing to generate an initial feature map, capturing basic image information. This module serves as a primary feature extractor, laying the spatial feature foundation for subsequent processing.

[0037] S52: The feature map is progressively deepened through 4 Stage Blocks. Each Stage Block extracts features through the CM module, which then fuses the features through the C2f module via multi-branch features, and finally uses the DAA dual-axis attention module to suppress silicon background noise.

[0038] Existing attention mechanisms (such as CBAM and CoordAtt) can enhance global features, but the DAA dual-axis attention module is specifically designed for directional stripe noise, with a structure as follows: Figure 4 As shown, DyC-C2f solves the problem of complex background interference by decoupling through orthogonal spatial dependencies, unlike the fixed convolutions of the YOLO series or the static FPN of Faster R-CNN. DyC-C2f addresses the deficiency of large pixel spans by adaptively fusing features through convolutional kernel weights, improving mAP@0.5 by 1.8%. The specific processing procedure of the DAA dual-axis attention module is as follows:

[0039] Given input features Adaptive average pooling is performed along both the height and width dimensions. Height-dimensional pooling compresses the features into... Tensors are used to capture long-range dependency features in the vertical direction; width-dimensional pooling is used to generate... The feature map focuses on contextual information in the horizontal direction. The spatial dimension of the original feature is decomposed into two orthogonal axes, significantly reducing computational complexity. The compressed axial features interact across channels through a one-dimensional convolutional module with shared parameters. A 7-pixel-wide convolutional kernel is used to expand the receptive field, and group normalization is employed to enhance channel independence. Its mathematical expression is shown below:

[0040] ; in, This indicates an axial pooling operation. It has a 7×1 convolution kernel. The axial attention map is activated by the sigmoid function. GN represents a normalization layer with 16 groups, h represents the height dimension of the feature map (corresponding to the number of pixels in the vertical direction), w represents the width dimension of the feature map (corresponding to the number of pixels in the horizontal direction), and d refers to the channel dimension of the feature map, i.e., the dimension of the feature vector of each pixel. The generated axial attention map is then element-wise multiplied with the original features via tensor broadcasting to achieve spatially sensitive feature enhancement.

[0041] S53: Cross-level feature fusion (Neck) adopts a bidirectional cross-scale connection mechanism. In the upsampling path, after deep features are amplified by interpolation, they are concatenated with the mid-level 96×96×64 features through Concat. The concatenated features are input into the DyC-C2f module, and the receptive field is adaptively adjusted through K learnable convolutional kernels to optimize the multi-scale defect feature response.

[0042] S54: In the object detection and loss calculation (Head) section, Inner-IoU loss is adopted to address core issues such as the complex interaction between background texture and target features in silicon wafer edge defect detection. In the field of object detection, IoU loss can accurately describe the matching degree between the predicted bounding box and the ground truth bounding box, ensuring that the model can learn the target's positional information during training. The mathematical expression of the traditional IoU loss function is:

[0043] ; in, and These represent the predicted bounding box and the ground truth bounding box, respectively.

[0044] However, this function has some drawbacks. For example, the gradient vanishes when the predicted bounding box does not overlap with the ground truth bounding box, causing the model to fail to update parameters effectively. It also struggles to adapt to the regression requirements of complex geometric features in silicon wafer defect detection. To address this, we propose an Inner-IoU loss function, the core innovation of which lies in constructing a scale-adjustable auxiliary bounding box system. The bounding box parameters and calculation process are as follows:

[0045] The formula for calculating the lateral boundary of the target bounding box is shown in the following equation: ; in, and The coordinates of the left and right boundaries of the target bounding box. With the x-axis as the center, For width, This is a scale adjustment factor used to control the scaling ratio of the auxiliary bounding box. The formula for calculating the vertical boundary of the target bounding box is shown in the following equation:

[0046] ; in, and The coordinates of the upper and lower boundaries of the target bounding box. With the central ordinate as the coordinate, The height is given. The predicted horizontal boundary of the bounding box is calculated as shown in the formula:

[0047] ; in, and The coordinates of the left and right boundaries of the predicted bounding box. Let w be the x-coordinate of the prediction center and w be the prediction width. The vertical boundary of the prediction bounding box is calculated as shown in the formula:

[0048] ; in, and The coordinates of the upper and lower boundaries of the prediction box. Let y be the predicted center coordinate and h be the predicted height. The area of ​​the overlapping region between the target bounding box and the predicted bounding box is calculated by comparing their boundary coordinates. The area of ​​the intersection region is calculated as shown in the formula:

[0049] ; The Inner-IoU loss function overcomes the limitations of variants such as GIoU and DIoU in micro-defect regression, and its scale-adjustable auxiliary bounding box optimizes the localization accuracy of high IoU targets.

[0050] Taking into account the total area of ​​the target region, the predicted region, and the overlapping area, the area of ​​the auxiliary bounding box is calculated by multiplying the original size by the square of the ratio, and the area of ​​the union region is calculated using the following formula: ; The localization accuracy is measured by the ratio of the intersection to the union. This loss function dynamically adjusts the ratio parameter to improve the sub-pixel-level localization accuracy of high-IoU targets while maintaining the regression stability of low-IoU targets, thus achieving adaptive focusing of multi-scale defect features. The Inner-IoU loss function achieves adaptive focusing of multi-scale defect features within the YOLO framework by dynamically balancing the sub-pixel-level localization accuracy of high-IoU targets with the global regression stability of low-IoU targets.

[0051] The Inner-IoU loss function introduces a scale adjustment factor to control the scaling range, constructs a scaled "inner frame" to calculate IoU, and optimizes the localization of micro-defects.

[0052] The three modules of SiED-YOLO work together to enable the DAA dual-axis attention module to suppress background texture at a shallow level while preserving high-frequency components of microcracks. The enhanced feature input DyC-C2f is dynamically weighted by convolutional kernels to focus on the defect region, avoiding multi-scale feature confusion. Finally, the localization accuracy is optimized through Inner-IoU loop closure.

[0053] S55: Finally, the SiED-YOLO network outputs the defect bounding box (position + size), defect category probability, and detection confidence. Combined with the coordinate markers of the input image, the predicted box is mapped back to the physical location of the silicon wafer's solid edge. Specific defect categories include: edge chipping, cracks, or dirt.

[0054] This invention also provides a silicon wafer edge defect detection system under a special chamfering process, comprising: The image classification module is used to acquire the edge image of the beveled silicon wafer; it performs layer-by-layer convolution on the edge image of the silicon wafer to extract the target contour features, and uses grouped convolution to capture the local detail features in the target contour features; it performs global average pooling and activation function calculation on the local detail features to obtain the defect probability; and it filters out the defective images in the edge image of the silicon wafer based on the defect probability.

[0055] The defect detection module is used to extract edge texture features from the defect image; the extracted edge texture features are weighted by multi-channel dynamic convolution kernels, and the weighted multi-channel features are fused. The fused feature information is spatially enhanced to obtain the enhanced target features; regression calculation is performed based on the enhanced target features to output the defect bounding box.

[0056] The modules in the silicon wafer edge defect detection system under the aforementioned special chamfering process can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in the processor of a computer device in hardware form or independent of it, or stored in the memory of a computer device in software form, so that the processor can call and execute the corresponding operations of each module.

[0057] The present invention also provides a computer device, including a memory, a processor, and a computer program stored in the memory. The processor executes the computer program to implement the steps in an embodiment of a silicon wafer edge defect detection method under a special chamfering process. Specific implementation methods can be found in the method embodiments, and will not be repeated here.

[0058] Furthermore, the present invention also provides a non-transitory computer-readable storage medium containing instructions on which a computer program is stored. For example, a memory containing instructions that can be executed by a processor of a computer device to perform the above-described method. For example, the non-transitory computer-readable storage medium may be a ROM, random access memory (RAM), CD-ROM, magnetic tape, floppy disk, and optical data storage device, etc. When the computer program is executed by the processor, it can implement the steps in an embodiment of a silicon wafer edge defect detection method under a special chamfering process. Specific implementation methods can be found in the method embodiments, which will not be repeated here.

[0059] Those skilled in the art will understand that embodiments of the present invention can provide methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0060] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, as well as combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0061] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0062] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0063] It should be noted that the specific embodiments described above enable those skilled in the art to more fully understand the present invention, but do not limit the present invention in any way. Therefore, although the present invention has been described in detail in this specification and embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the present invention; and all technical solutions and improvements that do not depart from the spirit and scope of the present invention are covered within the protection scope of the present invention patent. No reference numerals in the claims should be construed as limiting the scope of the claims. Any simple variations or equivalent substitutions of technical solutions that can be readily obtained by those skilled in the art within the scope of the technology disclosed in the present invention are within the protection scope of the present invention.

Claims

1. A method for detecting edge defects in silicon wafers under a special chamfering process, characterized in that, Includes the following steps: Obtain the edge image of the beveled silicon wafer; perform layer-by-layer convolution on the edge image to extract target contour features, and use grouped convolution to capture local detail features in the target contour features; perform global average pooling and activation function calculation on the local detail features to obtain the defect probability; and filter out defective images from the edge image of the silicon wafer based on the defect probability. Extract the edge texture features of the image containing the defect; The extracted edge texture features are weighted by multi-channel dynamic convolution kernels, the weighted multi-channel features are fused, and the fused feature information is spatially enhanced to obtain the enhanced target features. Regression calculations are performed based on the enhanced target features to output defect bounding boxes.

2. The method for detecting silicon wafer edge defects under a special chamfering process according to claim 1, characterized in that, The cropped images are processed using a lightweight residual binary classification neural network model to filter out defective images. Specifically, the lightweight residual binary classification neural network model uses a ResNet34 residual network as the backbone network and introduces an EMA mechanism to capture local detail features in the target contour features through grouped convolutions. The first traditional convolution in ResNet34 is replaced by a DP convolution, and the second traditional convolution in ResNet34 is replaced by a GS convolution.

3. The method for detecting silicon wafer edge defects under a special chamfering process according to claim 1, characterized in that, The SiED-YOLO object detection network is used to process images with defects to obtain defect bounding boxes. Specifically, the SiED-YOLO object detection network is based on the YOLO network architecture and introduces a dual-axis attention mechanism (DAA) module after convolution. This module is used to perform multi-channel dynamic convolution kernel weighting on the extracted edge texture features and to fuse the weighted multi-channel features. The receptive field is adaptively adjusted using the learnable convolution kernel of the DyC-C2f module to optimize the multi-scale feature response.

4. The method for detecting silicon wafer edge defects under a special chamfering process according to claim 3, characterized in that, When training the SiED-YOLO object detection network, the Inner-IoU loss function is used to calculate the model error, and the model parameters are adjusted according to the error; the Inner-IoU loss function sets a scale adjustment factor to control the scaling ratio of the auxiliary bounding box.

5. The method for detecting silicon wafer edge defects under a special chamfering process according to claim 1, characterized in that, Specifically, the acquisition of the edge image of the beveled silicon wafer is achieved by using a dual CCD line array camera, in conjunction with a ring light source, to acquire the elongated edge image of the upper and lower beveled arc surfaces of the silicon wafer after the secondary bevel.

6. The method for detecting silicon wafer edge defects under a special chamfering process according to claim 1, characterized in that, The defect bounding box includes the defect's location, size, category probability, and detection confidence.

7. A silicon wafer edge defect detection system under a special chamfering process, characterized in that, include: An image classification module is used to acquire the edge image of the beveled silicon wafer; to extract target contour features by performing layer-by-layer convolution on the edge image of the silicon wafer, and to capture local detail features in the target contour features by using grouped convolution; to calculate the defect probability by performing global average pooling and activation function on the local detail features; and to filter out defective images in the edge image of the silicon wafer based on the defect probability. The defect detection module is used to extract the edge texture features of the image of the defect; The extracted edge texture features are weighted by multi-channel dynamic convolution kernels, the weighted multi-channel features are fused, and the fused feature information is spatially enhanced to obtain the enhanced target features. Regression calculations are performed based on the enhanced target features to output defect bounding boxes.

8. A computer device, comprising a memory, a processor, and a computer program stored in the memory, characterized in that, The processor executes the computer program to implement the steps of the method according to any one of claims 1 to 6.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is loaded by the processor, it is able to perform the steps of the method according to any one of claims 1 to 6.

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