A multi-layer circuit board quality inspection method and system based on machine learning

Abstract

The application discloses a kind of based on machine learning multilayer circuit board quality inspection method and system, method includes: using adaptive weighted fusion algorithm to the multi-source data of collection carries out space-time registration, generates and contains line topological structure and material characteristic multimodal quality inspection dataset;Based on multimodal quality inspection dataset, using pre-trained nested attention deep learning model, output fused circuit board defect sensitive feature vector set;Defect sensitive feature vector set is inputted into twin network architecture, and potential defect area is positioned by dynamic anchor frame generation mechanism, and the defect type is classified with Bayes probability model Multi-label, simultaneously introduce defect severity evaluation module Quantifies the degree of influence of defect on circuit performance, output includes defect location type and severity Detection result.Utilize the embodiment of the application, can realize the collaborative determination of defect type, position and severity, improve the detection precision and generalization ability of multilayer circuit board defect.

Description

Technical Field

[0001] This invention belongs to the field of machine learning technology, specifically a machine learning-based method and system for quality inspection of multilayer circuit boards. Background Technology

[0002] As electronic devices become increasingly dense and miniaturized, the manufacturing process of multilayer circuit boards is becoming more complex. Traditional manual visual inspection or single optical inspection methods are no longer sufficient to meet the demands of high-precision quality inspection. While existing technologies such as X-ray tomography and infrared thermography can detect some inner-layer defects, they suffer from insufficient resolution and an inability to correlate material properties with morphological data. Furthermore, convolutional neural network-based algorithms primarily focus on surface defect identification, lacking the ability to comprehensively analyze interlayer anomalies and three-dimensional morphology. In addition, conventional inspection systems suffer from high false detection rates due to multi-source data registration errors and limited feature extraction, particularly lacking sensitivity to hidden defects such as microcracks and poor solder joints. Summary of the Invention

[0003] The purpose of this invention is to provide a machine learning-based method and system for quality inspection of multilayer circuit boards, in order to overcome the shortcomings of the prior art, and to achieve collaborative determination of defect type, location and severity, thereby improving the detection accuracy and generalization ability of defects in multilayer circuit boards.

[0004] One embodiment of this application provides a machine learning-based quality inspection method for multilayer circuit boards, the method comprising:

[0005] The surface and inner cross-sectional image sequences of multilayer circuit boards are acquired by a multispectral imaging system, and three-dimensional morphology data of the circuit are acquired by laser confocal scanning. The multi-source data are spatiotemporally registered using an adaptive weighted fusion algorithm to generate a multimodal quality inspection dataset containing circuit topology and material properties.

[0006] Based on the multimodal quality inspection dataset, a pre-trained nested attention deep learning model is used to extract the gradient of the circuit edge and the geometric features of the pad through the bottom branch, and capture the infrared spectral response of the interlayer dielectric layer defects through the high-level branch. The feature pyramid network is used to achieve cross-scale feature fusion and output the fused circuit board defect sensitive feature vector set.

[0007] The defect-sensitive feature vector set is input into the Siamese network architecture. Potential defect regions are located through a dynamic anchor box generation mechanism. The defect type is classified by multiple labels using a Bayesian probability model. At the same time, a defect severity assessment module is introduced to quantify the impact of defects on circuit performance. The output includes the detection results containing the defect location, type, and severity.

[0008] Optionally, the step involves acquiring surface and inner layer cross-sectional image sequences of multilayer circuit boards using a multispectral imaging system, combining this with laser confocal scanning to acquire three-dimensional topographic data of the circuit, and using an adaptive weighted fusion algorithm to perform spatiotemporal registration of the acquired multi-source data to generate a multimodal quality inspection dataset containing circuit topology and material properties, including:

[0009] Using a multispectral imaging system with a ring light source array, cross-sectional images of the surface and inner layers of a multilayer circuit board are simultaneously acquired from multiple angles. At the same time, a laser confocal scanning module acquires three-dimensional topographic data along the circuit path. The positioning holes on the edge of the circuit board are used as initial markers to generate raw data sets with angle markings.

[0010] Multi-angle imaging features of the positioning holes are extracted from the original data set, and their spatial coordinates are calculated by triangulation. Based on this, a spatial transformation matrix between multispectral images and three-dimensional topography data is established to form a spatial correlation template.

[0011] Based on spatial association templates, the occurrence time sequence of line features in images from different angles is compared. Linear interpolation is used to correct time deviations, and multi-source data are aligned to the same spatiotemporal coordinate system to obtain a spatiotemporal calibration dataset.

[0012] Based on the difference in the number of layers of the circuit board, different weights are assigned to the surface and inner layer data in the spatiotemporal calibration dataset. A multimodal quality inspection dataset containing circuit topology and material properties is generated through pixel-level fusion. The weight of the inner layer data increases proportionally with the number of layers.

[0013] Optionally, based on the multimodal quality inspection dataset, a pre-trained nested attention deep learning model is used to extract the gradient of the circuit edge and the geometric features of the pads through the lower-level branches, and to capture the infrared spectral response of defects in the interlayer dielectric layer through the higher-level branches. A feature pyramid network is then used to achieve cross-scale feature fusion, outputting a fused set of circuit board defect-sensitive feature vectors, including:

[0014] Using the low-level branch of a pre-trained nested attention model, the baseline grid lines on the circuit board are identified. A local coordinate system is established with the grid intersection as the origin. The gradient of the circuit edge and the geometric parameters of the pads in this coordinate system are extracted to generate a low-level feature map with coordinate labels.

[0015] By using the high-level branch of the nested attention model, the infrared spectrum of the interlayer medium is focused. By comparing the spectral reflectance differences of different layers at the same location, abnormal reflection regions are captured. The spectral characteristics of the abnormal reflection regions are converted into heat maps to generate high-level difference feature maps.

[0016] By using a feature pyramid network to map the coordinate information of the lower-level feature map to the higher-level differential feature map, features of different scales are associated with the same local coordinate system. Cross-scale feature fusion is achieved through coordinate matching, generating a fused feature map with spatial labels.

[0017] Feature points that deviate from the design coordinates are selected from the fused feature map. These feature points are key pixels at line corners, pad edges, and abnormal reflection areas of interlayer dielectric layers. The comprehensive features of these feature points, including geometric shape parameters, spectral reflectance, and coordinate offset, are combined to generate a circuit board defect sensitive feature vector set.

[0018] Optionally, the defect-sensitive feature vector set is input into the Siamese network architecture, potential defect regions are located through a dynamic anchor box generation mechanism, and multi-label classification of defect types is performed using a Bayesian probability model. Simultaneously, a defect severity assessment module is introduced to quantify the impact of defects on circuit performance, and the detection results, including defect location, type, and severity, are output, including:

[0019] Using a twin network architecture, the defect-sensitive feature vector set is first differentially analyzed with the feature vector of the defect-free template to obtain the feature difference value. The dynamic anchor box generates candidate boxes based on the distribution range of the difference value. The edges of the boxes fit the line direction, and the candidate regions with direction markings are output.

[0020] The feature vectors of the candidate regions are combined with the wiring rule base of the circuit board to perform Bayesian probability calculation. The rule base contains the defect probability distribution of different circuit types to generate a probability ranking of defect types, thus obtaining a type probability table.

[0021] Based on the signal transmission frequency of the line where the candidate area is located, the defect size is converted into an impact value on signal attenuation, and the impact value is divided into three levels: minor, moderate and severe, to generate a severity label.

[0022] The candidate region's direction markers, type probability tables, and severity labels are associated to remove defects that are repeatedly marked on the same line, generating detection results that include the defect's location, type, and severity. The location information includes a description of the line's direction.

[0023] Another embodiment of this application provides a machine learning-based multilayer circuit board quality inspection system, the system comprising:

[0024] The registration module is used to acquire surface and inner layer cross-sectional image sequences of multilayer circuit boards through a multispectral imaging system, combine laser confocal scanning to acquire three-dimensional topographic data of the circuit, and use an adaptive weighted fusion algorithm to perform spatiotemporal registration of the acquired multi-source data to generate a multimodal quality inspection dataset containing circuit topology and material properties.

[0025] The extraction module is used to extract the gradient of the circuit edge and the geometric features of the pad through the bottom branch, based on the multimodal quality inspection dataset and using a pre-trained nested attention deep learning model. The higher branch captures the infrared spectral response of the interlayer dielectric layer defects, and the feature pyramid network is used to achieve cross-scale feature fusion, outputting the fused circuit board defect sensitive feature vector set.

[0026] The detection module is used to input the defect-sensitive feature vector set into the Siamese network architecture, locate potential defect regions through a dynamic anchor box generation mechanism, perform multi-label classification of defect types by combining a Bayesian probability model, and simultaneously introduce a defect severity assessment module to quantify the impact of defects on circuit performance, and output detection results including defect location, type and severity.

[0027] Another embodiment of this application provides a storage medium storing a computer program, wherein the computer program is configured to execute the method described in any of the preceding claims when running.

[0028] Another embodiment of this application provides an electronic device including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the method described in any of the preceding claims.

[0029] Compared with existing technologies, this invention provides a machine learning-based quality inspection method for multilayer circuit boards. It utilizes an adaptive weighted fusion algorithm to perform spatiotemporal registration on collected multi-source data, generating a multimodal quality inspection dataset containing circuit topology and material properties. Based on this multimodal dataset, a pre-trained nested attention deep learning model is used to output a fused set of circuit board defect-sensitive feature vectors. This set is then input into a Siamese network architecture, where a dynamic anchor box generation mechanism locates potential defect regions. A Bayesian probability model is combined to perform multi-label classification of defect types, and a defect severity assessment module is simultaneously introduced to quantify the impact of defects on circuit performance. The output includes detection results containing defect location, type, and severity, thereby enabling collaborative determination of defect type, location, and severity, and improving the detection accuracy and generalization ability of multilayer circuit board defects. Attached Figure Description

[0030] Figure 1 A hardware structure block diagram of a computer terminal for a machine learning-based multilayer circuit board quality inspection method provided in an embodiment of the present invention;

[0031] Figure 2 A flowchart illustrating a machine learning-based quality inspection method for multilayer circuit boards provided in an embodiment of the present invention;

[0032] Figure 3This is a schematic diagram of a multilayer circuit board quality inspection system based on machine learning, provided in an embodiment of the present invention. Detailed Implementation

[0033] The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0034] This invention first provides a machine learning-based method for quality inspection of multilayer circuit boards, which can be applied to electronic devices, such as computer terminals, specifically ordinary computers.

[0035] The following detailed explanation uses a computer terminal as an example. Figure 1 This is a hardware structure block diagram of a computer terminal for a machine learning-based multilayer circuit board quality inspection method provided in an embodiment of the present invention. Figure 1 As shown, the computer device includes a processor, memory, and network interface connected via a system bus, wherein the memory may include non-volatile storage media and internal memory.

[0036] Non-volatile storage media can store operating systems and computer programs. These computer programs include program instructions that, when executed, cause the processor to perform any machine learning-based multilayer circuit board quality inspection method.

[0037] The processor provides computing and control capabilities, supporting the operation of the entire computer device.

[0038] Internal memory provides an environment for the execution of computer programs in non-volatile storage media. When the computer program is executed by the processor, it enables the processor to perform any machine learning-based multilayer circuit board quality inspection method.

[0039] This network interface is used for network communication, such as sending assigned tasks. Those skilled in the art will understand that... Figure 1 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0040] It should be understood that the processor can be a Central Processing Unit (CPU), but it can also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Among these, a general-purpose processor can be a microprocessor or any conventional processor.

[0041] See Figure 2 The present invention provides a machine learning-based method for quality inspection of multilayer circuit boards, which may include the following steps:

[0042] S201 acquires surface and inner layer cross-sectional image sequences of multilayer circuit boards through a multispectral imaging system, combines laser confocal scanning to acquire three-dimensional topographic data of the circuit, and uses an adaptive weighted fusion algorithm to perform spatiotemporal registration of the acquired multi-source data to generate a multimodal quality inspection dataset containing circuit topology and material properties.

[0043] Specifically, a multispectral imaging system can be used with a ring light source array to simultaneously acquire cross-sectional images of the surface and inner layers of a multilayer circuit board from multiple angles. At the same time, a laser confocal scanning module acquires three-dimensional topographic data along the circuit path. The positioning holes on the edge of the circuit board are used as initial markers to generate raw data sets with angle markings.

[0044] Multi-angle synchronous acquisition and control

[0045] The multispectral imaging system is equipped with a ring light source array (composed of 12 independently controlled LED light strips, each covering a 30-degree ring area). Each light source can emit a specific wavelength of spectrum (such as ultraviolet 365nm, visible light 550nm, and infrared 850nm). During acquisition, the system drives all light sources to synchronously illuminate the circuit board surface in pulse mode (Pulse Width = 10ms, Duty Cycle = 50%). At the same time, six high-resolution CCD cameras (Resolution = 2048×2048 pixels) surround the circuit board at 60-degree intervals, capturing multispectral images of the surface and inner cross-sections (exposed through pre-cut observation windows) at a rate of 5 frames per second (Frame Rate = 5fps). The Laser Confocal Module (LCM) is equipped with a 532nm green laser source. A Galvo Mirror system controls the beam to move along a preset trace path at a speed of 0.1mm / s, achieving a scanning depth resolution of 0.5μm and generating point cloud data (Point Cloud Density = 1000 points / mm) containing height information. 2 All devices ensure time alignment via a Sync Trigger (ST), with an error of less than 1ms.

[0046] Positioning hole markings and data identification

[0047] The positioning holes (2.0mm ± 0.05mm in diameter) at the four corners of the circuit board serve as spatial references. During acquisition, each frame of image and scan data is embedded with an angle identifier (Angle ID, AID) and a timestamp (Timestamp, TS). The AID records the azimuth angle of the camera / laser head (e.g., Camera_30°, Laser_120°), and the TS marks the acquisition start time with microsecond-level precision (μs-level). The raw data is stored as a structured array, containing: a multispectral image group (including AID, TS, and wavelength parameters), a 3D topographic point cloud (including TS and coordinates XYZ), and the pixel coordinates (Pixel_X, Pixel_Y) of the positioning holes in each image.

[0048] Data preprocessing and validation

[0049] The system automatically verifies the integrity of the positioning holes in each image frame: if the contrast of the hole edge is lower than the threshold (ContrastThreshold = 0.3), a re-image is triggered; if the point density of the positioning hole area in the laser scan point cloud is insufficient (DensityThreshold = 800 points / mm), a re-image is triggered. 2If the scan fails, the scan will be automatically re-scanned. After passing the scan, the data is packaged into raw data groups with angle tags (RDG-AT) and stored in the cache (Buffer Size = 128GB).

[0050] Multi-angle imaging features of the positioning holes are extracted from the original data set, and their spatial coordinates are calculated by triangulation. Based on this, a spatial transformation matrix between multispectral images and three-dimensional topography data is established to form a spatial correlation template.

[0051] Positioning Hole Feature Extraction

[0052] A subset of multispectral images with the same timestamp (TS error < 1ms) was selected from RDG-AT. For each positioning hole image, the Canny edge detection algorithm (parameters: Gaussian kernel σ = 1.0, high / low threshold ratio 1:2) was used to extract the hole contour, and then the center pixel coordinates (Center_X, Center_Y) and aspect ratio (AR) were calculated using Least Squares Ellipse Fitting. Simultaneously, a 3D point set of the positioning hole region was extracted from the laser point cloud, and a cylindrical model was fitted using the Random Sample Consensus Algorithm (RANSAC, Iterations = 1000) to output the spatial coordinates of the hole center (3D_X, 3D_Y, 3D_Z).

[0053] Triangulation and Coordinate Mapping

[0054] Take two cameras at different angles (e.g., 30° and 150°) as an example:

[0055] Given the camera's intrinsic parameters (focal length f = 35mm, pixel size 5μm) and extrinsic parameters (mounting angle θ);

[0056] The center pixel coordinates (Pix1, Pix2) of the positioning hole from both perspectives are converted into normalized camera coordinates (NCC).

[0057] Based on the triangulation method, the intersection point of two optical rays is solved by: constructing an overdetermined system of equations and solving for the three-dimensional coordinates (Calc_X, Calc_Y, Calc_Z) using singular value decomposition (SVD).

[0058] Repeat the calculation for all viewpoint combinations and take the average coordinate as the final spatial coordinates (Final_3D).

[0059] Transformation matrix generation and template construction

[0060] Pair the multi - spectral image pixel coordinates with the Final_3D coordinates, and use Procrustes Analysis to solve for the optimal rigid body transformation (rotation matrix R, translation vector T). For example:

[0061] Input: Set of image pixel points (including AID), corresponding set of Final_3D points;

[0062] Output: Spatial transformation matrix (Transformation Matrix, TM) with size 4×4, including rotation components (R11~R33) and translation components (T_x, T_y, T_z).

[0063] After calculating for all positioning holes, generate a Spatial Correlation Template (SCT), and store the TM corresponding to each camera angle AID and the error tolerance (Error Tolerance = ±5μm).

[0064] Based on the spatial correlation template, compare the appearance timings of line features in images at different angles, use linear interpolation to correct the time deviation, align the multi - source data to the same spatio - temporal coordinate system, and obtain a spatio - temporal calibration data set;

[0065] Timing deviation detection

[0066] Select high - contrast feature points on the circuit board (such as the edge of the pad) as timing markers. Select a reference perspective (such as AID = 0°) in the SCT, and extract the timestamp (Ref_TS) of the appearance of the feature points in the image of this perspective. For other perspectives (such as AID = 60°), search for similar features near the same physical location (using Scale - Invariant Feature Transform (SIFT) descriptor matching), and record its timestamp (Comp_TS). Calculate the timing deviation (Time Offset, TO = Comp_TS - Ref_TS), and if |TO|>2ms, it is determined that there is a significant deviation.

[0067] Linear interpolation correction

[0068] For the data stream with deviation (such as the laser scan point cloud), use the reference timing as the benchmark:

[0069] Let the timestamp of a certain laser point be L_TS, and its theoretical alignment time should be L_TS - TO.

[0070] If there is no data point at the target time, take two adjacent frames of data (TS1, TS2 and TS1 < L_TS - TO < TS2), and linearly interpolate the point cloud coordinates according to the weight ratio (Weight Ratio, WR=(L_TS - TO - TS1) / (TS2 - TS1)):

[0071] Interp_X = X1 + WR × (X2 - X1);

[0072] Interp_Y = Y1 + WR × (Y2 - Y1);

[0073] Interp_Z = Z1 + WR × (Z2 - Z1);

[0074] Interpolation generates a time-aligned point cloud.

[0075] Spacetime coordinate system integration

[0076] The corrected multispectral image (pixel coordinates + timestamp) is transformed into three-dimensional space using TM in SCT:

[0077] Input: pixel coordinates (Pix_X, Pix_Y), timestamp TS, corresponding TM.

[0078] Output: Spatial coordinates (Space_X, Space_Y, Space_Z) and attributes (spectral values, timestamp).

[0079] The laser point cloud is directly used as the Aligned Point Cloud. The final result is a Spatiotemporal Calibrated Dataset (SCD), in which each data point contains: spatial coordinates, timestamp, spectral intensity / height value, and data source identifier (Image / Laser).

[0080] Based on the difference in the number of layers of the circuit board, different weights are assigned to the surface and inner layer data in the spatiotemporal calibration dataset. A multimodal quality inspection dataset containing circuit topology and material properties is generated through pixel-level fusion. The weight of the inner layer data increases proportionally with the number of layers.

[0081] Layer depth weight allocation strategy

[0082] Define the relationship between the weight coefficient (WC) and the layer number (LN):

[0083] Surface layer (LN=0): WC0=0.3;

[0084] Inner layer 1 (LN=1): WC1=0.3+0.1×1=0.4;

[0085] Second inner layer (LN=2): WC2=0.3+0.1×2=0.5; ...

[0087] The weight values ​​are determined by the Layer Depth-Detectability Model (LDDM): the inner layer signal attenuation rate (Attenuation Rate = 0.05 dB / layer) is positively correlated with the detection error, so the weight increases linearly with the layer depth.

[0088] Pixel-level fusion algorithm

[0089] Rasterize the image data in the SCD into a uniform grid (Grid Size = 10μm × 10μm):

[0090] Spectral data fusion: For all multispectral pixels within the grid, calculate the weighted mean (WeightedMean) by wavelength grouping: Fused_Spectralλ=Σ(WC I ×Spectral_Intensityλ) / ΣWC I .

[0091] Topographic data fusion: The height values ​​of the laser point cloud are weighted and the median is used to suppress outliers.

[0092] After fusion, each grid cell contains: spectral intensity values ​​for 6 bands (λ=365 / 450 / 550 / 650 / 850 / 1050nm), average height value (Avg_Z), and maximum height difference (Delta_Z).

[0093] Topology and material property enhancement

[0094] Line topology: Based on the grid with a height difference Delta_Z>8μm, the line area is marked and a binary topology map is generated.

[0095] Material properties: Reflectivity ratio in the infrared band (850 / 1050nm) (Ratio_IR = Intensity) 1050 / Intensity 850 Identification materials: FR4 epoxy resin: Ratio_IR<0.7; copper layer: Ratio_IR>1.3.

[0096] Defect-sensitive channel: The intensity of the ultraviolet band (365nm) is multiplied by the height gradient (|ΔZ / ΔXY|) to generate the defect-enhanced channel (DEC).

[0097] The final output is a multimodal quality dataset (MQD), which includes: a fused spectral cube, a topology map, a material classification map, and a defect enhancement map.

[0098] S202, based on the multimodal quality inspection dataset, a pre-trained nested attention deep learning model is used to extract the gradient of the circuit edge and the geometric features of the pad through the bottom branch, and the infrared spectral response of the interlayer dielectric layer defects is captured by the high-level branch. The feature pyramid network is used to achieve cross-scale feature fusion and output the fused circuit board defect sensitive feature vector set.

[0099] Specifically, the underlying branches of a pre-trained nested attention model can be used to identify the baseline grid lines on the circuit board, establish a local coordinate system with the grid intersection as the origin, extract the gradient of the circuit edge and the geometric parameters of the pads in this coordinate system, and generate a low-level feature map with coordinate labels.

[0100] Reference mesh identification and local coordinate system construction

[0101] Multilayer circuit boards typically have reference grid lines etched on their surfaces for precise positioning. These grids consist of crisscrossing micrometer-level lines (approximately 10-20 micrometers wide). The lower branches of a pre-trained nested attention model first capture grid images using high-resolution imaging (e.g., a 50-megapixel industrial camera) and then enhance the line edges using Histogram of Oriented Gradients Enhancement (HOGE). The model identifies grid intersection points (GIPs), and the pixel coordinates of each GIP are accurate to 0.1 pixels using sub-pixel localization (SPL). Using a single GIP as the origin of the local coordinate system (LCO), a coordinate system is established with the X and Y axes parallel to the grid lines (e.g., the X-axis along the horizontal grid line direction and the Y-axis along the vertical grid line direction). This coordinate system covers a square region centered on the GIP with a side length of 1 millimeter (called a local detection unit), providing a spatial reference for subsequent feature extraction.

[0102] Extraction of line edge gradient and pad geometry parameters

[0103] Within the local coordinate system, the bottom-level branch performs gradient field analysis (GFA) on the line edges. First, the Sobel operator is used to calculate the gradient magnitude (GM) and direction (GD) of each pixel, and pixels with GM exceeding a threshold (e.g., 150 grayscale value) are selected as candidate edge points. The edges are refined to a single pixel width using a non-maximum suppression (NMS) algorithm, and then a Hough transform (HT) is used to fit line segments, recording the start / end coordinates (based on the local coordinate system), length, and angle (angle with the X-axis) of each line segment. For the pad area (typically 100-500 micrometers in diameter), the model uses an ellipse fitting (EF) algorithm to calculate the pad center coordinates, major / minor axis lengths, eccentricity, and edge smoothness index (SI). All parameters are bound to the local coordinate system origin coordinates (e.g., GIP-23 coordinates: X = 1.2mm, Y = 3.5mm).

[0104] Low-level feature map generation and coordinate labeling

[0105] The extracted geometric parameters are organized into structured data by local detection units: each unit contains a local coordinate system origin (GIP coordinates), multiple line edge records (each containing start coordinates, end coordinates, length, and angle), and multiple pad records (each containing center coordinates, major axis, minor axis, and eccentricity). This data is encoded into a bottom-layer feature map (BFM), whose data structure is a multidimensional tensor. For example, the feature vector of a local detection unit can be represented as: [GIP_X, GIP_Y, Edge1_StartX, Edge1_StartY, Edge1_Length,..., Pad1_CenterX, Pad1_CenterY, Pad1_MajorAxis,...]. The feature map covers the entire circuit board surface, and adjacent units share edge data to ensure continuity.

[0106] By using the high-level branch of the nested attention model, the infrared spectrum of the interlayer medium is focused. By comparing the spectral reflectance differences of different layers at the same location, abnormal reflection regions are captured. The spectral characteristics of the abnormal reflection regions are converted into heat maps to generate high-level difference feature maps.

[0107] Interlayer dielectric layer infrared spectral acquisition and alignment

[0108] The higher-level branch processes inner-layer data (e.g., 8-12 layer plates) from a multispectral imaging system (MIS). The system scans the inter-layer dielectric (ILD) in the near-infrared band (wavelength 900-1700 nm), acquiring spectral reflectance curves (SRCs) at the same physical location in each layer (ensuring this through spatiotemporal registration). Each SRC contains 200 sampling points (wavelength intervals of 4 nm), recording the reflectance value (RV, ranging from 0-100%). The model uses a spectral registration (SRG) algorithm to align the SRCs of different layers at the same location along the wavelength dimension (eliminating device drift errors) to ensure data comparability.

[0109] Detection of anomalous reflectance regions and quantification of spectral differences

[0110] Cross-layer reflectance comparison (CRC) is performed on the registered SRC: the reflectance difference (RD) between two adjacent layers (e.g., L3 and L4) at the same wavelength is calculated. If the percentage of wavelengths where the RD continuously exceeds a threshold (e.g., ±5%) at a certain location exceeds 30%, it is marked as an anomalous reflectance zone (ARZ). For each ARZ, its spectral characteristics are extracted, including the maximum reflectance difference (Max RD), the peak wavelength (PW), and the curvature variation (CV) of the reflectance curve. For example, bubble defects in the dielectric layer show a significant increase in RD at a specific wavelength (e.g., 1200 nm).

[0111] Heatmap generation and high-level feature map construction

[0112] The spectral features of the ARZ are converted into a heatmap: using the circuit board plane coordinates as a reference, the anomaly intensity is represented by color coding. For example, the Max RD value is mapped to the red channel (0-255), the PW value to the green channel (wavelength 900 nm = 0, 1700 nm = 255), and the CV value to the blue channel. Each ARZ generates a heatmap layer (HL), and multiple layers are stacked to form a top-layer difference feature map (TDFM). This map is a three-dimensional tensor (width × height × spectral feature dimension), for example, with a size of 2000 × 1500 pixels × 3 channels (corresponding to Max RD, PW, and CV respectively).

[0113] By using a feature pyramid network to map the coordinate information of the lower-level feature map to the higher-level differential feature map, features of different scales are associated with the same local coordinate system. Cross-scale feature fusion is achieved through coordinate matching, generating a fused feature map with spatial labels.

[0114] Multi-scale coordinate mapping of feature pyramid networks

[0115] The Feature Pyramid Network (FPN) comprises three levels of resolution: original resolution (bottom layer feature map), 1 / 2 downsampling (middle layer), and 1 / 4 downsampling (higher layer). First, the origin (GIP coordinates) of the local coordinate system of the bottom layer feature map (BFM) is passed to each layer:

[0116] Original layer: directly retain GIP coordinates (e.g., GIP-23: X = 1.2mm, Y = 3.5mm);

[0117] 1 / 2 layer: Coordinates scaled proportionally (X' = 0.6mm, Y' = 1.75mm);

[0118] 1 / 4 layer: coordinate scaled to (X” = 0.3mm, Y” = 0.875mm).

[0119] The high-level difference feature map (TDFM) is upsampled to the original resolution using bilinear interpolation (BI) to align it with the size of the low-level feature map (e.g., 2000×1500 pixels).

[0120] Spatial correlation of cross-scale features

[0121] For each local detection unit (1mm × 1mm area):

[0122] Low-level features: Extract the mean edge angle (MEA) and maximum pad eccentricity (MPE) of all traces within the cell;

[0123] High-level features: Extract the Max RD mean (MMRD) and CV variance (CVV) of the corresponding location heatmap.

[0124] Features of the same unit are bound by the coordinate matching (CM) algorithm: if the GIP coordinates of the bottom unit are (X,Y), then the statistical values ​​of the circular region with a radius of 0.5mm centered at (X,Y) are extracted from the high-level feature map.

[0125] Fusion feature map generation and spatial labeling

[0126] The fused feature vectors are organized by unit: [GIP_X,GIP_Y,MEA,MPE,MMRD,CVV], for example: [1.2,3.5,45.3°,0.12,8.7%,0.05].

[0127] The feature vectors of all cells are arranged in spatial order to form a fused feature map (FFM). This map has a two-dimensional structure: the row number corresponds to the Y coordinate (1 row per millimeter), the column number corresponds to the X coordinate (1 column per millimeter), and each cell contains a 6-dimensional feature vector. Spatial labeling is implicitly implemented through row and column indexing (e.g., the coordinates of the 3rd row and 1st column correspond to Y = 3mm, X = 1mm).

[0128] Feature points that deviate from the design coordinates are selected from the fused feature map. These feature points are key pixels at line corners, pad edges, and abnormal reflection areas of interlayer dielectric layers. The comprehensive features of these feature points, including geometric shape parameters, spectral reflectance, and coordinate offset, are combined to generate a circuit board defect sensitive feature vector set.

[0129] Feature point selection and deviation calculation

[0130] Load the standard coordinates of the design blueprint (DB):

[0131] Standard coordinates of trace corner points (TCP) (e.g., X_s = 1.205mm, Y_s = 3.502mm);

[0132] The standard coordinates of the pad edge centers (PEC) (e.g., X_s = 1.198 mm, Y_s = 3.498 mm).

[0133] Calculate the offset (Coordinate Offset, CO) between the actual detected coordinates (GIP coordinates from the fused feature map) and the standard coordinates: ΔX = |X_actual - X_s|; ΔY = |Y_actual - Y_s|.

[0134] If the offset exceeds the tolerance threshold (e.g., ΔX>5 micrometers or ΔY>5 micrometers), it is marked as a deviated feature point (DFP).

[0135] Multimodal feature combination

[0136] Three types of features are extracted for each DFP:

[0137] Geometric parameters: derived from the underlying feature map (e.g., line corner angle deviation ±2°, pad eccentricity increase of 0.1);

[0138] Spectral reflectance parameters: derived from high-level feature maps (e.g., Max RD = 12.3%, CV = 0.08);

[0139] Coordinate offsets: ΔX and ΔY (e.g., ΔX = 7 micrometers, ΔY = 3 micrometers).

[0140] Combined into an Integrated Feature Vector (IFV), for example: [ΔX,ΔY,Angle_Deviation,Eccentricity_Change,Max_RD,CV]→[7,3,2,0.1,12.3,0.08].

[0141] Defect-sensitive feature vector set generation

[0142] The IFVs of all DFPs constitute a Defect-sensitive Feature Vector Set (DFVS). This set has a matrix structure: each row corresponds to a DFP (e.g., 1200 points are selected from the entire board); each column corresponds to the feature dimension (6 dimensions: ΔX, ΔY, geometric deviation ×2, spectral parameter ×2).

[0143] The vector set is sorted by spatial position (from left to right, from top to bottom) to facilitate subsequent Siamese network processing. For example, DFP number 305 is located at Y = 15.2 mm, X = 22.7 mm, and its feature vector is [5, 2, 1.5, 0.08, 9.1, 0.03].

[0144] S203, the defect-sensitive feature vector set is input into the Siamese network architecture, the potential defect region is located through the dynamic anchor box generation mechanism, the defect type is classified by multiple labels by combining the Bayesian probability model, the defect severity assessment module is introduced simultaneously to quantify the impact of the defect on the circuit performance, and the detection result including the defect location type and severity is output.

[0145] Specifically, the twin network architecture can be used to first perform a difference operation between the defect-sensitive feature vector set and the feature vector of the defect-free template to obtain the feature difference value. The dynamic anchor box generates candidate boxes based on the distribution range of the difference value. The edges of the boxes fit the line direction, and the candidate regions with direction markings are output.

[0146] The Siamese Network Architecture consists of two parallel sub-networks with identical structures and shared parameters. The left sub-network takes into account the Defect-Sensitive Feature Vector Set (DSFVS) of the current inspection board, containing the geometric parameters of each feature point (e.g., edge curvature, pad roundness), spectral reflectance (e.g., infrared reflectance intensity), and coordinate offset (e.g., X / Y axis deviation). The right sub-network takes into account the feature vectors of a defect-free sample (Golden Sample, GS) of the same model at the same coordinate points. The system compares the two sets of vectors point-by-point using Difference Calculation (DC): for pad edge points, it calculates the Radius Difference Value (RDV); for dielectric layer feature points, it calculates the Reflectance Deviation Value (RDV). If the RDV of a point exceeds a preset threshold (e.g., 15%), it is marked as a Significant Difference Point (SDP). All SDPs constitute a Feature Difference Value Set (FDVS), whose spatial distribution reveals clusters of potential defects.

[0147] The Dynamic Anchor Frame Generation (DAFG) mechanism operates based on the spatial density distribution of FDVS. First, a kernel density estimation (KDE) algorithm is used to calculate the probability density field of the difference values ​​on the circuit board surface: a Gaussian kernel (GK) is generated centered on each SDP, with an initial kernel radius (KR) of 0.1 mm and a standard deviation (SD) of 0.05 mm. Density peak regions (e.g., exceeding 50 SDPs per square millimeter) are identified as Core Anomaly Zones (CAZs). Subsequently, the anchor frame generator expands outward from the center of the CAZ, with the extension direction of the frame boundary (FB) dynamically controlled by the trace routing: the main routing angle (e.g., a 45° diagonal line or a 90° right angle) is extracted by analyzing the directional derivative (DD) of the traces surrounding the CAZ. The final generated candidate frames (CFs) are polygonal in structure, with their edges strictly parallel to the extension direction of the adjacent lines (such as generating wavy boundaries along serpentine lines). Each CF is accompanied by a direction tag (DT), such as "horizontal direction (H)" or "45° diagonal direction (D45)".

[0148] To optimize positioning accuracy, the system introduces a hierarchical validation strategy (HVS). Level 1 validation: Calculate the Spatial Consistency Index (SCI) of the SDP within the CF (Cross-Frame). If the SCI is below a threshold (e.g., 0.7), the CF is split into multiple sub-frames. Level 2 validation: Analyze the geometric deformation of the lines within the CF using a Lissajous Pattern Matcher (LPM), comparing the curvature changes of lines at the same location in a defect-free template. For example, when detecting via offset, the LPM matches the elliptical trajectory formed by the center points of the via group; if the trajectory distortion exceeds 5 micrometers, it is confirmed as a valid candidate frame. The final output is a Direction-Tagged Candidate Region (DTCR), where each region contains: 1) polygon vertex coordinates; 2) main line direction label; and 3) internal SDP density value (unit: points / square millimeter).

[0149] The feature vectors of the candidate regions are combined with the wiring rule base of the circuit board to perform Bayesian probability calculation. The rule base contains the defect probability distribution of different circuit types to generate a probability ranking of defect types, thus obtaining a type probability table.

[0150] The Wiring Rule Library (WRL) stores topology constraints and historical defect data for multilayer circuit boards. Its structure consists of three layers:

[0151] Physical layer rules: Record line width / spacing design values ​​(e.g., signal line width 100 micrometers, minimum spacing 50 micrometers), pad diameter standards (e.g., standard pad 200 micrometers, BGA pad 150 micrometers);

[0152] Electrical layer rules: Define high-frequency signal paths (such as differential pairs > 5 GHz) and power plane partitions (such as separating the 12V power area from the 3.3V logic area);

[0153] The Defect Probability Distribution Table (DPDT) statistically analyzes the prior probability of faults for different line types. For example, the short probability (SP) of a differential pair is 0.12%, and the Kelvin defect probability (KDP) of the power plane is 0.08%.

[0154] Bayesian Probability Calculation (BPC) uses the feature vectors of candidate regions as input evidence (E). Taking the detection of "cold solder pads" as an example:

[0155] Extract evidence E: Pad edge gradient change value (Edge Gradient Delta, EGD = 0.35) and infrared reflectance shift (IRS = 12%).

[0156] Query the prior probability P(H): Obtain the probability of this type of pad being a cold solder joint in the power area from the DPDT (P(H) = 0.15);

[0157] Calculate the likelihood P(E|H): Based on historical data, when EGD>0.3 and IRS>10%, the likelihood of the cold solder joint hypothesis being true is 0.92;

[0158] The output posterior probability P(H|E) is calculated using Bayes' formula P(H|E)=[P(E|H)×P(H)] / P(E) and is 0.78.

[0159] The system performs multi-label classification (MLC) on each candidate region and simultaneously calculates the posterior probabilities of six core defect types:

[0160] Open circuit (OC); Short circuit (SC); Dielectric void (DV); Pad detachment (PD); Copper crack (CC); Ionic contamination (IC).

[0161] Output a Type Probability Table (TPT), formatted as ordered triples: [defect type, probability value, confidence factor]. For example, the TPT for a certain region is: [(SC, 0.63, 0.89), (DV, 0.21, 0.75), (OC, 0.08, 0.65)].

[0162] The confidence factor (CF) is determined by the completeness of the feature vector (e.g., CF = 0.9 when it contains three types of features: spectral, geometric, and coordinate, and CF = 0.6 when it contains only two types).

[0163] Based on the signal transmission frequency of the line where the candidate area is located, the defect size is converted into an impact value on signal attenuation, and the impact value is divided into three levels: minor, moderate and severe, to generate a severity label.

[0164] The Signal Frequency Mapping (SFM) module establishes a path-frequency mapping table based on the circuit board design documents:

[0165] High-speed signal lines: Marked with frequency values ​​(e.g., 8GHz for PCIe channels, 6.4GHz for DDR5 data lines);

[0166] Power supply path: equivalent to DC 0Hz, but transient response frequency needs to be considered (usually treated as 1MHz);

[0167] Standard I / O lines: uniformly classified as low-frequency group (≤100MHz).

[0168] Each candidate region is associated with the frequency tag (FT) of its corresponding line through coordinate matching, such as "High Frequency (HF)", "Medium Frequency (MF)" or "Low Frequency (LF)".

[0169] The Defect Impact Quantization Model (DIQM) converts physical defect parameters into electrical performance degradation values.

[0170] Size conversion: For short-circuit defects (SC), calculate the equivalent short length (ESL). For example, for a copper slag bridging between two adjacent differential lines, if the bridging width is 30 micrometers and the thickness is 18 micrometers, then the ESL = 45 micrometers.

[0171] Frequency weighting: Attenuation factor formula (AFF) is used: Attenuation value (dB) = K_f × (defect size)^P_f. Wherein, for high-frequency paths (>5GHz), the coefficient K_f = 2.5 and the exponent P_f = 1.2; for low-frequency paths, K_f = 0.8 and P_f = 1.0. Example: For a short-circuit defect with ESL = 45 micrometers on a high-frequency line, the attenuation value = 2.5 × (45)^1.2 ≈ 2.5 × 98.5 = 246.25 dB.

[0172] Three-Level Severity Classification (TLSC) Rules:

[0173] Minor: Attenuation value ≤3dB (e.g., a crack <100 micrometers in a low-frequency line);

[0174] Moderate: 3dB < attenuation value ≤ 10dB (e.g., a 50-micron diameter hole in the intermediate frequency power supply plane);

[0175] Critical: Attenuation value >10dB (e.g., >30 micrometer bridging between high-frequency differential pairs).

[0176] The final result is a severity label (SL), formatted as [level:quantification value]. For example: "Severity: 12.4dB".

[0177] The candidate region's direction markers, type probability tables, and severity labels are associated to remove defects that are repeatedly marked on the same line, generating detection results that include the defect's location, type, and severity. The location information includes a description of the line's direction.

[0178] The Multi-Dimension Association Engine (MDAE) performs three-source data fusion:

[0179] Extract the orientation markers (e.g., "Pad array area - radial orientation (R)") from the DTCR;

[0180] Extract the highest probability defect type from TPT (e.g., short circuit with a probability of 0.63);

[0181] Extract the severity level from SL (e.g., "Severe: 12.4dB").

[0182] Association rule: If multiple high-probability defects exist in the same candidate region (such as short circuit probability 0.63, medium void probability 0.21), only the type with a probability greater than 0.6 is retained; if all are less than 0.6, they are marked as "composite defects".

[0183] The Redundant Annotation Elimination Algorithm (RAEA) addresses the problem of the same physical defect being covered by multiple candidate bounding boxes.

[0184] Spatial overlap detection: Calculate the IoU (Intersection over Union) value of the candidate boxes. If the IoU of two boxes is greater than 0.65, they are considered duplicate annotations.

[0185] Feature similarity comparison: Cosine similarity (CS) is calculated for feature vectors within overlapping boxes. If CS > 0.85, the same defect is confirmed.

[0186] Preferred selection rule: retain the label with the highest severity (e.g., "severe" is better than "moderate"); if the severity is the same, take the label with the highest probability value.

[0187] The Location Descriptor Generator (LDG) transforms coordinate data into an engineering-readable Circuit Path Description (CPD): it locates the coordinates (X, Y) of the Defect CenterPoint (DCP) and matches the circuit path in the design file that is closest to the DCP (such as "address line A5 from U12 chip to R34 resistor").

[0188] Additional relative position description:

[0189] Straight path: Label the percentage from the starting point (e.g., "path midpoint + 15%)".

[0190] Curved path: Use key inflection point references (such as "on the outside of the third bend").

[0191] The final output is a structured inspection result (IR). For example, each record contains: [Location] U12-A5 address line (45% from the starting point); [Type] Short circuit (probability 0.63); [Severity] Severe (12.4dB); [Route] Horizontal serpentine trace.

[0192] As can be seen, by using an adaptive weighted fusion algorithm to perform spatiotemporal registration on the collected multi-source data, a multimodal quality inspection dataset containing circuit topology and material properties is generated. Based on the multimodal quality inspection dataset, a pre-trained nested attention deep learning model is used to output a fused circuit board defect-sensitive feature vector set. The defect-sensitive feature vector set is input into a Siamese network architecture, and potential defect regions are located through a dynamic anchor box generation mechanism. A Bayesian probability model is combined to perform multi-label classification of defect types. Simultaneously, a defect severity assessment module is introduced to quantify the impact of defects on circuit performance. The output includes detection results containing defect location, type, and severity, thereby enabling collaborative determination of defect type, location, and severity, and improving the detection accuracy and generalization ability of multilayer circuit board defects.

[0193] Another embodiment of the present invention provides a multilayer circuit board quality inspection system based on machine learning, see [link to relevant documentation]. Figure 3 The system may include:

[0194] The registration module 301 is used to acquire the surface and inner cross-sectional image sequence of the multilayer circuit board through the multispectral imaging system, combine the laser confocal scanning to acquire the three-dimensional topography data of the circuit, and use the adaptive weighted fusion algorithm to perform spatiotemporal registration on the acquired multi-source data to generate a multimodal quality inspection dataset containing the circuit topology and material properties.

[0195] Extraction module 302 is used to extract the gradient of the circuit edge and the geometric features of the pad through the bottom branch, and capture the infrared spectral response of the interlayer dielectric layer defects through the high-level branch based on the multimodal quality inspection dataset and the pre-trained nested attention deep learning model, and output the fused circuit board defect sensitive feature vector set.

[0196] The detection module 303 is used to input the defect-sensitive feature vector set into the Siamese network architecture, locate potential defect regions through a dynamic anchor box generation mechanism, perform multi-label classification of defect types by combining a Bayesian probability model, and simultaneously introduce a defect severity assessment module to quantify the degree of impact of defects on circuit performance, and output detection results including defect location, type and severity.

[0197] This invention also provides a storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above method embodiments when running.

[0198] Specifically, in this embodiment, the storage medium can be configured to store a computer program for performing the following steps:

[0199] S201 acquires surface and inner layer cross-sectional image sequences of multilayer circuit boards through a multispectral imaging system, combines laser confocal scanning to acquire three-dimensional topographic data of the circuit, and uses an adaptive weighted fusion algorithm to perform spatiotemporal registration of the acquired multi-source data to generate a multimodal quality inspection dataset containing circuit topology and material properties.

[0200] S202, based on the multimodal quality inspection dataset, a pre-trained nested attention deep learning model is used to extract the gradient of the circuit edge and the geometric features of the pad through the bottom branch, and the infrared spectral response of the interlayer dielectric layer defects is captured by the high-level branch. The feature pyramid network is used to achieve cross-scale feature fusion and output the fused circuit board defect sensitive feature vector set.

[0201] S203, the defect-sensitive feature vector set is input into the Siamese network architecture, the potential defect region is located through the dynamic anchor box generation mechanism, the defect type is classified by multiple labels by combining the Bayesian probability model, the defect severity assessment module is introduced simultaneously to quantify the impact of the defect on the circuit performance, and the detection result including the defect location type and severity is output.

[0202] This invention also provides an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to perform the steps in any of the above method embodiments.

[0203] Specifically, the aforementioned electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the aforementioned processor, and the input / output device is connected to the aforementioned processor.

[0204] Specifically, in this embodiment, the processor can be configured to perform the following steps via a computer program:

[0205] S201 acquires surface and inner layer cross-sectional image sequences of multilayer circuit boards through a multispectral imaging system, combines laser confocal scanning to acquire three-dimensional topographic data of the circuit, and uses an adaptive weighted fusion algorithm to perform spatiotemporal registration of the acquired multi-source data to generate a multimodal quality inspection dataset containing circuit topology and material properties.

[0206] S202, based on the multimodal quality inspection dataset, a pre-trained nested attention deep learning model is used to extract the gradient of the circuit edge and the geometric features of the pad through the bottom branch, and the infrared spectral response of the interlayer dielectric layer defects is captured by the high-level branch. The feature pyramid network is used to achieve cross-scale feature fusion and output the fused circuit board defect sensitive feature vector set.

[0207] S203, the defect-sensitive feature vector set is input into the Siamese network architecture, the potential defect region is located through the dynamic anchor box generation mechanism, the defect type is classified by multiple labels by combining the Bayesian probability model, the defect severity assessment module is introduced simultaneously to quantify the impact of the defect on the circuit performance, and the detection result including the defect location type and severity is output.

[0208] The above description, based on the embodiments shown in the figures, details the structure, features, and effects of the present invention. The above description is only a preferred embodiment of the present invention, but the present invention is not limited to the scope of implementation shown in the figures. Any changes made in accordance with the concept of the present invention, or equivalent embodiments modified to have equivalent changes, that do not exceed the spirit covered by the specification and figures, should be within the protection scope of the present invention.

Claims

1. A machine learning-based method for quality inspection of multilayer circuit boards, characterized in that, The method includes: The surface and inner cross-sectional image sequences of multilayer circuit boards are acquired by a multispectral imaging system, and three-dimensional morphology data of the circuit are acquired by laser confocal scanning. The multi-source data are spatiotemporally registered using an adaptive weighted fusion algorithm to generate a multimodal quality inspection dataset containing circuit topology and material properties. Based on the aforementioned multimodal quality inspection dataset, a pre-trained nested attention deep learning model is used. The model extracts circuit edge gradients and pad geometric features through low-level branches, while high-level branches capture the infrared spectral response of defects in the interlayer dielectric layer. A feature pyramid network is then used to achieve cross-scale feature fusion, outputting a fused set of circuit board defect-sensitive feature vectors. Specifically, the low-level branches of the pre-trained nested attention model identify baseline grid lines on the circuit board, establishing a local coordinate system with the grid intersections as the origin. Circuit edge gradients and pad geometric parameters are extracted from this coordinate system, generating a low-level feature map with coordinate labels. The high-level branches of the nested attention model focus on the infrared spectrum of the interlayer dielectric layer, comparing the same location... By setting the spectral reflectance differences between different layers, abnormal reflection areas are captured, and the spectral features of the abnormal reflection areas are converted into heat maps to generate high-level difference feature maps. A feature pyramid network is used to map the coordinate information of the bottom-level feature maps to the high-level difference feature maps, so that features of different scales are associated with the same local coordinate system. Cross-scale feature fusion is achieved through coordinate matching to generate a fused feature map with spatial labels. Feature points that deviate from the design coordinates are selected from the fused feature map. These feature points are key pixels in abnormal reflection areas of line corners, pad edges, and interlayer dielectric layers. The comprehensive features of the feature points, including geometric shape parameters, spectral reflectance, and coordinate offset, are combined to generate a circuit board defect-sensitive feature vector set. The defect-sensitive feature vector set is input into the Siamese network architecture. Potential defect regions are located through a dynamic anchor box generation mechanism. The defect type is classified by multiple labels using a Bayesian probability model. At the same time, a defect severity assessment module is introduced to quantify the impact of defects on circuit performance. The output includes the detection results containing the defect location, type, and severity.

2. The method according to claim 1, characterized in that, The process involves acquiring surface and inner layer cross-sectional image sequences of multilayer circuit boards using a multispectral imaging system, combining this with laser confocal scanning to acquire three-dimensional topographic data of the circuit, and using an adaptive weighted fusion algorithm to perform spatiotemporal registration of the acquired multi-source data to generate a multimodal quality inspection dataset containing circuit topology and material properties, including: Using a multispectral imaging system with a ring light source array, cross-sectional images of the surface and inner layers of a multilayer circuit board are simultaneously acquired from multiple angles. At the same time, a laser confocal scanning module acquires three-dimensional topographic data along the circuit path. The positioning holes on the edge of the circuit board are used as initial markers to generate raw data sets with angle markings. Multi-angle imaging features of the positioning holes are extracted from the original data set, and their spatial coordinates are calculated by triangulation. Based on this, a spatial transformation matrix between multispectral images and three-dimensional topography data is established to form a spatial correlation template. Based on spatial association templates, the occurrence time sequence of line features in images from different angles is compared. Linear interpolation is used to correct time deviations, and multi-source data are aligned to the same spatiotemporal coordinate system to obtain a spatiotemporal calibration dataset. Based on the difference in the number of layers of the circuit board, different weights are assigned to the surface and inner layer data in the spatiotemporal calibration dataset. A multimodal quality inspection dataset containing circuit topology and material properties is generated through pixel-level fusion. The weight of the inner layer data increases proportionally with the number of layers.

3. The method according to claim 2, characterized in that, The defect-sensitive feature vector set is input into the Siamese network architecture. Potential defect regions are located through a dynamic anchor box generation mechanism. A Bayesian probability model is used for multi-label classification of defect types. Simultaneously, a defect severity assessment module is introduced to quantify the impact of defects on circuit performance. The output includes detection results containing defect location, type, and severity, including: Using a twin network architecture, the defect-sensitive feature vector set is first differentially analyzed with the feature vector of the defect-free template to obtain the feature difference value. The dynamic anchor box generates candidate boxes based on the distribution range of the difference value. The edges of the boxes fit the line direction, and the candidate regions with direction markings are output. The feature vectors of the candidate regions are combined with the wiring rule base of the circuit board to perform Bayesian probability calculation. The rule base contains the defect probability distribution of different circuit types to generate a probability ranking of defect types, thus obtaining a type probability table. Based on the signal transmission frequency of the line where the candidate area is located, the defect size is converted into an impact value on signal attenuation, and the impact value is divided into three levels: minor, moderate and severe, to generate a severity label. The candidate region's direction markers, type probability tables, and severity labels are associated to remove defects that are repeatedly marked on the same line, generating detection results that include the defect's location, type, and severity. The location information includes a description of the line's direction.

4. A multilayer circuit board quality inspection system based on machine learning, characterized in that, The system includes: The registration module is used to acquire surface and inner layer cross-sectional image sequences of multilayer circuit boards through a multispectral imaging system, combine laser confocal scanning to acquire three-dimensional topographic data of the circuit, and use an adaptive weighted fusion algorithm to perform spatiotemporal registration of the acquired multi-source data to generate a multimodal quality inspection dataset containing circuit topology and material properties. The extraction module, based on the multimodal quality inspection dataset, utilizes a pre-trained nested attention deep learning model to extract circuit edge gradients and pad geometric features through low-level branches, capture the infrared spectral response of interlayer dielectric layer defects through high-level branches, and achieve cross-scale feature fusion using a feature pyramid network, outputting a fused circuit board defect-sensitive feature vector set. Specifically, the low-level branches of the pre-trained nested attention model identify the baseline grid lines on the circuit board, establish a local coordinate system with the grid intersections as the origin, extract the circuit edge gradients and pad geometric parameters in this coordinate system, and generate a low-level feature map with coordinate labels. The high-level branches of the nested attention model focus on the infrared spectrum of the interlayer dielectric layer, and through... By comparing the spectral reflectance differences between different layers at the same location, abnormal reflection areas are captured. The spectral characteristics of these abnormal reflection areas are converted into heat maps to generate high-level difference feature maps. A feature pyramid network is used to map the coordinate information of the bottom-level feature maps to the high-level difference feature maps, so that features at different scales are associated with the same local coordinate system. Cross-scale feature fusion is achieved through coordinate matching to generate a fused feature map with spatial labels. Feature points that deviate from the design coordinates are selected from the fused feature map. These feature points are key pixels in abnormal reflection areas of circuit corners, pad edges, and interlayer dielectric layers. The comprehensive features of these feature points, including geometric parameters, spectral reflectance, and coordinate offset, are combined to generate a circuit board defect-sensitive feature vector set. The detection module is used to input the defect-sensitive feature vector set into the Siamese network architecture, locate potential defect regions through a dynamic anchor box generation mechanism, perform multi-label classification of defect types by combining a Bayesian probability model, and simultaneously introduce a defect severity assessment module to quantify the impact of defects on circuit performance, and output detection results including defect location, type and severity.

5. The system according to claim 4, characterized in that, The registration module is specifically used for: Using a multispectral imaging system with a ring light source array, cross-sectional images of the surface and inner layers of a multilayer circuit board are simultaneously acquired from multiple angles. At the same time, a laser confocal scanning module acquires three-dimensional topographic data along the circuit path. The positioning holes on the edge of the circuit board are used as initial markers to generate raw data sets with angle markings. Multi-angle imaging features of the positioning holes are extracted from the original data set, and their spatial coordinates are calculated by triangulation. Based on this, a spatial transformation matrix between multispectral images and three-dimensional topography data is established to form a spatial correlation template. Based on spatial association templates, the occurrence time sequence of line features in images from different angles is compared. Linear interpolation is used to correct time deviations, and multi-source data are aligned to the same spatiotemporal coordinate system to obtain a spatiotemporal calibration dataset. Based on the difference in the number of layers of the circuit board, different weights are assigned to the surface and inner layer data in the spatiotemporal calibration dataset. A multimodal quality inspection dataset containing circuit topology and material properties is generated through pixel-level fusion. The weight of the inner layer data increases proportionally with the number of layers.

6. The system according to claim 5, characterized in that, The detection module is specifically used for: Using a twin network architecture, the defect-sensitive feature vector set is first differentially analyzed with the feature vector of the defect-free template to obtain the feature difference value. The dynamic anchor box generates candidate boxes based on the distribution range of the difference value. The edges of the boxes fit the line direction, and the candidate regions with direction markings are output. The feature vectors of the candidate regions are combined with the wiring rule base of the circuit board to perform Bayesian probability calculation. The rule base contains the defect probability distribution of different circuit types to generate a probability ranking of defect types, thus obtaining a type probability table. Based on the signal transmission frequency of the line where the candidate area is located, the defect size is converted into an impact value on signal attenuation, and the impact value is divided into three levels: minor, moderate and severe, to generate a severity label. The candidate region's direction markers, type probability tables, and severity labels are associated to remove defects that are repeatedly marked on the same line, generating detection results that include the defect's location, type, and severity. The location information includes a description of the line's direction.

7. A storage medium, characterized in that, The storage medium stores a computer program, wherein the computer program is configured to execute the method of any one of claims 1-3 when it is run.

8. An electronic device comprising a memory and a processor, characterized in that, The memory stores a computer program, and the processor is configured to run the computer program to perform the method of any one of claims 1-3.

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